A multi-source heterogeneous data anomaly identification and feature screening method
By using graph neural network models and the maximum likelihood method for analog integrated circuit size prediction and topology optimization, the problems of circuit topology limitations and low optimization efficiency in analog integrated circuit design are solved, and efficient and automated circuit generation and optimization are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU UNIVERSITY
- Filing Date
- 2022-10-08
- Publication Date
- 2026-05-26
AI Technical Summary
Existing technologies for analog integrated circuit design suffer from limitations in circuit topology, low optimization efficiency, and excessive and time-consuming manual intervention. Furthermore, EDA software does not support the generation and optimization of circuit topology for analog circuits.
Anomaly identification and feature screening methods based on multi-source heterogeneous data are adopted, circuit topology optimization is performed using a graph neural network model, and the size prediction of analog integrated circuits is performed using the maximum likelihood method. Combined with multiple constraints, a circuit structure with performance superior to that of manual design is generated.
It achieves efficient and automated circuit structure generation and optimization, and the performance indicators of the generated circuits reach or even exceed the level of manual design, with the advantages of high time efficiency and strong integration integrity.
Smart Images
Figure CN116245061B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog circuit design technology, specifically to a method for anomaly identification and feature screening of multi-source heterogeneous data. Background Technology
[0002] Analog integrated circuits play an indispensable role in circuit systems. The vast majority of electronic devices in the electronics market rely on analog circuits. Designing analog circuits remains a demanding task requiring significant time and effort. However, most commercially available EDA software does not support circuit topology generation and optimization for analog circuits, and its time efficiency is also low. Compared to digital integrated circuit (IC) design, the design of analog integrated circuits, such as voltage references with complex parameter evolution, must simultaneously consider multiple factors such as power consumption, temperature coefficient (TC), and line sensitivity (LS). Therefore, manual design is time-consuming and inefficient, leading to the need for automated circuit design. Unlike the mature Electronic Design Automation (EDA) technology in digital integrated circuits, there are relatively few reports on automated design systems for some analog integrated circuits, such as bandgap voltage references, error amplifiers, and traditional LDOs. Furthermore, current technical solutions suffer from the following drawbacks: limited circuit topology generation, low efficiency in circuit topology optimization, significant manual intervention, and time-consuming optimization methods. Summary of the Invention
[0003] The purpose of this invention is to provide a method for anomaly identification and feature screening of multi-source heterogeneous data, so as to solve the problems mentioned in the background art.
[0004] To achieve the above objectives, the present invention provides the following technical solution: A method for anomaly identification and feature screening of multi-source heterogeneous data includes generating and optimizing a custom multi-parameter, multi-constraint circuit topology under analog circuit conditions. In a multi-constraint custom circuit environment, the analog integrated circuit netlist is used as graph theory input. The maximum likelihood comparison prediction function is used to predict the size of the analog integrated circuit. The graph neural network model is used for circuit topology optimization. Optimization is performed on complex designs containing MOSFETs to generate circuit structures with performance indicators superior to manually designed circuits. Specifically, the method includes the following steps:
[0005] 1) First, perform multi-constraint customization. The specific steps are as follows:
[0006] a. Input circuit constraints: The circuit is used as a graph theory input and is divided into concrete structures and structures to be changed;
[0007] b. Use the two major structures as a custom system environment for analog integrated circuits;
[0008] c. Based on the initial system environment, taking the generation of a full MOS voltage reference source circuit as an example, and using multiple constraints as a basis, we will conduct a comparison of analog integrated circuit dimensions.
[0009] d. To improve the circuit system environment and feasibility, add constraints and utilize V when deriving the output voltage. DS ≥4V T To simplify the conditions, V at room temperature T If the voltage is 26mV, then the V of the MOSFET is... DS It needs to be greater than 104mV, while V ref =V DS6 +V DS7 V ref The minimum voltage should have a limit value.
[0010] 2) The maximum likelihood method is used to predict the size of analog integrated circuits. The specific steps are as follows:
[0011] a. Using the MOSFET state as observation data, randomly sample and generate the MOSFET data structure;
[0012] b. Observe and predict the specific MOS transistor data structure, compare its advantages, and start sampling and observation from the structure to be changed.
[0013] c. By comparing advantages, retain the data of the superior MOS transistors and use them as the offspring structure. Preserve the individuals and expand the data based on the offspring data to achieve automatic generation of the structure to be evolved.
[0014] d. From the structure to be evolved to the specific structure, realize the expansion generation of the structure, and after predicting the size of the analog integrated circuit, realize the automatic generation of the entire circuit.
[0015] 3) In automated analog integrated circuit design, the netlist is equivalent to a graph. To better enable intelligent learning and interaction with analog integrated circuits, a graph neural network is used to optimize the circuit topology. The specific steps are as follows:
[0016] a. The netlist of the initial circuit topology is derived using the HSPICE simulation tool. A graph neural network (GNN) is then used to normalize the modifiable parts of the netlist, making them individual entities within the GNN algorithm. Based on an information propagation mechanism, the GNN model, after simulating integrated circuit size prediction, updates the node state of each node by exchanging information until the MOSFET reaches a stable state. Let a graph-node pair data set be... in Represents a set of graphs. This represents the set of MOS transistor nodes, establishing the topology framework of an analog integrated circuit, and its dataset. for
[0017]
[0018] b. Based on the desired goal of the node, optimize and define x. n ∈R s For the state of node n, o n For the output of this node, the function f updates the node's state. w and the node's output function o n The update definition is as follows:
[0019] x n =f w (l n ,l c[n] ,x n[n] ,l n[n] (2)
[0020] o n =g w (x n ,l n (3)
[0021] c. Then, sum the above values individually to obtain a vector composed of all the summed values: state x, label l, output o, and node label l. n Thus, f w and o n superposition form F w and G w :
[0022] x = F w (x,l) (4)
[0023] o = G w (x,l N (5)
[0024] d. By Banach's fixed-point theory, it can be proven that the above expression has a unique solution, and this unique solution can be iteratively calculated using the following expression:
[0025] x(t+1)=F w (x(t),l) (6)
[0026] e. Finally, through iterative updates and using graph neural network algorithms to optimize predictions, the following can be calculated:
[0027] x n (t+1)=f w (l n ,l c[n] ,x n[n] (t),l n[n] (7)
[0028] o n (t)=g w (xn (t),l n ), n∈N (8)
[0029] This represents the optimal result for each MOS transistor circuit topology, and so on, to achieve topology optimization of the overall circuit structure.
[0030] Preferably, in step 1c, the processed final data is used as the initial value of the circuit topology.
[0031] Preferably, in step 1d, under normal circuit conditions, the output voltage is ensured not to be too high.
[0032] Preferably, when using the algorithm for optimization, a certain output voltage range is provided, and the output voltage range is set to 0.3-1.2V.
[0033] Preferably, in step 1, constraints are set on the current of the circuit to ensure that the current is not too large when the algorithm is automatically optimized, and to ensure that the power consumption of the circuit is within a reasonable range. The current range is set to 50nA-500nA.
[0034] Preferably, in step 3, n in a i,j ∈N i Represents a set The j-th node in t i,j Represents node n ij The expected goal.
[0035] Preferably, in step 3b, l n ,l c[n] ,x n[n] ,l n[n] , where represents the label of n, the label of n's edge, the node state, and the label of each of n's neighboring nodes, respectively.
[0036] Preferably, in step 3, x(t) represents the value of x in the t-th iteration, F w If x(t) is the transition function that updates the state of x(t), then for any initial value, the dynamic system can converge to a solution at an exponential rate.
[0037] Compared with the prior art, the beneficial effects of the present invention are:
[0038] 1. The anomaly identification and feature screening method for multi-source heterogeneous data uses a multi-constraint custom circuit, takes the initial circuit structure as graph theory input, and then uses maximum likelihood to predict the size of analog integrated circuits, and uses the simulation netlist as graph theory update.
[0039] 2. By comparing and continuously updating the dimensions, the circuit structure is eventually generated automatically, transforming the structure to be changed into a specific structure.
[0040] 3. By observing the state, the circuit topology is optimized using a graph neural network model, and finally a feasible circuit topology is output, so that the performance parameters of the generated circuit can reach or even exceed those of analog integrated circuits designed manually.
[0041] 4. This invention has the advantages of high time efficiency, strong integration integrity, short optimization time, automatic generation and optimization of circuit structure, and superior final circuit performance indicators. Attached Figure Description
[0042] Figure 1 This is a schematic diagram illustrating the basic ideas and steps of the present invention. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] Please see Figure 1 This invention provides a technical solution: a method for anomaly identification and feature screening of multi-source heterogeneous data, including custom multi-parameter and multi-constraint circuit topology generation and optimization under analog circuit conditions. In the multi-constraint custom circuit environment, the analog integrated circuit netlist is used as graph theory input, the maximum likelihood comparison prediction function is used to predict the size of the analog integrated circuit, and the circuit topology is optimized using a graph neural network model. For complex designs containing MOSFETs, optimization is performed to generate circuit structures with performance indicators superior to manually designed circuits. Specifically, the method includes the following steps:
[0045] 1) First, perform multi-constraint customization. The specific steps are as follows:
[0046] a. Input circuit constraints: The circuit is used as a graph theory input and is divided into concrete structures and structures to be changed;
[0047] b. Use the two major structures as a custom system environment for analog integrated circuits;
[0048] c. Based on the initial system environment, taking the generation of a full MOS voltage reference source circuit as an example, and using multiple constraints as a basis, perform analog integrated circuit size comparison, and use the processed final data as the initial value of the circuit topology.
[0049] d. To improve the circuit system environment and feasibility, add constraints and utilize V when deriving the output voltage. DS ≥4V T To simplify the conditions, V at room temperatureT If the voltage is 26mV, then the V of the MOSFET is... DS It needs to be greater than 104mV, while V ref =V DS6 +V DS7 V ref The minimum voltage should have a limit value. Under normal circuit conditions, the output voltage should not be too high. Therefore, when using the algorithm for optimization, a certain output voltage range is given. The output voltage range is set to 0.3-1.2V. Constraints are set on the current of the circuit to ensure that the current is not too large when the algorithm is automatically optimized, and to ensure that the power consumption of the circuit is within a reasonable range. The current range is set to 50nA-500nA.
[0050] 2) The maximum likelihood method is used to predict the size of analog integrated circuits. The specific steps are as follows:
[0051] a. Using the MOSFET state as observation data, randomly sample and generate the MOSFET data structure;
[0052] b. Observe and predict the specific MOS transistor data structure, compare its advantages, and start sampling and observation from the structure to be changed.
[0053] c. By comparing advantages, retain the data of the superior MOS transistors and use them as the offspring structure. Preserve the individuals and expand the data based on the offspring data to achieve automatic generation of the structure to be evolved.
[0054] d. From the structure to be evolved to the specific structure, realize the expansion generation of the structure, and after predicting the size of the analog integrated circuit, realize the automatic generation of the entire circuit.
[0055] 3) In automated analog integrated circuit design, the netlist is equivalent to a graph. To better enable intelligent learning and interaction with analog integrated circuits, a graph neural network is used to optimize the circuit topology. The specific steps are as follows:
[0056] a. The netlist of the initial circuit topology is derived using the HSPICE simulation tool. A graph neural network (GNN) is then used to normalize the modifiable parts of the netlist, making them individual entities within the GNN algorithm. Based on an information propagation mechanism, the GNN model, after simulating integrated circuit size prediction, updates the node state of each node by exchanging information until the MOSFET reaches a stable state. Let a graph-node pair data set be... in Represents a set of graphs. This represents the set of MOS transistor nodes, establishing the topology framework of an analog integrated circuit, and its dataset. for
[0057]
[0058] n i,j ∈N i Represents a set The j-th node in t i,j Represents node n ij Expected goals;
[0059] b. Based on the desired goal of the node, optimize and define x. n ∈R s For the state of node n, o n For the output of this node, the function f updates the node's state. w and the node's output function o n The update definition is as follows:
[0060] x n =f w (l n ,l c[n] ,x n[n] ,l n[n] (2)
[0061] o n =g w (x n ,l n (3)
[0062] l n ,l c[n] ,x n[n] ,l n[n] , representing the label of n, the label of n's edge, the node state, and the label of each of n's neighboring nodes, respectively;
[0063] c. Then, sum the above values individually to obtain a vector composed of all the summed values: state x, label l, output o, and node label l. n Thus, f w and o n superposition form F w and G w :
[0064] x = F w (x,l) (4)
[0065] o = G w (x,l N (5)
[0066] d. By Banach's fixed-point theory, it can be proven that the above expression has a unique solution, and this unique solution can be iteratively calculated using the following expression:
[0067] x(t+1)=F w(x(t),l) (6)
[0068] x(t) represents the value of x in the t-th iteration, F w If x(t) is the transition function that updates the state of x(t), then for any initial value, the dynamic system can converge to a solution at an exponential rate.
[0069] e. Finally, through iterative updates and using graph neural network algorithms to optimize predictions, the following can be calculated:
[0070] x n (t+1)=f w (l n ,l c[n] ,x n[n] (t),l n[n] (7)
[0071] o n (t)=g w (x n (t),l n ),n∈N (8)
[0072] This represents the optimal result for each MOS transistor circuit topology, and so on, to achieve topology optimization of the overall circuit structure.
[0073] In practice, this method for anomaly identification and feature filtering of multi-source heterogeneous data uses a multi-constraint custom circuit. An initial circuit structure is used as graph theory input, and maximum likelihood is used to predict the size of the analog integrated circuit. The simulation netlist is then used for graph theory updates. Through comparison, the size is continuously updated, ultimately generating the circuit structure automatically from the structure to be changed to the specific structure. Through state observation, a graph neural network model is used to optimize the circuit topology, ultimately outputting a highly feasible circuit topology. The generated circuit performance parameters can reach or even surpass those of manually designed analog integrated circuits. This invention has the advantages of high time efficiency, strong integration integrity, short optimization time, automatic generation and optimization of circuit structures, and superior final circuit performance indicators.
[0074] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A method for anomaly identification and feature selection of multi-source heterogeneous data, characterized in that: This includes generating and optimizing custom multi-parameter, multi-constraint circuit topologies in analog circuits. In a multi-constraint custom circuit environment, the analog integrated circuit netlist is used as graph theory input. Maximum likelihood comparison prediction is used to predict the size of the analog integrated circuit. A graph neural network model is used for circuit topology optimization. Optimization is performed on complex designs containing MOSFETs, generating circuit structures with performance superior to manually designed circuits. Specifically, the steps include: 1) First, perform multi-constraint customization. The specific steps are as follows: a. Input circuit constraints: The circuit is used as a graph theory input and is divided into concrete structures and structures to be changed; b. Use the two major structures as a custom system environment for analog integrated circuits; c. Based on the initial system environment, taking the generation of a full MOS voltage reference source circuit as an example, and using multiple constraints as a basis, we will conduct a comparison of analog integrated circuit dimensions. d. To improve the circuit system environment and feasibility, additional constraints are imposed. When deriving the output voltage, utilize... V DS ≥4 V T To simplify the conditions, at room temperature V T If the voltage is 26mV, then the MOSFET's... V DS It needs to be greater than 104mV, and V ref = V DS6 + V DS7 ,Right now V ref The minimum voltage should have a defined value; 2) The maximum likelihood method is used to predict the size of analog integrated circuits. The specific steps are as follows: a. Using the MOSFET state as observation data, randomly sample and generate the MOSFET data structure; b. Observe and predict the specific MOS transistor data structure, compare its advantages, and start sampling and observation from the structure to be changed. c. By comparing advantages, retain the data of the superior MOS transistors and use them as the offspring structure. Preserve the individuals and expand the data based on the offspring data to achieve automatic generation of the structure to be evolved. d. From the structure to be evolved to the specific structure, realize the expansion generation of the structure, and after predicting the size of the analog integrated circuit, realize the automatic generation of the entire circuit; 3) In the automated design of analog integrated circuits, the netlist is equivalent to a graph. To better enable intelligent learning and interaction with analog integrated circuits, a graph neural network is used to optimize the circuit topology. The specific steps are as follows: a. The netlist of the initial circuit topology is derived using the HSPICE simulation tool. A graph neural network (GNN) is then used to normalize the modifiable parts of the netlist, making them individual entities within the GNN algorithm. Based on an information propagation mechanism, the GNN model, after simulating integrated circuit size prediction, updates the node state of each node by exchanging information until the MOSFET reaches a stable state. Let a graph-node pair data set be... ,in Represents a set of graphs. This represents the set of MOS transistor nodes, establishing the topology framework of an analog integrated circuit, and its dataset. for ； b. Based on the desired goals of the nodes, optimize and define... For the state of node n, The function that updates the node's state is the output of that node. and node output function The update definition is as follows: ； c. Then, sum the above values individually to obtain a vector composed of all the summed values: State ,Label Output and node labels Thus obtain and superposition form and : ； d. Using Banach's fixed-point theory, prove that the above expression has a unique solution, and iteratively calculate this unique solution using the following expression: ； e. Finally, through iterative updates and using graph neural network algorithms to optimize predictions, the following can be calculated: This represents the optimal result for each MOS transistor circuit topology, and so on, to achieve topology optimization of the overall circuit structure.
2. The method for anomaly identification and feature filtering of multi-source heterogeneous data according to claim 1, characterized in that: In step 1), c, the processed final data is used as the initial value of the circuit topology.
3. The method for anomaly identification and feature filtering of multi-source heterogeneous data according to claim 1, characterized in that: When using the algorithm for optimization, the output voltage range is set to 0.3-1.2V.
4. The method for anomaly identification and feature filtering of multi-source heterogeneous data according to claim 1, characterized in that: In step 1), constraints are set on the current of the circuit operation, and the current range is set to 50nA-500nA.
5. The method for anomaly identification and feature filtering of multi-source heterogeneous data according to claim 1, characterized in that: In step 3), a) Represents a set The j-th node in Represents a node The expected goal.
6. The method for anomaly identification and feature filtering of multi-source heterogeneous data according to claim 1, characterized in that: In step 3) b) , where represents the label of n, the label of n's edge, the node state, and the label of each of n's neighboring nodes, respectively.
7. The method for anomaly identification and feature filtering of multi-source heterogeneous data according to claim 1, characterized in that: In step 3), d express In the The value of the next iteration. Is to make If the state update transition function is used, the dynamic system can converge to a solution exponentially for any initial value.