Clock division method, circuit, and storage medium

Abstract

Embodiments of the present application disclose a clock frequency division method, a circuit and a storage medium. The scheme can select a clock source on a microcontroller chip to determine an oscillator clock signal, input the oscillator clock signal to a pre-frequency divider to output a pre-divided system clock signal, input the pre-divided system clock signal to a post-frequency divider to output a plurality of non-overlapping quadrature clock signals, and divide an instruction period into a plurality of clock periods according to the plurality of non-overlapping quadrature clock signals. The scheme provided by the embodiments of the present application can support 4T mode and 2T mode by dividing the system clock, and can improve the CPU operation speed and peripheral device working speed of the microcontroller chip.

Description

Technical Field

[0001] This application relates to the field of chip processing technology, specifically to a clock division method, circuit, and storage medium. Background Technology

[0002] For a CPU, only one basic action is performed within one clock cycle. The clock pulse is the fundamental operating pulse of a computer, controlling its operating rhythm. The higher the clock frequency, the shorter the clock cycle, and the faster the operating speed. In CPU terminology, the clock cycle is also called a tick, which divides a machine cycle into several equal time segments, each segment performing only one basic operation, represented by a single voltage level signal width.

[0003] In practical applications, existing 8-bit MCUs are limited by their intended use and cost, and generally provide internal high-speed clocks of 16MHz or 8MHz. Taking 16MHz as an example, the instruction cycle of a PIC microcontroller is four times the clock cycle. Therefore, for the CPU and peripherals, the actual usable clock speed is 4MHz, resulting in long CPU processing times and slow peripheral operation. Summary of the Invention

[0004] This application provides a clock division method, circuit, and storage medium, which can improve the CPU processing speed and peripheral operating speed of a microcontroller chip by dividing the system clock.

[0005] This application provides a clock division method, including:

[0006] Select a clock source on the microcontroller chip to determine the oscillator clock signal;

[0007] The oscillator clock signal is input to the prescaler to output the prescaled system clock signal;

[0008] The pre-divided system clock signal is input to the post-divider to output multiple non-overlapping quadrature clock signals;

[0009] The instruction cycle is divided into multiple clock cycles based on the multiple non-overlapping quadrature clock signals.

[0010] This application also provides a clock divider circuit, including:

[0011] The first multiplexer is used to select a clock source on the microcontroller chip to determine the oscillator clock signal;

[0012] A prescaler is used to prescale the oscillator clock signal;

[0013] The second multiplexer is used to output the pre-divided oscillator clock signal as the system clock signal;

[0014] The post-divider is used to divide the system clock signal to output multiple non-overlapping quadrature clock signals, wherein the multiple non-overlapping quadrature clock signals divide the instruction cycle into multiple clock cycles.

[0015] This application also provides a storage medium storing multiple instructions adapted for loading by a processor to execute any of the clock division methods provided in this application.

[0016] The clock division scheme provided in this application embodiment allows selection of a clock source on the microcontroller chip to determine the oscillator clock signal. This oscillator clock signal is then input to a prescaler to output a prescaled system clock signal. The prescaled system clock signal is then input to a postscaler to output multiple non-overlapping quadrature clock signals. The instruction cycle is divided into multiple clock cycles based on these multiple non-overlapping quadrature clock signals. The scheme provided in this application embodiment, by dividing the system clock, supports not only 4T mode but also 2T mode, thereby improving the CPU processing speed and peripheral operating speed of the microcontroller chip. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of the first clock division method provided in the embodiments of this application;

[0019] Figure 2 This is a schematic diagram of the clock divider circuit provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the instruction cycle in 4T mode provided in the embodiments of this application;

[0021] Figure 4 This is a schematic diagram of the instruction cycle in 2T mode provided in the embodiments of this application;

[0022] Figure 5 This is a schematic diagram of the terminal structure provided in the embodiments of this application. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0025] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0026] It should be noted that step designations such as 101 and 102 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute 102 first and then 101, etc., but these should all be within the protection scope of this application.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] This application provides a clock frequency division method. The main body executing the clock frequency division method can be the clock frequency division circuit provided in this application, or an electronic device that integrates the clock frequency division circuit. The clock frequency division circuit can be implemented in hardware.

[0029] Before describing the technical solution of this application, let's briefly explain the relevant technical terms:

[0030] MCU: Microcontroller chip, which is a chip that appropriately reduces the frequency and specifications of the Central Processing Unit (CPU) and integrates memory, timer, USB, A / D conversion, UART, PLC, DMA and other peripheral interfaces, and even LCD driver circuits on a single chip to form a chip-level computer, which can perform different combinations of control for different applications.

[0031] Fosc: The frequency of the oscillator, also known as the crystal oscillator frequency. Crystal oscillators exhibit the piezoelectric effect, meaning that when a voltage is applied to the two electrodes of the crystal, the crystal will deform. Conversely, if an external force deforms the crystal, a voltage will be generated on the metal plates at the two electrodes. If an appropriate alternating voltage is applied to the crystal, it will resonate.

[0032] Fsys: System clock. Fsys is a reference clock signal that can be output to external systems. The system clock Fsys can come from multiple internal and external clock sources.

[0033] Fcpu: CPU clock refers to the frequency of the CPU. The processor chip operates at a specific clock frequency. The speed of the processor is measured by its clock frequency.

[0034] Clock cycle: also known as oscillation period, is defined as the reciprocal of the clock pulse and is the most basic time unit in MCU.

[0035] Instruction cycle: The time required to execute one instruction.

[0036] like Figure 1 As shown, Figure 1 This is a first flowchart illustrating the clock division method provided in this application embodiment. The specific flow of the clock division method can be as follows:

[0037] 101. Select a clock source on the microcontroller chip to determine the oscillator clock signal.

[0038] In one embodiment, an 8-bit microcontroller is used as an example. This microcontroller can have four system oscillators, including two high-speed oscillators and two low-speed oscillators, which serve as the system clock source for the microcontroller. Specifically, it may include an external high-speed crystal oscillator HXT with a frequency of 400kHz to 16MHz, an internal high-speed RC oscillator HIRC with a frequency of 4 / 8 / 12 / 16MHz, an external low-speed crystal oscillator LXT with a frequency of 32.768kHz, and an internal low-speed RC oscillator LIRC with a frequency of 32kHz. The selection of whether to use a high-speed or low-speed oscillator as the system clock is determined by setting bits CKS2 to CKS0 in the SCC register, and the system clock can be dynamically selected. The actual clock source for the low-speed oscillator is selected by the FSS bit of the SCC register, and the actual clock source for the high-speed oscillator is selected by the FHS bit of the SCC register. The frequency of the low-speed or high-speed system clock is determined by bits CKS2 to CKS0 of the SCC register. In this embodiment, the Fosc generally defaults to selecting HIRC as the clock source. In other words, the steps of selecting a clock source on a microcontroller chip may include: selecting a high-speed clock as the clock source in the microcontroller chip through a clock selection signal.

[0039] 102. Input the oscillator clock signal to the prescaler to output the prescaled system clock signal.

[0040] In one embodiment, the first division factor can be determined based on the application to be run by the MCU chip, and the clock source selected by Fosc can be multiplied based on this factor. Therefore, the step of inputting the oscillator clock signal to the prescaler to output the pre-divided system clock signal may include: determining the first division factor based on the target application, inputting the oscillator clock signal to the prescaler to output the pre-divided system clock signal based on the first division factor.

[0041] In this application, the oscillator clock signal needs to be divided by an even number, such as 1, 2, 4, 8, and 16. Even-number division reduces the frequency of the source clock signal by a factor, resulting in a lower-frequency divided clock signal. The ratio between the frequency of the resulting divided clock signal and the frequency of the source clock signal matches the division factor of the even-number division. For example, dividing a 1GHz source clock signal by 8 yields a 125MHz divided clock signal with a period of 8ns. The timing accuracy when sampling based on the rising and falling edges is only 4ns. Optionally, in an ASIC (Application Specific Integrated Circuit), the frequency divider can set the output signal toggles based on the number of times a counter counts the rising or falling edges of the oscillator clock signal to achieve even-number division with different division factors. The divided clock signal obtained after frequency division is the system clock signal.

[0042] In one embodiment, the oscillator clock signal can also be kept in a non-divided state. For example, if the 16MHz HIRC in the MCU is selected as the clock source, then the Fsys clock frequency is 16MHz.

[0043] 103. Input the pre-divided system clock signal to the post-divider to output multiple non-overlapping quadrature clock signals.

[0044] In one embodiment, the above steps may include: receiving a mode switching signal, determining a second division number based on the mode switching signal, and inputting the pre-divided system clock signal to a post-divider to output multiple non-overlapping quadrature clock signals based on the second division number. The second division number can be determined based on the architecture of the microcontroller chip or the number of bits in the counter, thereby generating the corresponding mode switching signal.

[0045] 104. Divide the instruction cycle into multiple clock cycles based on multiple non-overlapping quadrature clock signals.

[0046] Among them, common ICs are all 4T architecture, that is, one instruction cycle is 4 clock cycles. Assuming the IC's main frequency Fsys is HIRC 16MHz, then:

[0047] Clock period = 1T = 1 ÷ Fsys = 1 ÷ (16MHz) = 0.0625μs

[0048] Instruction cycle = 4T = 4 × 0.0625us = 0.25μs

[0049] In this embodiment, a 2T mode is added. Selecting the 2T mode allows the final output clock frequency to reach 8MHz. This clock frequency is then used as the CPU clock for the CPU and peripherals, thereby achieving acceleration.

[0050] As described above, the clock division method proposed in this application can select a clock source on the microcontroller chip to determine the oscillator clock signal, input the oscillator clock signal to a prescaler to output a prescaled system clock signal, and input the prescaled system clock signal to a postscaler to output multiple non-overlapping quadrature clock signals. The instruction cycle is then divided into multiple clock cycles based on these multiple non-overlapping quadrature clock signals. The solution provided in this application can improve the CPU processing speed and peripheral operating speed of the microcontroller chip by dividing the system clock, supporting not only 4T mode but also 2T mode.

[0051] To implement the above methods, this application also provides a clock divider circuit, which can be integrated into a terminal device such as a terminal or tablet computer.

[0052] For example, such as Figure 2 The diagram shown is a schematic representation of a clock divider circuit provided in an embodiment of this application. This clock divider circuit may include:

[0053] The first multiplexer U1 is used to select a clock source on the microcontroller chip to determine the oscillator clock signal and output the Fosc clock. Here, OSCM is the selection signal, HIRC is the high-speed clock (16MHz), and LIRC is the low-speed clock (32kHz).

[0054] The prescaler U2 is used to prescale the oscillator clock signal. For example, it can prescale the input Fosc clock to: divide by 1, divide by 2, divide by 4, divide by 8, and divide by 16.

[0055] The second multiplexer U3 is used to output the pre-divided oscillator clock signal as the system clock signal, wherein FINTOSC is the selection signal.

[0056] The post-divider U4 is used to divide the system clock signal to output multiple non-overlapping quadrature clock signals, wherein the multiple non-overlapping quadrature clock signals divide the instruction cycle into multiple clock cycles. For example, if the input is the Fsys clock, the outputs are 2T and 4T clocks.

[0057] The third multiplexer U5 is used to output the multiple non-overlapping quadrature clock signals as the CPU clock for use by the CPU and external devices. Here, FCPUS is the selection signal.

[0058] In this embodiment, the post-divider U4 and the third multiplexer U5 together form a selector for 2T and 4T cycles, and FCPUS is the control signal for switching between 2T and 4T modes.

[0059] Further reading Figure 3 , Figure 3 This describes the operation in 4T mode. Fsys is the system clock. Fsys generates four non-overlapping quadrature clock signals, Q1, Q2, Q3, and Q4, after being divided by 4 by the U4 device. One instruction cycle consists of four Q cycles. During Q4, the instruction is fetched from the instruction memory and latched into the instruction register, and then executed in the next instruction cycle.

[0060] Please continue reading. Figure 4 , Figure 4 This describes the operation in 2T mode. Fsys is the system clock. Fsys generates two non-overlapping quadrature clock signals, Q1 and Q2, by dividing the frequency by 2 using the U4 device. One instruction cycle consists of two Q cycles. During Q2, the instruction is fetched from the instruction memory and latched into the instruction register, and then executed in the next instruction cycle.

[0061] The instruction register (IR) is a register that temporarily stores program instructions fetched from memory. When an instruction is executed, it is first fetched from memory into the data register (DR), and then transferred to the IR. Instructions are divided into opcode and address fields, composed of binary numbers. To execute any given instruction, the opcode must be tested to identify the requested operation. The instruction decoder performs this task. The output of the opcode field in the instruction register is the input of the instruction decoder. Once the opcode is decoded, it sends a specific signal to the operation controller to perform the desired operation.

[0062] As described above, the clock divider circuit provided in this application can select a clock source on the microcontroller chip to determine the oscillator clock signal. The oscillator clock signal is then input to a prescaler to output a prescaled system clock signal. This prescaled system clock signal is then input to a postscaler to output multiple non-overlapping quadrature clock signals. The instruction cycle is divided into multiple clock cycles based on these multiple non-overlapping quadrature clock signals. The solution provided in this application's embodiments can improve the CPU processing speed and peripheral operating speed of the microcontroller chip by dividing the system clock, supporting not only 4T mode but also 2T mode.

[0063] This application also provides a terminal, such as... Figure 5As shown, the terminal may include a radio frequency (RF) circuit 601, a memory 602 including one or more computer-readable storage media, an input unit 603, a display unit 604, a sensor 605, an audio circuit 606, a wireless Fidelity (WiFi) module 607, a processor 608 including one or more processing cores, and a power supply 609, among other components. Those skilled in the art will understand that... Figure 5 The terminal structure shown does not constitute a limitation on the terminal and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0064] RF circuit 601 can be used for receiving and transmitting signals during information transmission or calls. Specifically, it receives downlink information from the base station and hands it over to one or more processors 608 for processing; additionally, it transmits uplink data to the base station. Typically, RF circuit 601 includes, but is not limited to, an antenna, at least one amplifier, a tuner, one or more oscillators, a Subscriber Identity Module (SIM) card, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, RF circuit 601 can also communicate wirelessly with networks and other devices. Wireless communication can use any communication standard or protocol, including but not limited to GSM, GPRS, CDMA, WCDMA, LTE, email, and SMS.

[0065] The memory 602 can be used to store software programs and modules. The processor 608 executes various functional applications and information processing by running the software programs and modules stored in the memory 602. The memory 602 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the terminal (such as audio data, phone book, etc.). In addition, the memory 602 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 602 may also include a memory controller to provide access to the memory 602 for the processor 608 and the input unit 603.

[0066] The input unit 603 can be used to receive input digital or character information, and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control. Specifically, in one embodiment, the input unit 603 may include a touch-sensitive surface and other input devices. The touch-sensitive surface, also known as a touch display or touchpad, can collect user touch operations on or near it (e.g., user operations using fingers, styluses, or any suitable object or accessory on or near the touch-sensitive surface), and drive corresponding connection devices according to a pre-set program. Optionally, the touch-sensitive surface may include a touch detection device and a touch controller. The touch detection device detects the user's touch orientation and the signal generated by the touch operation, transmitting the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, sends it to the processor 608, and can receive and execute commands from the processor 608. Furthermore, various types of touch-sensitive surfaces, such as resistive, capacitive, infrared, and surface acoustic wave, can be used. In addition to the touch-sensitive surface, the input unit 603 may also include other input devices. Specifically, other input devices may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons, power buttons, etc.), trackball, mouse, joystick, etc.

[0067] Display unit 604 can be used to display information input by the user or information provided to the user, as well as various graphical user interfaces of the terminal. These graphical user interfaces can be composed of graphics, text, icons, video, and any combination thereof. Display unit 604 may include a display panel, optionally configured as a liquid crystal display (LCD), organic light-emitting diode (OLED), or similar form. Furthermore, a touch-sensitive surface may cover the display panel. When the touch-sensitive surface detects a touch operation on or near it, it transmits the information to processor 608 to determine the type of touch event. Subsequently, processor 608 provides corresponding visual output on the display panel according to the type of touch event. Although in Figure 5 In this context, the touch-sensitive surface and the display panel are two separate components for implementing input and output functions. However, in some embodiments, the touch-sensitive surface and the display panel can be integrated to achieve both input and output functions.

[0068] The terminal may also include at least one sensor 605, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display panel according to the ambient light level, and the proximity sensor can turn off the display panel and / or backlight when the terminal is moved to the ear. As a type of motion sensor, a gravity acceleration sensor can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity and can be used for applications that identify the terminal's posture (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition-related functions (such as pedometers, taps), etc. Other sensors that the terminal may also be equipped with, such as gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, will not be described in detail here.

[0069] Audio circuitry 606, a speaker, and a microphone provide an audio interface between the user and the terminal. Audio circuitry 606 converts received audio data into electrical signals, transmits them to the speaker, and the speaker converts them into sound signals for output. Conversely, the microphone converts collected sound signals into electrical signals, which are then received by audio circuitry 606, converted back into audio data, and processed by processor 608. The processed data is then transmitted via RF circuitry 601 to, for example, another terminal, or output to memory 602 for further processing. Audio circuitry 606 may also include an earphone jack to facilitate communication between a peripheral headset and the terminal.

[0070] WiFi is a short-range wireless transmission technology. A terminal using a WiFi module 607 can help users send and receive emails, browse web pages, and access streaming media, providing users with wireless broadband internet access. Although Figure 5 WiFi module 607 is shown, but it is understood that it is not a necessary component of the terminal and can be omitted as needed without changing the essence of the invention.

[0071] The processor 608 is the control center of the terminal, connecting various parts of the terminal through various interfaces and lines. It executes software programs and / or modules stored in the memory 602, and calls data stored in the memory 602 to perform various functions and process data, thereby providing overall monitoring of the terminal. Optionally, the processor 608 may include one or more processing cores; preferably, the processor 608 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 608.

[0072] The terminal also includes a power supply 609 (such as a battery) to power various components. Preferably, the power supply can be logically connected to the processor 608 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. The power supply 609 may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0073] Although not shown, the terminal may also include a camera, Bluetooth module, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 608 in the terminal loads the executable files corresponding to the processes of one or more applications into the memory 602 according to the following instructions, and the processor 608 runs the applications stored in the memory 602 to realize various functions:

[0074] Select a clock source on the microcontroller chip to determine the oscillator clock signal;

[0075] The oscillator clock signal is input to the prescaler to output the prescaled system clock signal;

[0076] The pre-divided system clock signal is input to the post-divider to output multiple non-overlapping quadrature clock signals;

[0077] The instruction cycle is divided into multiple clock cycles based on the multiple non-overlapping quadrature clock signals.

[0078] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed description of the clock division method above, which will not be repeated here.

[0079] As can be seen from the above, the terminal in this embodiment can select a clock source on the microcontroller chip to determine the oscillator clock signal, input the oscillator clock signal to a prescaler to output a prescaled system clock signal, and input the prescaled system clock signal to a postscaler to output multiple non-overlapping quadrature clock signals. The instruction cycle is divided into multiple clock cycles based on these multiple non-overlapping quadrature clock signals. The solution provided in this embodiment can improve the CPU processing speed and peripheral operating speed of the microcontroller chip by dividing the system clock, supporting not only 4T mode but also 2T mode.

[0080] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0081] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the clock division methods provided in embodiments of this application. For example, the instructions can execute the following steps:

[0082] Select a clock source on the microcontroller chip to determine the oscillator clock signal;

[0083] The oscillator clock signal is input to the prescaler to output the prescaled system clock signal;

[0084] The pre-divided system clock signal is input to the post-divider to output multiple non-overlapping quadrature clock signals;

[0085] The instruction cycle is divided into multiple clock cycles based on the multiple non-overlapping quadrature clock signals.

[0086] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0087] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0088] Since the instructions stored in the storage medium can execute the steps of any clock division method provided in the embodiments of this application, the beneficial effects that any clock division method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0089] The clock division method, circuit, and storage medium provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A clock dividing method, characterized by, include: Select a clock source on the microcontroller chip to determine the oscillator clock signal; The oscillator clock signal is input to the prescaler to output the prescaled system clock signal; The pre-divided system clock signal is input to the post-divider to output multiple non-overlapping quadrature clock signals; The instruction cycle is divided into multiple clock cycles based on the multiple non-overlapping quadrature clock signals; The step of inputting the pre-divided system clock signal to the post-divider to output multiple non-overlapping quadrature clock signals includes: receiving a mode switching signal, determining a second division number based on the mode switching signal; and inputting the pre-divided system clock signal to the post-divider to output multiple non-overlapping quadrature clock signals based on the second division number. The generation process of the mode switching signal includes: determining the target mode according to the architecture of the microcontroller chip or the number of bits of the counter, wherein the target mode includes a 2-cycle mode and a 4-cycle mode; generating the mode switching signal in the target mode; in the 2-cycle mode, two non-overlapping quadrature clock signals are generated after frequency division by 2, and in the 4-cycle mode, four non-overlapping quadrature clock signals are generated after frequency division by 4. After dividing the instruction cycle into multiple clock cycles based on the multiple non-overlapping quadrature clock signals, the method further includes: fetching an instruction from the instruction memory in each clock cycle and storing the instruction in the instruction register for execution in the next cycle; and outputting the multiple non-overlapping quadrature clock signals as a CPU clock for use by the CPU and external devices.

2. The clock division method of claim 1, wherein, The step of inputting the oscillator clock signal to the prescaler to output the prescaled system clock signal includes: Determine the first frequency division number based on the target application; The oscillator clock signal is input to the prescaler to output the prescaled system clock signal based on the first division number.

3. The clock division method of claim 2, wherein, The step of outputting the pre-divided system clock signal based on the first division number includes: The oscillator clock signal is divided by an even number of times to generate the divided system clock signal.

4. The clock division method according to any one of claims 1 to 3, wherein Selecting a clock source on the microcontroller chip includes: A high-speed clock is selected in the microcontroller chip as the clock source by a clock selection signal.

5. A clock dividing circuit, characterized by comprising: include: The first multiplexer is used to select a clock source on the microcontroller chip to determine the oscillator clock signal; A prescaler is used to prescale the oscillator clock signal; The second multiplexer is used to output the pre-divided oscillator clock signal as the system clock signal; A frequency divider is used to divide the system clock signal to output multiple non-overlapping quadrature clock signals, wherein the multiple non-overlapping quadrature clock signals divide the instruction cycle into multiple clock cycles. The step of inputting the pre-divided system clock signal to the post-divider to output multiple non-overlapping quadrature clock signals includes: receiving a mode switching signal, determining a second division number based on the mode switching signal; and inputting the pre-divided system clock signal to the post-divider to output multiple non-overlapping quadrature clock signals based on the second division number. The generation process of the mode switching signal includes: determining the target mode according to the architecture of the microcontroller chip or the number of bits of the counter, wherein the target mode includes a 2-cycle mode and a 4-cycle mode; generating the mode switching signal in the target mode; in the 2-cycle mode, two non-overlapping quadrature clock signals are generated after frequency division by 2, and in the 4-cycle mode, four non-overlapping quadrature clock signals are generated after frequency division by 4. After dividing the instruction cycle into multiple clock cycles based on the multiple non-overlapping quadrature clock signals, the method further includes: fetching an instruction from the instruction memory in each clock cycle and storing the instruction in the instruction register for execution in the next cycle; The circuit further includes a third multiplexer for outputting the plurality of non-overlapping quadrature clock signals as a CPU clock for use by the CPU and external devices.

6. A storage medium, characterized by The storage medium stores a plurality of instructions, which are adapted for loading by a processor to execute the clock division method according to any one of claims 1 to 4.

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