FPGA prototype verification method and system for smart meter chip

Abstract

The application relates to an FPGA prototype verification method and system of a smart meter chip, and belongs to the field of integrated circuit testing and electric power metering. The method aims to solve the problems of ASIC design transplantation to an FPGA platform, large difference between a verification environment and a real power grid, and lack of a real-time closed-loop verification mechanism. A technical scheme efficiently transplants the design to the FPGA by optimizing ASIC front-end synthesis constraints and adopting a netlist-level IP replacement strategy; a hardware-in-the-loop system is constructed, which comprises a real power grid signal source, a separation device simulation front end, an FPGA verification board, a high-precision standard electric energy meter and a host computer. The system can generate a real power grid excitation and realize synchronous collection of prototype output and the standard meter, real-time error analysis and dynamic adjustment of parameters, thereby forming a closed-loop verification. The application significantly improves code transplantation efficiency, provides a highly consistent real power grid verification environment, and greatly improves verification iteration and defect positioning speed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing and power metering, and relates to an FPGA prototype verification method and system for a smart meter chip. Background Technology With the deepening of smart grid construction and the increasing demands for accuracy and reliability in electricity metering, smart meter chips are becoming increasingly complex. They have evolved from simple energy metering to System-on-Chips (SoCs) integrating multiple communication protocols, data processing, anti-theft detection, load monitoring, event logging, and other functional modules. This increased integration and complexity presents significant challenges to chip design and verification.

[0002] Currently, the verification of smart meter chips mainly relies on two methods: digital simulation verification (RTL-level simulation and gate-level simulation) and silicon verification after tape-out. In the digital simulation stage, although high-performance simulators or accelerators can be used to functionally verify the design, the simulation speed is limited, making it difficult to fully cover the chip's behavior under long-term (months or even years) and multi-condition (voltage fluctuations, harmonic interference, three-phase imbalance, instantaneous overvoltage / undervoltage, strong magnetic field interference, etc.) conditions in a real power grid environment. In actual engineering, simulating a few seconds of power grid signal often requires hours or even days of machine time, severely limiting the verification depth. Many deep-seated defects related to long-term stability, edge scenarios, and accumulated errors are difficult to expose before tape-out.

[0003] To compensate for the shortcomings of pure software simulation, the industry has gradually adopted FPGA prototyping technology, porting ASIC design code or netlists to the FPGA platform to run the design at speeds close to real hardware, thereby enabling longer-term and larger-scale verification tests. However, existing FPGA prototyping methods still have the following main problems when applied to smart meter chips: First, the architectural differences between ASIC and FPGA platforms make porting difficult. The dedicated standard cell library, clock tree synthesis results (containing numerous clock gating mechanisms), reset tree structures, and some hard-core IPs (such as PLLs and the digital interface portions of analog-related IPs) used extensively in ASIC design cannot be directly mapped to FPGAs. This often requires engineers to make significant modifications to the RTL code, replace IP cores one by one, or even redesign equivalent logic. This process is not only time-consuming and inefficient, but also highly prone to introducing new functional deviations or timing issues. Especially in projects with a large number of IPs and complex meter-specific algorithm modules, the porting cycle often becomes a critical bottleneck in project progress.

[0004] Second, most existing FPGA verifications use laboratory signal generators or pre-recorded idealized / simplified waveform files as excitation sources, which differ significantly from the complex power grid environment in actual smart meter deployments. Real power grid signals have various non-ideal characteristics such as high harmonic content, random noise, voltage spikes and drops, phase jumps, and frequency drift. Laboratory excitations cannot fully and continuously reproduce these characteristics, leading to a large deviation between verification results and actual field performance. This makes it impossible to effectively assess the long-term metrological stability and reliability of the chip under real service conditions.

[0005] Third, traditional FPGA verification platforms typically lack a real-time closed-loop comparison mechanism with high-precision reference standards. During the verification process, the electrical energy data output by the FPGA prototype is often analyzed for errors only through post-event comparison or manual statistics, making it difficult to achieve real-time error monitoring and rapid parameter tuning, resulting in low defect location and convergence efficiency.

[0006] The existence of the above-mentioned problems means that some key defects can only be discovered after tape-out or even after large-scale field deployment, resulting in serious consequences such as high rework costs, extended delivery cycles, and field measurement disputes.

[0007] Therefore, there is an urgent need for a method and system for FPGA prototype verification of smart meter chips that can improve the efficiency of ASIC to FPGA porting, enhance the realism of the verification environment, and realize real-time closed-loop error analysis, so as to more fully and efficiently verify the long-term performance of the chip in a real power grid environment before tape-out. Summary of the Invention

[0008] In view of this, the purpose of this invention is to provide an FPGA prototype verification method and system for smart meter chips. To achieve the above objectives, the present invention provides the following technical solution: An FPGA prototype verification method for a smart meter chip includes the following steps: Perform application-specific integrated circuit (ASIC) front-end synthesis to generate an ASIC netlist. The ASIC front-end synthesis ensures that the logic of the clock tree does not need to be optimized and the generation of clock gates is eliminated during synthesis, that the logic of the reset tree does not need to be optimized during synthesis, and that the hierarchical structure of the ASIC netlist obtained after synthesis is consistent with the original design. The intellectual property core IP is replaced by using a script to filter out the standard cell devices used in the ASIC netlist from the standard cell library file of the ASIC netlist, forming an engineering standard cell library file. The logic relationship described by the truth table in the engineering standard cell library file is then redescribed using synthesizable syntax to obtain a standard cell library file for FPGA. Perform FPGA synthesis: synthesize the ASIC netlist after IP replacement to obtain the FPGA netlist. FPGA implementation involves mapping the FPGA netlist to the physical resources of the FPGA chip through placement and routing. FPGA programming is performed, and the mapped FPGA netlist is programmed onto the FPGA verification board. An FPGA prototype verification system is constructed, which includes a real power grid signal source, a discrete device analog front-end module, a signal acquisition and transmission link, the FPGA verification board, a high-precision standard energy meter, and a host computer. The real power grid signal source generates a signal containing harmonics, noise, and voltage dips and outputs it to the discrete device analog front-end module. The discrete device analog front-end module includes a high-precision analog-to-digital converter (ADC) and a programmable gain amplifier (PGA). The FPGA (Programmable Array of Independent Controllers) system is located at the front end of the signal chain and is used to dynamically adjust the gain of the input signal. The ADC device converts the grid signal into a digital code stream. The signal acquisition and transmission link transmits the digital code stream to the FPGA verification board via a high-speed interface and shielded signal line. The FPGA verification board carries the programmed FPGA chip and generates signals. The high-precision standard energy meter and the FPGA verification board receive the acquired data in parallel and calculate the error between the FPGA verification board data and the high-precision data in real time. The host computer issues commands in real time through host computer software to configure the working mode of the FPGA verification board, adjust dynamic parameters, and complete register read and write operations. A closed-loop real-time comparison mechanism is built through the FPGA prototype verification system to realize the synchronous acquisition of the FPGA verification board output and the high-precision standard energy meter and the instant error analysis. The parameters of the FPGA verification board are dynamically adjusted according to the real-time error to verify the correctness of the algorithm and function.

[0009] Furthermore, the IP replacement includes the replacement of soft-core IP and hard-core IP. The soft-core IP is synthesized into a netlist during the ASIC synthesis stage and replaced by obtaining the ASIC netlist. The hard-core IP is replaced by equivalent IP on the FPGA platform or by re-describing its function using a synthesizable language.

[0010] Furthermore, the real power grid signal source generates a signal containing harmonics, noise, and voltage dips through a high-fidelity power grid simulator.

[0011] Furthermore, the ADC device of the discrete device analog front-end module is comparable to the ASIC design specifications, and different versions of the ASIC analog front-end can be simulated by replacing the ADC device with one of different performance.

[0012] Furthermore, the signal acquisition and transmission link ensures that the materials used for signal transmission meet the operating frequency requirements from the analog circuit to the FPGA verification board.

[0013] An FPGA prototype verification system for a smart meter chip includes a real power grid signal source, a discrete device analog front-end module, a signal acquisition and transmission link, an FPGA verification board, a high-precision standard energy meter, and a host computer. The real power grid signal source generates a signal containing harmonics, noise, and voltage dips, which is then output to the discrete device analog front-end module. This module includes a high-precision ADC and a PGA (Power Generation Array). The PGA is located at the front end of the signal chain and is used to dynamically adjust the gain of the input signal. The ADC converts the power grid signal into a digital stream. The signal acquisition and transmission link transmits the digital stream to the FPGA verification board via a high-speed interface and shielded signal lines. The FPGA verification board carries a programmed FPGA chip and generates signals. The FPGA chip is obtained through ASIC front-end synthesis, IP replacement, FPGA synthesis, FPGA implementation, and FPGA programming. ASIC front-end synthesis ensures that the clock tree logic does not need optimization and eliminates clock gate generation, that the reset tree logic does not need optimization, and that the hierarchical structure of the resulting ASIC netlist is consistent with the original design. IP replacement uses a script to filter the standard cell library files in the ASIC netlist to select the standard cell devices used in the ASIC netlist, forming a working... The standard cell library file is generated, and the logical relationships described in the truth table of the standard cell library file are redescribed using synthesizable syntax to obtain the standard cell library file for FPGA. FPGA synthesis is performed on the ASIC netlist after IP replacement to obtain the FPGA netlist. FPGA implementation maps the FPGA netlist to the physical resources of the FPGA chip through placement and routing. FPGA programming programs the mapped FPGA netlist to the FPGA verification board. The high-precision standard energy meter and the FPGA verification board are connected in parallel to collect data, and the error between the FPGA verification board data and the high-precision data is calculated in real time. The host computer issues instructions in real time through host computer software to configure the working mode of the FPGA verification board, adjust dynamic parameters, and complete register read and write. This FPGA prototype verification system realizes synchronous acquisition of the FPGA verification board output and the high-precision standard energy meter and instant error analysis by constructing a closed-loop real-time comparison mechanism, and dynamically adjusts the FPGA verification board parameters according to the real-time error to verify the correctness of the algorithm and function.

[0014] Furthermore, the IP replacement includes the replacement of soft-core IP and hard-core IP. The soft-core IP is synthesized into a netlist during the ASIC synthesis stage and replaced by obtaining the ASIC netlist. The hard-core IP is replaced by equivalent IP on the FPGA platform or by re-describing its function using a synthesizable language.

[0015] Furthermore, the real power grid signal source generates a signal containing harmonics, noise, and voltage dips through a high-fidelity power grid simulator.

[0016] Furthermore, the ADC device of the discrete device analog front-end module is comparable to the ASIC design specifications, and different versions of the ASIC analog front-end can be simulated by replacing the ADC device with one of different performance.

[0017] Furthermore, the signal acquisition and transmission link ensures that the materials used for signal transmission meet the operating frequency requirements from the analog circuit to the FPGA verification board.

[0018] The beneficial effects of this invention are as follows: (1) In terms of code porting, this invention significantly improves the portability of gate-level netlists to FPGA platforms by imposing specific constraints on clock trees and reset trees during the ASIC front-end synthesis stage (canceling clock gating optimization, disabling reset tree optimization, and retaining the design hierarchy). This avoids the large amount of RTL modification or logic rewriting work caused by differences in clock gating and reset strategies in traditional methods. At the same time, by adopting a standard cell library replacement strategy based on netlists, the invention directly utilizes the synthesized netlist to avoid the redesign process of soft core IPs. Furthermore, it efficiently completes the FPGA adaptation of standard cells and some hard core IPs through scripting and truth table conversion to synthesizable descriptions. This makes the entire ASIC to FPGA porting process standardized and repeatable, shortening the porting cycle by more than 70% compared to the traditional manual module-by-module replacement method. It also retains the complete design hierarchy, facilitating rapid and accurate bug tracking and repair on the FPGA platform, and reducing the risk of introducing new errors due to porting.

[0019] (2) In terms of verifying the authenticity of the environment, the present invention uses a real power grid signal source or a high-fidelity power grid simulator as the excitation source, which can continuously reproduce long-term signals containing various non-ideal characteristics of the actual power grid, such as high-order harmonics, random noise, voltage sag / surge, frequency drift, and three-phase imbalance. Compared with traditional laboratory signal generators or pre-recorded ideal waveform files, the verification scenario is highly consistent with the future field service environment of the chip, which makes the verification results more predictive and reference value for actual measurement performance. It can more reliably expose deep design defects related to long-term accumulated errors and complex power grid adaptability before tape-out.

[0020] (3) In terms of verifying closed-loop efficiency, this invention constructs a complete hardware-in-the-loop closed-loop system including a discrete device analog front end, a high-speed signal transmission link, an FPGA verification board, a high-precision standard energy meter, and a host computer real-time control software. It realizes the synchronous parallel acquisition and real-time error calculation of the energy data output by the FPGA prototype and the high-precision standard energy meter. Engineers can observe the error trend in real time through the host computer, dynamically issue parameter adjustment instructions or register configuration, thereby quickly verifying and optimizing algorithm parameters and functional logic, which significantly improves the defect location speed and verification iteration efficiency. Compared with the traditional post-event offline comparison or verification method that only relies on simulation, the convergence cycle can be shortened by several times.

[0021] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 A streamlined method for code porting from ASIC to FPGA platforms; Figure 2 This is an FPGA prototype verification system for smart meter chips. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0025] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0026] This invention provides an FPGA prototype verification method and system for smart meter chips, aiming to solve the problems of difficult ASIC-to-FPGA porting, insufficient verification environment realism, and low verification efficiency in existing technologies. This method and system achieve efficient porting and reliable verification by optimizing the ASIC synthesis process, IP replacement strategy, and constructing a closed-loop verification system under a real power grid environment.

[0027] The following section first describes in detail the FPGA prototype verification method for the smart meter chip provided by this invention.

[0028] like Figure 1 As shown, the method includes the following steps: Step 1: Perform ASIC front-end synthesis to generate the ASIC netlist. Specifically, during ASIC front-end synthesis, specific settings are made for the clock tree and reset tree to improve netlist portability. These include: ensuring that clock tree logic does not need optimization and clock gate generation is eliminated during synthesis; ensuring that reset tree logic does not need optimization during synthesis; and ensuring that the hierarchical structure of the synthesized ASIC netlist is consistent with the original design. These settings can be implemented through synthesis tool options, and some clock gating can also be accomplished by modifying a small amount of code. Since power consumption is not a concern during the FPGA prototyping stage, these steps improve the portability of the clock tree and reset tree and facilitate subsequent hierarchical tracing of design defects. After synthesis, equivalence verification is performed to ensure the correctness of the synthesis tool's flow.

[0029] Step 2: IP Core Replacement. Specifically, the standard cell library file in the ASIC netlist is filtered using a script to identify the standard cell devices used by the ASIC netlist, forming an engineering standard cell library file. Then, the logic relationships described in the truth table of the engineering standard cell library file are redescribed using synthesizable syntax to obtain a standard cell library file for FPGA. This step simultaneously replaces both soft-core IPs and hard-core IPs. Soft-core IPs are synthesized into a netlist during the ASIC synthesis stage and replaced by obtaining the ASIC netlist; hard-core IPs are replaced by equivalent IPs on the FPGA platform, or by redescribed their functions using a synthesizable language. In smart meter chips, soft-core IPs are mainly used for basic operations, such as addition, subtraction, multiplication, and division units and standard protocol modules. Direct replacement using the netlist avoids the step of redesigning equivalent logic. Hard-core IPs, such as phase-locked loops (PLLs) and random access memory (RAMs), have a lower proportion and can be replaced by FPGA built-in IPs or by redescribed. This IP replacement strategy avoids the inefficiency of manually modifying each IP one by one in traditional methods, ensuring functional consistency and timing compatibility.

[0030] Step 3: Perform FPGA synthesis. The ASIC netlist after IP replacement is synthesized using FPGA technology to obtain the FPGA netlist. This step benefits from the aforementioned optimizations, resulting in high code portability, a significant reduction in timing issues, and preliminary logic optimization.

[0031] Step 4: Perform FPGA implementation. Map the FPGA netlist to the physical resources of the FPGA chip through placement and routing, and further complete resource allocation and timing optimization.

[0032] Step 5: Perform FPGA programming, programming the mapped FPGA netlist to the FPGA verification board to complete the code porting.

[0033] Step 6: Build an FPGA prototype verification system. For example... Figure 2As shown, the system includes a real power grid signal source, a discrete device analog front-end module, a signal acquisition and transmission link, an FPGA verification board, a high-precision standard energy meter, and a host computer. The real power grid signal source generates a signal containing harmonics, noise, and voltage dips through a high-fidelity power grid simulator and outputs it to the discrete device analog front-end module. The discrete device analog front-end module includes a high-precision analog-to-digital converter (ADC) and a programmable gain amplifier (PGA). The PGA is located at the front end of the signal link and is used to dynamically adjust the gain of the input signal. The ADC device has specifications comparable to ASIC design and converts the power grid signal into a digital code stream. By replacing the ADC device with one of different performance characteristics, different versions of the ASIC analog front-end can be simulated. The signal acquisition and transmission link transmits the digital code stream to the FPGA verification board via a high-speed interface and shielded signal lines, ensuring that the components used for signal transmission meet the operating frequencies from the analog circuit to the FPGA verification board. The FPGA verification board carries the programmed FPGA chip and generates signals. The high-precision standard energy meter and the FPGA verification board are connected in parallel to collect data, and the error between the FPGA verification board data and the high-precision data is calculated in real time. The host computer issues commands in real time through host computer software to configure the working mode of the FPGA verification board, adjust dynamic parameters, and complete register read and write operations.

[0034] Step 7: Construct a closed-loop real-time comparison mechanism using an FPGA prototype verification system. This mechanism enables synchronous acquisition of the FPGA verification board output and the high-precision standard energy meter's data, along with real-time error analysis. The FPGA verification board parameters are dynamically adjusted based on the real-time error to verify the correctness of the algorithm and functions. Specifically, the signal generated by the real power grid signal source is converted into a digital stream by the analog front-end module of the discrete device and transmitted to the FPGA verification board. The FPGA verification board runs the programmed FPGA network meter processing data and outputs the energy metering results. Simultaneously, this output data is compared in parallel with the reference data from the high-precision standard energy meter, and the host computer software displays the error curve in real time. If the error exceeds a threshold, the engineer issues commands through the host computer to adjust the FPGA parameters, such as algorithm coefficients or register configurations, achieving dynamic debugging until the error converges. This closed-loop mechanism ensures that verification is conducted in a real power grid environment, covering long-term stability testing.

[0035] The following describes in detail the FPGA prototype verification system for the smart meter chip provided by the present invention.

[0036] like Figure 2 As shown, the system includes a real power grid signal source, a discrete device analog front-end module, a signal acquisition and transmission link, an FPGA verification board, a high-precision standard energy meter, and a host computer.

[0037] A real power grid signal source is connected to a discrete device analog front-end module to generate and output a signal containing harmonics, noise, and voltage dips. This signal source can be used with a high-fidelity power grid simulator to simulate the actual power grid environment.

[0038] The discrete device analog front-end module connects to the real power grid signal source and the signal acquisition and transmission link, including a high-precision ADC device and a PGA. The PGA is located at the front end of the signal link and is used to dynamically adjust the gain of the input signal, while the ADC device converts the power grid signal into a digital code stream. The ADC device has specifications comparable to ASIC design specifications; different versions of the ASIC analog front-end can be simulated by replacing ADC devices with different performance characteristics.

[0039] The signal acquisition and transmission link connects the analog front-end module of the discrete device and the FPGA verification board. The digital code stream is transmitted to the FPGA verification board through a high-speed interface via shielded signal lines, ensuring that the materials used for signal transmission meet the operating frequency of the analog circuit to the FPGA verification board.

[0040] The FPGA verification board connects to the signal acquisition and transmission link, a high-precision standard energy meter, and a host computer. It carries a programmed FPGA chip and generates signals. The FPGA chip is obtained through the aforementioned ASIC front-end synthesis, IP replacement, FPGA synthesis, FPGA implementation, and FPGA programming.

[0041] The high-precision standard energy meter is connected to the FPGA verification board, and the collected data is received in parallel with the FPGA verification board, and the error between the FPGA verification board data and the high-precision data is calculated in real time.

[0042] The host computer connects to the FPGA verification board and sends commands in real time through the host computer software to configure the working mode of the FPGA verification board, adjust dynamic parameters, and complete register read and write operations.

[0043] This system achieves synchronous acquisition and real-time error analysis of the FPGA verification board output and the high-precision standard energy meter output by constructing a closed-loop real-time comparison mechanism. It also dynamically adjusts the FPGA verification board parameters based on the real-time error to verify the correctness of the algorithm and functions. Specifically, the output of the real power grid signal source is processed by the discrete device's analog front-end module and then transmitted to the FPGA verification board. The FPGA verification board processes the data and outputs it. The high-precision standard energy meter synchronously acquires and calculates the error. The host computer adjusts the parameters in real time based on the error, achieving closed-loop verification.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An FPGA prototype verification method for a smart meter chip, characterized in that: Includes the following steps: Perform application-specific integrated circuit (ASIC) front-end synthesis to generate an ASIC netlist. The ASIC front-end synthesis ensures that the logic of the clock tree does not need to be optimized and the generation of clock gates is eliminated during synthesis, that the logic of the reset tree does not need to be optimized during synthesis, and that the hierarchical structure of the ASIC netlist obtained after synthesis is consistent with the original design. IP core replacement is performed. The standard cell library file in the ASIC netlist is filtered out by the script to select the standard cell devices used by the ASIC netlist, forming an engineering standard cell library file. The logic relationship described by the truth table in the engineering standard cell library file is then redescribed using synthesizable syntax to obtain a standard cell library file for FPGA. Perform FPGA synthesis: synthesize the ASIC netlist after IP replacement to obtain the FPGA netlist. FPGA implementation involves mapping the FPGA netlist to the physical resources of the FPGA chip through placement and routing. FPGA programming is performed, and the mapped FPGA netlist is programmed onto the FPGA verification board. An FPGA prototype verification system is constructed, which includes a real power grid signal source, a discrete device analog front-end module, a signal acquisition and transmission link, the FPGA verification board, a high-precision standard energy meter, and a host computer. The real power grid signal source generates a signal containing harmonics, noise, and voltage dips and outputs it to the discrete device analog front-end module. The discrete device analog front-end module includes a high-precision analog-to-digital converter (ADC) and a programmable gain amplifier (PGA). The FPGA (Programmable Array of Independent Controllers) system is located at the front end of the signal chain and is used to dynamically adjust the gain of the input signal. The ADC device converts the grid signal into a digital code stream. The signal acquisition and transmission link transmits the digital code stream to the FPGA verification board via a high-speed interface and shielded signal line. The FPGA verification board carries the programmed FPGA chip and generates signals. The high-precision standard energy meter and the FPGA verification board receive the acquired data in parallel and calculate the error between the FPGA verification board data and the high-precision data in real time. The host computer issues commands in real time through host computer software to configure the working mode of the FPGA verification board, adjust dynamic parameters, and complete register read and write operations. A closed-loop real-time comparison mechanism is built through the FPGA prototype verification system to realize the synchronous acquisition of the FPGA verification board output and the high-precision standard energy meter and the instant error analysis. The parameters of the FPGA verification board are dynamically adjusted according to the real-time error to verify the correctness of the algorithm and function.

2. The FPGA prototype verification method for a smart meter chip according to claim 1, characterized in that: The IP replacement includes the replacement of soft-core IP and hard-core IP. Soft-core IP is synthesized into a netlist during the ASIC synthesis stage and replaced by obtaining the ASIC netlist. Hard-core IP is replaced by equivalent IP on the FPGA platform or by re-describing its function using a synthesizable language.

3. The FPGA prototype verification method for a smart meter chip according to claim 1, characterized in that: The real power grid signal source generates a signal containing harmonics, noise, and voltage dips through a high-fidelity power grid simulator.

4. The FPGA prototype verification method for a smart meter chip according to claim 1, characterized in that: The ADC device of the discrete device simulation front-end module is comparable to the ASIC design specifications, and different versions of the ASIC simulation front-end can be simulated by replacing the ADC device with one of different performance.

5. The FPGA prototype verification method for a smart meter chip according to claim 1, characterized in that: The signal acquisition and transmission link ensures that the materials used for signal transmission meet the operating frequency requirements from the analog circuit to the FPGA verification board.

6. An FPGA prototype verification system for a smart meter chip, characterized in that: It includes a real power grid signal source, a discrete device analog front-end module, a signal acquisition and transmission link, an FPGA verification board, a high-precision standard energy meter, and a host computer; The real power grid signal source generates a signal containing harmonics, noise, and voltage dips, which is then output to the discrete device analog front-end module. This module includes a high-precision ADC and a PGA (Power Generation Array). The PGA is located at the front end of the signal chain and is used to dynamically adjust the gain of the input signal. The ADC converts the power grid signal into a digital stream. The signal acquisition and transmission link transmits the digital stream to the FPGA verification board via a high-speed interface and shielded signal lines. The FPGA verification board carries a programmed FPGA chip and generates signals. The FPGA chip is obtained through ASIC front-end synthesis, IP replacement, FPGA synthesis, FPGA implementation, and FPGA programming. ASIC front-end synthesis ensures that the clock tree logic does not need optimization and eliminates clock gate generation, that the reset tree logic does not need optimization, and that the hierarchical structure of the resulting ASIC netlist is consistent with the original design. IP replacement uses a script to filter the standard cell library files in the ASIC netlist to select the standard cell devices used in the ASIC netlist, forming a working... The standard cell library file is generated, and the logical relationships described in the truth table of the standard cell library file are redescribed using synthesizable syntax to obtain the standard cell library file for FPGA. FPGA synthesis is performed on the ASIC netlist after IP replacement to obtain the FPGA netlist. FPGA implementation maps the FPGA netlist to the physical resources of the FPGA chip through placement and routing. FPGA programming programs the mapped FPGA netlist to the FPGA verification board. The high-precision standard energy meter and the FPGA verification board are connected in parallel to collect data, and the error between the FPGA verification board data and the high-precision data is calculated in real time. The host computer issues instructions in real time through host computer software to configure the working mode of the FPGA verification board, adjust dynamic parameters, and complete register read and write. This FPGA prototype verification system realizes synchronous acquisition of the FPGA verification board output and the high-precision standard energy meter and instant error analysis by constructing a closed-loop real-time comparison mechanism, and dynamically adjusts the FPGA verification board parameters according to the real-time error to verify the correctness of the algorithm and function.

7. The FPGA prototype verification system for a smart meter chip according to claim 6, characterized in that: The IP replacement includes the replacement of soft-core IP and hard-core IP. Soft-core IP is synthesized into a netlist during the ASIC synthesis stage and replaced by obtaining the ASIC netlist. Hard-core IP is replaced by equivalent IP on the FPGA platform or by re-describing its function using a synthesizable language.

8. The FPGA prototype verification system for a smart meter chip according to claim 6, characterized in that: The real power grid signal source generates a signal containing harmonics, noise, and voltage dips through a high-fidelity power grid simulator.

9. The FPGA prototype verification system for a smart meter chip according to claim 6, characterized in that: The ADC device of the discrete device simulation front-end module is comparable to the ASIC design specifications, and different versions of the ASIC simulation front-end can be simulated by replacing the ADC device with one of different performance.

10. The FPGA prototype verification system for a smart meter chip according to claim 6, characterized in that: The signal acquisition and transmission link ensures that the materials used for signal transmission meet the operating frequency requirements from the analog circuit to the FPGA verification board.

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