A data transmission method and electronic device

Abstract

This invention relates to the field of computers and discloses a data transmission method and an electronic device. The data transmission method of this invention is applied to an electronic device, which includes: an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor. The method includes: the application processor sending a data transmission command to the coprocessor via the low-speed interface; the coprocessor responding to the data transmission command, reading data from the hard disk, and transferring the data read from the hard disk to the memory; wherein the application processor operates on the data on the hard disk via the hard disk interface and through the coprocessor. This method simultaneously solves the performance loss and interface compatibility issues of data transmission, and eliminates the need for customized modifications to the underlying driver of the application processor, thereby reducing the adaptation difficulty and making hardware integration more convenient.

Description

Technical Field

[0001] This invention relates to the field of computers, and in particular to a data transmission method and an electronic device. Background Technology

[0002] With the rapid development of large-scale model technology, the AI ​​computing efficiency of application processors (AP SoCs) is no longer sufficient to meet the demands of large-scale model inference. Therefore, many integrators are considering integrating coprocessors (CO-NPUs) into their products to accelerate AI applications. However, during these inference processes, weight data and key-value cache (KV Cache) data often reach gigabyte levels and are stored on hard drives. Upon power-on or wake-up, the system needs to move this data from hard drive (FLASH) to coprocessor memory (DRAM) for processing.

[0003] In relevant technical architectures, coprocessors typically connect to application processors via high-speed interfaces and can only indirectly access the hard drive. When the coprocessor needs to retrieve data from the hard drive for computation, the data must first be transferred from the hard drive to the application processor's memory, and then moved from the application processor to the coprocessor's memory. This intermediate process not only wastes processing resources but also increases system power consumption, impacting the overall performance of large model inference. Furthermore, due to limited device space and scarce interface resources, existing architectures typically do not reserve interfaces for direct interaction with external coprocessors. Therefore, related technologies rely on high-speed interfaces such as DSI or PCIe for data transmission, but these interfaces have poor cross-device compatibility and limited transmission speed, further restricting system performance. Thus, this data transmission method is difficult to efficiently support large model inference applications, adversely affecting power consumption and processing performance. Summary of the Invention

[0004] The purpose of this invention is to provide a data transmission method and an electronic device that solves the problems of data transmission performance loss and interface compatibility.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a data transmission method applied to an electronic device. The electronic device includes: an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor. The method includes: the application processor sending a data transmission command to the coprocessor via the low-speed interface; the coprocessor responding to the data transmission command by reading data from the hard disk and transferring the data read from the hard disk to the memory; wherein the application processor operates on the data in the hard disk via the hard disk interface and through the coprocessor.

[0006] Embodiments of the present invention also provide an electronic device, including: an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor; wherein the application processor is configured to send a data transfer command to the coprocessor via the low-speed interface, and the application processor is further configured to operate on data in the hard disk via the hard disk interface and through the coprocessor; the coprocessor responds to the data transfer command by reading data from the hard disk and transferring the data read from the hard disk to the memory.

[0007] In this embodiment of the invention, by directly connecting the hard drive to the coprocessor, data can be directly transferred from the hard drive to the coprocessor's memory, eliminating the reliance on the application processor as an intermediary, thereby significantly improving transmission efficiency and reducing the resource burden on the application processor. The coprocessor can thus run more independently on various application processor platforms without considering the application processor's memory capacity and bandwidth limitations. Furthermore, this solution uses a low-speed interface to transmit control commands, while data transmission is completed through a high-speed hard drive interface. This design utilizes the low-speed interface configured on the device to send control commands, reducing dependence on specific high-speed interfaces. Since most application processors are typically equipped with low-speed interfaces, even devices with limited interface resources can adapt to this solution, achieving high cross-platform compatibility. In this structure, the application processor operates on hard drive data via the hard drive interface through the coprocessor, with the coprocessor acting as a data bridge. The application processor always perceives the hard drive as a direct connection, thus eliminating the need for customized modifications to the application processor's underlying drivers, reducing adaptation difficulty and making hardware integration more convenient.

[0008] Furthermore, before the application processor sends a data transmission command to the coprocessor through the low-speed interface, the method further includes: the application processor performing security verification on the coprocessor through the low-speed interface; and after the security verification is successful, the data transmission command is then sent. This interactive security verification method ensures secure communication between the coprocessor and the application processor, provides a trusted environment for data transmission, and effectively guarantees the security of the data copying process.

[0009] Furthermore, before sending a data transfer command to the coprocessor via the low-speed interface after the security verification is passed, the method further includes: the application processor sending data copy configuration information to the coprocessor via the low-speed interface; in the step of transferring data read from the hard disk to the memory, the DMA engine built into the coprocessor transfers the data read from the hard disk to the memory based on the data copy configuration information. Based on the copy configuration information in the DMA engine built into the coprocessor, the application processor only needs to notify the coprocessor of the transfer command. After receiving the data transfer command from the application processor, the coprocessor will autonomously execute the data copying task from the hard disk to the memory, without the application processor's participation. The advantage of this is that the entire copying process is executed autonomously by the coprocessor, and the application processor only needs to issue the transfer command without participating in the actual transfer operation, thereby avoiding additional modifications to the application processor driver for command transmission, simplifying adaptation work, and further improving cross-platform compatibility. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0011] Figure 1 This is a schematic diagram of an electronic device used for data transmission in related technologies;

[0012] Figure 2 This is a schematic diagram of a device for data transmission based on a DSI interface in related technologies;

[0013] Figure 3 This is a schematic diagram illustrating the principle of data transmission based on the DSI interface in related technologies.

[0014] Figure 4 This is a schematic diagram of a device for data transmission based on a PCIe interface in related technologies;

[0015] Figure 5 This is a flowchart of a data transmission method provided in an embodiment of this application;

[0016] Figure 6 This is a schematic diagram of an electronic device that applies a data transmission method according to an embodiment of this application;

[0017] Figure 7 This is a flowchart illustrating the security verification process in a data transmission method provided in an embodiment of this application;

[0018] Figure 8This is a schematic diagram of an electronic device including the internal structure of a coprocessor, provided in an embodiment of this application. Detailed Implementation

[0019] In the relevant technical architecture, such as Figure 1 As shown, the application processor typically connects to the hard drive via a high-speed interface and to the coprocessor via another high-speed interface. The coprocessor, in turn, connects to memory via a memory interface. In this architecture, since the hard drive is only connected to the application processor, the coprocessor can only access the hard drive's data indirectly through the application processor. In big data inference applications, the weighted data and key-value cache data often reach gigabyte levels, and this data is stored on the hard drive. When the system powers on or wakes up, it needs to move the data from the hard drive to the coprocessor's memory for processing. This process requires first transferring the data from the hard drive to the application processor's memory, and then from the application processor to the coprocessor's memory. This intermediate method leads to unnecessary resource consumption, increases system power consumption, and negatively impacts the overall performance of large model inference.

[0020] Furthermore, due to space constraints and limited high-speed interface resources, existing architectures typically do not reserve interfaces for direct interfacing with coprocessors. In mobile terminal devices, application processors have limited high-speed interface resources, typically including UFS, PCIe, DRAM, and DSI (see Table 1). UFS interfaces are usually used for the system hard drive, with only one set; PCIe interfaces are mostly used to connect Wi-Fi modules, with 1-2 sets, but not all application processors support PCIe interfaces; DRAM interfaces are used for system memory, with only one set; and DSI interfaces are used to connect the display, with 1-3 sets. Existing architectures have already allocated the uses of these interfaces during design, without reserving external high-speed interfaces for coprocessors. Therefore, the lack of suitable high-speed interfaces for coprocessor interfacing is one of the main problems with existing technologies.

[0021] Table 1

[0022]

[0023] To overcome this interface limitation, some related technologies attempt to utilize DSI or PCIe interfaces for data transmission, as detailed below:

[0024] In some mobile terminal devices, the DSI interface is used for data communication between the application processor and the coprocessor (e.g., Figure 2 The DSI interface is designed for transmitting display data, supporting both Video Mode and Command Mode, and possessing bidirectional transmission capabilities. Video Mode transmits user-display data, while Command Mode can be used for writing data to a specified address (e.g., ...). Figure 3This allows for data copying from the application processor's memory to the coprocessor. Specifically, when using the DSI interface for data transfer, such as... Figure 2 As shown, the application processor first transfers data stored on the hard disk to the application processor's memory via the hard disk interface, and then sends instructions (such as...) based on the Command Mode of the DSI interface. Figure 3 The DSI interface transfers data from the application processor's memory to the coprocessor. However, this method has significant limitations when handling large data transfers. First, the DSI interface is primarily designed for transferring display data, and its bandwidth and efficiency may be insufficient for large-scale data processing. Second, the continuous processor involvement during data copying increases system resource consumption and processing time, thus impacting overall performance. Therefore, while the DSI interface performs well for small-scale data transfers, its efficiency and performance are limited in scenarios involving large data transfers.

[0025] In addition, some mobile terminal devices use the PCIe interface as the interface for interaction between the application processor and the coprocessor (e.g. Figure 4 As a widely used high-speed serial bus standard, PCIe is often used to connect high-performance devices such as graphics cards and solid-state drives (SSDs). Application processors and coprocessors connect via the PCIe interface, while hard drives are indirectly connected to the application processor and coprocessor (e.g., ...). Figure 4 When the coprocessor needs to retrieve data from the hard drive, the data is first transferred from the hard drive to the application processor's memory, and then transferred to the coprocessor's memory via the PCIe interface. This indirect data transfer method reduces transfer efficiency and increases the burden on the application processor. Furthermore, the PCIe interface also has some drawbacks during data copying. First, the use of PCIe interfaces on application processors is decreasing, and some application processors no longer provide this interface. Second, due to application limitations, PCIe interfaces typically only provide one or two lanes, with performance limited by the PCIe 4.0 standard, at a speed of approximately 16GT / s. In addition, the PCIe protocol is complex and has relatively high power consumption, making it less user-friendly for design applications. These factors make PCIe potentially less than optimal for large data transfers.

[0026] In summary, current technical architectures require the application processor as an intermediary when the coprocessor reads data from the hard drive, which not only wastes resources but also significantly increases power consumption. Furthermore, the application processor has limited high-speed interface resources and lacks a dedicated interface for interfacing with the coprocessor, making it difficult to achieve the ideal data transmission speed, low power consumption, and compatibility requirements. Therefore, current technical solutions are insufficient in supporting efficient data transmission for large model inference, negatively impacting system power consumption and performance.

[0027] To address the aforementioned technical problems, one embodiment of the present invention relates to a data transmission method applicable to electronic devices (such as mobile phones, computers, and other terminal devices, or servers). The electronic device includes: an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor. The method includes: the application processor sending a data transmission command to the coprocessor via the low-speed interface; the coprocessor responding to the data transmission command by reading data from the hard disk and transferring the data read from the hard disk to the memory; wherein the application processor operates on the data on the hard disk via the hard disk interface and the coprocessor. This embodiment of the present invention directly connects the hard disk to the coprocessor, allowing data to be directly transferred from the hard disk to the coprocessor's memory, eliminating the reliance on the application processor as an intermediary, thereby significantly improving transmission efficiency and reducing the resource burden on the application processor. Furthermore, this solution uses a low-speed interface to transmit control commands, while data transmission is completed through a high-speed hard disk interface. This design utilizes common low-speed interfaces on the device to send control commands, reducing reliance on specific high-speed interfaces. In this architecture, the application processor operates on hard drive data via the hard drive interface through a coprocessor, which acts as a data transfer bridge. The application processor always perceives the hard drive as a direct connection; therefore, data transfer does not require customized modifications to the application processor's underlying drivers, reducing adaptation difficulty and making hardware integration more convenient.

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0029] The following is a detailed description of the implementation details of a data transmission method according to an embodiment of the present invention. The following content is only for the convenience of understanding the implementation details and is not necessary for implementing this solution.

[0030] like Figure 5 As shown, this invention provides a data transmission method. This method can be applied to applications such as... Figure 6The illustrated electronic device architecture includes an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor. This electronic device architecture achieves a connection between the application processor and the coprocessor based on the hard disk interface and the low-speed interface, and enables a direct connection between the coprocessor and the hard disk by connecting the application processor to the hard disk via the hard disk interface, thereby improving data transfer efficiency.

[0031] In one possible implementation, the hard disk interface used for connecting the application processor and coprocessor, and the coprocessor and hard disk in the above-mentioned electronic device, can be a UFS interface, and the low-speed interface used for transmitting commands between the application processor and coprocessor can be an SDIO interface or an SPI interface.

[0032] Example, Figure 6 As shown, the electronic device includes an application processor, a coprocessor, and a hard disk. The coprocessor connects to the application processor via a UFS hard disk interface and an SDIO low-speed interface, while the hard disk connects directly to the coprocessor via the UFS interface. The memory connects to the coprocessor via a DRAM interface. Furthermore, the coprocessor integrates a command processing mechanism (CMD) and a data copying mechanism (Direct Memory Access, DMA). CMD receives instructions from the application processor via the SDIO interface, while DMA is responsible for transferring data from the hard disk to the memory via the UFS interface. Those skilled in the art will understand that the electronic device may also include an antenna for transmitting and receiving signals, a WiFi module connected to the application processor via a PCIe interface, and high-speed memory (LPDDR) connected to the application processor, among other common modules, which will not be elaborated upon here.

[0033] In the above, as Figure 6In the illustrated electronic device architecture, the coprocessor integrates a command processing mechanism (CMD) to receive and process instructions sent by the application processor through a low-speed interface, such as the address for data copying, data length, and startup instructions. Furthermore, the coprocessor is configured with a data copy mechanism (DMA), which automatically completes data transfer tasks from the hard drive to memory after system startup, based on the configuration. Specifically, the coprocessor provides both a hard drive interface and a low-speed interface externally to connect with the application processor; internally, it integrates the command processing mechanism (CMD) and the data copy mechanism (DMA), enabling completely autonomous data transfer. Since hard drive interfaces and low-speed interfaces are common interface types for application processors, this design enhances the coprocessor's compatibility across different application processor platforms. Through its internal command processing mechanism and DMA engine, the coprocessor can independently complete data copying; the application processor only needs to send transfer commands without participating in the actual data transfer process. Therefore, the application processor driver does not need additional adjustments to adapt to the transfer commands, simplifying the system adaptation process and further improving cross-platform compatibility.

[0034] Furthermore, since the SDIO interface is rarely used for SD or eMMC card expansion in current mobile terminal device designs and is usually relatively idle, therefore, in the above-mentioned... Figure 6 In the illustrated electronic device architecture, the SDIO interface can be used as a low-speed interface to connect to the application processor. Using it for command transmission between the application processor and the coprocessor effectively utilizes existing resources, and the SDIO speed fully meets the requirements. Of course, using the SDIO interface as a low-speed interface to connect to the application processor is just one specific example. In other examples, besides SDIO, interfaces such as SPI, IIC, and UART can be chosen as alternatives. These interfaces are also common in mobile terminal devices. For example, SPI is suitable for high-frequency, short data transmission, IIC has low power consumption characteristics, and UART is often used for debugging communication. Flexible selection of low-speed interfaces can help to transmit commands more efficiently, while improving system compatibility and resource utilization.

[0035] The data transmission method in this embodiment is as follows: Figure 5 As shown, in step 501, the application processor sends a data transfer command to the coprocessor through the low-speed interface. For example, the application processor sends the data transfer command to the coprocessor through a low-speed interface (such as SDIO or SPI). This command typically contains key information such as the data storage address, the size of the data to be transferred, and a transfer start instruction, so that the coprocessor can accurately perform data reading and moving operations. Transmitting commands through a low-speed interface helps reduce the occupation of high-bandwidth interface resources, and the low-speed interface is sufficient to meet the bandwidth requirements of command transmission, ensuring fast and stable transmission of control commands.

[0036] In step 502, the coprocessor responds to the data transfer command, reads data from the hard disk, and transfers the data read from the hard disk to the memory. For example, the coprocessor responds to a data transfer command sent by the application processor, reads a specified data block from the hard disk, and transfers it to the coprocessor's memory. The coprocessor automatically performs the data transfer operation through its built-in Data Copy Mechanism (DMA). The DMA engine completes the high-speed copy process from the hard disk to memory based on parameters in the transfer command, such as the data starting address and data size. Throughout the data transfer process, the application processor directly controls the coprocessor to access data using an interface connected to the hard disk (such as UFS) through data transfer instructions, allowing data to be transferred directly from the hard disk to the coprocessor's memory without passing through the application processor's memory. This allows the application processor to offload the data transfer burden to the coprocessor, reducing its resource consumption and processing load. After the coprocessor completes the data transfer, the data is available in its memory for subsequent computation or inference tasks. This design not only improves data transfer efficiency but also enhances the overall system performance and response speed.

[0037] It should be noted that in this embodiment, the application processor can operate on the data in the hard drive via the hard drive interface and the coprocessor. In one example, the coprocessor has a high-speed interface bridge. The application processor connects to one end of the high-speed interface bridge of the coprocessor through its own UFS interface, and the other end of the high-speed interface bridge is connected to the hard drive. The application processor sends read and write commands for data in the hard drive to the hard drive through the high-speed interface bridge built into the coprocessor. That is, the high-speed interface bridge is responsible for the read and write paths of the application processor to the hard drive, as well as the read and write paths within the coprocessor. By using the high-speed interface bridge in the coprocessor to seamlessly forward the read and write requests of the application processor to the hard drive, the coprocessor acts as a "bridge" in this process. This allows the application processor to not directly control the specific connection of the hard drive, but for the application processor, the hard drive can still be regarded as a direct connection. Therefore, the data transmission process does not require customized modification of the application processor's underlying driver, thereby reducing the adaptation difficulty and making hardware integration more convenient.

[0038] Furthermore, the operations performed by the application processor on the data on the hard drive via the hard drive interface and through the coprocessor are completely independent of steps 501 and 502. In other words, the operations performed by the application processor on the data on the hard drive via the hard drive interface can occur before, after, or simultaneously with steps 501 or 502. Since the application processor interacts with the data on the hard drive via the hard drive interface and through the coprocessor, and during the process of copying data from the hard drive to the coprocessor's memory (i.e., steps 501 and 502), the application processor sends data transfer commands to the coprocessor through a low-speed interface (such as an SDIO interface or an SPI interface). Therefore, the interaction interface between the application processor and the hard drive is independent of the interaction interface between the application processor and the coprocessor. The process by which the application processor controls the coprocessor to copy data from the hard drive to memory does not affect the process by which the application processor reads data from the hard drive.

[0039] In addition, after the system is powered on, it can check whether the high-speed interface bridge is in normal operating condition. If an abnormality is detected, an error warning will be issued to the user. If it is determined that the high-speed interface bridge is in normal operating condition, the coprocessor will be started, its ROM code will be run and internal initialization will be completed.

[0040] In one possible implementation, after the above-mentioned anomaly detection and internal initialization, before the application processor sends a data transmission command to the coprocessor through the low-speed interface, a security verification can also be performed. That is, the application processor performs security verification on the coprocessor through the low-speed interface; after the security verification is passed, the data transmission command is then sent.

[0041] In one possible implementation, the specific steps of the application processor performing security verification on the coprocessor via a low-speed interface are as follows: Figure 7 As shown, the specific steps include: Step 701, the application processor encrypts the data to be verified using a preset key and sends it to the coprocessor via a low-speed interface; Step 702, the coprocessor decrypts the data to be verified based on a pre-stored key, processes the decrypted data according to a preset algorithm to obtain verification data, encrypts the verification data, and sends it to the application processor via a low-speed interface; wherein, the key is pre-stored in the coprocessor's built-in key memory, such as a one-time programmable (OTP) memory. Step 703, after confirming that the decrypted verification data matches the expected data, the application processor confirms that the security verification is successful; if the decrypted verification data does not match the expected data, the application processor considers the coprocessor it interacted with to be untrusted and closes the hard disk interface and low-speed interface connected to the coprocessor.

[0042] For example, the keys pre-stored in the coprocessor's built-in key memory (OTP) may include at least a basic authentication key and a user authentication key. The basic authentication key is programmed into the coprocessor at the factory, and its calculation method is communicated to the equipment integrator. The user authentication key is programmed into the system by the equipment integrator during the printed circuit board assembly (PCBA) production process and is held by the equipment integrator. Therefore, the interaction process between the application processor and the coprocessor can include authentication based on the basic key and authentication based on the user key. Figure 7 The method illustrated describes an authentication process based on a base key. On top of this, device integrators can perform further user authentication. User authentication is conducted by the device integrator after taking over the coprocessor, according to a custom process and algorithm, to achieve higher security. This interactive security verification method ensures secure communication between the coprocessor and the application processor, providing a trusted environment for data transmission and effectively guaranteeing the security of the data copying process.

[0043] In addition, in one possible implementation, after the security verification is passed and before sending the data transfer command to the coprocessor through the low-speed interface, the application processor can also send data copy configuration information to the coprocessor through the low-speed interface. This configuration can be a chain structure. In the step of transferring the data read from the hard disk to the memory (i.e., in step 502), the DMA engine built into the coprocessor transfers the data read from the hard disk to the memory based on the data copy configuration information.

[0044] In one possible implementation, after the DMA engine built into the coprocessor completes the data transfer, a flag indicating that the data transfer is complete is set and queried by the application processor through the low-speed interface. Specifically, when the application processor detects that it has received an interrupt task, it queries the status flag of the DMA engine in the coprocessor through the low-speed interface; when the flag indicates that the data transfer is complete, the application processor acknowledges and terminates the copy task.

[0045] Therefore, in one example, the electronic device operates as follows:

[0046] (1) The system is powered on and the high-speed interface bridge is in normal operating condition;

[0047] (2) The coprocessor runs the ROM code and completes the internal initialization;

[0048] (3) The application processor interacts with the coprocessor through a low-speed port to perform security verification;

[0049] (4) After confirming the security of the interface, the application processor sends the data copy configuration to the DMA through the low-speed interface. The configuration is a chain structure.

[0050] (5) After the processor sends the configuration information, it sends a copy command to start DMA operation;

[0051] (6) DMA performs data copying. After the copy is completed, the internal flag is set, which can be configured to trigger an interrupt to the application processor.

[0052] (7) After receiving an interrupt or timer trigger, the application processor queries the DMA completion flag through the low-speed interface. Once the flag is found, the task is completed.

[0053] In summary, this invention, by moving the application processor's hard drive to the coprocessor side and connecting it to commonly used low-speed interfaces such as SDIO / SPI, achieves a highly compatible, fast, and independently data-copying interface solution, thus solving several major problems currently faced:

[0054] (1) The interface scheme is not compatible with various application processors. For example, the PCIe scheme cannot be used in some mobile phone solutions;

[0055] (2) The interface solution is not fast enough. For example, the DSI solution is slow due to protocol constraints, and data migration takes a long time.

[0056] (3) Interface solutions require modification of underlying code such as drivers. For example, the DSI solution requires modification of driver code to meet data transmission needs;

[0057] (4) Interface scheme affects system performance. For example, the DSI scheme requires the processor to perform tasks such as framing, which affects performance.

[0058] This invention connects the hard drive directly to the coprocessor, enabling direct data transfer from the hard drive to the coprocessor's memory. This eliminates the reliance on the application processor as an intermediary, significantly improving transmission efficiency and reducing the resource burden on the application processor. It also solves the performance loss and interface compatibility issues associated with data transmission. Furthermore, it eliminates the need for customized modifications to the application processor's underlying drivers, reducing adaptation difficulty and facilitating hardware integration. The coprocessor can thus run more independently on various application processor platforms without considering the application processor's memory capacity and bandwidth limitations. In addition, this solution uses a low-speed interface to transmit control commands, while data transmission is completed through a high-speed hard drive interface. This design utilizes common low-speed interfaces on the device to send control commands, reducing reliance on specific high-speed interfaces. Since most application processors typically have low-speed interfaces, even devices with limited interface resources can adapt to this solution, achieving high cross-platform compatibility. Simultaneously, by directly connecting the hard drive to the coprocessor, data transmission does not require customized modifications to the application processor's underlying drivers, reducing adaptation difficulty and facilitating hardware integration.

[0059] The steps described above are for clarity only. In practice, they can be combined into one step or some steps can be broken down into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0060] Furthermore, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The terms "embodiment" or "example" appearing in various locations in the specification do not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0061] Another embodiment of the present invention relates to an electronic device, such as Figure 8 As shown, the device includes an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor. The application processor sends data transfer commands to the coprocessor via the low-speed interface, and also operates on data in the hard disk via the hard disk interface and the coprocessor. The coprocessor responds to the data transfer commands by reading data from the hard disk and transferring the data read from the hard disk to the memory. Of course, this electronic device may also include an antenna for transmitting and receiving signals, a WiFi module connected to the application processor via a PCIe interface, and high-speed memory (LPDDR) connected to the application processor, among other common modules, which will not be described in detail here.

[0062] In one possible embodiment, the coprocessor includes: a key memory (such as an OTP), a DMA engine, a high-speed interface bridge, a low-speed slave interface, a DRAM controller (DCTRL), a bus, and a processor subsystem (CoreSubsys); wherein the key memory, the DMA engine, the high-speed interface bridge, the low-speed slave interface, and the DRAM controller are all connected to the processor subsystem, such as... Figure 8 As shown.

[0063] The various modules of the coprocessor include the following functions:

[0064] 1. Processor Subsystem (Core Subsys): This includes the processor and its associated ROM / RAM, and is responsible for coprocessor initialization and interaction with the application processor;

[0065] 2. Key Memory (OTP): Stores encrypted data exchanged with the application processor, ensuring the security of the communication path;

[0066] 3. DMA Engine: Responsible for copying data from Flash memory to DRAM according to the configuration;

[0067] 4. High-speed interface bridge: Responsible for the application processor's read and write path to Flash, as well as the read path within the coprocessor;

[0068] 5. Low-speed slave interface: Responsible for communication via the low-to-medium speed communication port; the relevant communication protocol can be customized.

[0069] 6. DRAM Controller (DCTRL): Responsible for the read and write paths of DRAM.

[0070] In one possible embodiment, the hard disk interface includes a UFS interface; the low-speed interface includes an SDIO interface or an SPI interface.

[0071] The electronic device in this embodiment can be applied as follows: Figure 8 The data transmission method shown has been described in detail in the above embodiments and will not be repeated here.

[0072] This invention directly connects the hard drive to the coprocessor, enabling direct data transfer from the hard drive to the coprocessor's memory. This eliminates the reliance on the application processor as an intermediary, significantly improving transmission efficiency and reducing the resource burden on the application processor. Furthermore, this solution uses a low-speed interface to transmit control commands, while data transmission is completed through a high-speed hard drive interface. This design utilizes common low-speed interfaces on the device to send control commands, reducing dependence on specific high-speed interfaces. In this structure, the application processor operates on hard drive data via the hard drive interface through the coprocessor, with the coprocessor acting as a data bridge. The application processor always perceives the hard drive as a direct connection; therefore, data transmission does not require customized modifications to the application processor's underlying drivers, reducing adaptation difficulty and facilitating hardware integration.

[0073] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A data transmission method, characterized in that, The method is applied to an electronic device, the electronic device comprising: an application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor; the method includes: The application processor sends a data transmission command to the coprocessor through the low-speed interface; The coprocessor responds to the data transfer command, reads data from the hard disk, and transfers the data read from the hard disk to the memory; The application processor operates on the data in the hard disk through the hard disk interface and via the coprocessor.

2. The data transmission method according to claim 1, characterized in that, The hard disk interface includes a UFS interface; the low-speed interface includes an SDIO interface or an SPI interface.

3. The data transmission method according to claim 1, characterized in that, Before the application processor sends a data transfer command to the coprocessor via the low-speed interface, the method further includes: The application processor performs security verification on the coprocessor through the low-speed interface; After the security verification is passed, the data transmission command is sent.

4. The data transmission method according to claim 3, characterized in that, The application processor performs security verification on the coprocessor through the low-speed interface, including: The application processor encrypts the data to be verified using a preset key and then sends it to the coprocessor through the low-speed interface. After the coprocessor decrypts the data to be verified based on the pre-stored key, it operates on the decrypted data according to a preset algorithm to obtain verification data, and then encrypts the verification data and sends it to the application processor through the low-speed interface; wherein, the key is pre-stored in the built-in key memory; The application processor confirms that the security verification is successful after verifying that the decrypted verification data matches the expected data; if the decrypted verification data does not match the expected data, the hard disk interface and the low-speed interface are shut down.

5. The data transmission method according to claim 3, characterized in that, After the security verification is passed, but before sending a data transmission command to the coprocessor via the low-speed interface, the method further includes: The application processor sends data copy configuration information to the coprocessor through the low-speed interface; In the step of transferring data read from the hard disk to the memory, the DMA engine built into the coprocessor transfers the data read from the hard disk to the memory based on the data copy configuration information.

6. The data transmission method according to claim 5, characterized in that, The method further includes: After the DMA engine built into the coprocessor completes the data transfer, a flag is set to indicate that the data transfer is complete, which the application processor can then query through the low-speed interface.

7. The data transmission method according to any one of claims 1 to 6, characterized in that, The application processor operates on the data in the hard disk via the hard disk interface and the coprocessor, including: The application processor sends read and write commands for data on the hard disk to the hard disk via the hard disk interface and a high-speed interface bridge built into the coprocessor.

8. An electronic device, characterized in that, include: An application processor, a coprocessor connected to the application processor via a hard disk interface and a low-speed interface, memory connected to the coprocessor, and a hard disk connected to the coprocessor; The application processor is configured to send data transmission commands to the coprocessor via the low-speed interface, and the application processor is also configured to operate on data in the hard disk via the hard disk interface and the coprocessor. The coprocessor responds to the data transfer command, reads data from the hard disk, and transfers the data read from the hard disk to the memory.

9. The electronic device according to claim 8, characterized in that, The coprocessor includes: a key memory, a DMA engine, a high-speed interface bridge, a low-speed slave interface, a DRAM controller, a bus, and a processor subsystem; The key memory, the DMA engine, the high-speed interface bridge, the low-speed slave interface, and the DRAM controller are all connected to the processor subsystem.

10. The electronic device according to claim 8 or 9, characterized in that, The hard disk interface includes a UFS interface; the low-speed interface includes an SDIO interface or an SPI interface.

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