A position recognition system for an array server hardware board

Abstract

The present invention provides a position recognition system for the hardware boards of an array server, which includes a plurality of blade interfaces, a plurality of blade nodes, and a plurality of array cards. One blade node is connected to one blade interface, and at least one array card is provided on one blade node; a plurality of backplane IO pins are provided on the blade interface, and the array card includes an IO level detection chip. At least one of the backplane IO pins is floating, and the other backplane IO pins are grounded; a plurality of card IO pins are provided on the array card, and the card IO pins include a backplane connection area and a board connection area. The backplane connection area is connected to the backplane IO pins, and at least one of the card IO pins in the board connection area is pulled up to the power supply, and the others are grounded. The card IO pins pulled up to the power supply in the board connection area of each array card are different. By setting the IO interface, a hardware connection method is realized to obtain the specific numbers of each blade node and array card in the array server, so as to obtain the detailed physical positions.

Description

Technical Field

[0001] The present invention relates to the field of hardware management of array servers, and particularly to a position recognition system for hardware boards of an array server. Background Art

[0002] With the development of the cloud mobile phone and cloud game industries, array servers have come into the view of major hardware device manufacturers and game manufacturers. A significant difference between array servers and traditional general-purpose servers is that the number of hardware boards to be managed increases exponentially, posing challenges to hardware management and operation and maintenance. There are only a few boards inside a general-purpose server. Even for blade servers, the number of boards does not exceed 10. Hardware information management is relatively simple and easy. However, the number of hardware boards inside a 2U chassis of an array server can easily reach seventy or eighty, and most of these boards have the same hardware attributes, presenting new challenges to hardware information management.

[0003] Taking a traditional general server as an example, since the functions of each hardware board are different (motherboard, HBA card, network card, hard disk backplane, etc.), there is no need to identify and distinguish the positions of the boards. Even for a four-star blade server, because the number of boards of the same type is small, physical position recognition of hardware boards can be omitted. Even if it is implemented, it can be achieved through simple 2 GPIO signals. However, if physical position recognition of hardware boards is not performed on an array server, it is very inconvenient for hardware operation and maintenance because when remotely logging in to a certain board, it is difficult to determine the specific position of this board in the chassis, and it will also increase the development difficulty of the operation and maintenance software system. Summary of the Invention

[0004] In order to overcome the problem of the lack of physical position recognition function for hardware boards in existing array servers, the present invention provides a position recognition system for hardware boards of an array server.

[0005] The present invention provides a position recognition system for hardware boards of an array server, which includes a plurality of blade interfaces, a plurality of blade nodes and a plurality of array cards. One blade node is connected to one blade interface, and at least one array card is provided on one blade node; a plurality of backplane IO pins are provided on the blade interface, and the plurality of backplane IO pins are arranged in sequence, and the backplane IO pins are connected to the blade nodes; the array card includes an IO level detection chip, and the IO level detection chip is connected to the backplane IO pins, at least one of the backplane IO pins is floating, and the other backplane IO pins are grounded; the plurality of blade interfaces are arranged in sequence, and the floating backplane IO pins in each blade interface are different; a plurality of card IO pins are provided on the array card, and the card IO pins include a backplane connection area and a board card connection area, the backplane connection area is connected to the backplane IO pins, and at least one of the card IO pins in the board card connection area is pulled up to the power supply, and the others are grounded; the card IO pins pulled up to the power supply in the board card connection area of each array card are different.

[0006] Preferably, the array card further includes an array card processor, and the array card processor is connected to the IO level detection chip through a bus.

[0007] Preferably, among the plurality of blade interfaces arranged in sequence, different backplane IO pins are sequentially floated in order among the plurality of backplane IO pins.

[0008] Preferably, among the plurality of array cards, different pins are sequentially pulled up to the power supply in order among the plurality of card IO pins.

[0009] Preferably, the backplane IO pins are set to be grounded or pulled up to the power supply, and the blade nodes are set to be pulled up to the power supply or grounded.

[0010] Compared with the prior art, the position recognition system for hardware boards of an array server provided by the present invention has the following advantages:

[0011] 1. By setting the IO interface, a hardware connection method is realized to obtain the specific numbers of each blade node and array card in the array server, so as to obtain the detailed physical positions. That is, the hardware solution is more stable and reliable than the software solution, and even if the array card is replaced, it will not affect the position information. At the same time, during operation and maintenance, when logging in to a certain array card, its position in the server chassis can be obtained as long as a simple command is used, which is convenient for troubleshooting. Further, in the design of the upper-layer server management software, the relationship between the obtained physical position information and the array card can be corresponded, which can simplify the software implementation solution.

[0012] 2. The IO level detection chip of the array card can be directly placed on the blade node backplane and communicate with the processor of the array card only through the 2-wire I2C bus, which greatly saves the IO resources of the processor and the physical pin resources of the array card connector. At the same time, the array cards are not directly interconnected through the IO bus, so even if a certain array card is damaged, it will have no impact on other array cards. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 FIG. 1 is a schematic structural diagram of a position recognition system for a hardware board of an array server provided by the first embodiment of the present invention.

[0014] DESCRIPTION OF REFERENCE NUMERALS:

[0015] 1. Blade interface; 2. Blade node;

[0016] 31. IO level detection chip; 32. Array card processor;

[0017] 100. Backplane connection area; 200. Board card connection area. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] Please refer to Figure 1 , the first embodiment of the present invention provides a position recognition system for a hardware board of an array server, including a plurality of blade interfaces 1, a plurality of blade nodes 2 and a plurality of array cards. One of the blade nodes 2 is connected to one of the blade interfaces 1, and at least one array card is provided on one of the blade nodes 2.

[0020] It can be understood that the blade interface 1 is provided on the backplane. A plurality of blade interfaces 1 are provided on one backplane, and each blade interface 1 is connected to one blade node 2. A plurality of array cards can be provided on one blade node 2.

[0021] A plurality of backplane IO pins are provided on the blade interface 1, and the plurality of backplane IO pins are arranged in sequence, and the backplane IO pins are connected to the blade node 2. For example, in the present embodiment, taking an array server of X*Y specification as an example, as Figure 1 shown in FIG. 1, three blade interfaces 1 are provided on the backplane, and N backplane IO pins SLOT_IO 1-1, SLOT_IO 1-2... SLOT_IO 1-N are provided in each blade interface 1. The value of N depends on the number of blades that the backplane needs to support. For example, if there are four IO, the maximum number of supported blades is 16 (2 N =X).

[0022] The array card includes an IO level detection chip 31, which is connected to the backplane IO pins. At least one of the backplane IO pins is floating, and the other backplane IO pins are grounded. A plurality of the blade interfaces 1 are arranged in sequence, and the floating backplane IO pins in each blade interface 1 are different. Specifically, in this embodiment, among the plurality of blade interfaces 1 arranged in sequence, different backplane IO pins are sequentially floated among the plurality of backplane IO pins. As Figure 1 shown in the figure, 0 backplane IO pins are set to float on the first blade interface 1, the first backplane IO pin is set to float on the second blade interface 1, the second backplane IO pin is set to float on the third blade interface 1, and so on. Of course, in other embodiments, it can also be set that the first backplane IO pin is set to float on the first blade interface 1, the second backplane IO pin is set to float on the second blade interface 1, and so on. Or in other embodiments, floating processing with different rules can also be set according to needs, which will not be elaborated here.

[0023] It can be understood that when determining the position of the blade node 2, the IO level detection chip of each array card can collect the slot number of its own blade node 2 on the backplane through the IO level states of N slot numbers, that is, obtain the specific position information.

[0024] Please continue to refer to Figure 1 , a plurality of card IO pins are provided on the array card. The card IO pins include a backplane connection area 100 and a board card connection area 200. The backplane connection area 100 is connected to the backplane IO pins. At least one of the card IO pins in the board card connection area 200 is pulled up to the power supply, and the others are grounded. And the card IO pins pulled up to the power supply in each board card connection area 200 of each array card are different. Specifically, as Figure 1 shown in the figure, the first array card 1-1 includes M IO pins, specifically pins IO_N+1, IO_N+2, IO_N+3... IO_N+M. The value of M depends on the number of array cards supported by the blade node. For example, 3 IO can support up to 8 array cards (2 M =Y). Among them, 0 pins of the first array card 1-1 are pulled up to the power supply, the first pin IO_N+1 of the second array card 1-1 is pulled up to the power supply, the second pin IO_N+2 of the third array card 1-1 is pulled up to the power supply, and so on. Of course, in other embodiments, the selection of the pins pulled up to the power supply can be adjusted according to needs, as long as there is a regular adjustment. For example, it can be set to be selected in sequence as Figure 1 shown in the figure, or it can be set to be selected in reverse order.

[0025] It can be understood that when determining the position of the array card, the IO level detection chip of each array card can collect its own position information on the blade node 2 through the level states of the M position number IOs.

[0026] Please continue to refer to Figure 1 , the array card further includes an array card processor 32, and the array card processor 32 is connected to the IO level detection chip 31 through a bus. That is, inside each array card, the array card processor 32 is connected to the IO level detection chip 31 through an I2C bus.

[0027] It can be understood that each array card processor 32 communicates with its IO level detection chip 31 through the I2C bus. The IO level detection chip 31 can be designed on the bottom board of the blade node 2, and the array card is installed on the bottom board of the blade node 2 through an interface connector (such as Mini-PCIe, etc.). The IO level detection chip 31 can simultaneously collect the blade slot number information where it is located and its position number information on this blade through the N+M IO results in the above-mentioned blade node 2 and array card, so that the physical position of each array card in the server can be uniquely determined.

[0028] Optionally, as an embodiment, multiple backplane IO pins in the blade interface 1 on the backplane can be pulled up to the power supply VCC, and the IO interfaces on the blade node 2 are set to be grounded. At the same time, the position number IO state on the IO level detection chip 31 can also be implemented with reverse level logic. That is, swapping with the Figure 1 shown in the figure can achieve the purpose of flexible identification of the physical position of the hardware board.

[0029] It can be understood that in this embodiment, as Figure 1 shown in the figure, one end of multiple backplane IO pins in the blade interface 1 is grounded, and the other end is pulled up to the power supply VCC through a pull-up resistor at the IO end of the blade node. The card IO pins in the card connection area of the array card are pulled up to the ground GNC through a pull-up resistor, and one of the card IO pins is pulled up to the voltage VCC through a pull-up resistor.

[0030] It can be understood that in this embodiment, the number of blade nodes 2 is determined according to the number of blade interfaces 1 on the backplane. The blade nodes 2 are numbered according to the suspension order of the backplane IO interfaces. Each array card in each blade node 2 is numbered according to the order of the pull-up power supplies in the card IO pins of the card connection area. As Figure 1 shown in the figure, in an array server with an X*Y specification, the blade node 2 located in the first blade interface 1 is numbered as blade slot 1, and the first array card in blade slot 1 is numbered as array card 1-1, the second is numbered as 1-2, and so on.

[0031] Compared with the prior art, a position recognition system for an array server hardware board provided by the present invention has the following advantages:

[0032] 1. By setting up the IO interface, a hardware connection method is implemented to obtain the specific numbers of each blade node and the array card in the array server, so as to obtain the detailed physical positions. That is, the hardware solution is more stable and reliable than the software solution, and even if the array card is replaced, it will not affect the position information. At the same time, during operation and maintenance, when logging in to a certain array card, the position of the array card in the server chassis can be obtained as long as a simple command is used, which is convenient for troubleshooting. Further, in the design of the upper-layer server management software, the relationship between the obtained physical position information and the array card can be corresponded, which can simplify the software implementation solution.

[0033] 2. The IO level detection chip of the array card can be directly placed on the blade node backplane and communicate with the processor of the array card only through the 2-wire I2C bus, which greatly saves the IO resources of the processor and the physical pin resources of the array card connector. At the same time, the array cards are not directly interconnected through the IO bus, so even if a certain array card is damaged, it will have no impact on other array cards.

[0034] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A position recognition system for an array server hardware board, characterized in that: It includes multiple blade interfaces, multiple blade nodes, and multiple array cards. One of the blade nodes is connected to a blade interface, and at least one array card is provided on one blade node. Multiple backplane IO pins are provided on the blade interface. The multiple backplane IO pins are arranged in sequence, and the backplane IO pins are connected to the blade nodes. The array card includes an IO level detection chip. The IO level detection chip is connected to the backplane IO pins. At least one of the backplane IO pins is floating, and the other backplane IO pins are grounded. The multiple blade interfaces are arranged in sequence, and the floating backplane IO pins in each blade interface are different. Multiple card IO pins are provided on the array card. The card IO pins include a backplane connection area and a board card connection area. The backplane connection area is connected to the backplane IO pins. At least one of the card IO pins in the board card connection area is pulled up to the power supply, and the others are grounded. The card IO pins pulled up to the power supply in the board card connection area of each array card are different.

2. The position recognition system of the array server hardware board as described in claim 1, wherein: The array card further includes an array card processor. The array card processor is connected to the IO level detection chip through a bus.

3. The position recognition system of the array server hardware board as described in claim 1, characterized in that: Among the multiple blade interfaces arranged in sequence, different backplane IO pins are sequentially floated in order among the multiple backplane IO pins.

4. The position recognition system for the array server hardware board as described in claim 1, characterized in that: Among the multiple array cards, different pins are sequentially pulled up to the power supply in order among the multiple card IO pins.

5. The position recognition system for the array server hardware board as described in claim 1, characterized in that: The backplane IO pins are set to be grounded or pulled up to the power supply, and the blade nodes are set to be pulled up to the power supply or grounded.

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