A control method and apparatus

Abstract

The embodiment of the application discloses a control method, comprising: monitoring the load of a processor core set of an electronic device, the processor core set comprising at least one processor core; and adjusting the configuration information of the processor core set based on at least the load; wherein the processing capacity of different processor core sets is the same or different. The embodiment of the application also discloses a control device.

Description

TECHNICAL FIELD

[0001] The present application relates to the control technology in the computer field, and particularly relates to a control method and device. BACKGROUND

[0002] Intel Speed Select Technology (SST) is a central processing unit (CPU) power management technology proposed by Intel. The SST technology provides multiple methods for configuring the CPU frequency range and performance distribution. Among them, one power management technology divides the CPU into two priority groups with different computing capabilities, which facilitates users to divide the application programs according to the service level and run them on the CPU of the corresponding group. However, because the CPU grouping is static, in the case that the CPU load of the high priority group is not full, the performance of the CPU of the low priority group may be limited, thereby causing the problem of performance waste. SUMMARY

[0003] The technical solution of the present application is implemented as follows:

[0004] A control method comprises:

[0005] monitoring the load of a processor core set of an electronic device, the processor core set comprising at least one processor core;

[0006] adjusting the configuration information of the processor core set based at least on the load;

[0007] wherein the processing capabilities of different processor core sets are the same or different.

[0008] In the above solution, adjusting the configuration information of the processor core set based on the load comprises:

[0009] determining a target processor core in each processor core set based at least on the load of each processor core in the processor core set, and adjusting the target processor core from the processor core set where it is currently located to another processor core set; and / or,

[0010] determining a target frequency range of the target processor core set based at least on the load of each processor core in the processor core set, and adjusting the frequency range of the processor core set to the target frequency range.

[0011] In the above solution, determining a target processor core in each processor core set based at least on the load of each processor core in the processor core set comprises:

[0012] obtaining source information of each processor core, the source information representing a processor core set information to which the processor core belongs before last processor core set adjustment;

[0013] determining a target processor core in each processor core set based on the source information and the load.

[0014] In the above solution, adjusting the configuration information of the processor core set based on the load comprises at least one of:

[0015] if a first processor core in a first processor core set comes from a second processor core set and its load is greater than or equal to a first threshold, determining the first processor core as a first target processor core;

[0016] adjusting the first processor core to the second processor core set, or,

[0017] adjusting the first processor core to the second processor core set and adjusting a second target processor core in the second processor core set to the first processor core set; or,

[0018] adjusting the first processor core to the second processor core set and adjusting a third target processor core in a third processor core set to the first processor core set.

[0019] In the above solution, adjusting the configuration information of the processor core set based on the load comprises at least one of:

[0020] if a second processor core in a second processor core set has a load less than or equal to a second threshold and a duration greater than or equal to a first time length, determining the second processor core as a second target processor core, adjusting the second processor core to a first processor core set, or adjusting the second processor core to the first processor core set and adjusting a first target processor core in the first processor core set to the second processor core set;

[0021] if a third processor core in the second processor core set comes from the first processor core set and has a load less than or equal to a third threshold and a duration greater than or equal to a second time length, determining the third processor core as the second target processor core, adjusting the third processor core to the first processor core set, or adjusting the third processor core to the first processor core set and adjusting the first target processor core in the first processor core set to the second processor core set;

[0022] If the load of a fourth processor core in the first set of processor cores is greater than a fourth threshold value and the duration is greater than or equal to a third time length, the fourth processor core is determined as a first target processor core, the fourth processor core is adjusted to the second set of processor cores, or the fourth processor core is adjusted to the second set of processor cores and a second target processor core in the second set of processor cores is adjusted to the first set of processor cores.

[0023] In the above solution, the method further includes:

[0024] Determining the number of processor cores in the first set of processor cores and the second set of processor cores;

[0025] Based on the number of processor cores, the first target processor core is adjusted to the second set of processor cores, or the first target processor core is adjusted to the second set of processor cores and a second target processor core in the second set of processor cores is adjusted to the first set of processor cores; or,

[0026] Based on the number of processor cores, the second target processor core is adjusted to the first set of processor cores, or the second target processor core is adjusted to the first set of processor cores and a first target processor core in the first set of processor cores is adjusted to the second set of processor cores.

[0027] In the above solution, the at least adjusting the configuration information of the set of processor cores based on the load includes at least one of:

[0028] Adjusting the configuration information of the set of processor cores based on the change information of the load;

[0029] Obtaining power information of the electronic device, and adjusting the configuration information of the set of processor cores based on the power information and the load;

[0030] Obtaining a configuration instruction acting on the electronic device, and adjusting the configuration information of the set of processor cores based on the configuration instruction and the load;

[0031] Obtaining task change information of the electronic device, and adjusting the configuration information of the set of processor cores based on the task change information and the load.

[0032] In the above solution, adjusting the configuration information of the set of processor cores based on the change information of the load includes:

[0033] If the load of a fifth processor core in the first set of processor cores increases from a fifth threshold value to a sixth threshold value, the fifth processor core is adjusted to the second set of processor cores and / or the frequency range of the first set of processor cores is increased; or,

[0034] If the load on the sixth processor core in the second processor core set decreases from the seventh threshold to the eighth threshold, the sixth processor core is adjusted to the frequency range of the first processor core set and / or the frequency range of the second processor core set is reduced.

[0035] In the above scheme, adjusting the configuration information of the processor core set based on the power information and the load includes:

[0036] Obtain power supply information and / or power receiving information of the electronic device, and adjust at least one of the target processor core location, number of processor cores, or frequency range of the processor core set based on at least one of the power supply information, power receiving information, and the load.

[0037] A control device, comprising:

[0038] A monitoring module is used to monitor the load of a processor core set in an electronic device, the processor core set including at least one processor core;

[0039] A processing module, configured to adjust the configuration information of the processor core set based at least on the load;

[0040] Different processor core sets may have the same or different processing capabilities.

[0041] An electronic device, comprising: a processor, a memory, and a communication bus;

[0042] The communication bus is used to realize the communication connection between the processor and the memory;

[0043] The processor is used to execute the control program in the memory to implement the steps of the above control method.

[0044] A computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps of the control method described above.

[0045] The control method and apparatus provided in the embodiments of this application can monitor the load of the processor core set of an electronic device and adjust the configuration information of the processor core set based at least on the load. Different processor core sets may have the same or different processing capabilities. In this way, the configuration information of the processor core set can be dynamically adjusted according to the load of the processor cores in the processor core set. The grouping of processor cores is not always constant. This solves the problem in the power management technology of related technologies that when the CPU load of the high-priority group is not full, the CPU performance of the low-priority group is limited, thus ensuring the performance of the CPU. Attached Figure Description

[0046] Figure 1 A flowchart of a control method provided for an embodiment of the present application is shown in FIG. 1;

[0047] Figure 2 A flowchart of another control method provided for an embodiment of the present application is shown in FIG. 2;

[0048] Figure 3 A flowchart of still another control method provided for an embodiment of the present application is shown in FIG. 3;

[0049] Figure 4 A flowchart of a control method provided for another embodiment of the present application is shown in FIG. 4;

[0050] Figure 5 A flowchart of another control method provided for another embodiment of the present application is shown in FIG. 5;

[0051] Figure 6 A flowchart of still another control method provided for another embodiment of the present application is shown in FIG. 6;

[0052] Figure 7 A structural diagram of a control device provided for an embodiment of the present application is shown in FIG. 7;

[0053] Figure 8 A structural diagram of an electronic device provided for an embodiment of the present application is shown in FIG. 8. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0055] An embodiment of the present application provides a control method, which is applied to an electronic device, as shown in FIG. 1, and the method comprises the following steps: Figure 1

[0056] Step 101: Monitor the load of a processor core set of the electronic device.

[0057] The processor core set comprises at least one processor core.

[0058] ​In the embodiments of the present application, the processor core can refer to a CPU core, a Graphics Processing Unit (GPU) core, or even a Data Processing Unit (DPU) core, a Video Processing Unit (VPU) core, and the like, that is, the processor core set can refer to a CPU core set, a GPU core set, or a CPU core and GPU core set; it should be noted that the processor core set can refer to a set of multiple CPU cores in a CPU in the electronic device, or can refer to a set formed by grouping multiple CPUs in the electronic device. In addition, the types of processor cores in different processor core sets are different.

[0059] Step 102, adjusting configuration information of the processor core set based at least on the load.

[0060] In which the processing capabilities of different processor core sets are the same or different.

[0061] In the embodiments of the present application, in addition to considering the load of the processor core set when adjusting the configuration information of the processor core set, the specific needs of the user (that is, user intervention), the power supply parameters of the electronic device, and the requirements of the corresponding task (for example, the task requires high efficiency) can also be combined. In a feasible implementation manner, the configuration information can include the frequency, type and number of the processor core set and the like.

[0062] It should be noted that when the configuration information mainly includes the number, type and frequency, the processing capability of the processor core set can be the same in different processor core sets due to the three factors of number, type and frequency. Of course, the processing capabilities of different processor core sets can also be different.

[0063] The control method provided by the embodiments of the present application can monitor the load of the processor core set of the electronic device, adjust the configuration information of the processor core set based at least on the load, and the processing capabilities of different processor core sets are the same or different. In this way, the configuration information of the processor core set can be dynamically adjusted according to the load of the processor core in the processor core set, and the grouping of the processor core is not always the same. The problem that the performance of the CPU (and / or GPU) in the low-priority group is limited when the load of the CPU (and / or GPU) in the high-priority group is not full in the power management technology in the related art is solved, and the performance of the CPU is guaranteed.

[0064] Based on the foregoing embodiments, the embodiments of the present application provide a control method, referring to FIG. 10, the method comprises the following steps: Figure 2

[0065] ​Step 201, the electronic device monitors the load of the processor core set of the electronic device.

[0066] The processor core set includes at least one processor core.

[0067] It should be noted that after step 201, step 202 or step 203 can be executed, or steps 202-203 can be executed (which is shown in the embodiment of the present application). Figure 2

[0068] Step 202, the electronic device determines a target processor core in each processor core set based on the load of each processor core in the processor core set, and adjusts the target processor core from the current processor core set to another processor core set.

[0069] The processing capabilities of different processor core sets are the same or different.

[0070] In the embodiment of the present application, the target processor core can be determined from each processor core set according to the load of each processor core, and the load meets the target load condition; in a feasible implementation manner, the target load condition can refer to the maximum load or the minimum load; that is, the target processor core can be the processor core with the maximum load or the minimum load in each processor core set.

[0071] It should be noted that in the process of adjusting the target processor core from the current processor core set to another processor core set, the two different processor core sets in which the processor core exchange occurs can be paired to exchange the processor cores; of course, they can also not be paired to exchange the processor cores. That is, when a target processor core in the processor core set A1 is adjusted to the processor core set A2, a target processor core in the processor core set A2 is also adjusted to the processor core set A1; of course, only a target processor core in the processor core set A1 can be adjusted to the processor core set A2, but a corresponding target processor core in the processor core set A2 is not adjusted to the processor core set A1.

[0072] In step 202, "determining a target processor core in each processor core set based on the load of each processor core in the processor core set", can be implemented in the following manner:

[0073] Step 202a, the electronic device obtains the source information of each processor core.

[0074] ​The source information represents a processor core set to which the processor core belongs before the last processor core set adjustment.

[0075] In the embodiments of the present application, the source information of each processor core can include frequency information of the processor core set to which the processor core belongs before the last processor core set adjustment.

[0076] In step 202b, the electronic device determines a target processor core in each processor core set based on the source information and the load.

[0077] In the embodiments of the present application, when determining the target processor core, the processor core before the target processor core and the load of the target processor core can be combined to select the target processor core from each processor core set. That is, the frequency before the target processor core satisfies a certain condition, and the load of the target processor core also satisfies a certain condition.

[0078] In step 203, the electronic device determines a target frequency range of the target processor core set based on at least the load of each processor core in the processor core set, and adjusts the frequency range of the processor core set to the target frequency range.

[0079] In the embodiments of the present application, the frequency range of the processor core set can be adjusted only according to the load of each processor core in the processor core set. In a feasible implementation manner, the average load of the processor core set can be calculated based on the load of each processor core. If the average load is greater than a preset load threshold, it is considered that the load of the processor core set is too large at this time, and in order to ensure the processing efficiency of data, the frequency of the processor core set can be increased, that is, the target frequency range is greater than the current frequency of the processor core set. If the average load is less than a preset load threshold, it is considered that the load of the processor core set is too low at this time, and in order to avoid waste of resources, the frequency of the processor core set can be reduced, that is, the target frequency range is less than the current frequency of the processor core set.

[0080] Of course, the frequency range of the processor core set can also be adjusted jointly according to the load of each processor core in the processor core set and the number of processor cores included in the processor core set; if the number of processor cores with a load greater than a preset load threshold in the processor core set is large, the frequency of the processor core set needs to be increased at this time, that is, the target frequency range is determined to be greater than the current frequency of the processor core set, to ensure processing efficiency. If the number of processor cores with a load less than a preset load threshold in the processor core set is large, the frequency of the processor core set needs to be reduced at this time, that is, the target frequency range is determined to be less than the current frequency of the processor core set, to ensure effective use of resources. It should be noted that the explanation of the same or related steps in the present embodiment as in other embodiments can refer to the explanation in other embodiments, and will not be repeated here.

[0081] The control method provided by the embodiments of the present application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set. The grouping of the processor cores is not always the same, which solves the problem in the related art that the performance of the CPU in the low-priority group is limited when the load of the CPU in the high-priority group is not full, and guarantees the performance of the CPU.

[0082] Based on the foregoing embodiments, the embodiments of the present application provide a control method, which, with reference to Figure 3 the method includes the following steps:

[0083] Step 301: The electronic device monitors the load of the processor core set of the electronic device.

[0084] The processor core set includes at least one processor core.

[0085] Step 302: If the first processor core in the first processor core set is from the second processor core set and its load is greater than or equal to the first threshold, the electronic device determines the first processor core as the first target processor core.

[0086] The processing capacity of the first processor core set and the second processor core set is the same or different.

[0087] In the embodiments of the present application, the first processor core set can include processor cores with lower frequencies, and correspond to processor cores of a low priority group; the second processor core set can include processor cores with higher frequencies, and correspond to processor cores of a high priority group. The first processor core in the first processor core set is transferred from the second processor core set, which indicates that the priority of the first processor core before the transfer is high, and the current priority is low, and the current load of the first processor core is greater than or equal to a first threshold, at which time the frequency of the first processor core needs to be re-adjusted. It should be noted that the first threshold can be a load threshold set in advance according to historical data. In a feasible implementation manner, the first threshold can be 10%, for example, as shown in FIG. 3. If the first processor core originally (before the frequency adjustment) belongs to the high priority group and currently belongs to the low priority group, when the load is greater than or equal to 10%, any one of steps 303-305 can be performed. Figure 4 Figure 4 The step 304 is shown by performing the step 304.

[0088] After the step 302, any one of steps 303-305 can be performed.

[0089] The step 303 is to transfer the first processor core to the second processor core set.

[0090] In the embodiments of the present application, the first processor core can be transferred to the second processor core set with a frequency greater than that of the first processor core set, without the need to correspondingly transfer the second target processor core in the second processor core set to the first processor core set.

[0091] The step 304 is to transfer the first processor core to the second processor core set, and transfer the second target processor core in the second processor core set to the first processor core set.

[0092] In the embodiments of the present application, the first processor core is transferred to the second processor core set B2 with a frequency greater than that of the first processor core set B1, and the second target processor core in the second processor core set B2 is transferred to the first processor core set B1 with a lower frequency. It should be noted that the second target processor core can be the processor core with the smallest load in the second processor core set.

[0093] The step 305 is to transfer the first processor core to the second processor core set, and transfer the third target processor core in the third processor core set to the first processor core set.

[0094] ​The processing capabilities of the first processor core set, the second processor core set and the third processor core set are the same or different.

[0095] In the embodiment of the application, the first processor core is adjusted to the second processor core set with a frequency greater than that of the first processor core set. In this way, there is a vacancy for adjusting a processor core in the first processor core set, and a third target processor core in another third processor core set can be adjusted to the first processor core set. It should be noted that the frequency of the third processor core set can be greater than or less than the frequency of the first processor core set.

[0096] It should be noted that in the embodiment, the first processor core is initially high priority and is currently low priority. When the load of the first processor core is greater than or equal to 10%, it indicates that the first processor core has more tasks to process. At this time, in order to ensure processing efficiency, the priority of the first processor core can be adjusted back to the original high priority.

[0097] Based on the foregoing embodiment, in other embodiments of the application, referring to FIG. 3, after step 302, any one of steps 306-308 can be performed. Figure 5

[0098] In step 306, if the load of the second processor core in the second processor core set is less than or equal to the second threshold value and the duration is greater than or equal to the first time length, the electronic device determines the second processor core as a second target processor core, adjusts the second processor core to the first processor core set, or adjusts the second processor core to the first processor core set and adjusts a first target processor core in the first processor core set to the second processor core set.

[0099] In the embodiment of the application, the second processor in the second processor core set B2 can always be in the second processor core set, that is, the second processor core is originally (before adjusting the frequency) and currently in the high priority group. In a feasible implementation manner, the second threshold value can be 5%, and the first time length is t1, as shown in FIG. 3. Figure 4 ​As shown, when the load of the second processor core in the second processor core set B2 is less than or equal to 5%, and the duration of the load being less than or equal to 5% is greater than or equal to t1, the second processor core is considered as the second target processor core which needs to adjust the priority; at this time, the second processor core can be downgraded, that is, the second processor core is adjusted to the first processor core set B1 with lower priority. Alternatively, after the second processor core is adjusted to the first processor core set B1 with lower priority, because a vacancy is left in the second processor core set, the first target processor core in the first processor core set B1 can be adjusted to the second processor core set B2.

[0100] It should be noted that in this embodiment, because the initial priority and the current priority of the second processor core are both high priority, the priority of the second processor core can be adjusted to low priority when the load of the second processor core is less than 5% in order to maximize the utilization of resources and avoid resource waste.

[0101] In step 307, if the third processor core in the second processor core set is from the first processor core set, and the load of the third processor core is less than or equal to a third threshold value and the duration of the load being less than or equal to the third threshold value is greater than or equal to a second time length, the electronic device determines the third processor core as the second target processor core, adjusts the third processor core to the first processor core set, or adjusts the third processor core to the first processor core set and adjusts the first target processor core in the first processor core set to the second processor core set.

[0102] In the embodiment of the present application, the third processor core in the second processor core set is adjusted from the first processor core set, which indicates that the third processor core is in the low priority group before adjustment and is in the high priority group at present. In a feasible implementation manner, the third threshold value can be 50%, and the second time length is t2, such as Figure 4 As shown, when the load of the third processor core in the second processor core set B2 is less than or equal to 50% (that is, the current load is less than half), and the duration of the load being less than or equal to 50% is greater than or equal to t2, the third processor core is considered as the second target processor core which needs to adjust the priority; at this time, the third processor core can be downgraded, that is, the third processor core is adjusted to the first processor core set B1 with lower priority. Alternatively, after the third processor core is adjusted to the first processor core set B1 with lower priority, because a vacancy is left in the second processor core set, the first target processor core in the first processor core set B1 can be adjusted to the second processor core set B2.

[0103] It should be noted that in this embodiment, since the initial priority of the third processor core is low, the priority of the third processor core can be adjusted back to the original low priority when the load of the third processor core is less than half of the full load, in order to avoid wasting resources.

[0104] Step 308: If the load of the fourth processor core in the first processor core set is greater than the fourth threshold and the duration is greater than or equal to the third duration, the electronic device determines the fourth processor core as the first target processor core, moves the fourth processor core to the second processor core set, or moves the fourth processor core to the second processor core set and moves the second target processor core in the second processor core set to the first processor core set.

[0105] In this embodiment, the fourth processor core may always be in the first processor core set, meaning the fourth processor core was and currently belongs to the low-priority group. In one feasible implementation, the fourth threshold can be 100%, and the third duration is t3, such as... Figure 4 As shown, when the load of the fourth processor core in the first processor core set B1 is greater than or equal to 100% (i.e., the current load is full), and the duration of full load is greater than or equal to t3, the fourth processor core is considered to be the first target processor core whose priority needs to be adjusted. At this time, the fourth processor core can be upgraded, that is, the fourth processor core can be moved to the second processor core set B2 with a higher priority. Alternatively, after the fourth processor core is moved to the second processor core set B2 with a higher priority, because a slot becomes available in the first processor core set B1, the second target processor core in the second processor core set B2 can be moved to the first processor core set B1.

[0106] It should be noted that in this embodiment, since the fourth processor core was originally and currently has a low priority, its priority can be upgraded to a high priority when the fourth processor core is fully loaded in order to ensure that the task can be processed successfully and in a timely manner.

[0107] In other embodiments of this application, the second target processor core may be determined based on the load of processor cores in the second processor core set, or it may be a specific processor core, or it may be determined based on factors such as whether a group switch or swap frequency has occurred. Here, swap frequency refers to the frequency at which the processor core set is swapped.

[0108] In addition, such as Figure 4In the process of degrading or upgrading the priority of the processor core, the processor core needing to be degraded or upgraded can be added to the corresponding degradation list or upgrade list first, and then the processor core in the degradation list or upgrade list is degraded or upgraded according to the principle of "first in, first out, last in, last out". In a possible implementation, when the degradation list and the upgrade list are not empty, the degradation and upgrade processes can be performed simultaneously; when the upgrade list is empty and the degradation list is not empty, the degradation process can be performed.

[0109] Based on the foregoing embodiment, in other embodiments of the present application, the method can further include the following steps:

[0110] In step 309, the electronic device determines the number of processor cores in the first processor core set and the second processor core set.

[0111] After step 309, step 310 or step 311 can be performed.

[0112] In step 310, the electronic device determines, based on the number of processor cores, whether to adjust the first target processor core to the second processor core set, or to adjust the first target processor core to the second processor core set and adjust the second target processor core in the second processor core set to the first processor core set.

[0113] In step 311, the electronic device determines, based on the number of processor cores, whether to adjust the second target processor core to the first processor core set, or to adjust the second target processor core to the first processor core set and adjust the first target processor core in the first processor core set to the second processor core set.

[0114] In the embodiments of the present application, only when the number of processor cores in the first processor core set and the second processor core set is not empty, the electronic device can upgrade the priority of the first target processor core and degrade the priority of the second target processor core.

[0115] In other embodiments of the present application, the levels of the processor core sets with different priorities have a certain corresponding relationship with the tasks in the electronic device.

[0116] It should be noted that the explanation of the same or related steps in the present embodiment as in other embodiments can refer to the explanation in other embodiments, which will not be repeated here.

[0117] The control method provided by the embodiments of the present application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set. The grouping of the processor cores is not always fixed, and the problem that the performance of the CPU in the low-priority group is limited when the load of the CPU in the high-priority group is not full is solved, and the performance of the CPU is ensured.

[0118] Based on the foregoing embodiments, the embodiments of the present application provide a control method, as shown in FIG. 4, the method comprises the following steps: Figure 6

[0119] Step 401: The electronic device monitors the load of the processor core set of the electronic device.

[0120] The processor core set comprises at least one processor core.

[0121] It should be noted that after step 401, any one of steps 402-405 can be performed.

[0122] Step 402: The electronic device adjusts the configuration information of the processor core set based on the change information of the load.

[0123] In the embodiments of the present application, the change information of the load of the processor core set of the electronic device can be monitored. Only the priority of the processor core whose load changes or the frequency of the processor core set to which the processor core belongs is adjusted based on whether the load is increasing or decreasing, so that the processor core whose load changes can still efficiently process tasks.

[0124] Step 402 can be implemented in the following manner:

[0125] Step 402a: If the load of the fifth processor core in the first processor core set increases from the fifth threshold value to the sixth threshold value, the electronic device adjusts the fifth processor core to the second processor core set and / or increases the frequency range of the first processor core set.

[0126] If the load of a processor core (for example, the fifth processor core) in the first processor core set increases, the fifth processor core can be adjusted to the second processor core set with a higher priority, or the frequency range of the first processor core set can be increased. Of course, the fifth processor core can also be adjusted to the second processor core set with a higher priority while the frequency range of the first processor core set is increased. It should be noted that when the frequency range of the first processor core set is increased, the load of other processor cores in the first processor core set can also be increased. ​

[0127] Step 402b, if the load of the sixth processor core in the second processor core set decreases from the seventh threshold value to the eighth threshold value, the electronic device adjusts the sixth processor core to the first processor core set and / or reduces the frequency range of the second processor core set.

[0128] If the load of a certain processor core (for example, the sixth processor core) in the second processor core set decreases, the sixth processor core can be adjusted to the first processor core set with lower priority, or the frequency range of the second processor core set can be reduced. Of course, the sixth processor core can be adjusted to the first processor core set with lower priority while the frequency range of the second processor core set is reduced. It should be noted that when the frequency range of the second processor core set is reduced, it can also be performed when the load of other processor cores in the second processor core set decreases.

[0129] Step 403, the electronic device obtains power supply information of the electronic device, and adjusts the configuration information of the processor core set based on the power supply information and the load.

[0130] In the embodiment of the present application, the power supply information can include power supply information of the electronic device and / or power receiving information of the electronic device.

[0131] The step 403 can be implemented in the following way:

[0132] Step 403a, the electronic device obtains power supply information and / or power receiving information of the electronic device.

[0133] Step 403b, the electronic device adjusts at least one of the position of the target processor core in the processor core set, the number of processor cores, or the frequency range of the processor core set based on at least one of the power supply information, the power receiving information, and the load.

[0134] The position of the target processor core in the processor core set, the number of processor cores, or the frequency range of the processor core set can be adjusted based on the power supply information and the load. Or, the position of the target processor core in the processor core set, the number of processor cores, or the frequency range of the processor core set can be adjusted based on the power receiving information and the load. Or, the position of the target processor core in the processor core set, the number of processor cores, or the frequency range of the processor core set can be adjusted based on the power supply information, the power receiving information, and the load.

[0135] Step 404, the electronic device obtains a configuration instruction acting on the electronic device, and adjusts the configuration information of the processor core set based on the configuration instruction and the load.

[0136] The configuration instruction can be an instruction for reconfiguring the SST configuration file according to actual needs of a user. In this case, the electronic device can obtain, from the configuration instruction, related configuration information about the SST configuration file, update the SST configuration file based on the configuration information, and jointly adjust the configuration information of the processor core set based on the updated SST configuration file and the load.

[0137] In step 405, the electronic device obtains task change information of the electronic device, and adjusts the configuration information of the processor core set based on the task change information and the load.

[0138] In the embodiment of the present application, the processor cores in the processor core set are used to process tasks in the electronic device. In this case, the task change information can refer to change information of tasks that need to be processed by the processor core set. In a feasible implementation manner, if the task of the seventh processor core in the first processor core set is increased, the seventh processor core will be moved to the second processor core set when the load of the seventh processor core is increased, so as to reduce the priority of the seventh processor core. Alternatively, if the task of the eighth processor core in the second processor core set is reduced, the eighth processor core will be moved to the first processor core set when the load of the eighth processor core is reduced, so as to increase the priority of the eighth processor core.

[0139] It should be noted that the explanation of the same or related steps in the present embodiment as in other embodiments can refer to the explanation in other embodiments, which will not be repeated here.

[0140] The control method provided by the embodiments of the present application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set. The grouping of the processor cores is not always constant, which solves the problem that the performance of the CPU in the low-priority group is limited when the load of the CPU in the high-priority group is not full in the power management technology in the related art, and guarantees the performance of the CPU.

[0141] Based on the foregoing embodiments, in other embodiments of the present application, the control method can further include the following steps:

[0142] A1, the electronic device determines a ninth processor core from the first processor core set based on the load of each processor core in the first processor core set.

[0143] A2, the electronic device determines a tenth processor core from the second processor core set based on the load of each processor core in the second processor core set.

[0144] The ninth processor core can be a processor core selected from the first set of processor cores and satisfying a certain load condition, and the tenth processor core can be a processor core selected from the second set of processor cores and satisfying a certain load condition. It should be noted that the ninth processor core includes at least one processor core, and the tenth processor core also includes at least one processor core.

[0145] A3. The electronic device determines a fourth set of processor cores based on the ninth processor core and the tenth processor core.

[0146] The ninth processor core and the tenth processor core can be automatically grouped into a group, thereby obtaining the fourth set of processor cores.

[0147] Based on the foregoing embodiments, the embodiments of the present application provide a control device, which can be applied to Figures 1 to 3 The control method corresponding to the embodiments 5-6 can refer to the control device shown in FIG. 5, and the device 5 can include a monitoring module 51 and a processing module 52, where: Figure 7

[0148] The monitoring module 51 is configured to monitor the load of the set of processor cores of the electronic device, and the set of processor cores includes at least one processor core.

[0149] The processing module 52 is configured to adjust the configuration information of the set of processor cores based on at least the load.

[0150] The processing capabilities of different sets of processor cores are the same or different.

[0151] In other embodiments of the present application, the processing module 52 is further configured to perform the following steps:

[0152] Determine a target processor core in each set of processor cores based on at least the load of each processor core in the set of processor cores, and adjust the target processor core from the set of processor cores where the target processor core currently locates to another set of processor cores; and / or,

[0153] Determine a target frequency range of the target set of processor cores based on at least the load of each processor core in the set of processor cores, and adjust the frequency range of the set of processor cores to the target frequency range.

[0154] In other embodiments of the present application, the processing module 52 is further configured to perform the following steps:

[0155] Obtain source information of each processor core, where the source information represents the set of processor cores to which the processor core belongs before the last adjustment of the set of processor cores.

[0156] ​determine a target processor core in the set of processor cores based on the source information and the load.

[0157] In other embodiments of the application, the processing module 52 is further configured to perform at least one of the following steps:

[0158] If the first processor core in the first set of processor cores is from the second set of processor cores and has a load greater than or equal to a first threshold, determine the first processor core as a first target processor core;

[0159] adjust the first processor core to the second set of processor cores, or

[0160] adjust the first processor core to the second set of processor cores and adjust a second target processor core in the second set of processor cores to the first set of processor cores; or

[0161] adjust the first processor core to the second set of processor cores and adjust a third target processor core in a third set of processor cores to the first set of processor cores.

[0162] In other embodiments of the application, the processing module 52 is further configured to perform at least one of the following steps:

[0163] If a second processor core in the second set of processor cores has a load less than or equal to a second threshold and a duration greater than or equal to a first time length, determine the second processor core as a second target processor core, adjust the second processor core to the first set of processor cores, or adjust the second processor core to the first set of processor cores and adjust a first target processor core in the first set of processor cores to the second set of processor cores;

[0164] If a third processor core in the second set of processor cores is from the first set of processor cores and has a load less than or equal to a third threshold and a duration greater than or equal to a second time length, determine the third processor core as a second target processor core, adjust the third processor core to the first set of processor cores, or adjust the third processor core to the first set of processor cores and adjust a first target processor core in the first set of processor cores to the second set of processor cores;

[0165] If a fourth processor core in the first set of processor cores has a load greater than a fourth threshold and a duration greater than or equal to a third time length, determine the fourth processor core as a first target processor core, adjust the fourth processor core to the second set of processor cores, or adjust the fourth processor core to the second set of processor cores and adjust a second target processor core in the second set of processor cores to the first set of processor cores.

[0166] In other embodiments of the present application, the processing module 52 is further configured to perform the following steps:

[0167] determining the number of processor cores in the first set of processor cores and the second set of processor cores;

[0168] determining, based on the number of processor cores, to move the first target processor core to the second set of processor cores, or to move the first target processor core to the second set of processor cores and to move a second target processor core in the second set of processor cores to the first set of processor cores; or,

[0169] determining, based on the number of processor cores, to move the second target processor core to the first set of processor cores, or to move the second target processor core to the first set of processor cores and to move the first target processor core in the first set of processor cores to the second set of processor cores.

[0170] In other embodiments of the present application, the processing module 52 is further configured to perform at least one of the following steps:

[0171] adjusting the configuration information of the set of processor cores based on the change information of the load;

[0172] obtaining power supply information of the electronic device, and adjusting the configuration information of the set of processor cores based on the power supply information and the load;

[0173] obtaining a configuration instruction acting on the electronic device, and adjusting the configuration information of the set of processor cores based on the configuration instruction and the load;

[0174] obtaining task change information of the electronic device, and adjusting the configuration information of the set of processor cores based on the task change information and the load.

[0175] In other embodiments of the present application, the processing module 52 is further configured to perform the following steps:

[0176] if the load of a fifth processor core in the first set of processor cores increases from a fifth threshold value to a sixth threshold value, moving the fifth processor core to the second set of processor cores and / or increasing the frequency range of the first set of processor cores; or,

[0177] if the load of a sixth processor core in the second set of processor cores decreases from a seventh threshold value to an eighth threshold value, moving the sixth processor core to the first set of processor cores and / or decreasing the frequency range of the second set of processor cores.

[0178] In other embodiments of the present application, the processing module 52 is further configured to perform the following steps:

[0179] Obtaining power supply information and / or power receiving information of the electronic device, and adjusting at least one of a target processor core position, a number of processor cores, or a frequency range of the processor core set within the processor core set based on at least one of the power supply information, the power receiving information, and the load.

[0180] It should be noted that the interaction process between the various modules in this embodiment can refer to the implementation process of the control method provided in the embodiments of 5-6, which will not be described here again. Figures 1 to 3 The implementation process in the control method provided in the embodiments of 5-6, which will not be described here again.

[0181] The control device provided by the embodiments of the present application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set. The grouping of the processor cores is not always the same, which solves the problem that the performance of the CPU in the low-priority group is limited when the load of the CPU in the high-priority group is not full in the power management technology in the related art, and ensures the performance of the CPU.

[0182] Based on the foregoing embodiments, the embodiments of the present application provide an electronic device, which can be applied to Figures 1 to 3 The control method provided in the embodiments of 5-6, which will not be described here again. Figure 8 As shown in the figure, the electronic device 6 can include a processor 61, a memory 62, and a communication bus 63, wherein:

[0183] The communication bus 63 is used to realize the communication connection between the processor 61 and the memory 62;

[0184] The processor 61 is used to execute the control program in the memory 62 to realize the following steps:

[0185] Monitoring the load of the processor core set of the electronic device, the processor core set including at least one processor core;

[0186] Adjusting the configuration information of the processor core set based on at least the load;

[0187] Wherein, the processing capabilities of different processor core sets are the same or different.

[0188] The electronic device provided by the embodiments of the present application can dynamically adjust the configuration information of the processor core set according to the load of the processor cores in the processor core set. The grouping of the processor cores is not always the same, which solves the problem that the performance of the CPU in the low-priority group is limited when the load of the CPU in the high-priority group is not full in the power management technology in the related art, and ensures the performance of the CPU.

[0189] Based on the foregoing embodiments, the embodiments of the present application provide a computer readable storage medium storing one or more programs, which can be executed by one or more processors to implement the method as Figures 1 to 3 The embodiments corresponding to 5-6 provide the steps of the control method.

[0190] Those skilled in the art will understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage, etc.) containing computer-usable program code.

[0191] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more blocks or flows.

[0192] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more blocks or flows.

[0193] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 Figure 1 an apparatus that carries out the functions specified in one or more blocks or flows.

[0194] The above description is only a preferred embodiment of the present application, and is not intended to limit the protection scope of the present application.

Claims

1. A control method, comprising: Monitor the load of a set of processor cores in an electronic device, the set of processor cores including at least one processor core; The configuration information of the processor core set is adjusted based at least on the load. The processing capabilities of different processor core sets may be the same or different; the configuration information includes at least the number of processor cores in the processor core set.

2. The method according to claim 1, wherein, Adjusting the configuration information of the processor core set based on the load includes: The target processor core in each processor core set is determined based on at least the load of each processor core in each processor core set, and the target processor core is moved from its current processor core set to another processor core set; and / or, The target frequency range of the processor core set is determined based at least on the load of each processor core in the processor core set, and the frequency range of the processor core set is adjusted to the target frequency range.

3. The method according to claim 2, wherein, Determining the target processor core in each processor core set based at least on the load of each processor core in each processor core set includes: Obtain the source information for each processor core, wherein the source information represents the processor core set to which the processor core belonged before the last processor core set adjustment; The target processor core in each processor core set is determined based on the source information and the load.

4. The method according to claim 3, wherein, Adjusting the configuration information of the processor core set based on the load includes: If the first processor core in the first processor core set comes from the second processor core set, and its load is greater than or equal to the first threshold, the first processor core is determined to be the first target processor core. Move the first processor core to the second processor core set, or... Move the first processor core to the second processor core set and move the second target processor core from the second processor core set to the first processor core set; or, The first processor core is moved to the second processor core set, and the third target processor core in the third processor core set is moved to the first processor core set.

5. The method according to claim 3, wherein, Adjusting the configuration information of the processor core set based on the load includes at least one of the following: If the load of the second processor core in the second processor core set is less than or equal to the second threshold and the duration is greater than or equal to the first duration, the second processor core is identified as the second target processor core, and the second processor core is moved to the first processor core set, or the second processor core is moved to the first processor core set and the first target processor core in the first processor core set is moved to the second processor core set. If the third processor core in the second processor core set comes from the first processor core set, and its load is less than or equal to the third threshold and its duration is greater than or equal to the second duration, the third processor core is determined as the second target processor core, and the third processor core is moved to the first processor core set, or the third processor core is moved to the first processor core set and the first target processor core in the first processor core set is moved to the second processor core set. If the load of the fourth processor core in the first processor core set is greater than the fourth threshold and the duration is greater than or equal to the third duration, the fourth processor core is identified as the first target processor core, and the fourth processor core is moved to the second processor core set, or the fourth processor core is moved to the second processor core set and the second target processor core in the second processor core set is moved to the first processor core set.

6. The method according to claim 4 or 5, further comprising: Determine the number of processor cores in the first processor core set and the second processor core set; Based on the number of processor cores, determine whether to move the first target processor core to the second processor core set, or move the first target processor core to the second processor core set and move the second target processor core in the second processor core set to the first processor core set. or, Based on the number of processor cores, determine whether to move the second target processor core to the first processor core set, or move the second processor core to the first processor core set and move the first target processor core in the first processor core set to the second processor core set.

7. The method according to any one of claims 1 to 5, wherein adjusting the configuration information of the processor core set based at least on the load includes at least one of the following: Adjust the configuration information of the processor core set based on the load change information; Obtain power information of the electronic device, and adjust the configuration information of the processor core set based on the power information and the load; Obtain configuration instructions that act on the electronic device, and adjust the configuration information of the processor core set based on the configuration instructions and the load; Obtain task change information of the electronic device, and adjust the configuration information of the processor core set based on the task change information and the load.

8. The method according to claim 7, wherein, Adjusting the configuration information of the processor core set based on the load change information includes: If the load on the fifth processor core in the first processor core set increases from the fifth threshold to the sixth threshold, the fifth processor core is moved to the second processor core set and / or the frequency range of the first processor core set is increased; or, If the load on the sixth processor core in the second processor core set decreases from the seventh threshold to the eighth threshold, the sixth processor core is adjusted to the frequency range of the first processor core set and / or the frequency range of the second processor core set is reduced.

9. The method according to claim 7, wherein, Adjusting the configuration information of the processor core set based on the power information and the load includes: Obtain power supply information and / or power receiving information of the electronic device, and adjust at least one of the target processor core location, number of processor cores, or frequency range of the processor core set based on at least one of the power supply information, power receiving information, and the load.

10. A control device, comprising: A monitoring module is used to monitor the load of a processor core set in an electronic device, the processor core set including at least one processor core; A processing module, configured to adjust the configuration information of the processor core set based at least on the load; The processing capabilities of different processor core sets may be the same or different; the configuration information includes at least the number of processor cores in the processor core set.

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