A bonding method for a multi-layer chip stack and a multi-layer chip stack structure

Abstract

The application discloses a bonding method of a multilayer chip stack and a multilayer chip stack structure. An insulating layer, a barrier layer, a metal seed layer and a photoetchable insulating bonding adhesive are prepared on the surface of a chip respectively, metal interconnection windows are opened on the insulating bonding adhesive layers of two chips through a photoetching process respectively, the two-layer chip stack structure is realized through alignment bonding of the insulating bonding adhesives on the two chips, and then the metal bonding of the two-layer chip is realized by using a copper electroplating process and an electroplating filling mode. The electroplating process and the electroplating filling can be carried out in a room temperature environment, thereby avoiding high-temperature residual thermal stress. The metal bonding is realized through the electroplating process, an integrated metal connection structure is formed, the metal-metal bonding interface is eliminated, the van der Waals force suffered by the atoms of the upper and lower bonding interfaces is reduced, and the shear force and von Mises stress suffered by the bonding interface are reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a bonding method and a multilayer chip stacking structure. Background Technology

[0002] 3D integration technology is considered one of the most likely integration technologies to sustain the rapid development of the semiconductor industry. Integrated circuits are no longer limited to the X and Y planes; instead, they fully utilize vertical space to stack various chips along the Z direction, significantly increasing system integration, shortening interconnect lengths, and reducing signal delay. However, with the continuous increase in the number of stacked layers and the increase in heat generation per unit area of ​​the chip, reliability issues become increasingly apparent as heat accumulates. Under prolonged high and low temperature cycling, bonding interfaces are highly susceptible to cracks and voids, leading to bonding interface breakage and failure. Therefore, the reliability of bonding interfaces is crucial for 3D integrated systems.

[0003] Traditional 3D integrated microbump bonding also serves as the bonding interface between circuits, requiring careful consideration of the bonding interface's reliability. Furthermore, the increasing number of stacked layers leads to heat accumulation in the system, causing an increase in the chip's operating temperature. Cyclic operation at high and low temperatures causes continuous accumulation of damage within the bonding area, and the increased shear force forms stress loops, leading to defects such as voids and cracks. As damage accumulates and expands, it can ultimately cause the bonding interface to fracture, resulting in significant reliability issues or even system failure in the power electronic system.

[0004] Bonding is a key technology for achieving 3D integrated chip stacking. Currently, the main bonding methods applicable to 3D integration technology include direct bonding, surface activation bonding, adhesive bonding, eutectic bonding, and nanostructure bonding. However, these technologies all involve a high-temperature process, with some processes reaching 500°C or higher. The residual thermal stress from these high temperatures can affect device performance and system reliability, and may even lead to damage to the connection structure and thermally sensitive devices. Furthermore, surface activation bonding and nanostructure bonding have extremely stringent requirements for the flatness and cleanliness of the bonding interface, and also place very high demands on the environment and equipment, which is not conducive to commercialization and mass production. Summary of the Invention

[0005] This application provides a bonding method and a multi-layer chip stacking structure, which solves the technical problem that existing bonding technologies basically involve a high-temperature process, some of which even reach 500°C or above. The residual thermal stress at high temperatures can have a certain impact on the performance of devices and the reliability of systems, and may even lead to the destruction of the connection structure and damage to thermally sensitive devices.

[0006] In view of this, the first aspect of this application provides a bonding method for multilayer chip stacking, the method comprising:

[0007] S1. An insulating layer, a barrier layer, and a metal seed layer are sequentially fabricated at the connection surfaces of the first chip and the second chip, respectively.

[0008] S2. A photolithographically readable insulating bonding adhesive layer is prepared on the seed layer surface of the first chip and the second chip, and a window for metal interconnection is opened on the insulating bonding adhesive layer by photolithography.

[0009] S3. Based on the pattern of insulating bonding adhesive, the first chip and the second chip are bonded together by the bonding of insulating bonding adhesive to form a chip stack structure;

[0010] S4. Connect an electroplated cathode to the metal seed layer at the edge of the first chip, and cover the area except for the window with insulating material;

[0011] S5. The chip stack structure is immersed in an electroplating solution. After immersion, metal material is filled into the window of the chip stack structure through an electroplating process to complete the metal bonding between the first chip and the second chip.

[0012] Optionally, the specific steps in step S1 of preparing insulating layers at the connection surfaces of the first chip and the second chip are as follows:

[0013] Insulating layer materials are deposited on the interface between the first chip and the second chip using a high-temperature oxidation process or a plasma-enhanced chemical vapor deposition method to form an insulating layer.

[0014] Optionally, in step S1, the preparation of barrier layers at the connection surfaces of the first chip and the second chip specifically involves:

[0015] Barrier layer materials are deposited on the insulating layer surfaces of the first and second chips respectively using a DC magnetron sputtering process to form barrier layers.

[0016] Optionally, the preparation of metal seed layers at the connection surfaces of the first chip and the second chip in step S1 specifically involves:

[0017] Metal seed layer materials are deposited on the barrier layer surfaces of the first and second chips respectively using a DC magnetron sputtering process to form a metal seed layer.

[0018] Optionally, step S2 specifically includes:

[0019] After photolithographically lithographic insulating bonding adhesive is dropped onto the seed layer surfaces of the first and second chips placed on a spin coater, a spin coater process is performed.

[0020] The first and second chips after the homogenization process are then subjected to soft baking.

[0021] Photolithography is performed on the first and second chips after soft baking to determine the first area to be exposed and the second area not to be exposed on the first and second chips.

[0022] The first and second chips after photolithography are baked a second time.

[0023] After the second baking, the first and second chips are placed in the developing solution for development, and the developing solution is spun dry using a spin coater.

[0024] After cleaning and drying the first chip and the second chip, a first chip and a second chip with insulating bonding adhesive as steps are obtained, and the first chip and the second chip include a first area covered by the insulating bonding adhesive steps and a second area not covered by the insulating bonding adhesive steps.

[0025] Optionally, step S3 specifically includes:

[0026] The insulating bonding adhesive steps of the first chip are bonded to the insulating bonding adhesive steps of the second chip using a bonding machine to form a chip stack structure.

[0027] Optionally, step S5 specifically includes:

[0028] The temporary chip stack structure was placed in an electroplating solution for vacuum wetting;

[0029] Connect the electroplating cathode to the negative terminal of the power supply, and connect the phosphor bronze plate as the electroplating anode to the positive terminal of the power supply.

[0030] During the electroplating process, the electroplating solution is agitated by a blower, and metal material is used to fill the gaps in the chip stacking structure, completing the metal bonding between the first chip and the second chip, forming a two-layer chip stacking structure with insulating layer-insulator bonding and metal-metal bonding.

[0031] Optionally, it also includes:

[0032] S6. If it is necessary to continue stacking chips on the chip stacking structure, grind the upper chip of the chip stacking structure to the preset thickness and polish the top surface of the upper chip in the chip stacking structure.

[0033] S7. An insulating layer is prepared on the top surface of the upper chip using plasma-enhanced chemical vapor deposition. A barrier layer and a seed layer are then prepared sequentially on the surface of the insulating layer.

[0034] S8. An insulating layer, a barrier layer, and a metal seed layer are sequentially fabricated on the connection surface of the third chip.

[0035] S9. Prepare a photolithographic insulating bonding adhesive layer on the surface of the metal seed layer of the two-layer chip stack structure and the third chip, and open a window for metal interconnection on the insulating bonding adhesive layer by photolithography.

[0036] S10. Based on the pattern of insulating bonding adhesive, the two-layer chip stack structure is bonded to the third chip through the bonding of insulating bonding adhesive to form a three-layer chip stack structure.

[0037] S11. Connect an electroplated cathode to the metal seed layer at the edge of the two-layer chip stacked structure, and cover the area except for the window with insulating material.

[0038] S12. The three-layer chip stack structure is immersed in an electroplating solution. After immersion, metal material is filled into the window of the three-layer chip stack structure through an electroplating process to form a new chip stack structure formed by bonding the two-layer chip stack structure with the third chip, and so on.

[0039] Optionally, in step S6, the preset thickness is 40–150 μm.

[0040] The second aspect of this application provides a multi-layer chip stacking structure, characterized in that it includes a chip stacking structure formed by bonding based on the multi-layer chip stacking bonding method described in any one of the first aspects of this application.

[0041] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0042] This application provides a bonding method for multilayer chip stacking. An insulating layer, a barrier layer, a metal seed layer, and a photolithographically identifiable insulating bonding adhesive are prepared on the chip surface. Metal interconnect windows are then created on the insulating bonding adhesive layers of both chip layers using photolithography. The stacked chip structure is achieved by aligning and bonding the insulating bonding adhesives on the two chip layers. Metal bonding between the two chip layers is then achieved using copper electroplating and electroplating filler processes. Both the electroplating process and electroplating filler can be performed at room temperature, avoiding high-temperature residual thermal stress. This solves the technical problem commonly found in existing metal-to-metal bonding technologies, where high-temperature processes (up to 500°C and above) cause residual thermal stress that can affect device performance and system reliability, and even lead to damage to the connection structure and thermally sensitive devices. Achieving metal bonding through electroplating forms an integrated metal connection structure, eliminating the metal-to-metal bonding interface, reducing the van der Waals forces on the atoms at the bonding interface between the upper and lower layers, and reducing the shear force and von Mises stress at the bonding interface. Attached Figure Description

[0043] Figure 1 This is a flowchart of a bonding method for multilayer chip stacking according to this application;

[0044] Figure 2 This is a schematic diagram of the bonding method for stacking two-layer chips in this application.

[0045] Figure 3 This is a schematic diagram of the bonding method for stacking two or more chip layers in this application. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0047] This application designs a bonding method and a multi-layer chip stacking structure for multi-layer chip stacking, which solves the technical problem that existing bonding technologies basically involve a high-temperature process, some of which even reach 500°C or above. The residual thermal stress at high temperatures can have a certain impact on the performance of devices and the reliability of systems, and may even lead to the destruction of the connection structure and damage to thermally sensitive devices.

[0048] For easier understanding, please refer to Figure 1 and Figure 2 , Figure 1 This is a flowchart illustrating a bonding method for multilayer chip stacking according to an embodiment of this application. Figure 1 As shown, specifically:

[0049] S1. An insulating layer, a barrier layer, and a metal seed layer are sequentially fabricated at the connection surfaces of the first chip and the second chip, respectively.

[0050] It should be noted that for two chips to be bonded, an insulating layer, a barrier layer, and a seed layer need to be fabricated sequentially on the bonding surfaces of the chips, respectively:

[0051] Insulating layer material is deposited on the interface between the first chip and the second chip by high-temperature oxidation process or plasma-enhanced chemical vapor deposition to form an insulating layer.

[0052] Barrier layer materials are deposited on the insulating layer surfaces of the first and second chips respectively using DC magnetron sputtering process to form barrier layers.

[0053] Metal seed layer materials are deposited on the barrier layer surfaces of the first and second chips respectively using a DC magnetron sputtering process to form a metal seed layer.

[0054] Specifically:

[0055] Insulating layer materials include, but are not limited to, silicon dioxide, rubber, plastics, and PVC polyethylene, with silicon dioxide being the preferred choice. This is because silicon-based semiconductors, which use silicon as a substrate, currently account for a large market share in the integrated circuit market. Silicon dioxide is formed simply by exposing silicon to a high-temperature oxygen environment. Therefore, considering factors such as the material itself, process cost, and convenience, this solution optimally selects silicon dioxide as the insulating layer material to form the silicon dioxide insulating layer.

[0056] The barrier layer material includes, but is not limited to, titanium, forming a titanium barrier layer.

[0057] The metal seed layer material is copper, forming a copper seed layer.

[0058] The high-temperature oxidation process involves sequentially performing dry oxidation, wet oxidation, and dry oxidation at an environment of 900–1200 degrees Celsius. The time for each oxidation step can be selected from 1 to 180 minutes depending on the requirements. The oxygen flow rate can be 0.1–2 L / min depending on the requirements. Protective gases can also be used during the heating and cooling process. Protective gases include, but are not limited to, oxygen, carbon dioxide, inert gases (such as argon), and nitrogen. The flow rate of the protective gas can be 0.1–2 L / min depending on the requirements.

[0059] The preferred method is to sequentially perform dry oxidation for 10 min, wet oxidation for 120 min, and dry oxidation for 10 min at 1150℃, with an oxygen flow rate of 1.5 L / min. Nitrogen is used as a protective gas during both heating and cooling processes, with a nitrogen flow rate of 0.5 L / min. This method can produce an insulating layer with a thickness of approximately 800 nm.

[0060] Dry oxidation involves the reaction of silicon and oxygen at high temperatures to produce silicon dioxide. This method has an extremely slow growth rate, but produces silicon dioxide with excellent density. Wet oxidation, on the other hand, involves the reaction of silicon and water at high temperatures to produce silicon dioxide and hydrogen. This method has a very fast growth rate, but produces poor density. Therefore, this solution employs a combination of dry oxidation, wet oxidation, and dry oxidation to form a dense, "sandwich-like" oxide layer on the outer surface, offering extremely high cost-effectiveness.

[0061] Considering factors such as safety (excessive oxygen concentration and high temperature environment can easily lead to explosion) and gas cost (inert gas is expensive), nitrogen was selected as the protective gas in this solution.

[0062] This solution proposes room-temperature bonding and filling, meaning that electroplating and bonding can be performed simultaneously at room temperature. Currently, the entire industry is exploring low-temperature or even room-temperature bonding methods (such as surface activation bonding and nanoarray bonding), but these generally involve high-temperature steps above 150°C. A method that truly achieves bonding at low temperatures or even room temperature has not yet been discovered, which is currently the biggest advantage and potential of electroplating bonding.

[0063] This solution combines bonding and filling on top of electroplating, achieving effective interface-free bonding, which is one of its biggest highlights and innovations. Therefore, to avoid the high-temperature environment required for thermal oxidation to deposit the insulating layer, and to prevent residual thermal stress from affecting the overall stability and reliability of the system, this solution can also employ plasma-enhanced chemical vapor deposition (PECVD), a method that avoids high-temperature processes, to prepare the silicon dioxide insulating layer in chip stacking bonding technology.

[0064] The specific process parameters for the DC magnetron sputtering fabrication of the barrier layer are as follows: substrate heating temperature of 400-600℃, cavity gas pressure of 0.4-1.0Pa, vacuum degree of 9.0×10-4Pa or above, argon gas flow rate of 20-40sccm, sputtering current of 0.2-0.5A, and sputtering time of 5-90min.

[0065] The preferred method is as follows: a titanium barrier layer with a thickness of about 1.5 μm can be prepared under the following conditions: substrate heating temperature of 600℃, cavity gas pressure of 1.0 Pa, vacuum degree of 9.0×10-4 Pa, argon gas flow rate of 25 sccm, sputtering current of 0.5 A, and sputtering time of 30 min.

[0066] The specific process parameters for the preparation of the metal seed layer by DC magnetron sputtering are as follows: substrate heating temperature is 200-300℃, cavity gas pressure is 0.4-1.0Pa, vacuum degree is 9.0×10-4Pa or above, argon gas flow rate is 20-40sccm, sputtering current is 0.2-0.5A, and sputtering time is 1-10min.

[0067] The preferred method is as follows: a copper seed layer with a thickness of about 1.5 μm can be prepared under the following conditions: substrate heating temperature of 200℃, cavity gas pressure of 1.0 Pa, vacuum degree of 9.0×10-4 Pa, argon gas flow rate of 25 sccm, sputtering current of 0.3 A, and sputtering time of 5 min.

[0068] S2. A photolithographically readable insulating bonding adhesive layer is prepared on the seed layer surface of the first chip and the second chip, and a window for metal interconnection is opened on the insulating bonding adhesive layer by photolithography.

[0069] It should be noted that the photolithography process uses a maskless photolithography machine to photolithographically print a pre-set pattern at the corresponding position. The thickness of the insulating bonding adhesive is used to form steps. The pre-set pattern can be a cross pattern, so that the steps formed by the insulating bonding adhesive are distributed at the four corners of the chip. The purpose is to control the distance between the two chip layers and prepare for subsequent electroplating bonding.

[0070] The step height is the thickness of the bonding layer. Different types of insulating bonding adhesives will have different step heights. For example, the step thickness of insulating bonding adhesive AZ4620 is about 6μm-20μm, the step thickness of insulating bonding adhesive HTG910 is about 20μm-100μm, and the step thickness of insulating bonding adhesive lift-off is about 1μm-6μm.

[0071] Specifically:

[0072] After photolithographically lithographic insulating bonding adhesive is dropped onto the seed layer surfaces of the first and second chips placed on a spin coater, a spin coater process is performed.

[0073] The first and second chips after the homogenization process are then subjected to soft baking.

[0074] Photolithography is performed on the first and second chips after soft baking to determine the first area to be exposed and the second area not to be exposed on the first and second chips.

[0075] The first and second chips after photolithography are baked a second time.

[0076] After the second baking, the first and second chips are placed in the developing solution for development, and the developing solution is spun dry using a spin coater.

[0077] After cleaning and drying the first chip and the second chip, a first chip and a second chip with insulating bonding adhesive as steps are obtained, and the first chip and the second chip include a first area covered by the insulating bonding adhesive steps and a second area not covered by the insulating bonding adhesive steps.

[0078] It should be noted that the spin coating process can be divided into two stages. In the first stage, the spin coater speed is 600 r / min and the spin coating time is 10 s. In the second stage, the spin coater speed is 1600 r / min and the spin coating time is 30 s. Then, the chip is pre-baked at a high temperature of 125℃ for 5 minutes. The pre-baked chip is then placed in a photolithography machine for photolithography.

[0079] The spin coating process parameters also vary depending on the type of insulating bonding adhesive. For example, the step thickness of insulating bonding adhesive AZ4620 is 13.4 μm under spin coating conditions of 1600 rpm and 60 s.

[0080] The lithography parameters are as follows: exposure dose is 18.5mW / cm2, exposure time is 14s, and focus value is -3.

[0081] After photolithography, the chip was developed using 2.38% TMAH developer for 2.5 minutes.

[0082] S3. Temporarily bond the first chip and the second chip together using steps to form a temporary chip stacking structure;

[0083] It should be noted that the insulating bonding adhesive steps of the first chip and the insulating bonding adhesive steps of the second chip are bonded together by a bonding machine to form a temporary chip stack structure.

[0084] S4. Connect an electroplated cathode to the metal seed layer at the edge of the first chip, and cover the area except for the window with insulating material;

[0085] S5. The chip stack structure is immersed in an electroplating solution. After immersion, metal material is filled into the window of the chip stack structure through an electroplating process to complete the metal bonding between the first chip and the second chip.

[0086] Specifically, it includes:

[0087] The chip stack structure is placed in an electroplating solution for vacuum wetting;

[0088] Connect the electroplating cathode to the negative terminal of the power supply, and connect the phosphor bronze plate as the electroplating anode to the positive terminal of the power supply.

[0089] During the electroplating process, the electroplating solution is agitated by a blower, and metal material is used to fill the gaps in the chip stacking structure, completing the metal bonding between the first chip and the second chip, forming a two-layer chip stacking structure with insulating layer-insulator bonding and metal-metal bonding.

[0090] It should be noted that before electroplating, the electroplating cathode is connected to the negative terminal of the power supply, and the phosphor bronze plate is used as the electroplating anode and connected to the positive terminal of the power supply.

[0091] When the power is turned on, the current is 1mA-5mA, and the electroplating time (6h-12h) is determined by the thickness (8μm-16μm) between the stacked chips.

[0092] During the electroplating process, an air blower is used to agitate the electroplating tank. Magnetic stirring and wetting utilizes magnetic stirring to ensure sufficient fluidity of the electroplating solution within the windows of each chip stack. The magnetic stirring speed ranges from 2000 r / min to 3000 r / min. The purpose is to ensure sufficient fluidity of the electroplating solution within the windows of each chip stack, while also ensuring the uniformity of copper ions in the electroplating solution. The wetting time is 15 min to 90 min.

[0093] During electroplating, a redox reaction is utilized. By controlling the current, the electroplating process achieves small-particle, highly dense filling of the bonding region under low-current conditions, thereby eliminating the bonding interface and achieving interface-free, room-temperature, high-reliability bonding. This solution can employ a constant current power supply (current source), allowing direct adjustment of the output current.

[0094] Further, please refer to Figure 3 , Figure 3 This is a schematic diagram of the bonding method for stacking two or more chip layers in this application. The bonding method also includes:

[0095] S6. If it is necessary to continue stacking chips on the chip stacking structure, grind the upper chip of the chip stacking structure to the preset thickness and polish the top surface of the upper chip in the chip stacking structure.

[0096] S7. An insulating layer is prepared on the top surface of the upper chip using plasma-enhanced chemical vapor deposition. A barrier layer and a seed layer are then prepared sequentially on the surface of the insulating layer.

[0097] S8. An insulating layer, a barrier layer, and a metal seed layer are sequentially fabricated on the connection surface of the third chip.

[0098] S9. Prepare a photolithographic insulating bonding adhesive layer on the surface of the metal seed layer of the two-layer chip stack structure and the third chip, and open a window for metal interconnection on the insulating bonding adhesive layer by photolithography.

[0099] S10. Based on the pattern of insulating bonding adhesive, the two-layer chip stack structure is bonded to the third chip through the bonding of insulating bonding adhesive to form a three-layer chip stack structure.

[0100] S11. Connect an electroplated cathode to the metal seed layer at the edge of the two-layer chip stacked structure, and cover the area except for the window with insulating material.

[0101] S12. The three-layer chip stack structure is immersed in an electroplating solution. After immersion, metal material is filled into the window of the three-layer chip stack structure through an electroplating process to form a new chip stack structure formed by bonding the two-layer chip stack structure with the third chip, and so on.

[0102] It should be noted that for chip stacking structures that already consist of two or more layers of chips, if additional chips need to be stacked on top of the existing chip stacking structure, chemical mechanical polishing technology must first be used to grind the upper layer of the chip stacking structure to a preset thickness, which is 40 to 150 μm. This is to avoid the overall thickness of the multi-layer chip stacking structure being too high.

[0103] Meanwhile, since a chip stack structure has already been formed, if a high-temperature oxidation process is still used to prepare the insulating layer on the chip stack structure, the high temperature required for the high-temperature oxidation process can easily lead to residual thermal stress, affecting the overall stability and reliability of the system. Therefore, in the process of continuing to stack chips on a chip stack structure containing at least two layers of chips, only plasma-enhanced chemical vapor deposition can be used to prepare an insulating layer on the top surface of the upper chip, and then a barrier layer and a seed layer are prepared sequentially on the surface of the insulating layer. The bonding process of the third chip to be stacked is the same as the aforementioned bonding process.

[0104] This application also provides a multi-layer chip stacking structure, characterized in that it includes a chip stacking structure formed by bonding based on the multi-layer chip stacking bonding method described in any one of the first embodiments of this application.

[0105] This application provides a bonding method and structure for multilayer chip stacking. An insulating layer, a barrier layer, a metal seed layer, and a photolithographically identifiable insulating bonding adhesive are prepared on the chip surface. Metal interconnect windows are then created on the insulating bonding adhesive layers of the two chip layers using photolithography. The two-layer chip stacking structure is achieved through alignment and bonding of the insulating bonding adhesive on the two chip layers. Metal bonding between the two chip layers is then achieved using copper electroplating and electroplating filling processes. Both the electroplating process and electroplating filling can be performed at room temperature, avoiding high-temperature residual thermal stress. This solves the technical problem commonly found in existing metal-to-metal bonding technologies, where high-temperature processes (up to 500°C and above) cause residual thermal stress that can affect device performance and system reliability, and even lead to damage to the connection structure and thermally sensitive devices. The electroplating process achieves metal bonding, forming an integrated metal connection structure, eliminating the metal-to-metal bonding interface, reducing the van der Waals forces on the atoms at the bonding interface between the upper and lower layers, and reducing the shear force and von Mises stress at the bonding interface.

[0106] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method of bonding a multi-layer chip stack, characterized by, The application relates to a method for preparing a chip stack structure. S1, respectively preparing an insulating layer, a barrier layer and a metal seed layer on the connecting surfaces of the first chip and the second chip; S2, preparing a photoetchable insulating bonding glue layer on the seed layer surfaces of the first chip and the second chip, and opening a window for metal interconnection on the insulating bonding glue layer through a photoetching process; S3, bonding the first chip and the second chip into one through the bonding of the insulating bonding glue based on the pattern of the insulating bonding glue, and forming a chip stack structure; S4, connecting an electroplating cathode on the edge metal seed layer of the first chip, and covering the insulating material on the area except the window; S5, placing the chip stack structure in an electroplating solution for soaking, filling the metal material in the window of the chip stack structure through an electroplating process after soaking, and completing the metal bonding of the first chip and the second chip.

2. The method of claim 1, wherein, In the step S1, the insulating layer is prepared on the connecting surfaces of the first chip and the second chip in the following way: The insulating layer is formed by depositing insulating layer material on the connecting surfaces of the first chip and the second chip through a high-temperature oxidation process or a plasma enhanced chemical vapor deposition method.

3. The method of claim 1, wherein, In the step S1, the barrier layer is prepared on the connecting surfaces of the first chip and the second chip in the following way: The barrier layer is formed by depositing barrier layer material on the insulating layer surfaces of the first chip and the second chip through a direct current magnetron sputtering process.

4. The method of claim 1, wherein, In the step S1, the metal seed layer is prepared on the connecting surfaces of the first chip and the second chip in the following way: The metal seed layer is formed by depositing metal seed layer material on the barrier layer surfaces of the first chip and the second chip through a direct current magnetron sputtering process.

5. The method of claim 1, wherein, The step S2 specifically comprises the following steps: After the photoetchable insulating bonding glue is dropped on the seed layer surfaces of the first chip and the second chip placed on a glue spreading table, glue spreading treatment is carried out; The first chip and the second chip after the glue spreading treatment are subjected to soft baking; The first chip and the second chip after the soft baking are subjected to photoetching, and the first area on the first chip and the second chip for exposure and the second area not for exposure are determined; The first chip and the second chip after the photoetching are subjected to secondary baking; The first chip and the second chip after the secondary baking are placed in a developing solution for development, and the developing solution is spun dry through a glue spreading machine; After the first chip and the second chip are cleaned and dried, the first chip and the second chip with the insulating bonding glue as a step are obtained, and the first chip and the second chip comprise the first area covered by the insulating bonding glue step and the second area not covered by the insulating bonding glue step.

6. The method of claim 1, wherein, The step S3 specifically comprises the following step: The insulating bonding steps of the first chip and the second chip are correspondingly bonded through a bonding machine, and the chip stack structure is formed.

7. The method of claim 1, wherein, The step S5 specifically comprises the following steps: The chip stack structure is placed in an electroplating solution for vacuum wetting; An electroplating cathode is connected to a power negative pole, and a phosphor copper plate is used as an electroplating anode and connected to a power positive pole; During the electroplating process, the electroplating solution is stirred through an air blower, the step gap of the chip stack structure is filled with metal material, the metal bonding of the first chip and the second chip is completed, and a two-layer chip stack structure with insulating layer-insulating layer bonding and metal-metal bonding is formed.

8. The method of claim 1, wherein, The application further relates to a chip stack structure prepared through the above method. S6, if it is needed to continue to stack chips on the chip stack structure, grinding the upper chip of the chip stack structure to a preset thickness, and polishing the top surface of the upper chip in the chip stack structure; S7, preparing an insulating layer on the top surface of the upper chip by plasma enhanced chemical vapor deposition, and sequentially preparing a barrier layer and a seed layer on the surface of the insulating layer; S8, sequentially preparing an insulating layer, a barrier layer and a metal seed layer on the connecting surface of the third chip; S9, preparing a photoresistable insulating bonding glue layer on the surface of the metal seed layer of the third chip and the two-layer chip stack structure, and opening a window for metal interconnection on the insulating bonding glue layer by a photoetching process; S10, based on the pattern of the insulating bonding glue, bonding the two-layer chip stack structure and the third chip by the bonding of the insulating bonding glue to form a three-layer chip stack structure; S11, connecting an electroplating cathode on the edge metal seed layer of the two-layer chip stack structure, and covering the area except the window with an insulating material; S12, placing the three-layer chip stack structure in an electroplating solution for immersion, filling the metal material in the window of the three-layer chip stack structure by an electroplating process after immersion, and forming a new chip stack structure bonded by the two-layer chip stack structure and the third chip, and so on.

9. The method of claim 8, wherein, In the step S6, the preset thickness is 40-150 μm.

10. A multi-tier chip stack structure, characterized by, A chip stack structure bonded by the bonding method of the multi-layer chip stack according to any one of claims 1-9.

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