High-voltage components and method for manufacturing the same

Abstract

The present invention provides a high-voltage component and a manufacturing method thereof. The high-voltage component is used in the power stage of a switching power supply circuit and serves as a lower-bridge switch. The high-voltage component includes at least one laterally diffused metal oxide semiconductor component, a first isolation region, a second isolation region, a third isolation region, and a current-limiting component. The first isolation region surrounds the laterally diffused metal oxide semiconductor component in the semiconductor layer. The second isolation region, having a first conductivity type, surrounds the first isolation region in the semiconductor layer. The third isolation region, having a second conductivity type, surrounds the second isolation region in the semiconductor layer. The current-limiting component is electrically connected to the second isolation region to inhibit the conduction of a parasitic silicon-controlled rectifier.

Description

Technical Field

[0001] The present invention relates to a high-voltage component and a manufacturing method thereof, and particularly to a high-voltage component capable of suppressing the conduction of a parasitic silicon controlled rectifier (SCR) in a switching power supply circuit and a manufacturing method thereof. Prior Art

[0002] Figure 1 The circuit schematic diagram of a typical switching power supply circuit is shown. The switching power supply circuit 10 includes a control circuit 1 and a power stage circuit 2. As Figure 1 shown, the power stage circuit 2 includes a high-voltage component 11 serving as an upper-bridge switch and a high-voltage component 12 serving as a lower-bridge switch, which operate according to an upper-bridge signal UG and a lower-bridge signal LG respectively to convert an input voltage Vin into an output voltage Vout; and an inductor current IL is generated on an inductor 13 of the power stage circuit 2.

[0003] When the high-voltage component 12 operates, when the load circuit 3 is lightly loaded, in a specific case, the inductor current IL turns into a negative current and flows through the high-voltage component 11 from a phase node PH, as Figure 1 indicated by the thick dashed arrow in the figure, causing the parasitic silicon controlled rectifier (SCR) between the high-voltage components 11 and 12 to conduct, resulting in incorrect operation and circuit damage of the high-voltage components 11 and 12. Therefore, the safe operation area (SOA) and the application range of the switching power supply circuit are limited. The definition of the safe operation area is well known to those skilled in the art and will not be elaborated herein.

[0004] In view of this, the present invention proposes a high-voltage component capable of suppressing the conduction of the parasitic SCR, improving the safe operation area, and further improving the application range and a manufacturing method thereof. Summary of the Invention

[0005] In one aspect, the present invention provides a high-voltage component for use in a power stage of a switching power supply circuit as a lower bridge switch, comprising: at least one Lateral Diffused Metal Oxide Semiconductor (LDMOS) component, which includes: a well region having a first conductivity type, formed in a semiconductor layer; a body region having a second conductivity type, formed in the well region; a gate formed above the body region and connected to the body region; and a source and a drain having the first conductivity type, the source and the drain being respectively located in the body region and the well region below different sides outside the gate; a first isolation region having the second conductivity type, in the semiconductor layer, surrounding the LDMOS component; a second isolation region having the first conductivity type, in the semiconductor layer, surrounding the first isolation region; a third isolation region having the second conductivity type, in the semiconductor layer, surrounding the second isolation region; and a current limiting component electrically connected to the second isolation region for inhibiting the conduction of a parasitic silicon controlled rectifier (SCR); wherein a part of the body region directly below the gate between the source and a boundary of the body region defines an inversion region for serving as an inversion current channel of the LDMOS component during a conduction operation; wherein a part of the well region between the body region and the drain defines a drift region for serving as a drift current channel of the LDMOS component during the conduction operation.

[0006] In another aspect, the present invention provides a method for manufacturing a high-voltage component, where the high-voltage component is used in a power stage of a switching power supply circuit as a lower-bridge switch. The method for manufacturing the high-voltage component includes: forming at least one Lateral Diffused Metal Oxide Semiconductor (LDMOS) component. The step of forming the LDMOS includes: forming a well region in a semiconductor layer, the well region having a first conductivity type; forming a body region in the well region, the body region having a second conductivity type; forming a gate above the body region and connected to the body region; and forming a source and a drain respectively in the body region and the well region below different sides outside the gate, the source and the drain having the first conductivity type; forming a first isolation region in the semiconductor layer, the first isolation region having the second conductivity type and surrounding the LDMOS component; forming a second isolation region in the semiconductor layer, the second isolation region having the first conductivity type and surrounding the first isolation region; forming a third isolation region in the semiconductor layer, the third isolation region having the second conductivity type and surrounding the second isolation region; and forming a current-limiting component electrically connected to the second isolation region to inhibit the conduction of a parasitic silicon controlled rectifier (SCR); wherein a part of the body region directly below the gate between the source and a boundary of the body region defines an inversion region, which is used as an inversion current path of the LDMOS component during a conduction operation; wherein a part of the well region between the body region and the drain defines a drift region, which is used as a drift current path of the LDMOS component during the conduction operation.

[0007] In a preferred embodiment, the current-limiting component includes a Schottky barrier diode (SBD), a resistor component, or a PN diode.

[0008] In a preferred embodiment, when the current-limiting component includes a Schottky barrier diode (SBD), the Schottky barrier diode includes: a Schottky metal unit formed on the second isolation region; and a Schottky semiconductor unit formed in the second isolation region, where the Schottky semiconductor unit and the Schottky metal unit form a Schottky contact, and a part of the second isolation region is used as the Schottky semiconductor unit.

[0009] In a preferred embodiment, the second isolation region is a circular region when viewed from a top view, and a part of the circular region closest to an upper bridge switch in the power stage is used as the Schottky semiconductor cell.

[0010] In a preferred embodiment, the part is at least one quarter of the circular region.

[0011] One advantage of the present invention is that the present invention can suppress the conduction of parasitic SCR, improve the safe operating area, and thus expand the application scope.

[0012] The following is a detailed description through specific embodiments, and it will be easier to understand the purpose, technical content, features and achieved effects of the present invention. Description of the Drawings

[0013] Figure 1 A circuit schematic diagram showing a typical switched-mode power supply circuit.

[0014] Figure 2A It is a top view schematic diagram of a high-voltage component used as a lower bridge switch in the power stage of a switched-mode power supply circuit according to an embodiment of the present invention.

[0015] Figure 2B It is a cross-sectional view schematic diagram of a high-voltage component used as a lower bridge switch in the power stage of a switched-mode power supply circuit according to an embodiment of the present invention.

[0016] Figure 3 It is a cross-sectional view schematic diagram of a high-voltage component used as a lower bridge switch in the power stage of a switched-mode power supply circuit according to another embodiment of the present invention.

[0017] Figure 4 It is a step flow chart showing a method for manufacturing a high-voltage component according to an embodiment of the present invention.

[0018] Symbol Description in the Figures

[0019] 1: Control circuit

[0020] 2: Power stage circuit

[0021] 3: Load circuit

[0022] 10: Switched-mode power supply circuit

[0023] 11, 12: High-voltage components

[0024] 13: Inductor

[0025] 21, 22, 31, 32: High-voltage components

[0026] 40: Method for manufacturing a high-voltage component

[0027] 211, 311: Substrate

[0028] 211’, 311’: Semiconductor layer

[0029] 211a, 311a: Upper surface

[0030] 211b, 311b: Lower surface

[0031] 212, 312: Well region

[0032] 212a, 212b: Drift region

[0033] 213, 223, 313, 323: Silicided metal layer

[0034] 213a, 223a, 313a, 323a: Inversion region

[0035] 214, 224, 314, 324: Drift oxide region

[0036] 215, 225, 315, 325: Body region

[0037] 216, 226, 316, 326: Body electrode

[0038] 217, 227, 317, 327: Gate

[0039] 2171, 2271, 3171, 3271: Dielectric layer

[0040] 2172, 2272, 3172, 3272: Conductive layer

[0041] 2173, 2273, 3173, 3273: Spacer layer

[0042] 218, 228, 318, 328: Source

[0043] 219, 229, 319, 329: Drain

[0044] 220, 320: Insulating structure

[0045] 231, 331: First isolation region

[0046] 232, 332: Second isolation region

[0047] 233, 333: Third isolation region

[0048] 234, 334: Fourth isolation region

[0049] 235, 335: Fifth isolation region

[0050] 236, 336: Sixth Isolation Zone

[0051] 237, 337: High-voltage well region

[0052] 241, 341: First isolation area contact

[0053] 242, 342: Second isolation area contact

[0054] 243, 343: Third isolation zone contact

[0055] 244, 344: Fourth isolation zone contact

[0056] 245, 345: Fifth isolation zone contact

[0057] 246, 346: Sixth isolation zone contact

[0058] 251, 351: Current limiting element

[0059] 252: Schottky semiconductor unit

[0060] 401, 4011, 4012, 4013, 4014, 402, 403, 404, 405: Steps

[0061] B: Distance

[0062] GND: Ground

[0063] IL: inductor current

[0064] LT, LT': Laterally diffused metal oxide semiconductor (LDMOS) devices

[0065] LG: Down bridge signal

[0066] OR3, OR4: Operation area

[0067] PH: Phase Node

[0068] UG: Up bridge signal

[0069] Vin: input voltage

[0070] Vout: output voltage DETAILED DESCRIPTION

[0071] The foregoing and other technical aspects, features, and benefits of the present invention are clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. The accompanying drawings are schematic, primarily intended to illustrate the process steps and the sequential relationship between layers. Shapes, thicknesses, and widths are not drawn to scale.

[0072] Please refer to Figure 2A andFigure 2B , which shows the first embodiment of the present invention. Figure 2A A top view schematic diagram showing the high-voltage element 21 used as the upper-bridge switch and the high-voltage element 22 used as the lower-bridge switch in the power stage of a switching power supply circuit. Figure 2B A cross-sectional schematic diagram showing the high-voltage element 21 used as the upper-bridge switch and the high-voltage element 22 used as the lower-bridge switch in the power stage of a switching power supply circuit. Figure 2B is Figure 2A A cross-sectional schematic diagram obtained along the line A-A' of the operating region OR3 to the operating region OR4 of. As Figure 2A and Figure 2B shown, the high-voltage element 22 used as the lower-bridge switch includes: a Lateral Diffused Metal Oxide Semiconductor (LDMOS) element LT, a Schottky barrier diode (SBD) 251, a first isolation region 231, a second isolation region 232, and a third isolation region 233. The high-voltage element 21 used as the upper-bridge switch includes: a Lateral Diffused Metal Oxide Semiconductor (LDMOS) element LT' and a fourth isolation region 234, a fifth isolation region 235, and a sixth isolation region 236. The LDMOS element LT includes: a well region 212, a drift oxide region 224, a body region 225, a body electrode 226, a gate 227, a source 228, and a drain 229. The LDMOS element LT' includes: a well region 212, a drift oxide region 214, a body region 215, a body electrode 216, a gate 217, a source 218, a drain 219, and a high-voltage well region 237.

[0073] A semiconductor layer 211' is formed on a substrate 211. The semiconductor layer 211' has an upper surface 211a and a lower surface 211b that are opposite in the vertical direction (as Figure 2B shown by the solid arrow direction in, the same below). The substrate 211 is, for example but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 211' is formed on the substrate 211, for example, by an epitaxial process step, or a part of the substrate 211 is used as the semiconductor layer 211'. The manner of forming the semiconductor layer 211' is well known to those skilled in the art and will not be elaborated here.

[0074] Please continue to refer to Figure 2B , the drift oxide regions 224 and 214 are respectively formed on the upper surface 211a and are respectively connected to the upper surface 211a, and are respectively located in the corresponding partial drift regions 212b and 212a (as Figure 2Bdirectly above the areas indicated by the dashed boxes in the LDMOS components LT and LT', and are respectively connected to the corresponding drift regions 212b and 212a. The drift oxide regions 224 and 214 are, for example but not limited to, local oxidation of silicon (LOCOS) structures as shown in the figure, and can also be shallow trench isolation (STI) structures.

[0075] The well region 212 has a first conductivity type and is formed in the semiconductor layer 211'. In the vertical direction, the well region 212 is located below the upper surface 211a and is connected to the upper surface 211a. The well region 212 is formed, for example, by at least one ion implantation process step. The body regions 225 and 215 have a second conductivity type and are respectively formed in the well region 212. In the vertical direction, the body regions 225 and 215 are respectively located below the upper surface 211a and are respectively connected to the upper surface 211a. The body electrodes 226 and 216 have a second conductivity type and are used as electrical contacts for the corresponding body regions 225 and 215 respectively. In the vertical direction, the body electrodes 226 and 216 are respectively formed below the upper surface 211a and are respectively connected to the corresponding body regions 225 and 215 in the upper surface 211a. The gates 227 and 217 are respectively formed on the upper surface 211a of the semiconductor layer 211'. In the vertical direction, parts of the body regions 225 and 215 are respectively located directly below the corresponding gates 227 and 217 and are respectively connected to the corresponding gates 227 and 217 to respectively provide the inversion regions 223a and 213a in the on-operation of the corresponding high-voltage components 22 and 21. The inversion regions 223a and 213a are respectively located directly below the corresponding parts of the gates 227 and 217 and are respectively connected to the corresponding gates 227 and 217.

[0076] Please continue to refer to Figure 2B , the source electrodes 228 and 218 and the drain electrodes 229 and 219 have a first conductivity type. In the vertical direction, the source electrodes 228 and 218 and the drain electrodes 229 and 219 are respectively formed below the upper surface 211a and are respectively connected to the upper surface 211a. The source electrodes 228 and 218 and the drain electrodes 229 and 219 are respectively located in the corresponding body regions 225 and 215 below the corresponding gates 227 and 217 in the channel direction (as indicated by the dashed arrow in the figure, the same below) and in the well regions 212 on the side away from the corresponding body regions 225 and 215. In the channel direction, the drift regions 212b and 212a are respectively located between the corresponding drain electrodes 229 and 219 and the corresponding body regions 225 and 215, in the well regions 212 close to the upper surface 211a, and are used as drift current channels in the on-operation of the LDMOS components LT and LT'.

[0077] It should be noted that the so-called inversion regions 223a and 213a refer to the regions where an inversion layer is formed under the corresponding gates 227 and 217 due to the voltage applied to the corresponding gates 227 and 217 during the conduction operation of the LDMOS elements LT and LT', so that the conduction current can pass through. These regions are between the corresponding sources 228 and 218 and the corresponding drift regions 212b and 212a, which are well-known to those skilled in the art and will not be elaborated here. The same applies to other embodiments of the present invention.

[0078] It should be noted that the first conductivity type and the second conductivity type can be P-type or N-type. When the first conductivity type is P-type, the second conductivity type is N-type; when the first conductivity type is N-type, the second conductivity type is P-type.

[0079] It should be noted that the so-called drift current channel refers to the region where the conduction current passes through in a drifting manner during the conduction operation of the high-voltage elements 21 and 22, which is well-known to those skilled in the art and will not be elaborated here.

[0080] It should be noted that in a preferred embodiment, the gates 227 and 217 respectively include corresponding dielectric layers 2271 and 2171 connected to the upper surface 211a, corresponding conductive layers 2272 and 2172 having conductivity, and corresponding spacer layers 2273 and 2173 having electrical insulation properties. Among them, the dielectric layers 2271 and 2171 are respectively formed on the corresponding body regions 225 and 215 and are respectively connected to the corresponding body regions 225 and 215. The conductive layers 2272 and 2172 are respectively used as the electrical contacts of the corresponding gates 227 and 217, are respectively formed on all the corresponding dielectric layers 2271 and 2171 and are respectively connected to the corresponding dielectric layers 2271 and 2171. The spacer layers 2273 and 2173 are respectively formed on both sides of the corresponding conductive layers 2272 and 2172 to serve as the electrical insulation layers on both sides of the corresponding gates 227 and 217. As Figure 2B shown, the high-voltage well region 237 has the second conductivity type and is formed below the body region 215 and adjacent to the well region 212.

[0081] In addition, it should be noted that the so-called high-voltage element refers to an element in which, during normal operation, the voltage applied to the drain is higher than a specific voltage, such as 5V, and the channel direction distance (the lengths of the drift regions 212b and 212a) between the body regions 225 and 215 and the corresponding drains 229 and 219 is adjusted according to the operating voltage borne during normal operation, so that it can operate at the aforementioned higher specific voltage. All of these are well-known to those skilled in the art and will not be elaborated here.

[0082] Please continue to refer to Figure 2B, the first isolation region 231 has a second conductivity type and surrounds the LDMOS device LT in the semiconductor layer 211'. The second isolation region 232 has a first conductivity type and surrounds the first isolation region 231 in the semiconductor layer 211'. The third isolation region 233 has a second conductivity type and surrounds the second isolation region 232 in the semiconductor layer 211'. The current limiting element 251 is electrically connected to the upper surface 211a of the second isolation region 232 to inhibit the conduction of a parasitic silicon controlled rectifier (SCR), thereby increasing the safe operating area and further expanding the application range. As Figure 2B shown, by providing the current limiting element 251, the parasitic NPN transistor can be prevented from conducting, thereby preventing the SCR from being triggered and inhibiting the conduction of the SCR. In one embodiment, the current limiting element 251 may include a Schottky barrier diode (SBD), a resistive element, or a PN diode. As Figure 2B shown, the distance from the edge of the current limiting element 251 to the edge of the body electrode 216 of the high voltage device 21 is defined as distance B. In one embodiment, distance B is preferably 66 micrometers (μm).

[0083] In one embodiment, when the current limiting element 251 is a Schottky barrier diode (SBD), the Schottky barrier diode includes a Schottky metal unit and a Schottky semiconductor unit 252. The Schottky metal unit is formed on the second isolation region 232, and the Schottky semiconductor unit 252 is formed in the second isolation region 232. The Schottky semiconductor unit 252 forms a Schottky contact with the Schottky metal unit. In one embodiment, a part of the second isolation region 232 is used as the Schottky semiconductor unit 252. In one embodiment, as Figure 2A shown, the second isolation region 232 is viewed as an annular region in a top view, and a part of the region closest to an upper bridge switch in the power stage in the annular region is used as the Schottky semiconductor unit 252, and the second isolation region contact 242 on the second isolation region 232 in this part of the region is replaced with the current limiting element 251, such as but not limited to the Schottky metal unit. The second isolation region contact 242 is still provided under the upper surface of the second isolation region 232 except for this part of the region. In one embodiment, the aforementioned part of the region may be the entire annular region. In another embodiment, the aforementioned part of the region is at least one quarter of the annular region. In a preferred embodiment, the aforementioned part of the region is at least one half of the annular region.

[0084] In one embodiment, the Schottky metal unit is electrically connected to a bias voltage. In a preferred embodiment, the Schottky metal unit is electrically connected to a current output terminal of the power stage circuit. In a preferred embodiment, the Schottky metal unit is electrically connected to the output terminal of the power stage circuit.

[0085] The first isolation region 231 and the third isolation region 233 respectively have corresponding first isolation region contacts 241 and third isolation region contacts 243. In the vertical direction, the first isolation region contact 241 is formed under the upper surface of the first isolation region 231 and is electrically connected to the first isolation region 231, while the third isolation region contact 243 is formed under the upper surface of the third isolation region 233 and is electrically connected to the third isolation region 233. In the vertical direction, corresponding insulating structures 220 are respectively formed between the drain 229 and the first isolation region contact 241, between the first isolation region contact 241 and the current limiting element 251, and between the current limiting element 251 and the third isolation region contact 243, which are formed under the upper surface 211a and are connected to the upper surface 211a.

[0086] Similarly, the sixth isolation region 236 has a first conductivity type and surrounds the high-voltage well region 237 of the LDMOS element LT' in the semiconductor layer 211'. The fifth isolation region 235 has a second conductivity type and surrounds the sixth isolation region 236 in the semiconductor layer 211'. The fourth isolation region 234 has a first conductivity type and surrounds the fifth isolation region 235 and is adjacent to the third isolation region 233 in the semiconductor layer 211'. The fourth isolation region 234, the fifth isolation region 235, and the sixth isolation region 236 respectively have corresponding fourth isolation region contacts 244, fifth isolation region contacts 245, and sixth isolation region contacts 246. In the vertical direction, the fourth isolation region contact 244 is formed under the upper surface of the fourth isolation region 234 and is electrically connected to the fourth isolation region 234, while the fifth isolation region contact 245 is formed under the upper surface of the fifth isolation region 235 and is electrically connected to the fifth isolation region 235. The sixth isolation region contact 246 is formed under the upper surface of the sixth isolation region 236 and is electrically connected to the sixth isolation region 236.

[0087] In the vertical direction, corresponding insulating structures 220 are respectively formed between the body electrode 216 and the sixth isolation region contact 246, between the sixth isolation region contact 246 and the fifth isolation region contact 245, between the fifth isolation region contact 245 and the fourth isolation region contact 244, and between the fourth isolation region contact 244 and the third isolation region contact 243, which are formed under the upper surface 211a and are connected to the upper surface 211a. The high-voltage elements 21 and 22 may further include a substrate 211 having a second conductivity type, covering the bottom surfaces of the well region 212, the first isolation region 231, the second isolation region 232, the third isolation region 233, the fourth isolation region 234, the fifth isolation region 235, the sixth isolation region 236, and the high-voltage well region 237. In one embodiment, in the LDMOS elements LT and LT', the source electrodes 228 and 218 and the body electrodes 226 and 216 are respectively electrically connected by silicided metal layers 223 and 213 as Figure 2B shown.

[0088] It should be noted that one of the technical features of the present invention that is superior to the prior art lies in that, according to the present invention, taking the Figure 2B illustrated embodiment as an example, the high-voltage element 22 includes a current-limiting element 251, which is disposed on the second isolation region 232, can inhibit the conduction of the parasitic SCR, and improve the safe operating region, thereby expanding the application scope.

[0089] Figure 3 FIG. is a cross-sectional schematic view showing a high-voltage element 31 serving as an upper-bridge switch and a high-voltage element 32 serving as a lower-bridge switch in the power stage of a switching power supply circuit according to another embodiment of the present invention. The difference between this embodiment and the Figure 2B embodiment is that the current-limiting element 351 of this embodiment is externally coupled to the second isolation region contact 342. The LDMOS elements LT and LT', the first isolation region 331, the second isolation region 332, the third isolation region 333, the fourth isolation region 334, the fifth isolation region 335, the sixth isolation region 336, the first isolation region contact 341, the second isolation region contact 342, the third isolation region contact 343, the fourth isolation region contact 344, the fifth isolation region contact 345, the sixth isolation region contact 346, and the insulating structure 320 of this embodiment are similar to the Figure 2B LDMOS elements LT and LT', the first isolation region 231, the second isolation region 232, the third isolation region 233, the fourth isolation region 234, the fifth isolation region 235, the sixth isolation region 236, the first isolation region contact 241, the second isolation region contact 242, the third isolation region contact 243, the fourth isolation region contact 244, the fifth isolation region contact 245, the sixth isolation region contact 246, and the insulating structure 220, and thus will not be elaborated. In one embodiment, the current-limiting element 351 may include a Schottky barrier diode (SBD), a resistive element, or a PN diode.

[0090] Figure 4 FIG. is a flowchart showing the steps of a method for manufacturing a high-voltage element according to an embodiment of the present invention. As shown in Figure 4As shown, in the power stage of the switching power supply circuit of the present invention, the manufacturing method 40 of the high-voltage element used as the lower-bridge switch includes step 401 of forming at least one laterally diffused metal oxide semiconductor (LDMOS) element. Step 401 includes steps 4011, 4012, 4013, and 4014. In step 4011, a well region is formed in a semiconductor layer, and the well region has a first conductivity type. Then, in step 4012, a body region is formed in the well region, and the body region has a second conductivity type. After that, in step 4013, a gate is formed above the body region and connected to the body region. Subsequently, in step 4014, a source and a drain are formed in the body region and the well region respectively below different sides outside the gate, and the source and the drain have the first conductivity type. After that, in step 402, a first isolation region is formed in the semiconductor layer, and the first isolation region has a second conductivity type and surrounds the laterally diffused metal oxide semiconductor element. Then, in step 403, a second isolation region is formed in the semiconductor layer, and the second isolation region has a first conductivity type and surrounds the first isolation region. After that, in step 404, a third isolation region is formed in the semiconductor layer, and the third isolation region has a second conductivity type and surrounds the second isolation region. Subsequently, in step 405, a current-limiting element is formed and electrically connected to the second isolation region to inhibit the conduction of a parasitic silicon-controlled rectifier (SCR).

[0091] The present invention has been described above with reference to the preferred embodiments. However, the above description is only for facilitating the understanding of the content of the present invention by those skilled in the art and is not used to limit the scope of the rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. In addition, the described embodiments are not limited to being applied alone and can also be applied in combination. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all the purposes or advantages, and therefore, any item of the claims should not be limited thereto.

Claims

1. A high-voltage component is used in a power stage of a switching power supply circuit as a lower bridge switch and includes: At least one laterally diffused metal oxide semiconductor (LDMOS) device, which includes: A well region having a first conductivity type is formed in a semiconductor layer; A body region having a second conductivity type is formed in the well region; A gate is formed above the body region and connected to the body region; And A source and a drain having the first conductivity type are respectively located in the body region and the well region below different sides outside the gate; A first isolation region having the second conductivity type surrounds the LDMOS device in the semiconductor layer; A second isolation region having the first conductivity type surrounds the first isolation region in the semiconductor layer; A third isolation region having the second conductivity type surrounds the second isolation region in the semiconductor layer; and A current-limiting component is electrically connected to the second isolation region to inhibit the conduction of a parasitic silicon-controlled rectifier; Wherein, a part of the body region directly below the gate between the source and a boundary of the body region defines an inversion region, which is used as an inversion current path of the LDMOS device during a conduction operation; Wherein, a part of the well region between the body region and the drain defines a drift region, which is used as a drift current path of the LDMOS device during the conduction operation; Wherein, when the current-limiting component includes a Schottky barrier diode, the Schottky barrier diode includes: A Schottky metal unit is formed on the second isolation region; and A Schottky semiconductor unit is formed in the second isolation region, wherein the Schottky semiconductor unit and the Schottky metal unit form a Schottky contact, and a part of the second isolation region is used as the Schottky semiconductor unit; Wherein, the second isolation region is a ring-shaped region when viewed from a top view, and a part of the ring-shaped region closest to an upper bridge switch in the power stage is used as the Schottky semiconductor unit.

2. The high-voltage component according to claim 1, wherein, This part of the region is at least one-fourth of the ring-shaped region.

3. A method for manufacturing a high-voltage component, wherein, The high-voltage component is used in a power stage of a switching power supply circuit as a lower bridge switch, and a manufacturing method of the high-voltage component includes: Forming at least one LDMOS device, and the steps of forming the LDMOS device include: Forming a well region in a semiconductor layer, the well region having a first conductivity type; Forming a body region in the well region, the body region having a second conductivity type; Forming a gate above the body region and connected to the body region; and Forming a source and a drain respectively located in the body region and the well region below different sides outside the gate, the source and the drain having the first conductivity type; Forming a first isolation region in the semiconductor layer, the first isolation region having the second conductivity type and surrounding the LDMOS device; Forming a second isolation region in the semiconductor layer, the second isolation region having the first conductivity type and surrounding the first isolation region; Form a third isolation region in the semiconductor layer. The third isolation region has the second conductivity type and surrounds the second isolation region; and Form a current limiting element electrically connected to the second isolation region to inhibit the conduction of a parasitic silicon controlled rectifier; Wherein, a part of the body region directly under the gate between the source and a boundary of the body region defines an inversion region, which is used as an inversion current channel of the laterally diffused metal oxide semiconductor device during a conduction operation; Wherein, a part of the well region between the body region and the drain defines a drift region, which is used as a drift current channel of the laterally diffused metal oxide semiconductor device during the conduction operation; Wherein, when the current limiting element includes a Schottky barrier diode, the Schottky barrier diode includes: A Schottky metal unit formed on the second isolation region; and A Schottky semiconductor unit formed in the second isolation region. The Schottky semiconductor unit forms a Schottky contact with the Schottky metal unit, and a part of the second isolation region is used as the Schottky semiconductor unit; Wherein, the second isolation region is a ring-shaped region when viewed from a top view, and a part of the region in the ring-shaped region closest to an upper bridge switch in the power stage is used as the Schottky semiconductor unit.

4. The method for manufacturing a high-voltage component according to claim 3, wherein, This part of the region is at least one quarter of the ring-shaped region.

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