LDMOS structure, design layout and manufacturing method thereof

Abstract

An LDMOS structure, its design layout, and manufacturing method are disclosed. The structure includes: a semiconductor substrate; a buried layer of a first doped type located within the semiconductor substrate; a well region of a second doped type located within the buried layer; and a drain region of a first doped type completely surrounding the well region located within the buried layer. In the channel direction parallel to the LDMOS structure, the buried layer within the drain region is divided into two parts by undoped buried regions. In the channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner sides of the drain regions. This invention can effectively improve the bottom volume (BV) of the device and enhance the quality of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS structure, its design layout, and manufacturing method. Background Technology

[0002] With the rapid development of the semiconductor industry, power integrated circuits (PICs) are increasingly being used in various fields, such as motor control, flat panel display driver control, and computer peripheral driver control.

[0003] Among various power devices, the Lateral Double Diffused MOSFET (LDMOS) is an example. It has the characteristics of high operating voltage, simple process, and easy process compatibility with low-voltage Complementary Metal Oxide Semiconductor (CMOS) circuits, and therefore has received widespread attention.

[0004] However, in the existing technology, the breakdown voltage (BV) of semiconductor devices, including LDMOS, needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an LDMOS structure, its design layout, and manufacturing method, which can effectively improve the BV of the device and enhance the quality of semiconductor devices.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide an LDMOS structure, comprising: a semiconductor substrate; a buried layer of a first doped type located within the semiconductor substrate; a well region of a second doped type located within the buried layer; and a drain region of a first doped type that completely surrounds the well region located within the buried layer; wherein, in the channel direction parallel to the LDMOS structure, the buried layer located within the drain region is divided into two parts by undoped buried regions; and in the channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner side of the drain region.

[0007] Optionally, the undoped buried region is in contact with the well region but does not overlap.

[0008] Optionally, the cross-sectional shape of the drain region is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is referred to as the first drain region; wherein, the undoped buried region is flush with the inner side of the first drain region.

[0009] Optionally, the rectangular border of the other two rectangular borders of the drain region that is adjacent to the channel of the LDMOS structure is designated as the second drain region; the distance between the undoped buried region and the second drain region is less than or equal to a preset distance.

[0010] Optionally, the first doping type is N-type and the second doping type is P-type.

[0011] Optionally, the dopant ion in the well region of the second doping type is a boron ion; the doping parameters of the well region of the second doping type satisfy one or more of the following: the doping dose of the well region of the second doping type is selected from: 5e11~5e12cm -2 The doping depth of the well region of the second doping type is selected from 0.5~2um.

[0012] Optionally, the LDMOS structure further includes: a gate structure located on the surface of the semiconductor substrate; wherein the undoped buried region is located below a portion of the gate structure.

[0013] To address the aforementioned technical problems, this invention provides a design layout for an LDMOS structure, comprising: a buried layer layout including a buried layer pattern; a well region layout including a well region pattern located within the buried layer pattern; and a drain region layout including a drain region pattern located within the buried layer pattern and completely surrounding the well region pattern. Specifically, in the channel direction parallel to the LDMOS structure, the buried layer pattern within the drain region pattern is divided into two parts by an undoped buried region pattern; in the channel direction perpendicular to the LDMOS structure, the undoped buried region patterns are flush with the inner side of the drain region pattern.

[0014] Optionally, the undoped buried region pattern is in contact with the well region pattern but does not overlap.

[0015] Optionally, the cross-sectional shape of the drain region pattern is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, denoted as the first drain region pattern; wherein, the inner side of the undoped buried region pattern is flush with the inner side of the first drain region pattern.

[0016] Optionally, the rectangular border of the other two rectangular borders of the drain region pattern that is adjacent to the channel of the LDMOS structure is denoted as the second drain region pattern; the distance between the undoped buried region pattern and the second drain region pattern is less than or equal to a preset distance.

[0017] Optionally, the design layout of the LDMOS structure further includes: a gate structure layout, comprising a gate structure pattern; wherein the undoped buried region pattern is located in the area covered by a portion of the gate structure pattern.

[0018] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing an LDMOS structure, comprising: providing a semiconductor substrate; forming a buried layer of a first doping type within the semiconductor substrate; forming a well region of a second doping type within the buried layer; forming a drain region of a first doping type within the buried layer that completely surrounds the well region; wherein, in a channel direction parallel to the LDMOS structure, the buried layer located within the drain region is divided into two parts by undoped buried regions; and in a channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner side of the drain region.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0020] In this embodiment of the invention, by dividing the buried layer in the drain region into two parts by an undoped buried region in the channel direction parallel to the LDMOS structure, and by aligning the undoped buried regions with the inner side of the drain region in the channel direction perpendicular to the LDMOS structure, the size of the undoped buried region can be maximized in the channel direction perpendicular to the LDMOS structure, thereby suppressing breakdown between the well region and the buried layer, especially suppressing breakdown between the well region edge and the buried layer on the side adjacent to the channel, thus effectively improving the BV of the device and enhancing the quality of the semiconductor device.

[0021] Furthermore, the undoped buried region is in contact with the well region but does not overlap, thereby maximizing the size of the undoped buried region at the edge of the well region on the side adjacent to the channel, reducing the contact between the well region and the buried region, and thus more effectively improving the device's BV.

[0022] Furthermore, the cross-sectional shape of the drain region is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is denoted as the first drain region. The undoped buried region is flush with the inner side of the first drain region. Compared with other shapes (such as rounded rectangles, polygons, etc.), the size of the undoped buried region can be maximized in areas prone to breakdown, reducing the contact between the well region and the buried region, thereby more effectively improving the BV of the device.

[0023] Furthermore, the rectangular border adjacent to the channel of the LDMOS structure among the other two rectangular borders of the drain region is designated as the second drain region; the distance between the undoped buried region and the second drain region is less than or equal to a preset distance. This allows for maximizing the size of the undoped buried region and further reducing the contact between the well region and the buried region.

[0024] Furthermore, the undoped buried region is located below a portion of the gate structure, thereby suppressing breakdown between the well region and the buried layer while reducing the impact on other electrical properties of the LDMOS structure. Attached Figure Description

[0025] Figure 1 This is a flowchart of a method for manufacturing an LDMOS structure according to an embodiment of the present invention;

[0026] Figure 2 This is a design layout of an LDMOS structure according to an embodiment of the present invention;

[0027] Figure 3 yes Figure 2 The diagram shows a cross-sectional view of an LDMOS structure.

[0028] Figure label:

[0029] Buried layer pattern 1110; well region pattern 1120; source region pattern 1131; drain region pattern 1132; undoped buried region pattern 1140; gate structure pattern 1150; semiconductor substrate 2100; buried layer 2110; well region 2120; source region 2131; drain region 2132; undoped buried region 2140; gate structure 2150. Detailed Implementation

[0030] Among various power devices, LDMOS high-voltage devices, for example, have attracted widespread attention due to their high operating voltage, simple manufacturing process, and ease of compatibility with low-voltage CMOS circuits. However, in existing technologies, the basis voltage (BV) of semiconductor devices, including LDMOS, needs to be improved.

[0031] The inventors of this invention discovered through research that, in the prior art, breakdown between the well region and the buried layer is easily formed in the direction perpendicular to the channel direction of the LDMOS structure. In particular, breakdown is prone to occur between the edge of the well region and the buried layer on the side adjacent to the channel, resulting in a more serious BV problem in the device structure.

[0032] In this embodiment of the invention, by dividing the buried layer in the drain region into two parts by an undoped buried region in the channel direction parallel to the LDMOS structure, and by aligning the undoped buried regions with the inner side of the drain region in the channel direction perpendicular to the LDMOS structure, the size of the undoped buried region can be maximized in the channel direction perpendicular to the LDMOS structure, thereby suppressing breakdown between the well region and the buried layer, especially suppressing breakdown between the well region edge and the buried layer on the side adjacent to the channel, thus effectively improving the BV of the device and enhancing the quality of the semiconductor device.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Reference Figure 1 , Figure 1 This is a flowchart of a method for manufacturing an LDMOS structure according to an embodiment of the present invention. The method for manufacturing the LDMOS structure may include steps S11 to S15:

[0035] Step S11: Provide a semiconductor substrate;

[0036] Step S12: Form a buried layer of the first doping type in the semiconductor substrate;

[0037] Step S13: Form a well region of the second doped type within the buried layer;

[0038] Step S14: Within the buried layer, a first doped drain region is formed that completely surrounds the well region, wherein, in the channel direction parallel to the LDMOS structure, the buried layer located within the drain region is divided into two parts by undoped buried regions, and in the channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner side of the drain region.

[0039] The following is combined with Figures 2 to 3 The steps described above will be explained.

[0040] Figure 2 This is a design layout of an LDMOS structure according to an embodiment of the present invention. Figure 3 yes Figure 2 The diagram shown is a cross-sectional view of an LDMOS structure. Figure 3 yes Figure 2 A cross-sectional view along cutting lines A1-A2.

[0041] The design layout of the LDMOS structure may include a buried layer layout, including a buried layer pattern 1110; a well region layout, including a well region pattern 1120, the well region pattern 1120 being located within the buried layer pattern 1110; and a drain region layout, including a drain region pattern 1132, the drain region pattern 1132 being located within the buried layer pattern 1110 and completely surrounding the well region pattern 1120; wherein, in the channel direction parallel to the LDMOS structure, the buried layer pattern 1110 located within the drain region pattern 1132 is divided into two parts by an undoped buried region pattern 1140; in the channel direction perpendicular to the LDMOS structure, the undoped buried region pattern 1140 is flush with the inner side of the drain region pattern 1132.

[0042] It should be noted that the design layout of the LDMOS structure may also include a source region layout, which includes a source region pattern 1131, and the source region pattern 1131 is located within the well region pattern 1120.

[0043] In a non-limiting manner, the same ion implantation process can be used to form the source and drain regions during the formation of the LDMOS structure. In this case, the source and drain layouts can be combined into a single layout.

[0044] In specific implementation, the layer structure of the LDMOS structure is obtained based on the design layout of the LDMOS structure. The LDMOS structure may include: a semiconductor substrate 2100; a first-doped buried layer 2110 located within the semiconductor substrate 2100; a second-doped well region 2120 located within the buried layer 2110; and a first-doped drain region 2132 that completely surrounds the well region 2120 located within the buried layer 2110. In the channel direction parallel to the LDMOS structure, the buried layer 2110 located within the drain region is divided into two parts by an undoped buried region 2140. In the channel direction perpendicular to the LDMOS structure, the undoped buried regions 2140 are flush with the inner side of the drain region 2132.

[0045] It should be noted that the LDMOS structure may further include a source region 2131 of a first doping type, located within the well region 2120.

[0046] Non-limitingly, the buried layer 2110 can be formed using ion implantation or epitaxial growth. It is understood that the buried layer 2110 is not formed in the undoped buried region.

[0047] Non-limiting, ion implantation can be used to form the well region 2120, source region 2131, drain region 2132, etc.

[0048] The channel direction can be the carrier flow direction between the source region 2131 and the drain region 2132 below the gate structure 2150, such as... Figure 2 The direction of the cutting lines A1-A2 in the figure. The gate structure 2150 is shown as a dotted line in the figure.

[0049] The semiconductor substrate 2100 may be a silicon substrate, or the material of the semiconductor substrate 2100 may include germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 2100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate with an epitaxy layer (Epi layer) grown on it.

[0050] In this embodiment of the invention, by dividing the buried layer 2110 within the drain region 2132 into two parts by undoped buried regions 2140 in the channel direction parallel to the LDMOS structure, and by aligning the undoped buried regions 2140 with the inner side of the drain region 2132 in the channel direction perpendicular to the LDMOS structure, the size of the undoped buried regions 2140 can be maximized in the channel direction perpendicular to the LDMOS structure, thereby suppressing breakdown between the well region 2120 and the buried layer 2110, especially suppressing breakdown between the edge of the well region 2120 and the buried layer 2110 on the side adjacent to the channel (e.g., Figure 2 (The direction indicated by the double-headed arrow in the middle), thereby effectively improving the BV of the device and enhancing the quality of the semiconductor device.

[0051] Furthermore, the undoped buried region pattern 1140 is in contact with the well region pattern 1120 but does not overlap.

[0052] In specific implementation, the structure of each layer of the LDMOS structure is obtained based on the design layout of the LDMOS structure, and the undoped buried region 2140 is in contact with the well region 2120 but does not overlap.

[0053] In this embodiment of the invention, the undoped buried region 2140 is in contact with the well region 2120 but does not overlap, thereby allowing the size of the undoped buried region 2140 to be maximized at the edge of the well region 2120 on the side adjacent to the channel, reducing the contact between the well region 2120 and the buried region 2110, thereby more effectively improving the BV of the device.

[0054] Furthermore, the cross-sectional shape of the drain pattern 1132 is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is denoted as the first drain pattern; wherein, the undoped buried region pattern 1140 is flush with the inner side of the first drain pattern.

[0055] In specific implementation, the layer structure of the LDMOS structure is obtained based on the design layout of the LDMOS structure. The cross-sectional shape of the drain region 2132 is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is denoted as the first drain region. The undoped buried region 2140 is flush with the inner side of the first drain region.

[0056] It should be noted that the cross-sectional shape of the leak area 2132 can also be a rounded rectangle, a polygon (e.g., an octagon), etc.

[0057] In this embodiment of the invention, the cross-sectional shape of the drain region 2132 is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is referred to as the first drain region. The undoped buried region 2140 is flush with the inner side of the first drain region. Compared with other shapes (such as rounded rectangles, polygons, etc.), the size of the undoped buried region 2140 can be increased as much as possible in the area where breakdown is likely to occur, reducing the contact between the well region 2120 and the buried region 2110, thereby more effectively improving the BV of the device.

[0058] Furthermore, the rectangular border of the other two rectangular borders of the drain region pattern 1132 that is adjacent to the channel of the LDMOS structure is denoted as the second drain region pattern; the distance between the undoped buried region pattern 1140 and the second drain region pattern is less than or equal to a preset distance.

[0059] In specific implementation, the structure of each layer of the LDMOS structure is obtained based on the design layout of the LDMOS structure. The rectangular border of the other two rectangular borders of the drain region 2132 that is adjacent to the channel of the LDMOS structure is denoted as the second drain region. The distance between the undoped buried region 2140 and the second drain region is less than or equal to a preset distance.

[0060] In this embodiment of the invention, the rectangular border adjacent to the channel of the LDMOS structure among the other two rectangular borders of the drain region 2132 is designated as the second drain region; the distance between the undoped buried region 2140 and the second drain region is less than or equal to a preset distance. This allows the size of the undoped buried region 2140 to be maximized, further reducing the contact between the well region 2120 and the buried region 2110.

[0061] In a specific implementation, the first doping type can be N-type and the second doping type can be P-type, thereby forming an N-type LDMOS structure. Since the N-type LDMOS structure is more sensitive to BV, the improvement of the N-type LDMOS structure in this embodiment of the invention helps to further improve the effectiveness of the invention.

[0062] As a non-limiting example, the dopant ion of the well region 2120 of the second doping type can be boron ions; the doping parameters of the well region 2120 of the second doping type can satisfy one or more of the following: the doping dose of the well region 2120 of the second doping type is selected from: 5e11~5e12cm -2 The doping depth of the well region 2120 of the second doping type is selected from 0.5~2um.

[0063] In this embodiment of the invention, by setting an appropriate doping dose and doping depth for the well region 2120 of the second doping type, it is helpful to suppress the breakdown between the well region 2120 and the buried layer 2110 while setting an appropriate size for the undoped buried region 2140, and reduce the impact on other electrical properties of the LDMOS structure.

[0064] Furthermore, the design layout of the LDMOS structure may also include: a gate structure layout, including a gate structure pattern 1150; wherein the undoped buried region pattern 1140 is located in a region covered by a portion of the gate structure pattern 1150.

[0065] In a specific implementation, the layer structure of the LDMOS structure can be obtained based on the design layout of the LDMOS structure. The LDMOS structure may also include: a gate structure 2150 located on the surface of the semiconductor substrate 2100; wherein the undoped buried region 2140 is located below a portion of the gate structure 2150.

[0066] In this embodiment of the invention, the undoped buried region 2140 is located below a portion of the gate structure 2150, thereby suppressing breakdown between the well region 2120 and the buried layer 2110 while reducing the impact on other electrical properties of the LDMOS structure.

[0067] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0068] In the embodiments of this application, "multiple" refers to two or more.

[0069] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0070] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An LDMOS structure, characterized in that, include: Semiconductor substrate; A first type of doped buried layer is located within the semiconductor substrate; A second type of doped well region is located within the buried layer; A first-doped drain region that completely surrounds the well region is located within the buried layer; In the channel direction parallel to the LDMOS structure, the buried layer located in the drain region is divided into two parts by an undoped buried region; In the channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner side of the drain regions.

2. The LDMOS structure according to claim 1, characterized in that, The undoped buried region is in contact with the well region but does not overlap.

3. The LDMOS structure according to claim 1, characterized in that, The cross-sectional shape of the drain region is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is denoted as the first drain region. The undoped buried region is flush with the inner side of the first drain region.

4. The LDMOS structure according to claim 3, characterized in that, The rectangular border of the other two rectangular borders of the drain region that is adjacent to the channel of the LDMOS structure is denoted as the second drain region. The distance between the undoped buried region and the second drain region is less than or equal to a preset distance to increase the size of the undoped buried region and reduce the contact between the well region and the buried region.

5. The LDMOS structure according to claim 1, characterized in that, The first doping type is N-type, and the second doping type is P-type.

6. The LDMOS structure according to claim 1, characterized in that, The dopant ions in the well region of the second doping type are boron ions; The doping parameters of the well region of the second doping type satisfy one or more of the following: The doping dose of the well region of the second doping type is selected from 5e11~5e12cm. -2 ; The doping depth of the well region of the second doping type is selected from 0.5~2um.

7. The LDMOS structure according to claim 1, characterized in that, Also includes: A gate structure is located on the surface of the semiconductor substrate; The undoped buried region is located below a portion of the gate structure.

8. A design layout of an LDMOS structure as described in any one of claims 1 to 7, characterized in that, include: Buried layer map, including buried layer graphics; A well area layout, including a well area graphic, wherein the well area graphic is located within the buried layer graphic; A leak area map, including a leak area graphic, wherein the leak area graphic is located within the buried layer graphic and completely surrounds the trap area graphic; In the channel direction parallel to the LDMOS structure, the buried layer pattern located within the drain region pattern is divided into two parts by the undoped buried region pattern. In the channel direction perpendicular to the LDMOS structure, the undoped buried region pattern is flush with the inner side of the drain region pattern.

9. The design layout of the LDMOS structure according to claim 8, characterized in that, The undoped buried region pattern is in contact with the well region pattern but does not overlap.

10. The design layout of the LDMOS structure according to claim 8, characterized in that, The cross-sectional shape of the drain region pattern is a rectangular frame, and the extension direction of the two opposite rectangular frames is parallel to the channel direction of the LDMOS structure, which is denoted as the first drain region pattern. The undoped buried region pattern is flush with the inner side of the first drain region pattern.

11. The design layout of the LDMOS structure according to claim 10, characterized in that, The rectangular border of the other two rectangular borders of the drain region pattern that is adjacent to the channel of the LDMOS structure is denoted as the second drain region pattern. The distance between the undoped buried region pattern and the second drain region pattern is less than or equal to a preset distance to increase the size of the undoped buried region and reduce the contact between the well region and the buried region.

12. The design layout of the LDMOS structure according to claim 8, characterized in that, Also includes: Gate structure layout, including gate structure pattern; The undoped buried region pattern is located in the area covered by a portion of the gate structure pattern.

13. A method for manufacturing an LDMOS structure as described in any one of claims 1 to 7, characterized in that, include: Provide semiconductor substrates; A buried layer of a first doping type is formed within the semiconductor substrate; A second type of doped well region is formed within the buried layer; Within the buried layer, a first-doped type drain region is formed that completely surrounds the well region; In the channel direction parallel to the LDMOS structure, the buried layer located in the drain region is divided into two parts by an undoped buried region; In the channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner side of the drain regions.

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