Lateral diffused metal oxide semiconductor device and method of manufacturing the same

Abstract

This invention relates to a laterally diffused metal-oxide-semiconductor (MOS) device and its manufacturing method. The MOS device includes: a substrate; a drift region disposed in the substrate; a drain region disposed in the substrate and in contact with the drift region; a body region disposed in the substrate; an insulating layer at least partially disposed in the body region; a source region located on the insulating layer; and a gate structure disposed on the substrate between the drain region and the source region. This invention, by forming isolation between the source region and the body region through the insulating layer, can mitigate the parasitic effects caused by the conduction of the PN junction formed between the source and body regions, reduce losses, and improve device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a laterally diffused metal-oxide-semiconductor device, and also to a method for manufacturing a laterally diffused metal-oxide-semiconductor device. Background Technology

[0002] In laterally diffused metal-oxide-semiconductor (LDMOS) devices, the presence of parasitic BJTs (bipolar junction transistors) can cause leakage current in practical applications due to the freewheeling current in the body diode, leading to the activation of the parasitic BJTs and affecting device performance. Summary of the Invention

[0003] Therefore, it is necessary to provide a laterally diffused metal-oxide-semiconductor device that can avoid the parasitic BJT from being turned on due to the conduction of the PN junction formed in the source region and the body region.

[0004] A laterally diffused metal-oxide-semiconductor device includes: a substrate; a drift region disposed in the substrate; a drain region disposed in the substrate and in contact with the drift region; a body region disposed in the substrate; an insulating layer at least partially disposed in the body region; a source region located on the insulating layer; and a gate structure disposed on the substrate between the drain region and the source region.

[0005] The aforementioned laterally diffused metal-oxide-semiconductor devices, through the isolation formed between the source and body regions by the insulating layer, can mitigate the parasitic effects caused by the conduction of the PN junction formed between the source and body regions, reduce losses, and improve device performance.

[0006] In one embodiment, one side of the gate structure is located on the drift region, and the other side of the gate structure is located on the body region.

[0007] In one embodiment, the drift region, drain region, and source region have a first conductivity type, and the substrate and body region have a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types.

[0008] In one embodiment, the system further includes a body lead-out region located within the body region. The conductivity type of the body lead-out region is the same as that of the body region and opposite to that of the source region. The doping concentration of the body lead-out region is greater than that of the body region. The source region is disposed within the body region, and the insulating layer is located between the body lead-out region and the source region.

[0009] In one embodiment, the insulating layer is made of silicon oxide.

[0010] In one embodiment, the source region is a strained silicon layer.

[0011] In one embodiment, the substrate further includes: a second conductivity type doped region disposed in the substrate, wherein the drift region is located between the second conductivity type doped region and the bulk region; and a substrate lead-out region disposed in the second conductivity type doped region, having a second conductivity type, wherein the doping concentration of the substrate lead-out region is greater than the doping concentration of the second conductivity type doped region.

[0012] It is also necessary to provide a method for manufacturing a laterally diffused metal-oxide-semiconductor device.

[0013] A method for manufacturing a laterally diffused metal-oxide-semiconductor device includes: obtaining a substrate in which a body region and a drift region are formed; removing a portion of the body region to form a groove; forming an insulating layer in the groove; forming a source region on the insulating layer; forming a gate structure and a drain region; wherein the drain region is in contact with the drift region, and the gate structure is disposed on the substrate between the drain region and the source region.

[0014] The laterally diffused metal-oxide-semiconductor device formed by the above-mentioned manufacturing method can reduce the parasitic effects caused by the conduction of the PN junction formed in the source and body regions by forming an isolation between the source and body regions through the insulating layer, thereby reducing losses and improving device performance.

[0015] In one embodiment, after the step of forming an insulating layer in the groove and before the step of forming a source region on the insulating layer, the method further includes a step of etching a portion of the insulating layer to expose a body region beneath the insulating layer; the step of forming the source region on the insulating layer involves etching the remaining insulating layer to form the source region; the manufacturing method further includes a step of forming a body lead-out region at the location of the exposed body region; the conductivity type of the body lead-out region is the same as that of the body region and opposite to that of the source region, the doping concentration of the body lead-out region is greater than that of the body region, and the insulating layer is located between the body lead-out region and the source region.

[0016] In one embodiment, the step of forming an insulating layer in the groove is to thermally oxidize and grow silicon oxide as the insulating layer.

[0017] In one embodiment, the step of forming the source region on the insulating layer is to epitaxially form the source region on the etched remaining insulating layer using strained silicon technology.

[0018] In one embodiment, the step of forming a body lead-out region at the exposed body region location precedes the step of epitaxially forming the source region on the etched remaining insulating layer using strained silicon technology. Attached Figure Description

[0019] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0020] Figure 1 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device in one embodiment;

[0021] Figure 2 This is a flowchart of a method for manufacturing a laterally diffused metal-oxide-semiconductor device in one embodiment;

[0022] Figures 3a to 3d Is adopted Figure 2 The diagram shows a cross-sectional view of the device during the manufacturing process of the laterally diffused metal-oxide-semiconductor device. Detailed Implementation

[0023] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0029] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0030] Traditional LDMOS structures form the P-body and source regions through double diffusion, resulting in relatively simple fabrication. However, in circuit applications, the PN junction in this region (the PN junction formed by the P-body and source regions) easily generates a voltage drop. When this voltage drop exceeds 0.7V, the PN junction conducts, causing the parasitic NPN junction to turn on, resulting in parasitic effects and unnecessary losses, thus affecting device performance. This application addresses this by growing an additional oxide layer after the P-body region is formed, and then forming the source region on this oxide layer. This achieves excellent isolation in the P-body region, reducing parasitic effects, minimizing losses, and improving device performance.

[0031] Figure 1 This is a schematic diagram of a laterally diffused metal-oxide-semiconductor (MOSFET) device in one embodiment. The MOSFET includes a substrate 110, a drift region 120, a drain region 122, a gate structure 160, a body region 130, an insulating layer 140, and a source region 124. The drift region 120 and the body region 130 are disposed within the substrate 110. The gate structure 160 is disposed on the substrate 110. The gate structure 160 includes a gate dielectric layer and a gate layer on the gate dielectric layer. The drain region 122 is disposed in the substrate 110 on one side of the gate structure 160. Figure 1In the illustrated embodiment, the drain region 122 is disposed in the substrate 110 on the right side of the gate structure 160, and is in contact with the drift region 120, which is also in contact with the gate structure 160. In one embodiment of this application, the drain region 122 is disposed in the drift region 120. The insulating layer 140 is disposed in the substrate 110 on the other side of the gate structure 160. Figure 1 In the illustrated embodiment, the gate structure 160 is disposed in the substrate 110 to the left of the gate structure 160, and the insulating layer 140 is at least partially disposed in the body region 130. The source region 124 is disposed on the insulating layer 140 and also contacts the gate structure 160. Figure 1 In the embodiment shown, the source region 124 is disposed in the body region 130.

[0032] The aforementioned laterally diffused metal-oxide-semiconductor device, through the insulating layer 140 forming isolation between the source region 124 and the body region 130, can mitigate the parasitic effects caused by the conduction of the PN junction formed between the source region 124 and the body region 130, reduce losses, and improve device performance. Since the on-state voltage drop of the PN junction formed between the source and body regions in traditional LDMOS is mainly due to the longitudinal drift of charge carriers, placing the insulating layer 140 below the source region 124 can achieve a better effect in blocking the conduction of the PN junction between the source region 124 and the body region 130.

[0033] In one embodiment of this application, the substrate 110 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 1 In the illustrated embodiment, the substrate 110 is made of monocrystalline silicon. Isolation structures such as STI (shallow trench isolation) may also be formed in the substrate 110.

[0034] In one embodiment, the substrate 110 and body region 130 have a second conductivity type, and the drift region 120, drain region 122, and source region 124 have a first conductivity type. In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0035] The substrate for laterally diffused metal-oxide-semiconductor (MOS) devices can be either a P-type or N-type semiconductor substrate. For example, N-type high-voltage devices can use a P-type semiconductor substrate, while P-type high-voltage devices can use an N-type semiconductor substrate. Figure 1 In the illustrated embodiment, substrate 110 is a P-type semiconductor substrate. In other embodiments, substrate 110 may also be a P-type epitaxial layer on the upper surface of a silicon wafer.

[0036] Depending on the specific type of LDMOS device, drift region 120 has different conductivity types. For example, if the LDMOS device is an N-type LDMOS device, then drift region 120 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, then drift region 120 is a P-type drift region. Figure 1 In the illustrated embodiment, drift region 120 is an N-type drift region. Generally, the doping concentration of drift region 120 is low, lower than that of drain region 122 and source region 124. This is equivalent to forming a region with higher resistance between the source and drain, which can improve the breakdown voltage and reduce the parasitic capacitance between the source and drain, thus improving the frequency characteristics of the device.

[0037] In one embodiment of this application, the gate dielectric layer of the gate structure 160 may include conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0038] In one embodiment of this application, the gate layer of the gate structure 160 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate layer.

[0039] In one embodiment of this application, the insulating layer 140 is a buried oxide layer, and its material is silicon oxide, such as silicon dioxide. The device forms a sandwich structure of silicon-oxide-silicon (source region 124-insulating layer 140-body region 130) at the source region 124 to block the parasitic effects caused by the conduction of the N+ region (source region 124) and the body region 130 diode.

[0040] exist Figure 1 In the illustrated embodiment, the laterally diffused metal-oxide-semiconductor device further includes a body lead-out region 132 located in the body region 130. The body lead-out region 132 has a second conductivity type, and the doping concentration of the body lead-out region 132 is greater than the doping concentration of the body region 130. Figure 1In the illustrated embodiment, the body lead-out region 132 is a P+ region. The insulating layer 140 is located between the body lead-out region 132 and the source region 124. A back-biased gate structure can be formed through the body lead-out region 132 (bulk lead-out), which enhances the control of the channel and makes the channel strongly inverted, thereby allowing the threshold voltage of the device to be adjusted while shielding leakage current.

[0041] exist Figure 1 In the illustrated embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second conductivity type doped region 150 and a substrate lead-out region 152. The second conductivity type doped region 150 is disposed in the substrate 110, and a drift region 120 is located between the second conductivity type doped region 150 and the body region 130. The substrate lead-out region 152 is disposed in the second conductivity type doped region 150. The substrate lead-out region 152 has a second conductivity type, and its doping concentration is greater than that of the second conductivity type doped region 150. In other embodiments, the substrate lead-out region 152 has a second conductivity type, and its doping concentration is greater than that of the second conductivity type doped region 150 but less than that of the body lead-out region 132.

[0042] In one embodiment of this application, the laterally diffused metal-oxide-semiconductor device further includes an interlayer dielectric layer. The recess in the body region 130 (located on the body lead-out region 132) is filled by the interlayer dielectric layer. In one embodiment of this application, the interlayer dielectric may be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (CVD) or high-density plasma (HDP) fabrication processes, specifically undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or boron phosphosilicate glass (BPSG). Alternatively, the interlayer dielectric may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS).

[0043] This application provides a method for manufacturing a laterally diffused metal-oxide-semiconductor device, which can be used to manufacture the laterally diffused metal-oxide-semiconductor device described in any of the foregoing embodiments.

[0044] Figure 2 This is a flowchart of a method for manufacturing a laterally diffused metal-oxide-semiconductor device in one embodiment, including the following steps:

[0045] S210, Obtain the substrate.

[0046] A drift region 120 and a body region 130 are formed in a substrate 110. The substrate 110 and the drift region 120 have a first conductivity type, and the body region 130 has a second conductivity type. In this embodiment, the drift region 120 and the body region 130 are spaced apart to improve the overall breakdown voltage (BV) of the device. In other embodiments, the drift region 120 and the body region 130 are arranged adjacent to each other. Although the breakdown voltage (BV) of the device is lower when arranged adjacently compared to when spaced apart, the device size can be reduced.

[0047] S220, a portion of the body area is removed to form a groove.

[0048] Subsequent manufacturing steps involve forming an insulating layer 140 and a source region 124 in the body region 130. Therefore, step S220 removes the body region 130 at the locations where the insulating layer 140 and the source region 124 need to be formed. Specifically, the area to be removed on the upper part of the body region 130 can be etched away using photolithography and etching.

[0049] S230, forming an insulating layer within the groove.

[0050] Reference Figure 3a In one embodiment of this application, a silicon oxide layer (e.g., silicon dioxide) can be grown within the groove etched in step S220 using a thermal oxidation process, serving as a buried oxide layer. The thermal oxidation temperature is high, thus simultaneously performing high-temperature push-well operation on the drift region 120 and the body region 130. In one embodiment of this application, thermal oxidation can be performed using a high-temperature furnace tube. After obtaining the desired oxide layer thickness through thermal oxidation, if the push-well operation does not reach the required junction depth, an additional push-well operation can be performed. Compared to first pushing-well the drift region 120 and the body region 130 and then thermally oxidizing to grow the oxide layer, this method facilitates more effective diffusion of doping in the body region 130 and promotes the formation of a better oxide layer and better isolation. In other embodiments, a silicon oxide layer is formed within the groove by deposition, followed by high-temperature push-well operation on the drift region 120 and the body region 130 to ensure that the depth of the drift region 120 and the body region 130 meets the device withstand voltage requirements.

[0051] S240 forms the source region on the insulating layer.

[0052] In one embodiment of this application, before step S240, it is necessary to etch a portion of the insulating layer 140 to expose the body region 130 beneath the insulating layer 140, such as... Figure 3b As shown. After etching, a body lead-out region 132 is formed at the exposed location of the body region 130, as shown. Figure 3cAs shown. The body lead-out region 132 can be formed by doping (e.g., ion implantation). In one embodiment of this application, the body lead-out region 132 has a second conductivity type and is formed by implanting ions of the second conductivity type. The doping concentration of the body lead-out region 132 is greater than the doping concentration of the body region 130. The body lead-out region 132 can improve the carrier extraction capability of the body region 130 for the source region 124.

[0053] like Figure 3d As shown, after forming the body lead-out region 132, the source region 124 is formed on the remaining structure etched in the insulating layer 140. In one embodiment of this application, the source region 124 is epitaxially formed on the insulating layer 140 using strained silicon technology. In other embodiments, the source region 124 can also be formed using other source region fabrication processes known in the art. The source region 124 has a first conductivity type. The insulating layer 140 is located between the body lead-out region 132 and the source region 124.

[0054] S250 forms the gate structure and drain region.

[0055] A drain region 122 can be formed in the drift region 120 using conventional LDMOS manufacturing processes and procedures, and a gate structure 160 can be formed on the substrate 110. The drain region 122 has a first conductivity type and its doping concentration is greater than that of the drift region 120. The gate structure 160 includes a gate dielectric layer and a gate layer on the gate dielectric layer. The gate structure 160 is disposed above the substrate 110 between the drain region 122 and the source region 124, with one side of the gate structure 160 contacting the drift region 120 and the other side of the gate structure 160 contacting the source region 124.

[0056] The laterally diffused metal-oxide-semiconductor device formed by the above-mentioned manufacturing method can reduce the parasitic effects caused by the conduction of the PN junction formed in the source and body regions by forming an isolation between the source and body regions through the insulating layer, thereby reducing losses and improving device performance.

[0057] In one embodiment of this application, a second conductivity type doped region 150 may also be formed in the substrate 110, and a substrate lead-out region 152 may be formed in the second conductivity type doped region 150, such as... Figure 1 As shown. Drift region 120 is located between second conductivity type doped region 150 and body region 130. Substrate lead-out region 152 has second conductivity type, and its doping concentration is greater than that of second conductivity type doped region 150.

[0058] In one embodiment of this application, the method for manufacturing a laterally diffused metal-oxide-semiconductor device further includes the step of forming an interlayer dielectric (ILD). The formed interlayer dielectric layer fills the groove in the body region 130 (located on the body lead-out region 132). After the groove in the body region 130 (located on the body lead-out region 132) is filled with the interlayer dielectric layer, a contact hole (not shown in the figures) penetrating the interlayer dielectric layer in the groove is also provided, and the body lead-out region 132 is led out through the contact hole.

[0059] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0060] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for manufacturing a laterally diffused metal-oxide-semiconductor device, comprising: Obtain a substrate in which a bulk region and a drift region are formed; A portion of the body region is removed to form a groove; An insulating layer is formed within the groove; The insulating layer is etched in a portion of the area to expose the body region beneath the insulating layer; After etching, a body lead-out area is formed at the exposed body area location; After the body lead-out region is formed, the source region is formed on the remaining insulating layer after etching. After the source region is formed, a gate structure and a drain region are formed; the drain region is in contact with the drift region, and the gate structure is disposed on a substrate between the drain region and the source region; The insulating layer is located between the body lead-out region and the source region; the step of forming the insulating layer in the groove is to thermally oxidize and grow silicon oxide as the insulating layer; the step of forming the source region on the insulating layer is to epitaxially form the source region on the etched remaining insulating layer by strained silicon technology.

2. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The conductivity type of the body lead-out region is the same as that of the body region and opposite to that of the source region, and the doping concentration of the body lead-out region is greater than that of the body region.

3. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The step of forming the body lead-out region at the exposed body region location precedes the step of epitaxially forming the source region on the etched remaining insulating layer using strained silicon technology.

4. A laterally diffused metal-oxide-semiconductor device, characterized in that, It is manufactured by the manufacturing method of any one of claims 1-3, wherein the laterally diffused metal-oxide-semiconductor device comprises: Substrate; A drift region is disposed in the substrate; The drain region is disposed in the substrate and is in contact with the drift region; The body region is disposed in the substrate; An insulating layer is disposed at least partially in the body region; The source region is located on the insulating layer; and A gate structure is disposed on the substrate between the drain region and the source region.

5. The laterally diffused metal-oxide-semiconductor device according to claim 4, characterized in that, The drift region, drain region, and source region have a first conductivity type, and the substrate and body region have a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types.

6. The laterally diffused metal-oxide-semiconductor device according to claim 4, characterized in that, The conductivity type of the body lead-out region located in the body region is the same as that of the body region and opposite to that of the source region. The doping concentration of the body lead-out region is greater than that of the body region. The source region is disposed in the body region. The insulating layer is located between the body lead-out region and the source region. One side of the gate structure is located on the drift region, and the other side of the gate structure is located on the body region.

7. The laterally diffused metal-oxide-semiconductor device according to claim 4, characterized in that, The insulating layer is made of silicon oxide, and the source region is a strained silicon layer.

8. The laterally diffused metal-oxide-semiconductor device according to claim 5, characterized in that, Also includes: A second conductivity type doped region is disposed in the substrate, and the drift region is located between the second conductivity type doped region and the bulk region; The substrate lead-out region is disposed in the second conductivity type doped region and has a second conductivity type. The doping concentration of the substrate lead-out region is greater than the doping concentration of the second conductivity type doped region.

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