Field effect transistor structure and method of making the same
By introducing first and second doped semiconductor structures into the CFET structure and forming a shared gate structure, the problem of insufficient gate control capability is solved, and better charge control and conduction performance are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-04-23
- Publication Date
- 2026-03-31
AI Technical Summary
In existing CFET structures, the gate's control over the channel is insufficient, resulting in poor charge control.
By introducing first and second doped semiconductor structures into the CFET structure and forming a shared gate structure around them, the channel length is increased to improve gate control capability.
It enhances the gate's control over the channel, increases the voltage control threshold, and improves the transistor's conduction performance.
Smart Images
Figure CN115241291B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a field-effect transistor structure and a method for fabricating the same. Background Technology
[0002] Complementary field-effect transistors (CFETs) are transistors that consist of one or more pairs of P-type and N-type transistors stacked vertically in a cross configuration. This stacking method reduces the area occupied by the transistors, thus increasing the transistor density per unit area.
[0003] CFETs mainly consist of nanowire channels and nanosheet channels, with the channel and gate isolated by an insulating dielectric. A gate bias voltage can be applied to allow majority carriers to accumulate within the channel, thereby controlling the channel current.
[0004] To achieve better control over the channel current, improving the control capability of the gate is particularly important.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a field-effect transistor structure and its fabrication method, which can improve the control capability of the gate.
[0007] According to one aspect of this disclosure, a field-effect transistor structure is provided, comprising:
[0008] Substrate;
[0009] A first dielectric layer covers the upper surface of the substrate;
[0010] A first doped semiconductor structure is formed on the upper surface of the first dielectric layer;
[0011] A second dielectric layer is formed on the upper surface of the first doped semiconductor structure, and a first sub-doped semiconductor structure is embedded in the second dielectric layer.
[0012] A second sub-doped semiconductor structure is formed on the upper surface of the second dielectric layer, and the second sub-doped semiconductor structure is connected to the first sub-doped semiconductor structure to form a second doped semiconductor structure.
[0013] A shared gate structure is filled in the first dielectric layer and the second dielectric layer, and surrounds the first doped semiconductor structure and the second doped semiconductor structure.
[0014] Optional, also includes:
[0015] A third dielectric layer is disposed between the second dielectric layer and the first doped semiconductor structure, serving to separate the first sub-doped semiconductor structure from the first doped semiconductor structure.
[0016] Optionally, there are at least two first sub-doped semiconductor structures, and in the extending direction of the second sub-doped semiconductor structure, the two first sub-doped semiconductor structures are located on both sides of the shared gate structure.
[0017] Optional, also includes:
[0018] A first gate dielectric layer is disposed on the surface of the first doped semiconductor structure portion;
[0019] A second gate dielectric layer is disposed on the surface of the second doped semiconductor structure portion;
[0020] The shared gate structure contacts the first gate dielectric layer to surround the first doped semiconductor structure; the shared gate structure contacts the second gate dielectric layer to surround the second doped semiconductor structure.
[0021] Optionally, a first trench is formed on the first dielectric layer, and a portion of the shared gate structure is filled within the first trench.
[0022] Optionally, a second trench and a third trench are formed on the second dielectric layer, with a portion of the shared gate structure filling the second trench and the first sub-doped semiconductor structure filling the third trench.
[0023] Optionally, a third gate dielectric layer is disposed between the shared gate structure and the substrate.
[0024] Optionally, in the extension direction of the first doped semiconductor structure, the length of the second dielectric layer is less than the length of the first doped semiconductor structure, so as to expose the upper surfaces at both ends of the first doped semiconductor structure.
[0025] In the extension direction of the second doped semiconductor structure, the length of the shared gate structure is less than the length of the second sub-doped semiconductor structure, so as to expose the upper surfaces at both ends of the second sub-doped semiconductor structure.
[0026] Optional, also includes:
[0027] An insulating dielectric layer is formed on the sidewall of the second dielectric layer, the sidewall of the second gate dielectric layer, the sidewall of the second doped semiconductor structure, and the sidewall of the shared gate structure.
[0028] According to one aspect of this disclosure, a method for fabricating a field-effect transistor structure is provided, comprising:
[0029] Provide substrate;
[0030] A first dielectric layer, a first doped semiconductor structure, and a second dielectric layer are sequentially formed on the substrate, wherein sacrificial layers are formed in the first dielectric layer and the second dielectric layer.
[0031] Partial removal of the second dielectric layer;
[0032] A second doped semiconductor structure is formed, the second doped semiconductor structure including a first sub-doped semiconductor structure and a second sub-doped semiconductor structure, wherein the first sub-doped semiconductor structure is embedded in the second dielectric layer;
[0033] The sacrificial layer is removed, and a shared gate structure is deposited surrounding the first doped semiconductor structure and the second doped semiconductor structure.
[0034] Optionally, the step of sequentially forming a first dielectric layer, a first doped semiconductor structure, and a second dielectric layer on the substrate includes:
[0035] A first dielectric layer is deposited on the substrate;
[0036] A first trench is formed in the first dielectric layer, and a first sacrificial layer is deposited in the first trench;
[0037] A first doped semiconductor structure is formed on the first dielectric layer;
[0038] A second dielectric layer is formed on the first doped semiconductor structure, a second trench is formed in the second dielectric layer, and a second sacrificial layer is filled in the second trench.
[0039] Optionally, the partial removal of the second dielectric layer includes:
[0040] A patterned first mask layer is formed on the second dielectric layer;
[0041] Using the first mask layer as a mask, the second dielectric layer is etched to form the third trench;
[0042] The formation of the second doped semiconductor structure includes:
[0043] A first sub-doped semiconductor structure is formed in the third trench, and a second sub-doped semiconductor structure is formed on the upper surface of the first sub-doped semiconductor structure and the second dielectric layer.
[0044] Optionally, the sacrificial layer is removed, and a shared gate structure is deposited surrounding the first doped semiconductor structure and the second doped semiconductor structure, including:
[0045] The first sacrificial layer and the second sacrificial layer are removed using a wet etching process to expose the first trench and the second trench;
[0046] A first gate dielectric layer is deposited on a portion of the surface of the first doped semiconductor structure;
[0047] A second gate dielectric layer is deposited on a portion of the surface of the second doped semiconductor structure;
[0048] A shared gate structure is deposited, which fills the first trench and the second trench and covers the upper surface of the second gate dielectric layer.
[0049] Optionally, forming a first doped semiconductor structure on the first dielectric layer includes:
[0050] The first doped semiconductor structure is formed on the first dielectric layer along a predetermined direction, and the extension direction of the second sub-doped semiconductor structure is in the same direction as the extension direction of the first doped semiconductor structure.
[0051] Optionally, after forming a first doped semiconductor structure on the first dielectric layer, the method further includes:
[0052] A second mask layer is formed on the first doped semiconductor structure, the second mask layer exposing both ends of the first doped semiconductor structure;
[0053] Source and drain regions are formed at both ends of the extension direction of the first doped semiconductor structure by ion implantation.
[0054] Remove the second mask layer.
[0055] Optionally, before forming the second dielectric layer on the first doped semiconductor structure, the method further includes:
[0056] A third dielectric layer is formed on the first doped semiconductor structure, the third dielectric layer being used to separate the second doped semiconductor structure from the first doped semiconductor structure.
[0057] Optionally, after forming the second doped semiconductor structure, the method further includes:
[0058] A third mask layer is formed on the second doped semiconductor structure, the third mask layer exposing both ends of the second doped semiconductor structure;
[0059] Source and drain regions are formed at both ends of the extension direction of the second doped semiconductor structure by ion implantation.
[0060] Remove the third mask layer.
[0061] Optionally, after removing the first and second sacrificial layers, the method further includes:
[0062] The first doped semiconductor structure and the second doped semiconductor structure are subjected to oxidation treatment and wet etching treatment;
[0063] The first doped semiconductor structure and the second doped semiconductor structure are subjected to hydrogen annealing at a preset temperature.
[0064] In an exemplary embodiment of this disclosure, by setting a first sub-doped semiconductor structure to increase the length of the second doped semiconductor structure, the channel length formed by the shared gate structure under the gate dielectric layer can be increased, thereby increasing the number of charges controllable by the gate structure, thereby increasing the voltage control threshold and achieving the purpose of improving the gate electrode control capability.
[0065] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0066] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0067] Figure 1 This is a three-dimensional schematic diagram of the CFET structure in related technologies.
[0068] Figure 2 for Figure 1 A schematic diagram of the first longitudinal section of the CFET.
[0069] Figure 3 for Figure 1 A schematic diagram of the second longitudinal section of the CFET, which is perpendicular to the first longitudinal section.
[0070] Figure 4 This is a schematic diagram of a field-effect transistor structure provided as an exemplary embodiment of the present disclosure.
[0071] Figure 5 This is a schematic diagram of another field-effect transistor structure provided as an exemplary embodiment of the present disclosure.
[0072] Figures 6(a)-6(i) are illustrative diagrams illustrating the fabrication of field-effect transistor structures provided by exemplary embodiments of this disclosure. Detailed Implementation
[0073] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0074] The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments, and the features discussed in the various embodiments are interchangeable where possible. In the above description, numerous specific details are provided to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details described, or other methods, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.
[0075] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0076] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and that other elements / components / etc. may exist in addition to those listed. The terms “first” and “second” are used only as markers and are not a limitation on the number of objects.
[0077] In related technologies, such as Figure 1-3As shown, the CFET mainly includes a silicon substrate 101, a buried oxide layer 102, a P-type transistor 105, and an N-type transistor 106. The P-type transistor 105 and the N-type transistor 106 are stacked and interleaved vertically within the gate electrode 103, and are composed of the gate electrode 103 and the gate oxide layer 104. The P-type transistor 105 and the N-type transistor 106 share a gate electrode 103 as the signal input terminal Vin and a drain as the signal output terminal Vout. One of the two sources of the P-type transistor 105 and the N-type transistor 106 is grounded, and the other is connected to the power supply V. DD .
[0078] The CFET structure described above is a three-dimensional electronic device that stacks two different types of transistors, namely P-type transistor 105 and N-type transistor 106, together. This can reduce the area occupied by the device and thus increase the density of transistors per unit area.
[0079] If the input voltage Vin at the gate and source is too small, it is insufficient to change the charge distribution within the semiconductor, and the transistor cannot be turned on. If the input voltage Vin is increased, the gate electrode 103 will cause a negatively charged electron layer to form on the other side of the gate oxide layer 104 that is not in contact with the gate electrode 103. This electron layer is called a channel, which provides a conductive path for the source and drain at both ends, thus putting the transistor in a conducting state.
[0080] However, due to the size limitations of CFET in the horizontal and vertical directions, the gate electrode 103 results in a shorter channel length formed on the other side of the gate oxide layer 104 that is not in contact with the gate electrode 103, leading to less charge in the electron layer controlled by the gate electrode and poorer controllability.
[0081] Based on this, the exemplary embodiments of this disclosure provide a field-effect transistor structure, such as... Figure 4 As shown, the field-effect transistor structure may include a substrate 410, a first dielectric layer 420, a first doped semiconductor structure 430, a second dielectric layer 440, a second doped semiconductor structure 450, and a shared gate structure 460, wherein:
[0082] The substrate 410 is mainly a silicon substrate used to ensure the mechanical strength of the transistor. Its structure can be cuboid, and its thickness can be set according to actual conditions, such as a few micrometers. This exemplary embodiment does not make any special limitations on this.
[0083] The first dielectric layer 420 covers the upper surface of the substrate 410 and is an insulating dielectric layer, mainly providing space for the formation of the shared gate structure 460.
[0084] Optionally, the first dielectric layer 420 may completely cover the upper surface of the substrate 410 or partially cover it.
[0085] It should be understood that in the exemplary embodiments of this disclosure, "coverage" can refer to either full coverage or partial coverage.
[0086] A first doped semiconductor structure 430 is formed on the upper surface of the first dielectric layer 420. The first doped semiconductor structure 430 can be an N-type semiconductor structure or a P-type semiconductor structure. If a small amount of arsenic or phosphorus is doped into a pure silicon structure, an N-type semiconductor structure can be formed; if a small amount of boron is doped into a pure silicon structure, a P-type semiconductor structure can be formed.
[0087] In practical applications, the shape of the formed first doped semiconductor structure 430 can be either a nanowire shape or a nanosheet shape. Alternatively, multiple first doped semiconductor structures 430 can be formed on the first dielectric layer 420 according to actual needs.
[0088] The second dielectric layer 440 is formed on the upper surface of the first doped semiconductor structure 430. The second dielectric layer 440 can provide space for the formation of the shared gate structure 460, and a first sub-doped semiconductor structure 451 is embedded in the second dielectric layer 440, wherein the first sub-doped semiconductor structure 451 is a part of the second doped semiconductor structure 450.
[0089] It should be noted that the second dielectric layer 440 not only covers the upper surface of the first doped semiconductor structure 430, but also covers the upper surface of the first dielectric layer 420 outside the first doped semiconductor structure 430. That is to say, the cross-sectional area of the second dielectric layer 440 in the horizontal direction is larger than the cross-sectional area of the first doped semiconductor structure 430 in the horizontal direction, thereby facilitating the formation of the second doped semiconductor structure 450.
[0090] In an exemplary embodiment of this disclosure, a second sub-doped semiconductor structure 452 for forming the second doped semiconductor structure 450 is formed on the upper surface of the second dielectric layer 440. The shape of the second sub-doped semiconductor structure 452 is the same as the shape of the first doped semiconductor structure 430. The formed second doped semiconductor structure 450 can be an N-type semiconductor structure or a P-type semiconductor structure. Specifically, when the first doped semiconductor structure 430 is an N-type semiconductor structure, the corresponding second doped semiconductor structure 450 is a P-type semiconductor structure; when the first doped semiconductor structure 430 is an N-type semiconductor structure, the corresponding second doped semiconductor structure 450 is a P-type semiconductor structure.
[0091] It should be noted that if multiple first-doped semiconductor structures 430 are formed on the first dielectric layer 420, then correspondingly, second-doped semiconductor structures 450 need to be formed at the positions corresponding to the first-doped semiconductor structures 430, so as to form multiple pairs of first-doped semiconductor structures 430 and second-doped semiconductor structures 450, which further reduces the area occupied by the transistor.
[0092] The shared gate structure 460 is filled in the first dielectric layer 420 and the second dielectric layer 440, and surrounds the first doped semiconductor structure 430 and the second doped semiconductor structure 450, so that after the channel is formed, the source and drain of the first doped semiconductor structure 430 and the source and drain of the second doped semiconductor structure 450 are connected.
[0093] To facilitate channel formation, the field-effect transistor structure provided in the exemplary embodiments of this disclosure further includes a first gate dielectric layer 470 and a second gate dielectric layer 480, wherein:
[0094] A first gate dielectric layer 470 is disposed on a portion of the surface of the first doped semiconductor structure 430. A shared gate structure 460 contacts the first gate dielectric layer 470 to surround the first doped semiconductor structure 430. The first gate dielectric layer 470 can isolate the shared gate structure 460 and the first doped semiconductor structure 430; and the first gate dielectric layer 470 is a gate oxide layer, which is used to form a channel connecting the source and drain at both ends of the first doped semiconductor structure 430.
[0095] The second gate dielectric layer 480 is disposed on a portion of the surface of the second doped semiconductor structure 450; the shared gate structure 460 contacts the second gate dielectric layer 480 to surround the second doped semiconductor structure 450. The second gate dielectric layer 480 can isolate the shared gate structure 460 and the second doped semiconductor structure 450; and the second gate dielectric layer 480 is also a gate oxide layer, which is used to form a channel connecting the source and drain at both ends of the second doped semiconductor structure 450.
[0096] In practical applications, the first gate dielectric layer 470 and the second gate dielectric layer 480 can be relatively thin gate dielectric layers, for example, their thickness can be between 2-20 nm. Using a thinner gate dielectric layer can effectively reduce the influence of charge centers in the gate dielectric. The material of the gate dielectric layer can include commonly used metal oxides or high-k oxides, or two-dimensional dielectric materials such as boron nitride, silicon dioxide, etc., and the exemplary embodiments of this disclosure do not impose any special limitations on this.
[0097] In an exemplary embodiment of this disclosure, to form the shared gate structure 460, a first trench is formed on the first dielectric layer 420, and a portion of the shared gate structure 460 fills the first trench; additionally, a second trench is formed on the second dielectric layer 440, and a portion of the shared gate structure 460 fills the second trench. (Refer to...) Figure 1 As can be seen, the gate material injected from above the second doped semiconductor structure 450 to form the shared gate structure 460 will be deposited in the first trench and the second trench, and eventually fill the first trench and the second trench. The gate material above the second doped semiconductor structure 450 and the gate material flowing into the first trench and the second trench will form an integral structure, which will eventually become the shared gate structure 460 surrounding the first doped semiconductor structure 430 and the second doped semiconductor structure 450.
[0098] Specifically, in order to form the second doped semiconductor structure 450, a third trench also needs to be formed in the second dielectric layer 440, and the first sub-doped semiconductor structure 451 is formed in the third trench. A second gate dielectric layer 480 is spaced between the first sub-doped semiconductor structure 451 and the partially shared gate structure 460 formed in the second trench. The second gate dielectric layer 480 can be formed simultaneously with the first gate dielectric layer 470.
[0099] In an exemplary embodiment of this disclosure, the first sub-doped semiconductor structure 451 is located at a local position on the lower surface of the second sub-doped semiconductor structure 452, and the first sub-doped semiconductor structure 451 may be disposed perpendicular to the second sub-doped semiconductor structure 452.
[0100] In practical applications, to further increase the channel length, multiple first sub-doped semiconductor structures 451 can be formed at intervals on the lower surface of the second sub-doped semiconductor structure 452 along its extension direction. For example, at least two first sub-doped semiconductor structures 451 can be formed on the lower surface of the second sub-doped semiconductor structure 452. To improve the symmetry of the structure, the two first sub-doped semiconductor structures 451 can be located on both sides of the shared gate structure 460 and symmetrically arranged. Alternatively, four or six first sub-doped semiconductor structures 451 can be provided, depending on the size of the second sub-doped semiconductor structure 452. This exemplary embodiment does not impose any special limitations on this.
[0101] The field-effect transistor structure provided in the exemplary embodiments of this disclosure further includes a third dielectric layer 490, which is disposed between the second dielectric layer 440 and the first doped semiconductor structure 430, serving to space the first sub-doped semiconductor structure 451 from the first doped semiconductor structure 430. When a third trench is formed in the second dielectric layer 440, the third dielectric layer 490 can prevent the third trench from directly penetrating to the first doped semiconductor structure 430, thereby preventing direct contact between the first sub-doped semiconductor structure 451 and the first doped semiconductor structure 430 and avoiding leakage failure of the device structure.
[0102] In practical applications, since the substrate 410 is usually also made of a conductive material, a third gate dielectric layer 411 is required between the shared gate structure 460 and the substrate 410 to isolate the shared gate structure 460 and the substrate 410. The third gate dielectric layer 411 can be formed simultaneously with the second gate dielectric layer 480 and the first gate dielectric layer 470.
[0103] In an exemplary embodiment of this disclosure, by providing a first sub-doped semiconductor structure 451, the length of the second doped semiconductor structure 450 can be increased, thereby increasing the channel length formed by the shared gate structure 460 under the second gate dielectric layer 480, which increases the number of charges in the electron layer controllable by the gate electrode, thereby increasing the voltage control threshold and achieving the purpose of improving the gate electrode control capability.
[0104] for Figure 4 In the field-effect transistor structure shown, the source and drain terminals of the first doped semiconductor structure 430 and the second doped semiconductor structure 450 can be set at both ends of the first doped semiconductor structure 430 and the second doped semiconductor structure 450, that is, lead lines can be set at the ends, thereby further increasing the channel length and achieving the effect of improving the gate electrode control capability.
[0105] Reference Figure 5 The diagram illustrates another field-effect transistor structure provided by an exemplary embodiment of this disclosure. Figure 5 In the extension direction of the first doped semiconductor structure 430, the lengths of the second doped semiconductor structure 450, the second dielectric layer 440, and the third dielectric layer 490 are all less than the length of the first doped semiconductor structure 430, so that the upper surfaces at both ends of the first doped semiconductor structure 430 can be exposed. The exposed upper surfaces can serve as the source and drain regions of the first doped semiconductor structure 430 for setting out leads.
[0106] Similarly, in the extension direction of the second doped semiconductor structure 450, the length of the shared gate structure 460 and the length of part of the second gate dielectric layer 480 are less than the length of the second sub-doped semiconductor structure 452, so that the upper surfaces at both ends of the second sub-doped semiconductor structure 452 can be exposed. The exposed upper surfaces can serve as the source and drain regions of the second doped semiconductor structure 450 for setting out leads.
[0107] for Figure 5 The field-effect transistor structure shown also requires an insulating dielectric layer 510, which is formed on the sidewalls of the second dielectric layer 440, the third dielectric layer 490, the second gate dielectric layer 480, the second doped semiconductor structure 450, and the shared gate structure 460, thereby achieving the function of insulating and protecting the transistor.
[0108] In practical applications, the thickness of the insulating dielectric layer 510 can be set to be relatively thin, for example, its thickness can be between 1-10 nm, as long as the purpose of insulation is achieved. The material of the insulating dielectric layer 510 can be silicon nitride, etc., and the exemplary embodiments of this disclosure do not impose any special limitations on it.
[0109] The above exemplary embodiments only illustrate field-effect transistor structures that increase the length of the second doped semiconductor structure 450. In practical applications, the length of the first doped semiconductor structure 430 can also be increased in the same way to improve the gate electrode control capability.
[0110] In other words, improving the gate electrode control capability can be achieved by simply increasing the length of the first doped semiconductor structure 430, or by simply increasing the length of the second doped semiconductor structure 450, or by simultaneously increasing the lengths of both the first doped semiconductor structure 430 and the second doped semiconductor structure 450. This exemplary embodiment does not limit the scope of the invention.
[0111] The fabrication method of the field-effect transistor structure provided by the exemplary embodiments of this disclosure will now be described in detail with reference to Figures 6(a)-6(i).
[0112] It should be understood that the accompanying drawings are not to scale according to the actual device structure, in order to illustrate the manufacturing process. The specific manufacturing steps are as follows:
[0113] Step 1: Provide a substrate. The substrate material needs to be conductive and can be common semiconductors such as Si and Ge. The formed substrate can be a rectangular substrate, and the doping concentration can be lightly doped, which can be determined according to actual needs.
[0114] Step 2: A first dielectric layer, a first doped semiconductor structure, and a second dielectric layer are sequentially formed on the substrate, and a sacrificial layer is formed in the first dielectric layer and the second dielectric layer.
[0115] As shown in Figure 6(a), a first dielectric layer 420 is deposited on the substrate 410. The first dielectric layer 420 is an insulating dielectric layer and can be fabricated using atomic layer deposition. A first trench is formed in the deposited first dielectric layer 420. Specifically, a mask layer can be used as a mask to form the first trench in the first dielectric layer 420. Next, a first sacrificial layer 601 is deposited in the first trench, and a first doped semiconductor structure 430 is formed on the first dielectric layer 420 on which the first sacrificial layer 601 is deposited.
[0116] Specifically, a first doped semiconductor structure 430 can be formed on the first dielectric layer 420 along a preset direction. The shape of the first doped semiconductor structure 430 can be a nanowire shape or a nanosheet shape. The method of forming the first doped semiconductor structure 430 can be determined according to the specific shape, and no special limitation is made here. In addition, the preset direction mentioned above can be set according to the actual situation, and the exemplary embodiments of this disclosure do not make special limitations in this regard.
[0117] As shown in Figure 6(b), after forming the first doped semiconductor structure 430, a second mask layer 602 can be formed on the first doped semiconductor structure 430, which exposes both ends of the first doped semiconductor structure 430. Then, source / drain regions can be formed at both ends of the first doped semiconductor structure 430 along the aforementioned predetermined direction using an ion implantation process. The second mask layer 602 can be removed after forming the source / drain regions. The specific ion implantation process will not be described in detail here.
[0118] As shown in Figure 6(c), after removing the second mask layer, a third dielectric layer 490 is formed on the first doped semiconductor structure 430. The third dielectric layer 490 is mainly used to separate the second doped semiconductor structure from the first doped semiconductor structure 430. Therefore, the thickness of the third dielectric layer 490 is smaller than the thickness of the first dielectric layer 420. The specific thickness can be determined according to the actual situation and is not specifically limited here.
[0119] As shown in Figure 6(c), a second dielectric layer 440 needs to be formed on the third dielectric layer 490, and a second trench is formed in the second dielectric layer 440. The second trench is filled with a second sacrificial layer 603. The formation process of the second trench and the second sacrificial layer 603 can be the same as the formation process of the first trench and the first sacrificial layer 601 described above, and will not be repeated here.
[0120] Step 3: Partially remove the second dielectric layer.
[0121] As shown in Figure 6(c), after the second sacrificial layer 603 is formed, a patterned first mask layer can be formed on the second dielectric layer 440, and the second dielectric layer 440 is etched using the first mask layer 604 as a mask to form a third trench 605, as shown in Figure 6(d). There can be two third trenches 605.
[0122] Step 4: Form a second doped semiconductor structure, which includes a first sub-doped semiconductor structure and a second sub-doped semiconductor structure. The first sub-doped semiconductor structure is embedded in the second dielectric layer.
[0123] As shown in Figure 6(e), a first sub-doped semiconductor structure 610 is formed in the third trench, and a second sub-doped semiconductor structure is formed on the upper surface of the first sub-doped semiconductor structure and the second dielectric layer 440. The second sub-doped semiconductor structure and the first sub-doped semiconductor structure are connected together to form a second doped semiconductor structure 450.
[0124] Step 5: Remove the sacrificial layer and deposit a shared gate structure surrounding the first doped semiconductor structure and the second doped semiconductor structure.
[0125] As shown in Figure 6(f), after forming the second doped semiconductor structure, a third mask layer 606 can be formed on the second doped semiconductor structure. Specifically, the third mask layer 606 is formed on the second sub-doped semiconductor structure, exposing both ends of the second doped semiconductor structure 450. Then, source / drain regions can be formed at both ends of the extension direction of the second doped semiconductor structure 450 using an ion implantation process. The extension direction of the second sub-doped semiconductor structure is the same as the extension direction of the first doped semiconductor structure 430. After forming the source / drain regions, the third mask layer 606 is removed.
[0126] As shown in Figure 6(g), the first sacrificial layer 601 and the second sacrificial layer 603 are removed by wet etching process to expose the first trench and the second trench, and at the same time, the second doped semiconductor structure 450 and the first doped semiconductor structure 430 are partially exposed.
[0127] The exposed second-doped semiconductor structure 450 and first-doped semiconductor structure 430 can also be treated using a method of oxidation followed by wet etching (e.g., dilute hydrofluoric acid) to form rounded outer surfaces, thereby obtaining P-type / N-type semiconductor nanosheets or nanowires with a roughly racetrack-shaped cross-section. Subsequently, hydrogen annealing can be performed at a preset temperature, for example, above 800°C-1200°C, for a time ranging from 5 minutes to 8 hours. Hydrogen annealing makes the surface of the etched P-type / N-type semiconductor nanosheets or nanowires smoother and denser.
[0128] As shown in Figure 6(h), a high-dielectric-constant dielectric is deposited as the gate dielectric layer using chemical vapor deposition or atomic layer deposition. Specifically, a first gate dielectric layer 470 is deposited on a portion of the surface of the first doped semiconductor structure 430; a second gate dielectric layer 480 is deposited on a portion of the surface of the second doped semiconductor structure, which also covers the upper surface of the second doped semiconductor structure 450. Additionally, a third gate dielectric layer 411 is deposited on the portion of the first trench near the substrate 410 and on the upper surface of the second doped semiconductor structure.
[0129] A shared gate structure 460 is deposited in the structure shown in Figure 6(h). This shared gate structure 460 fills the first trench and the second trench and covers the upper surface of the second gate dielectric layer 480, thereby obtaining the structure shown in Figure 6(h). Figure 4 The field-effect transistor structure shown.
[0130] In obtaining such Figure 4 Following the field-effect transistor structure shown, further processing can be performed to obtain, for example, Figure 5 The field-effect transistor structure shown may specifically include the following process steps:
[0131] As shown in Figure 6(i), the two ends of the third dielectric layer 490, the second dielectric layer 440, and the second doped semiconductor structure 450 can be removed using a mask process to expose the source and drain regions of the first doped semiconductor structure 430; the two ends of the second gate dielectric layer 480 deposited on the upper surface of the shared gate structure 460 and the second doped semiconductor structure 450 can be removed using a mask process to expose the source and drain regions of the second doped semiconductor structure 450.
[0132] Next, an insulating dielectric layer is deposited on the sidewalls of the third dielectric layer 490, the second dielectric layer 440, the second gate dielectric layer 480, the second doped semiconductor structure 450, and the shared gate structure 460. Finally, the source / drain regions of the first doped semiconductor structure 430 and the second doped semiconductor structure 450 that have leaked out form a connection terminal, resulting in the following... Figure 5 The field-effect transistor structure shown.
[0133] It should be noted that the fabrication method of the field-effect transistor structure provided in the exemplary embodiments of this disclosure is only illustrative, and this disclosure does not limit the fabrication process of each component.
[0134] It should be understood that in the various embodiments of this disclosure, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the exemplary embodiments of this disclosure.
[0135] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A field effect transistor structure, characterized by The application relates to a semiconductor structure, comprising: a substrate; a first dielectric layer covering the upper surface of the substrate; a first doped semiconductor structure formed on the upper surface of the first dielectric layer; a second dielectric layer formed on the upper surface of the first doped semiconductor structure, wherein a first sub-doped semiconductor structure is embedded in the second dielectric layer; a second sub-doped semiconductor structure formed on the upper surface of the second dielectric layer, wherein the second sub-doped semiconductor structure is connected with the first sub-doped semiconductor structure to form a second doped semiconductor structure; and a shared gate structure filled in the first dielectric layer and the second dielectric layer and surrounding the first doped semiconductor structure and the second doped semiconductor structure, wherein the first sub-doped semiconductor structure has at least two, and in the extending direction of the second sub-doped semiconductor structure, the two first sub-doped semiconductor structures are located on the two sides of the shared gate structure. Further comprising: a third dielectric layer arranged between the second dielectric layer and the first doped semiconductor structure, used for spacing the first sub-doped semiconductor structure and the first doped semiconductor structure. Further comprising: a first gate dielectric layer arranged on part of the surface of the first doped semiconductor structure; and a second gate dielectric layer arranged on part of the surface of the second doped semiconductor structure, wherein the shared gate structure is in contact with the first gate dielectric layer to surround the first doped semiconductor structure, and the shared gate structure is in contact with the second gate dielectric layer to surround the second doped semiconductor structure. The first dielectric layer is provided with a first groove, and part of the shared gate structure is filled in the first groove. The second dielectric layer is provided with a second groove and a third groove, part of the shared gate structure is filled in the second groove, and the first sub-doped semiconductor structure is filled in the third groove. The third gate dielectric layer is arranged between the shared gate structure and the substrate. In the extending direction of the first doped semiconductor structure, the length of the second dielectric layer is smaller than the length of the first doped semiconductor structure, so as to expose the upper surface of the two ends of the first doped semiconductor structure. In the extending direction of the second doped semiconductor structure, the length of the shared gate structure is smaller than the length of the second sub-doped semiconductor structure, so as to expose the upper surface of the two ends of the second sub-doped semiconductor structure.
2. The field effect transistor structure of claim 1, wherein Further comprising: an insulating dielectric layer formed on the sidewall of the second dielectric layer, the sidewall of the second gate dielectric layer, the sidewall of the second doped semiconductor structure and the sidewall of the shared gate structure. The application further relates to a semiconductor structure manufacturing method, comprising the following steps: providing a substrate; sequentially forming a first dielectric layer, a first doped semiconductor structure and a second dielectric layer on the substrate, wherein a sacrificial layer is formed in the first dielectric layer and the second dielectric layer; partially removing the second dielectric layer; forming a second doped semiconductor structure, wherein the second doped semiconductor structure comprises a first sub-doped semiconductor structure and a second sub-doped semiconductor structure, and the first sub-doped semiconductor structure is embedded in the second dielectric layer; 3. The field effect transistor structure of claim 1, wherein 4. The field effect transistor structure of claim 1, wherein 5. The field effect transistor structure of claim 4, wherein, 6. The field effect transistor structure of claim 1, wherein, 7. The field effect transistor structure of claim 1, wherein 8. The field effect transistor structure of claim 3, wherein, 9. A method of fabricating a field effect transistor structure, characterized by, removing the sacrificial layers, and depositing a shared gate structure surrounding the first doped semiconductor structure and the second doped semiconductor structure; wherein the first sub-doped semiconductor structure is at least two, and the two first sub-doped semiconductor structures are located on two sides of the shared gate structure in the extending direction of the second sub-doped semiconductor structure.
10. The method of manufacturing according to claim 9, wherein, The sequentially forming the first dielectric layer, the first doped semiconductor structure and the second dielectric layer on the substrate comprises: depositing a first dielectric layer on the substrate; forming a first trench in the first dielectric layer, and depositing a first sacrificial layer in the first trench; forming a first doped semiconductor structure on the first dielectric layer; forming a second dielectric layer on the first doped semiconductor structure, forming a second trench in the second dielectric layer, and filling a second sacrificial layer in the second trench.
11. The method of manufacturing according to claim 9, wherein, The partially removing the second dielectric layer comprises: forming a patterned first mask layer on the second dielectric layer; using the first mask layer as a mask to etch the second dielectric layer to form a third trench; The forming the second doped semiconductor structure comprises: forming a first sub-doped semiconductor structure in the third trench, and forming a second sub-doped semiconductor structure on the upper surface of the first sub-doped semiconductor structure and the second dielectric layer.
12. The method of making of claim 10, wherein, The removing the sacrificial layers, and depositing a shared gate structure surrounding the first doped semiconductor structure and the second doped semiconductor structure comprises: removing the first sacrificial layer and the second sacrificial layer by using a wet etching process to expose the first trench and the second trench; depositing a first gate dielectric layer on part of the surface of the first doped semiconductor structure; depositing a second gate dielectric layer on part of the surface of the second doped semiconductor structure; depositing a shared gate structure, which fills the first trench and the second trench, and covers the upper surface of the second gate dielectric layer.
13. The method of manufacturing according to claim 11, wherein, The forming the first doped semiconductor structure on the first dielectric layer comprises: forming the first doped semiconductor structure on the first dielectric layer in a preset direction, and the extending direction of the second sub-doped semiconductor structure is in the same direction as the extending direction of the first doped semiconductor structure.
14. The method of manufacturing according to claim 13, wherein, After forming the first doped semiconductor structure on the first dielectric layer, the method further comprises: forming a second mask layer on the first doped semiconductor structure, the second mask layer exposing two ends of the first doped semiconductor structure; forming source-drain regions at the two ends in the extending direction of the first doped semiconductor structure by using an ion implantation process; removing the second mask layer.
15. The method of manufacturing of claim 10, wherein, Before forming the second dielectric layer on the first doped semiconductor structure, the method further comprises: forming a third dielectric layer on the first doped semiconductor structure, the third dielectric layer being used to separate the second doped semiconductor structure from the first doped semiconductor structure.
16. The method of manufacturing of claim 13, wherein, After forming the second doped semiconductor structure, the method further comprises: forming a third mask layer on the second doped semiconductor structure, the third mask layer exposing two ends of the second doped semiconductor structure; forming source-drain regions at both ends of the second doped semiconductor structure by an ion implantation process; removing the third mask layer.
17. The method of making according to any one of claims 12-16, wherein, After removing the first and second sacrificial layers, the method further comprises: performing oxidation treatment and wet etching treatment on the first and second doped semiconductor structures; performing hydrogen annealing treatment on the first and second doped semiconductor structures at a preset temperature.
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