Switching converter and control circuit therefor

Abstract

The embodiment of the present disclosure provides a switching converter and a control circuit thereof. The switching converter adopts a power tube to control the transmission of electric energy from an input end to an output end, so as to generate a direct current output voltage according to a direct current input voltage. The control circuit comprises an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit and a latch circuit. In the oscillator circuit, a clock signal is generated according to a triangular wave voltage signal and a gate signal of a first power tube in the switching converter. The clock signal is allowed to reset the slope compensation current only when the lower power tube is in an open state, so that the modulation comparator is effectively prevented from being mis-triggered, and the inductance current waveform is prevented from being disturbed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a switching converter and a control circuit thereof. BACKGROUND

[0002] In a fixed-frequency valley current mode boost converter, the internal clock resets the slope compensation current every cycle, especially when the inductor current is higher than the current limit value. If the clock reset occurs before the valley current limit value, it can cause the PWM modulator to be triggered incorrectly. The inductor current waveform of the next cycle shows that the valley current is much lower than the limit value before the lower tube is turned on, resulting in a disordered inductor current waveform. Therefore, how to maintain the regularity of the inductor current waveform in a fixed-frequency valley current mode boost converter is one of the technical problems to be solved. SUMMARY

[0003] Embodiments described herein provide a switching converter and a control circuit thereof to solve the problem of disordered inductor current waveform in a fixed-frequency valley current mode boost converter.

[0004] According to a first aspect of the present disclosure, a control circuit of a switching converter is provided, the switching converter controls the transmission of electrical energy from an input end to an output end by a power tube to generate a direct current output voltage according to a direct current input voltage, the control circuit comprises an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit, and a latch circuit, wherein the oscillator circuit is configured to generate a triangular wave voltage signal according to a direct current source signal, and is also configured to generate a clock signal according to the triangular wave voltage signal and a gate signal of a first power tube in the switching converter; the slope compensation circuit is configured to generate a slope compensation current according to the triangular wave voltage signal; the duty cycle modulation circuit is configured to generate a sampling voltage according to the slope compensation current and a sampling current, and is also configured to generate a duty cycle modulation signal according to the sampling voltage and an error voltage; and the latch circuit is configured to generate a switching signal according to the clock signal and the duty cycle signal to control the conduction state of the power tube.

[0005] Optionally, the oscillator circuit comprises: a first current source, a first comparator, a first capacitor, a first transistor, an AND gate, a high-level pulse generating circuit, an input end of the first current source is connected to a voltage source, an output end of the first current source is connected to one end of the first capacitor and a positive input end of the first comparator, and the output end of the first current source generates the triangular wave voltage signal; the other end of the first capacitor is grounded, and an inverting input end of the first comparator receives a reference voltage; one input end of the AND gate is connected to an output end of the first comparator, the other input end of the AND gate receives a gate signal of the first power tube, and an output end of the AND gate is connected to an input end of the high-level pulse generating circuit; the first transistor is connected in parallel across the first capacitor, a control end of the first transistor is connected to an output end of the high-level pulse generating circuit, and the output end of the high-level pulse generating circuit generates the clock signal.

[0006] Optionally, the slope compensation circuit comprises: a second transistor, a third transistor and a first resistor, the second transistor, the third transistor and the first resistor are connected in series between an input end and a ground end of the first current source; a control end of the second transistor is connected to a first pole of the second transistor and a control end of a fourth transistor in the duty cycle modulation circuit, so as to mirror the generated slope compensation current to the duty cycle modulation circuit; a control end of the third transistor is connected to an output end of the first current source, so as to receive the triangular wave voltage signal.

[0007] Optionally, the duty cycle modulation circuit comprises: a second comparator, a fourth transistor, a second current source and a second resistor, the fourth transistor and the second resistor are connected in series between the input end and the ground end of the first current source; the second current source is connected in parallel with the fourth transistor; a positive input end of the second comparator is connected to a node between the fourth transistor and the second resistor and an output end of the second current source, so as to obtain the sampling voltage; an inverting input end of the second comparator receives an error amplification signal, and an output end of the second comparator outputs the duty cycle modulation signal.

[0008] Optionally, the latch circuit comprises: a first latch and a second latch, a set end of the first latch is connected to an output end of the second comparator, a reset end of the first latch is connected to an output end of the high-level pulse generating circuit, and an output end of the first latch is connected to a control end of the first power tube in the switching converter; a set end of the second latch is connected to the output end of the second comparator, a reset end of the second latch is connected to the output end of the high-level pulse generating circuit, and an output end of the second latch is connected to a control end of the second power tube in the switching converter.

[0009] Optionally, the error amplification signal is a signal obtained by an error amplifier according to the direct-current output voltage and a preset reference voltage.

[0010] Optionally, the control circuit is a constant frequency valley current mode.

[0011] According to a second aspect of the present disclosure, a switching converter is provided, comprising a main power circuit configured to control the transmission of electric energy from an input end to an output end by a power tube, thereby generating a direct-current output voltage according to a direct-current input voltage; and the control circuit of any one of the first aspect, configured to generate a switching control signal to control the conduction state of the power tube.

[0012] Optionally, the main power circuit comprises an inductor, a first power tube, a second power tube, an output capacitor, and a load, wherein the inductor and the first power tube are connected in series between the input end and a ground end; the second power tube is connected between the inductor, a middle node of the first power tube, and the output end; the output capacitor is connected between the output end and the ground end; and the load is connected in parallel across the output capacitor.

[0013] Optionally, the switching converter is a boost converter.

[0014] In the switching converter and the control circuit thereof according to the embodiments of the present disclosure, the transmission of electric energy from an input end to an output end is controlled by a power tube, thereby generating a direct-current output voltage according to a direct-current input voltage, wherein the control circuit comprises an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit, and a latch circuit, wherein the oscillator circuit is configured to generate a triangular wave voltage signal according to a direct-current source signal, and is further configured to generate a clock signal according to the triangular wave voltage signal and a gate signal of a first power tube in the switching converter; the slope compensation circuit is configured to generate a slope compensation current according to the triangular wave voltage signal; the duty cycle modulation circuit is configured to generate a sampling voltage according to the slope compensation current and a sampling current, and is further configured to generate a duty cycle modulation signal according to the sampling voltage and an error voltage; and the latch circuit is configured to generate a switching signal according to the clock signal and the duty cycle signal, so as to control the conduction state of the power tube. Compared with the control circuit of a conventional constant frequency valley current mode boost converter, the control logic of the lower power tube (the first power tube) is introduced, that is, the clock signal is generated according to the triangular wave voltage signal and the gate signal of the first power tube in the switching converter, so that when the inductor current is higher than the current limit value, the clock is allowed to reset the slope compensation current only when the lower power tube is in the open state. Thus, the PWM comparator can be prevented from being triggered by mistake, thereby ensuring the regularity of the waveform of the inductor current. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to make the technical solutions of the embodiments of the present disclosure clearer, the drawings of the embodiments will be briefly described below, and it should be known that the drawings described below only relate to some of the embodiments of the present disclosure, rather than limit the present disclosure, wherein:

[0016] Figure 1 is an exemplary circuit diagram of an existing switching converter;

[0017] Figure 2 is a waveform diagram corresponding to Figure 1

[0018] Figure 3 is a structural schematic diagram of a switching converter according to an embodiment of the present disclosure;

[0019] Figure 4 is an exemplary circuit diagram of a switching converter according to an embodiment of the present disclosure;

[0020] Figure 5 is a waveform diagram corresponding to a switching converter according to an embodiment of the present disclosure.

[0021] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0022] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without any creative effort also belong to the scope of protection of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0024] ​In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current direction between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor is opposite, in the embodiments of the present disclosure, the controlled middle terminal of the transistor is referred to as the control electrode (control terminal), and the remaining two terminals of the transistor are referred to as the first electrode and the second electrode, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0025] In order to solve the problem of inductance current waveform disorder in the fixed-frequency valley-current mode boost converter, first, the control of the fixed-frequency valley-current mode boost converter is analyzed. Specifically, as shown in Figure 1 The existing conventional fixed-frequency valley-current mode boost converter 100 is an exemplary circuit diagram, which is analyzed in combination with Figure 1 The inductance current waveform disorder problem is analyzed as follows: the current source Iosc charges the capacitor Css to generate a triangular wave VRAMP. This triangular wave signal VRAMP is used as an input signal of the comparator COMP, and at the same time, it is also dropped to the resistor R1 through the transistor Mn0 to generate a triangular wave current. After the mirror effect of the transistor Mp1 and the transistor Mp0, a slope compensation current I_slope is generated. Finally, the slope compensation current I_slope and the sampled current (Idc-Isns) (where Idc is a constant current, and Isns is related to the sampled inductance current, which can be 100,000 times of Isns) act on the resistor Rs to generate a sum point voltage (inductance sampling voltage). The sum voltage and the eaout voltage (output signal of the error amplifier) are compared by the comparator PWM_COMP to generate the MAIN_TRIP signal to turn on the lower transistor, thereby adjusting the BOOST duty cycle. Specifically, according to the MAIN_TRIP signal and the clock signal CLK (the output of the comparator COMP is obtained through the high-level pulse generator I1 to get CLK), the power transistor ML and MH are controlled to turn on and turn off. After the control according to the above control principle, the corresponding waveform diagram is as shown in Figure 2As shown, from top to bottom are the inductor current IL waveform, the clock signal CLK waveform, the slope compensation current I_slope waveform, the MAIN_TRIP signal waveform, and the waveform of the gate signal LG of the transistor ML. As can be seen from the waveforms, before time t1, the MAIN_TRIP signal has already turned high, but the inductor current IL is higher than the valley value current limit VY_LIM, so the upper transistor (MH) continues to conduct. At time t1, the CLK signal resets the I_slope current, causing the sum voltage to be lower than the eaout voltage, and the MAIN_TRIP signal turns low. Next, although the inductor current IL is lower than the current limit VY_LIM, the MAIN_TRIP signal is still low and cannot turn on the lower transistor (ML) because the I_slope current is small. The inductor current IL further decreases below the current limit VY_LIM, and the MAIN_TRIP signal does not turn on the lower transistor ML until time t2 when the sum voltage is higher than the eaout voltage. The inductor current IL starts to rise, and in the next period at time t3, the clock arrives to turn off the lower transistor ML, and the inductor current IL continues to decrease, thus forming a chaotic inductor current IL waveform. Figure 2 As shown, the inductor current IL waveform is chaotic.

[0026] Based on the above analysis, the embodiments of the present disclosure propose a new switching converter and a control circuit thereof to solve the problem of chaotic inductor current. The embodiments of the present disclosure will be described in detail below.

[0027] As Figure 3 As shown, the switching converter 200 proposed in the embodiments of the present disclosure is a structure schematic diagram. First of all, it needs to be explained that the switching converter 200 in the embodiments of the present disclosure uses power transistor control to transmit electrical energy from the input end to the output end, so as to generate a direct current output voltage Vout from a direct current input voltage Vin, as Figure 3 As shown, the control circuit of the switching converter 200 includes an oscillator circuit 210, a slope compensation circuit 220, a duty cycle modulation circuit 230, and a latch circuit 240.

[0028] The oscillator circuit 210 is connected with the slope compensation circuit 220, and is configured to generate a triangular wave voltage signal VRAMP according to the DC source signal, which is input into the slope compensation circuit 220 to generate a slope compensation current I_slope. In addition, the oscillator circuit 210 can also generate a clock signal according to the triangular wave voltage signal VRAMP and a gate signal LG of a first power tube in the switching converter; the first power tube is a lower tube in a main power circuit 250 of the switching converter. The slope compensation circuit 220 is connected with the oscillator circuit 210 and the duty cycle modulation circuit 230, and is configured to generate the slope compensation current I_slope according to the triangular wave voltage signal VRAMP generated by the oscillator circuit 210, which is used to compensate the waveform of the inductor current IL. The duty cycle modulation circuit 230 is connected with the slope compensation circuit 220, and is configured to generate a sampling voltage according to the slope compensation current I_slope obtained by the slope compensation circuit 220 and a sampling current, wherein the sampling current is obtained according to a constant current and the sampled inductor current. In addition, the duty cycle modulation circuit 230 can generate a duty cycle modulation signal MAIN_TRIP according to the sampling voltage and an error voltage after obtaining the sampling voltage, wherein the error voltage is an output signal of an error amplifier, and the specific error signal is obtained by the error amplifier according to the DC output voltage of the switching converter and a preset reference voltage. The latch circuit 240 is connected with the oscillator circuit 210 and the duty cycle modulation circuit 230, and is configured to generate a switching signal according to the clock signal CLK generated by the oscillator circuit 210 and the duty cycle modulation signal MAIN_TRIP generated by the duty cycle modulation circuit 230, to control the conduction state of the power tube.

[0029] With Figure 1 Compared with the control circuit of the conventional switching converter in the prior art, the clock signal CLK generated by the oscillator circuit 210 in the embodiment of the present disclosure refers to the gate signal LG of the first power tube, so as to control the timing of resetting the slope compensation current I_slope, and avoid the situation that the comparator (the comparator in the duty cycle modulation circuit) is triggered by mistake before the inductor current decreases to the valley current value, so as to ensure the regular waveform of the inductor current.

[0030] Specifically, as Figure 4As shown, the oscillator circuit 210 comprises a first current source Iosc, a first comparator COMP, a first capacitor Css, a first transistor MN1, an AND gate 211, a high level pulse generating circuit 212, the input terminal of the first current source Iosc is connected to a voltage source VCC, the output terminal of the first current source Iosc is connected to one end of the first capacitor Css and the non-inverting input terminal of the first comparator COMP, and the output terminal of the first current source Iosc generates a triangular wave voltage signal VRAMP; the other end of the first capacitor Css is grounded, the inverting input terminal of the first comparator COMP receives a reference voltage VBG; one input terminal of the AND gate 211 is connected to the output terminal of the first comparator COMP, the other input terminal of the AND gate 211 receives a gate signal LG of the first power transistor ML, and the output terminal of the AND gate 211 is connected to the input terminal of the high level pulse generating circuit 212; the first transistor MN1 is connected in parallel across the first capacitor Css, the control terminal of the first transistor MN1 is connected to the output terminal of the high level pulse generating circuit 212, and the output terminal of the high level pulse generating circuit 212 generates a clock signal CLK. In addition, the direct current source signal in the above-mentioned "generating a triangular wave voltage signal VRAMP according to a direct current source signal" refers to the first current source Iosc here. Further, the high level pulse generating circuit 212 can be a single shot circuit generating a 20ns-30ns pulse, for example, the high level pulse generating circuit 212 can be a 20ns one shot. The reference voltage VBG can be a voltage value of 0.6V or 1.2V, etc.

[0031] As shown in Figure 4 The slope compensation circuit 220 comprises a second transistor MP0, a third transistor MN0 and a first resistor R1, which are connected in series between the input terminal of the first current source Iosc and the ground terminal; the control terminal of the second transistor MP0 is connected to the first pole of the second transistor MP0 and the control terminal of the fourth transistor MP1 in the duty cycle modulation circuit 230, so as to mirror the generated slope compensation current I_slope to the duty cycle modulation circuit 230; the control terminal of the third transistor MN0 is connected to the output terminal of the first current source Iosc, so as to receive the triangular wave voltage signal VRAMP.

[0032] As shown in Figure 4As shown, the duty cycle modulation circuit 230 comprises a second comparator PWM_COMP, a fourth transistor MP1, a second current source (Idc-Isns), and a second resistor RS. The fourth transistor MP1 and the second resistor RS are connected in series between the input terminal of the first current source Iosc and the ground terminal. The second current source (Idc-Isns) is connected in parallel with the fourth transistor MP1. The positive input terminal of the second comparator PWM_COMP is connected to a node between the fourth transistor MP1 and the second resistor RS, and the output terminal of the second current source (Idc-Isns), to obtain a sampling voltage Vsum. The inverting input terminal of the second comparator PWM_COMP receives an error amplification signal eaout, and the output terminal of the second comparator PWM_COMP outputs a duty cycle modulation signal MAIN_TRIP. It should be noted that the error amplification signal eaout is a signal obtained by passing a direct current output voltage and a preset reference voltage through an error amplifier.

[0033] As shown in Figure 4 The latch circuit 240 comprises a first latch LH1 and a second latch LH2. The set terminal S of the first latch LH1 is connected to the output terminal of the second comparator PWM_COMP. The reset terminal R of the first latch LH1 is connected to the output terminal of the high-level pulse generation circuit 212. The output terminal Q of the first latch LH1 is connected to the control terminal of the first power transistor ML in the switching converter. The set terminal S of the second latch LH2 is connected to the output terminal of the second comparator PWM_COMP. The reset terminal R of the second latch LH2 is connected to the output terminal of the high-level pulse generation circuit 212. The output terminal Q of the second latch LH2 is connected to the control terminal of the second power transistor MH in the switching converter.

[0034] In combination Figure 4the working principle of the control circuit of the switching converter of the embodiment of the present disclosure is described with reference to the circuit diagram: the first current source Iosc charges the first capacitor Css to generate a triangular wave voltage signal VRAMP, which is used as the positive input signal of the first comparator COMP, and then the comparison result of the signal VBG at the negative input terminal of the first comparator COMP is output, and then the comparison result is calculated with the gate signal LG of the first power tube ML by the AND gate 211 to obtain a calculation result, and then the clock signal CLK is output by the high-level pulse generating circuit 212 according to the calculation result; on the other hand, the triangular wave voltage signal VRAMP is also dropped on the first resistor R1 through the third transistor MN0 to generate a triangular wave current, and the slope compensation current I_slope is generated through the mirror effect of the fourth transistor MP1 and the second transistor MP0, and finally the slope compensation current I_slope and the sampling current (Idc-Isns) act on the second resistor RS to obtain the sampling voltage Vsum, and the sampling voltage Vsum and the error voltage eaout (corresponding to the error amplification signal in the foregoing) are compared by the second comparator PWM_COMP to generate the duty cycle modulation signal MAIN_TRIP; the clock signal CLK and the duty cycle modulation signal MAIN_TRIP are input into the set end S and the reset end R of the first latch LH1 and the second latch LH2 respectively, and the first output signal and the second output signal of the first latch LH1 and the second latch LH2 are used as the gate signals LG and HG of the first power tube ML and the second power tube MH to control the turn-on and turn-off of the power tubes. Based on the above working principle, when the triangular wave voltage signal VRAMP (clock charging capacitor (first capacitor Css) voltage) is higher than VBG, the first comparator COMP outputs a high level, but cannot immediately reset the slope compensation current I_slope, and must wait for the gate signal LG of the first power tube ML to be high before resetting the slope compensation current I_slope, that is, in the process of the upper tube (the second power tube MH) current being higher than the valley current limiting value, the duty cycle modulation signal MAIN_TRIP is always high, and the inductor current IL continues to decrease, and once the upper tube (the second power tube MH) current decreases to the current limiting point (the valley current limiting value VY_LIM), the lower tube (the first power tube ML) is immediately turned on, and the inductor current IL rises. Figure 1 The LG signal is added to the traditional circuit to control the reset of the clock and the slope compensation triangular wave, so that Figure 2 At time t1 in the above formula, the first comparator COMP outputs a high level, but LG is not high, so the slope compensation current I_slope continues to increase and is not reset, and the sampling voltage Vsum is also still higher than the error voltage eaout, so in the process of the upper tube (the second power tube MH) current being higher than the valley current limiting value, the duty cycle modulation signal MAIN_TRIP is always high, and the inductor current IL continues to decrease, and once the upper tube (the second power tube MH) current decreases to the current limiting point (the valley current limiting value VY_LIM), the lower tube (the first power tube ML) is immediately turned on, and the inductor current IL rises.

[0035] Further, the waveform obtained by the control circuit of the switching converter according to the embodiment of the present disclosure is as followsFigure 5 As shown from top to bottom, the waveforms are inductive current IL waveform, clock signal CLK waveform, slope compensation current I_slope waveform, MAIN_TRIP signal waveform, and waveform of gate signal LG of the first power tube ML. As can be seen from the waveforms, at time t1, the slope compensation current I_slope continues to increase and will not reset until the upper tube (the second power tube MH) current is not less than the valley current limit value VY_LIM. During the process of the inductive current IL falling to the valley current limit value VY_LIM, the duty cycle modulation signal MAIN_TRIP is always high, and there is no case like Figure 2 the lower tube (the first power tube ML) opens immediately, and the inductive current IL rises. As can be seen from the waveforms, the waveform of the inductive current IL is relatively regular. Figure 5

[0036] In summary, compared with the control circuit of the existing switching converter, the control circuit of the switching converter of the embodiment of the present disclosure introduces the lower tube control logic. On the basis of the control circuit of the existing switching converter, the lower tube gate signal LG is added to control the reset of the clock and the slope compensation triangular wave. In this way, when the inductive current is higher than the current limit value, the clock is allowed to reset the slope compensation current only when the lower tube is in the open state, thereby ensuring the regularity of the waveform of the inductive current.

[0037] Further, the embodiment of the present disclosure proposes a switching converter, as Figure 3 shown, the switching converter 200 includes a main power circuit 250 configured to transmit electrical energy from an input end to an output end by using a power tube to generate a direct current output voltage Vout from a direct current input voltage Vin; and the control circuit (210 to 240) in the above embodiment for generating a switching drive signal to control the conduction state of the power tube. The description of the control circuit (210 to 240) can be found in the corresponding description in the foregoing embodiments, which will not be repeated here. It should be noted that in the present disclosure, the power tube is a transistor that works in switching mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The power tube includes a high potential end and a low potential end on the current path, and a control end for receiving a drive signal to control the conduction and turn-off of the power tube.

[0038] Preferably, as Figure 4 ​As shown, the main power circuit 250 includes an inductor L, a first power tube ML, a second power tube MH, an output capacitor Cout, and a load Rload. The inductor L and the first power tube ML are connected in series between an input terminal Vin and a ground terminal. The second power tube MH is connected between a middle node of the inductor L and the first power tube ML and an output terminal. The output capacitor Cout is connected between an output terminal Vout and the ground terminal. The load Rload is connected in parallel across the output capacitor Cout. The control circuit (210-240) controls the conduction and turn-off of the first power tube ML and the second power tube MH by sending a switching drive signal to the control terminals of the first power tube ML and the second power tube MH. It should be noted that, Figure 4 The DC input voltage Vin and the voltage source VCC of the control circuit are shared, but those skilled in the art should understand that Vin and VCC are not necessarily shared in actual applications. The embodiments of the present disclosure are only for simplifying the circuit diagram, and this is not the focus of the protection of the present disclosure.

[0039] In addition, in the above embodiments, the switching converter of the embodiments of the present disclosure is a boost converter, specifically a constant-frequency valley-current mode boost converter.

[0040] In summary, compared with the existing switching converter, the switching converter of the embodiments of the present disclosure introduces the lower tube control logic. On the basis of the control circuit of the existing switching converter, the lower tube gate signal is added to control the reset of the clock and the slope compensation triangular wave. Thus, when the inductor current is higher than the current limit value, the clock is allowed to reset the slope compensation current only when the lower tube is in the open state, thereby ensuring the regular waveform of the inductor current.

[0041] The description of the same or corresponding module units in the embodiments of the present disclosure can be referred to each other.

[0042] In the above description, the well-known structural elements and steps are not described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structural elements. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0043] In accordance with the embodiments of the present disclosure as described above, these embodiments do not describe all the details and do not limit the present disclosure to only the specific embodiments. Obviously, many modifications and changes can be made based on the above description. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can well utilize the present disclosure and make modifications based on the present disclosure. The scope of protection of the present disclosure should be subject to the scope defined by the claims of the present disclosure.

[0044] The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, the references "a" and "an" are typically used to describe a single item unless otherwise indicated. Similarly, the word "or" is generally intended to mean "and / or" unless otherwise indicated. The terms "comprises," "comprising," "includes," "including," and the like can be used herein and are intended to mean that an item includes one or more of the recited elements or a subset thereof. Similarly, the terms "includes," "including," and the like are intended to mean that an item includes one or more of the recited elements or a subset thereof, but does not require the presence of these elements or subsets at a particular time. The use of the term "or" in the context of a list of items is intended to mean that one or more of the items can be present, and the use of the term "and" in the context of a list of items is intended to mean that one or more of the items can be present. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration," and not to imply that a described embodiment is preferred or superior to other embodiments. The term "in response to" is used herein to mean "in response to a determination that" and not to imply that a described embodiment is preferred or superior to other embodiments.

[0045] Further aspects and scope of adaptations become apparent from the description provided herein. It should be understood that various aspects of the disclosure can be practiced alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0046] The foregoing detailed description of several embodiments of the disclosure has been presented for purposes of illustration and description. It is apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure. The disclosure is defined by the appended claims.

Claims

1. A control circuit for a switching converter, said switching converter being a fixed frequency valley current mode boost converter employing a power transistor controlled input to output transfer of electrical energy to produce a direct current output voltage from a direct current input voltage, characterised in that, The control circuit comprises: an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit, a latch circuit, The oscillator circuit is configured to generate a triangular wave voltage signal according to a direct current source signal, and is further configured to generate a clock signal according to the triangular wave voltage signal and a gate signal of a first power tube in the switching converter; The generation of the clock signal according to the triangular wave voltage signal and the gate signal of the first power tube comprises: outputting a comparison result of the triangular wave voltage signal as a positive-phase input signal and an inverted-phase input signal through a first comparator, performing AND calculation on the comparison result and the gate signal of the first power tube to obtain a calculation result, and outputting the clock signal from a high-level pulse generation circuit according to the calculation result; The slope compensation circuit is configured to generate a slope compensation current according to the triangular wave voltage signal; The duty cycle modulation circuit is configured to generate a sampling voltage according to the slope compensation current and a sampling current, and is further configured to generate a duty cycle modulation signal according to the sampling voltage and an error voltage; The latch circuit is configured to generate a switching signal according to the clock signal and the duty cycle modulation signal, so as to control a conduction state of the power tube.

2. The control circuit of claim 1, wherein, The oscillator circuit comprises: a first current source, a first comparator, a first capacitor, a first transistor, an AND gate, and a high-level pulse generation circuit, The input end of the first current source is connected to a voltage source, the output end of the first current source is connected to one end of the first capacitor and the positive-phase input end of the first comparator, and the output end of the first current source generates the triangular wave voltage signal; The other end of the first capacitor is grounded, and the inverted-phase input end of the first comparator receives a reference voltage; One input end of the AND gate is connected to the output end of the first comparator, the other input end of the AND gate receives the gate signal of the first power tube, and the output end of the AND gate is connected to the input end of the high-level pulse generation circuit; The first transistor is connected in parallel to the first capacitor, the control end of the first transistor is connected to the output end of the high-level pulse generation circuit, and the output end of the high-level pulse generation circuit generates the clock signal.

3. The control circuit of claim 2, wherein, The slope compensation circuit comprises a second transistor, a third transistor, and a first resistor, The second transistor, the third transistor, and the first resistor are connected in series between the input end of the first current source and the ground end; The control end of the second transistor is connected to the first pole of the second transistor and the control end of a fourth transistor in the duty cycle modulation circuit, so as to mirror the generated slope compensation current to the duty cycle modulation circuit; The control end of the third transistor is connected to the output end of the first current source, so as to receive the triangular wave voltage signal.

4. The control circuit of claim 3, wherein, The duty cycle modulation circuit comprises: a second comparator, a fourth transistor, a second current source, and a second resistor, The fourth transistor and the second resistor are connected in series between the input end of the first current source and the ground end; The second current source is connected in parallel to the fourth transistor; The positive input terminal of the second comparator is connected to a node between the fourth transistor and the second resistor and the output terminal of the second current source to obtain the sampling voltage; the inverting input terminal of the second comparator receives an error amplification signal, and the output terminal of the second comparator outputs the duty cycle modulation signal.

5. The control circuit of claim 4, wherein, The latch circuit comprises a first latch and a second latch, The set terminal of the first latch is connected to the output terminal of the second comparator, the reset terminal of the first latch is connected to the output terminal of the high-level pulse generation circuit, and the output terminal of the first latch is connected to the control terminal of the first power tube in the switch converter. The set terminal of the second latch is connected to the output terminal of the second comparator, the reset terminal of the second latch is connected to the output terminal of the high-level pulse generation circuit, and the output terminal of the second latch is connected to the control terminal of the second power tube in the switch converter.

6. The control circuit of claim 4, wherein, The error amplification signal is a signal obtained by an error amplifier according to a direct-current output voltage and a preset reference voltage.

7. The control circuit of claim 4, wherein, The control circuit is in a constant-frequency valley-current mode.

8. A switching converter, characterized by Comprise: A main power circuit configured to control the transmission of electrical energy from an input terminal to an output terminal by using a power tube, thereby generating a direct-current output voltage according to a direct-current input voltage; And The control circuit according to any one of claims 1 to 7 is used to generate a switch control signal to control the conduction state of the power tube.

9. The switching converter of claim 8, wherein, The main power circuit comprises an inductor, a first power tube, a second power tube, an output capacitor, and a load: The inductor and the first power tube are connected in series between the input terminal and the ground terminal; The second power tube is connected between the intermediate node of the inductor and the first power tube and the output terminal; The output capacitor is connected between the output terminal and the ground terminal; The load is connected in parallel across the output capacitor.

10. The switching converter of claim 8, wherein, The switch converter is a boost converter.

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