Method and associated device for controlling a manufacturing process

Abstract

Disclosed is a method for controlling a process of manufacturing a semiconductor device, the method comprising: obtaining a first control grid associated with a first lithography apparatus, the first lithography apparatus being used for a first patterning process of patterning a first substrate; obtaining a second control grid associated with a second lithography apparatus, the second lithography apparatus being used for a second patterning process of patterning a second substrate; and based on the first control grid and the second control grid, determining a common control grid definition for a bonding step, the bonding step being used for bonding the first substrate and the second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data, the bonded substrate metrology data including data related to metrology performed on the bonded substrate; and based on the bonded substrate metrology data, determining a correction to the execution of the bonding step, determining the correction including determining a common optimization correction to the bonding step and to the first patterning process and / or the second patterning process.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to European Application No. 20160538.3, filed on Mar. 3, 2020, and European Application No. 20164221.2, filed on Mar. 19, 2020, the entire contents of these European patent applications being incorporated herein by reference. Field of the invention

[0003] The present invention relates to methods and apparatus for applying a pattern to a substrate in a lithographic manufacturing process and subsequently bonding two or more substrates together. Background art

[0004] A lithographic apparatus is a machine that applies a desired pattern onto a substrate, typically onto a target portion of the substrate. A lithographic apparatus can be used in the manufacture of integrated circuits (ICs). In such a case, a patterning device, alternatively referred to as a mask or a reticle, can be used to generate a circuit pattern to be formed on a single layer of the IC. Such a pattern can be transferred onto a target portion (e.g., including a portion of a die, one or more dies) on a substrate (e.g., a silicon wafer). Typically, the pattern is transferred by imaging the pattern onto a layer of radiation-sensitive material (resist) provided on the substrate. Usually, a single substrate will contain a grid of adjacent target portions that are successively patterned. Known lithographic apparatuses include so-called steppers and so-called scanners, in which each target portion is irradiated by exposing the entire pattern onto the target portion at once in a stepper; and in a scanner, each target portion is irradiated by synchronously scanning the substrate in a direction parallel or anti-parallel to a given direction (“scan” direction) while the radiation beam scans the pattern in that given direction. The pattern can also be transferred from the patterning device onto the substrate by imprinting the pattern onto the substrate.

[0005] To monitor the lithographic process, parameters of the patterned substrate are measured. The parameters can include, for example, overlay errors between successive layers formed in or on the patterned substrate, and critical dimension (CD) of the developed photosensitive resist. Such measurements can be performed on product substrates and / or on dedicated metrology targets. There are various techniques for measuring microstructures formed during the lithographic process, including using scanning electron microscopes and various dedicated tools. A fast and non-invasive form of dedicated inspection tool is a scatterometer in which a radiation beam is directed onto a target on the surface of the substrate and the properties of the scattered or reflected beam are measured. Two main types of scatterometers are known. A spectroscopic scatterometer directs a broadband radiation beam onto the substrate and measures the spectrum (intensity as a function of wavelength) of the radiation scattered into a specific narrow angular range. An angularly resolved scatterometer uses a monochromatic radiation beam and measures the intensity of the scattered radiation as a function of angle.

[0006] Examples of known scatterometers include angular resolution scatterometers of the type described in US2006033921A1 and US2010201963A1. The targets used by such scatterometers are relatively large, e.g., 40 μm × 40 μm, and the grating and the measurement beam produce a spot smaller than the grating (i.e., the grating is underfilled). In addition to measuring feature shape by reconstruction, such devices can also be used to measure diffraction-based overlay, as described in the published patent application US2006066855A1. Diffraction-based overlay metrology using dark field imaging of diffraction orders enables overlay measurement of smaller targets. Examples of dark field imaging metrology can be found in international patent applications WO2009 / 078708 and WO2009 / 106279, the entire contents of which are hereby incorporated by reference. Further developments of the technology have been described in the published patent publications US20110027704A, US20110043791A, US2011102753A1, US20120044470A, US20120123581A, US20130258310A, US20130271740A, and WO2013178422A1. These targets can be smaller than the illumination spot and can be surrounded by product structures on the wafer. Multiple gratings can be measured in one image using a composite grating target. The contents of all these applications are hereby incorporated by reference into this document.

[0007] In the manufacture of integrated devices, process control methods are used to monitor and control the process of applying a pattern to a substrate or measuring such a pattern. Such process control techniques are typically performed to obtain corrections for control of the process. Subsequently, (for some devices) it is sometimes necessary to bond substrates together. The bonding processes include die-to-die, die-to-wafer, and wafer-to-wafer. Wafer-to-wafer bonding (where the entire wafers are permanently bonded together before dicing) has the potential to provide a high-accuracy and high-throughput bonding solution.

[0008] It is desired to improve process control methods in the manufacture of desired integrated devices. Summary of the Invention

[0009] In a first aspect of the present invention, there is provided a method for controlling the manufacture of semiconductor devices, the method comprising: obtaining a first control grid associated with a first lithography apparatus for a first patterning process of patterning a first substrate; obtaining a second control grid associated with a second lithography apparatus for a second patterning process of patterning a second substrate; determining, based on the first control grid and the second control grid, a common control grid definition for a bonding step for bonding the first substrate and the second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data related to metrology performed on the bonded substrate; and determining a correction for the performance of the bonding step on subsequent substrates based on the bonded substrate metrology data, wherein determining the correction includes: determining a common optimization correction for the bonding step and for one or both of the first patterning process and the second patterning process.

[0010] In a second aspect of the present invention, there is provided a lithography apparatus configured to provide a product structure to a substrate in a lithography process, the lithography apparatus comprising: a processor operable to optimize the control of the lithography apparatus during the lithography process by performing the method of the first aspect.

[0011] In a third aspect of the present invention, there is provided a computer program comprising program instructions operable to perform the method of the first aspect when run on a suitable device.

[0012] In the following, further aspects, features and advantages of the present invention and the structure and operation of various embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Based on the teachings contained in the present invention, those skilled in the relevant art will appreciate additional embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0014] Figure 1 A lithography apparatus forming a production facility for semiconductor devices and other equipment is depicted;

[0015] Figure 2 A schematic diagram of a scatterometer for use in measuring a target according to an embodiment of the present invention is included;

[0016] Figure 3 Is a schematic general view of a control mechanism utilizing a scanner stability module during a lithography process.

[0017] Figure 4 is a flowchart depicting a current method of fabricating integrated devices using die - to - die bonding;

[0018] Figure 5 is a flowchart depicting a method of fabricating integrated devices using die - to - die bonding according to an embodiment of the present invention;

[0019] Figure 6 illustrates a flowchart of an additional implementation for determining post - bonding lithography correction according to an embodiment of the present invention; and

[0020] Figure 7 is a schematic diagram of a diffractive metrology target for bond metrology according to an embodiment of the present invention. Detailed Description

[0021] Before describing embodiments of the present invention in detail, it is instructive to present an example environment in which embodiments of the present invention may be implemented.

[0022] Figure 1 A lithography apparatus LA is shown at 200 as part of an industrial production facility for implementing a high - volume lithography manufacturing process. In this example, the manufacturing process is adapted to fabricate semiconductor products (integrated circuits) on a substrate such as a semiconductor wafer. Those skilled in the art will appreciate that various products can be fabricated by processing different types of substrates in a variant of this process. The production of semiconductor products is presented only as an example of significant current commercial interest.

[0023] Within the lithography apparatus (or "litho - tool" 200), a measurement station MEA is shown at 202 and an exposure station EXP is shown at 204. A control unit LACU is shown at 206. In the example, each substrate visits the measurement station and the exposure station to have a pattern applied. For example, in an optical lithography apparatus, a projection system is used to transfer a product pattern from a patterning device MA to the substrate using conditioned radiation and the projection system. This is done by forming an image of the pattern in a layer of radiation - sensitive resist material.

[0024] As used herein, the term "projection system" should be construed broadly to include any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic, and electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used or for other factors such as the use of an immersion liquid or the use of a vacuum. The patterning device MA may be a mask or reticle to which a pattern is imparted to a radiation beam that is transmitted or reflected by the patterning device. Well-known operating modes include step and scan modes. It is well known that the projection system can cooperate with the support and positioning systems for the substrate and the patterning device in various ways to apply the desired pattern to many target portions on the substrate. A programmable patterning device may be used in place of a reticle with a fixed pattern. For example, the radiation may include electromagnetic radiation in the deep ultraviolet (DUV) or extreme ultraviolet (EUV) bands. The present disclosure is also applicable to other types of lithography processes, such as imprint lithography and direct write lithography, for example by an electron beam.

[0025] The lithography apparatus control unit LACU controls all movements and measurements of various actuators and sensors to receive the substrate W and the reticle MA and to implement the patterning operation. The LACU also includes signal processing and data processing capabilities to perform the desired calculations related to the operation of the apparatus. In practice, the control unit LACU will be implemented as a system of many sub-units, each sub-unit handling the real-time data acquisition, processing, and control of a subsystem or component within the apparatus.

[0026] Before applying a pattern to a substrate at exposure station EXP, the substrate is processed at measurement station MEA such that various preparatory steps can be carried out. The preparatory steps can include mapping the surface height of the substrate using a level sensor and measuring the positions of alignment marks on the substrate in height using an alignment sensor. The alignment marks are nominally arranged in a regular grid pattern. However, due to inaccuracies in mark generation and due to substrate deformation occurring during its entire processing, these marks deviate from the ideal grid. Therefore, in addition to measuring the position and orientation of the substrate, in practice the alignment sensor must measure in detail the positions of many marks across the substrate area if the device is to print product features at the correct locations with very high accuracy. The device can be of the so-called dual stage type, having two substrate stages, each substrate stage having a positioning system controlled by a control unit LACU. While one substrate on one substrate stage is being exposed at the exposure station EXP, another substrate can be loaded onto the other substrate stage at the measurement station MEA such that various preparatory steps can be carried out. Therefore, measurement of the alignment marks is very time-consuming, and having two substrate stages can significantly increase the throughput of the device. If the position sensor IF cannot measure the position of the substrate stage at both the measurement station and the exposure station, a second position sensor can be provided to enable tracking of the position of the substrate stage at both stations. The lithographic apparatus LA can for example be of the so-called dual platform type, having two substrate stages and two stations - an exposure station and a measurement station - between which the substrate stages can be exchanged.

[0027] Within the production facility, the device 200 forms part of a "lithography cell" or "lithography cluster" which also includes a coating device 208 for applying a photosensitive resist and other coatings to a substrate W for patterning by the device 200. At the output side of the device 200, a baking device 210 and a developing device 212 are provided for developing the exposed pattern into a solid resist pattern. Between all these devices, a substrate handling system is responsible for supporting the substrates and transferring them from one device to the next. These devices are commonly referred to as a track or a coat develop system and are controlled by a track or coat develop system control unit which itself is controlled by a management control system SCS which also controls the lithographic apparatus via the lithographic apparatus control unit LACU. Thus, the different devices can be operated to maximize throughput and processing efficiency. The management control system SCS receives option information R which provides in great detail a definition of the steps to be carried out to create each patterned substrate.

[0028] Once the pattern has been applied and developed in the lithography unit, the patterned substrate 220 is transferred to other processing equipment, such as the equipment illustrated at markers 222, 224, 226. Various processing steps are implemented by various equipment in a typical manufacturing facility. By way of example, the equipment 222 in the embodiment is an etch station, and the equipment 224 performs an etch anneal step. Additional physical and / or chemical processing steps are applied in additional equipment 226, etc. Fabricating a real device may require many types of operations, such as deposition of materials, modification of surface material properties (oxidation, doping, ion implantation, etc.), chemical mechanical polishing (CMP), etc. In practice, the equipment 226 may represent a series of different processing steps performed in one or more pieces of equipment. As another example, equipment and processing steps for implementing self-aligned multiple patterning may be provided to generate multiple smaller features based on a premise pattern placed by the lithography equipment.

[0029] As is well known, the fabrication of semiconductor devices involves many repetitions of such processing to build up a device structure with the appropriate materials and patterns layer by layer on a substrate. Thus, the substrates 230 arriving at the lithography cluster may be newly prepared substrates, or they may be substrates that have previously been fully processed in the cluster or in another piece of equipment. Similarly, depending on the processing required, the substrates 232 leaving the equipment 226 may be returned for subsequent patterning operations in the same lithography cluster, they may be designated for patterning operations in a different cluster, or they may be finished products to be sent for dicing and packaging.

[0030] Each layer in the product structure requires a different set of process steps, and the type of the equipment 126 used at each layer may be completely different. In addition, even when the processing steps to be applied by the equipment 226 are nominally the same, in a large facility, there may be several ostensibly identical machines working in parallel to perform step 226 on different substrates. Minor differences in the setup or malfunction between these machines may mean that they affect different substrates in different ways. Even for steps that are relatively common to each layer, such as etching (equipment 222), it may be implemented by several ostensibly identical etching devices working in parallel to maximize production volume. In addition, in practice, different layers require different etching processes, such as chemical etching, plasma etching, depending on the details of the material to be etched and specific requirements, such as anisotropic etching, for example.

[0031] The previous and / or subsequent processes (as mentioned just above) can be carried out in other lithography apparatuses, and even in different types of lithography apparatuses. For example, in the process of device manufacturing, some layers that require very high parameters such as resolution and overlay compared to other less demanding layers can be carried out in more advanced lithography tools. Thus, some layers can be exposed in immersion lithography tools, while other layers are exposed in "dry" tools. Some layers can be exposed in tools operating at DUV wavelengths, while other layers are exposed using EUV wavelength radiation.

[0032] In order to expose the substrate exposed by the lithography apparatus correctly and consistently, it is desirable to inspect the exposed substrate to measure properties such as overlay error between subsequent layers, line thickness, critical dimension (CD), etc. Thus, the manufacturing facility in which the lithography cell LC is located also includes a metrology system that receives some or all of the substrates W that have been processed in the lithography cell. The metrology results are provided directly or indirectly to the management control system SCS. If an error is detected, the exposure of subsequent substrates can be adjusted, especially if the metrology can be carried out quickly enough and rapidly such that other substrates of the same batch are still awaiting exposure. In addition, the substrates that have been exposed can be stripped and reworked to improve the yield, or discarded, thereby avoiding further processing of substrates known to be defective. In the case where only some target portions of the substrate are defective, further exposure can be carried out only on those good target portions.

[0033] Figure 1 A metrology device 240 is also shown, which is arranged to measure parameters of the product at desired stages in the manufacturing process. A common example of a metrology station in a modern lithography production facility is a scatterometer (e.g., a dark field scatterometer, an angular resolved scatterometer, or a spectroscopic scatterometer), and it can be applied to measure the properties of the developed substrate at 220 before etching at the device 222. Using the metrology device 240, it can be determined, for example, that important performance parameters such as overlay or critical dimension (CD) do not meet the specified accuracy requirements in the developed resist. Before the etching step, there is an opportunity to strip the developed resist and reprocess the substrate 220 through the lithography cluster. The metrology results 242 from the device 240 can be used to maintain the accurate performance of the patterning operation in the lithography cluster over time through small adjustments by the management control system SCS and / or the control unit LACU206, thereby minimizing the risk that the product is manufactured out of specification and the need for rework.

[0034] Additionally, metrology device 240 and / or other metrology devices (not shown) may be applied to measure the properties of the processed substrates 232, 134 and the incoming substrate 230. The metrology devices may be used on the processed substrates to determine critical parameters such as overlay or CD.

[0035] Shown in Figure 2 (a) of is a metrology device suitable for use in an embodiment of the present invention. Shown in more detail in Figure 2 (b) of are the target T for irradiating the target with measurement radiation and the diffracted light rays. The illustrated metrology device is of the type known as a dark field metrology device. The metrology device may be a stand-alone device or integrated into, for example, a lithography apparatus LA located at a measurement station or in a lithography cell LC. The optical axis with several branches throughout the device is indicated by the dashed line O. In this device, light emitted by the source 11 (e.g., a xenon lamp) is guided via a beam splitter 15 to the substrate W by an optical system including lenses 12, 14 and an objective 16. These lenses are arranged in a double sequence 4F arrangement. Different lens arrangements may be used, provided that the lens arrangement still provides an image of the substrate onto the detector and at the same time allows access to the intermediate pupil plane for spatial frequency filtering. Thus, the angular range of the radiation incident on the substrate may be selected by defining a spatial intensity distribution in the plane of the spatial spectrum of the substrate plane, where this plane is referred to as the (conjugate) pupil plane. In particular, this may be done by inserting an appropriately shaped aperture plate 13 between the lenses 12 and 14 in the plane of the back-projected image of the objective pupil plane. In the illustrated example, the aperture plate 13 has different forms labeled 13N and 13S to allow selection of different illumination modes. In the present example, the illumination system forms an off-axis illumination mode. In the first illumination mode, for ease of description only, the aperture plate 13N provides off-axis illumination from the direction designated as "north". In the second illumination mode, the aperture plate 13S is used to provide a similar illumination, but from the opposite direction labeled "south". By using different apertures, it is possible to configure different illumination modes. The remainder of the pupil plane is desired to be dark, since any unwanted light outside the desired illumination mode will interfere with the desired measurement signal.

[0036] As Figure 2As shown in (b) thereof, the target T is placed such that the substrate W is perpendicular to the optical axis O of the objective lens 16. The substrate W may be supported by a support member (not shown). The ray I of the measurement radiation is incident on the target T at an angle deviating from the axis O, generating a zero-order ray (solid line 0) and two first-order rays (the dotted line represents the +1 order, and the double dotted line represents the -1 order). It should be remembered that for a small overfilled target, these rays are just one of many parallel rays covering the substrate area including the measurement target T and other features. Since the holes in the plate 13 have a finite width (necessary for allowing an effective number of rays), the incident ray I will actually occupy an angular range, and the diffracted rays 0 and +1 / -1 will spread slightly. According to the point spread function of the small target, each of the orders +1 and -1 will further spread over an angular range, rather than being a single ideal ray as shown. Note that the grating pitch and the illumination angle of the target can be designed or adjusted such that the first-order rays entering the objective lens are closely aligned with the central optical axis. In Figure 2 of (a) and Figure 2 the rays illustrated in (b) of are shown to be slightly off-axis, which is purely for the purpose of making them more distinguishable in the figure.

[0037] At least the 0th order and the +1st order diffracted by the target T on the substrate W are collected by the objective lens 16 and guided back through the beam splitter 15. Returning to Figure 2 of (a), both the first illumination mode and the second illumination mode are illustrated by specifying diametrically opposite holes labeled North (N) and South (S). When the incident ray I of the measurement radiation comes from the north side of the optical axis, that is, when the first illumination mode is applied using the aperture plate 13N, the +1st order diffracted ray labeled +1(N) enters the objective lens 16. Conversely, when the second illumination mode is applied using the aperture plate 13S, the -1 diffracted ray (labeled -1(S)) is the ray entering the lens 16.

[0038] The second beam splitter 17 divides the diffracted beam into two measurement branches. In the first measurement branch, the optical system 18 forms a diffraction spectrum (pupil plane image) of the target on the first sensor 19 (e.g., a CCD or CMOS sensor) using the zero-order diffracted beam and the first-order diffracted beam. Each diffracted order hits different points on the sensor so that image processing can compare and contrast multiple orders. The pupil plane image captured by the sensor 19 can be used for many measurement purposes used in the methods described herein, such as reconstruction. The pupil plane image can also be used to focus the metrology device and / or normalize the intensity measurement results of the first-order beam.

[0039] In the second measurement branch, the optical systems 20, 22 form an image of the target T on a sensor 23 (e.g., a CCD or CMOS sensor). In the second measurement branch, an aperture stop 21 is disposed in a plane conjugate to the pupil plane. The aperture stop 21 serves to block the zero-order diffraction beam, such that the image of the target formed on the sensor 23 is formed only by the -1st order or +1st order beams. The images captured by sensors 19 and 23 are output to a processor PU that processes the images, and the functions of the processor will depend on the particular type of measurement being performed. Note that the term "image" is used here in a broad sense. If only one of the -1st order and +1st order exists, then similarly an image of the grating lines will not be formed.

[0040] Figure 2 The specific forms of the aperture plate 13 and the field stop 21 shown in [figures] are merely examples. In another embodiment of the present invention, coaxial illumination of the target is used, and an aperture stop with an off-axis hole is used to transmit substantially only one first-order diffracted light to the sensor. In still other embodiments, instead of or in addition to the first-order beams, second-order beams, third-order beams, and higher-order beams ( Figure 2 not shown in [figures]) can be used in the measurement.

[0041] The target T may include a number of gratings, which may have overlapping offsets that are biased in different ways to facilitate the measurement of the overlap between layers in which different portions of a composite grating are formed. The gratings may also differ in their orientation, such that incident radiation is diffracted along the X and Y directions. In one example, the target may include two X-direction gratings with biased overlapping offsets +d and -d, and Y-direction gratings with biased overlapping offsets +d and -d. Separate images of these gratings can be identified in the image captured by the sensor 23. Once the separate images of the gratings have been identified, the intensities of those individual images can be measured, e.g., by averaging or summing the selected pixel intensity values within the identified regions. The intensities and / or other properties of the images can be compared with each other. These results can be combined to measure different parameters of the lithography process.

[0042] A variety of techniques can be used to improve the accuracy of pattern reproduction on a substrate. Accurate reproduction of a pattern on a substrate is not the only concern in IC production. Another concern is the yield, which generally measures how many functional devices a device manufacturer or device manufacturing process can produce on each substrate. Various methods can be employed to increase the yield. One such method attempts to make the production of a device (e.g., imaging a portion of a design layout onto a substrate using a lithography apparatus such as a scanner) more tolerant to perturbations in at least one of the processing parameters during the processing of the substrate (e.g., during imaging a portion of a design layout onto a substrate using a lithography apparatus). The concept of the Overlapping Process Window (OPW) is a useful tool for such a method. The production of a device (e.g., an IC) can include other steps such as substrate measurement before, after, or during imaging, loading or unloading the substrate, loading or unloading the patterning device, positioning a die under a projection optics before exposure, stepping from one die to another die, and so on. Additionally, various patterns on the patterning device can have different process windows (i.e., the space of processing parameters employed for patterns within production specifications). Examples of pattern specifications related to potential systematic defects include inspection necking, line pullback, line thinning, CD, edge placement, overlap, resist top loss, resist undercut, and / or bridging. The process window of all or some of the patterns (usually patterns within a specific region) on the patterning device can be obtained by combining (e.g., overlapping) the process windows of each individual pattern. The process window of these patterns is thus referred to as the overlapping process window. The boundaries of the OPW can include the boundaries of the process windows of some of the individual patterns. In other words, these individual patterns limit the OPW. These individual patterns can be referred to as "hot spots" or "Process Window Limiting Patterns (PWLP)", which are used interchangeably herein. When controlling the lithography process, it is possible and generally economical to focus on the hot spots. When the hot spots are defect-free, it is very likely that all the patterns are defect-free. The imaging becomes more tolerant to perturbations if the value of the processing parameter is closer to the OPW when the value of the processing parameter is outside the OPW, or if the value of the processing parameter is farther from the boundary of the OPW when the value of the processing parameter is within the OPW.

[0043] The values of the process parameters can be selected such that they are away from the boundaries of the OPW or the fitted OPW, to reduce the chance that the process parameters deviate outside the OPW and thereby cause defects and reduce the yield. One method of selecting the values of the process parameters includes: before actual imaging, (1) optimizing the lithography apparatus (e.g., optimizing the source and projection optics) and optimizing the design layout, (2) determining the OPW or the fitted OPW (e.g., by simulation), and (3) determining a point in the space of the process parameters that is as far as possible from the boundaries of the OPW or the fitted OPW (this point can be referred to as the "center" of the OPW or the fitted OPW) (i.e., determining the values of the process parameters).

[0044] During or before actual imaging, the process parameters may have perturbations that cause them to deviate from the point that is as far as possible from the boundaries of the OPW or the fitted OPW. For example, the focal length may change due to the topography of the substrate to be exposed, drift in the substrate stage, deformation of the projection optics, etc.; the dose may change due to drift in the source intensity, dwell time, etc. The perturbations may be large enough to cause the process parameters to go outside the OPW and may therefore result in defects. Various techniques can be used to identify the perturbed process parameters and to correct the process parameters. For example, if the focal length is perturbed, e.g., because an area of the substrate that is slightly elevated from the rest of the substrate is being exposed, the substrate stage can be moved or tilted to compensate for the perturbation.

[0045] The control of the lithography process is typically based on measurement feedback or feedforward and is then modeled using, for example, inter-field (across-substrate fingerprint) or intra-field (across-field fingerprint) models. Within a die, there may be separate functional areas, such as a memory area, a logic area, a contact area, etc. Each different functional area or different functional area type may have a different process window, and each process window may have a different process window center. For example, different functional area types may have different heights and therefore different optimal focus settings. In addition, different functional area types may have different structural complexities and therefore different focal length tolerances (focal length process windows) around each optimal focal length. However, due to control grid resolution limitations, typically the same focal length (or dose or position, etc.) setting will be used to form each of these different functional areas.

[0046] Figure 3Depict an overall lithography and metrology method that includes a stability module 300, which in this example is substantially an application running on a server. Three main process control loops labeled LP1, LP2, and LP3 are shown. The first loop LP1 provides cyclic monitoring for the stability control of the lithography apparatus using the stability module 300 and monitors the wafers. Immediately after the lithography apparatus is calibrated, a reference wafer or wafer set is exposed on the lithography apparatus or scanner 310 and measured by a metrology tool 315 to set reference parameters such as for focus and / or overlay (e.g., the overlay and / or focus baseline fingerprint of the scanner). At a later time (e.g., periodically), a monitoring wafer 305 is exposed on the scanner 310 and measured by the metrology tool 315. The stability module 300 compares the parameters (e.g., the current overlay and / or focus fingerprint of the scanner) from the measurement results of the monitoring wafer 305 and compares these parameters with the (stored) reference parameters. Based on this comparison, the stability module 300 calculates a correction routine 350 to correct the drift of these parameters, which is fed back to the scanner 310 and used when performing additional exposures. This can be repeated periodically to control scanner drift. For example, to determine a correction that returns the scanner operation to (or close to) the reference parameters. The exposure of the monitoring wafer may involve printing a marked pattern on top of a reference mark. By measuring the overlay error between the top mark and the bottom mark, the deviation of the performance of the lithography apparatus can be measured, even when the wafer has been removed from the apparatus and the wafer is placed in the metrology tool. Such a monitoring wafer may also include focus marks for monitoring focus.

[0047] In some embodiments, the monitoring wafer is dedicated to a specific lithography apparatus. In other embodiments, a "gold reference" benchmark monitoring wafer is defined, and the "gold reference" benchmark monitoring wafer can be used with an associated set of differences for all lithography apparatuses to adapt each individual lithography apparatus to the reference parameters. The stability module 300 calculates the difference (as a set of differences or a correction set) between the gold reference wafer and a standard monitoring wafer exposed on each scanner. The standard monitoring wafer plus the set of differences serves as a new copy of the reference. In this way, each scanner in a manufacturing site (fab), regardless of scanner type or model and grid differences, can be matched to this gold reference, thereby significantly increasing fab efficiency.

[0048] A second (APC) loop is used for in-product control of the stepper (to determine focus, dose, and overlay on the product wafer). The exposed product wafer 320 is transferred to metrology unit 315, where information related to parameters such as critical dimension, sidewall angle, and overlay is determined and transferred to the Advanced Process Control (APC) module 325. This data is also transferred to the stability module 300. Process corrections 340 are made prior to takeover by the Manufacturing Execution System (MES) 335, thus providing control of the stepper 310 that communicates with the scanner stability module 300.

[0049] A third control loop allows metrology to be integrated into the second (APC) loop (e.g., for double patterning). The post-etch wafer 330 is transferred to metrology unit 315, which again measures parameters read from the wafer, such as critical dimension, sidewall angle, and overlay. The parameters are transferred to the Advanced Process Control (APC) module 325. The loop continues in the same manner as the second loop.

[0050] Figure 4 Shown is a device manufacturing arrangement for fabricating a bonded substrate (and thus fabricating an IC based on the bonded substrate), the device manufacturing arrangement including a first manufacturing lithography cell LC1 and a second manufacturing lithography cell LC2. Within each lithography cell is a pair of lithography processing systems 400a, 400b and first metrology systems 410a, 410b. The lithography processing systems 400a, 400b may include full patterning systems. Such systems may include, for example (as described with respect to Figure 1 ), optical lithography equipment or scanners, track or coat develop system tools, deposition tools, etch tools, any other equipment for the patterning process, or any combination selected therefrom. The systems may also each include software applications 420a, 420b that communicate with their corresponding lithography processing systems 400a, 400b and metrology systems 410a, 410b, such that the results, designs, data, etc. of the lithography processing systems 400a, 400b and / or the metrology devices 410a, 410b can be stored and analyzed by the software applications 420a, 420b at the same or different times.

[0051] Once pairs of substrates or wafers are completed from each of the lithography cells LC1 and LC2, these substrates or wafers can be bonded within the bonding tool 440 to obtain a bonded wafer. In this context, bonding is wafer-to-wafer bonding, where entire wafers are aligned and bonded together such that individual die on each wafer are aligned. The concept of wafer-to-wafer bonding is known and is used in many IC manufacturing processes. The bonding tool 440 can include a bonding alignment device for aligning the wafers together for bonding. For example, the bonding tool 440 can perform pre-alignment using box-in-box markings (e.g., one per wafer) provided to the wafers, where visual inspection of the markings is used for alignment quality / position control. Another method uses two imaging sensors (e.g., face-to-face), which are first calibrated together to find their relative positions; then each sensor is used to align with the respective wafer to be bonded separately.

[0052] The lithography cells LC1 and LC2 can be the same lithography cell, can be different lithography cells but include one or more common tools and elements, or can have completely different sets of equipment and tools, and may even be completely different lithography cells located at different sites or fabs. For example, one or more of the tools or equipment of the lithography processing systems 400a and 400b can include different tools, or include the same tools within each respective system. Similarly, the metrology devices 410 and 410b can be the same device or different devices. The software applications 420a, 420b can be included in one or both of the corresponding lithography processing systems 400a, 400b, and / or in one or both of the first metrology systems 410a, 410b, or elsewhere.

[0053] As mentioned above, the lithography processing systems 400a, 400b can be configured to include Figure 1The lithography apparatus LA therein. The lithography processing systems 400a, 400b can be set to perform the patterning aspects of the patterning process and can optionally be configured to correct deviations occurring within the lithography processing systems 400a, 400b or in one or more other processes or devices during the patterning process. The lithography processing systems 400a, 400b can be capable of applying corrections to errors (such as imaging errors, focus errors, dose errors, etc.) by adjusting one or more modification devices of the lithography processing systems 400a, 400b. That is, the corrections can be made by any manufacturing processing tool within the lithography processing systems 400a, 400b that can purposefully modify the patterning errors. However, in the current system, these corrections (scanner corrections or other processing tool corrections) do not take into account any of the bonding processes during the bonding process performed by the bonding tool 440.

[0054] For example, errors can be corrected by adjusting one or more modification devices of the lithography apparatus, such as correcting or applying optical aberrations by using an adjustment mechanism AM, correcting or modifying the irradiation intensity distribution by using an adjuster AD, correcting or modifying the positions of the patterning device support structure MT and / or the wafer stage WT by using a positioner PM of the patterning device support structure MT and / or a positioner PW of the wafer stage WT, etc. Among them, for example, the lithography processing systems 400a, 400b include a track or a coating and developing system tool, and errors can be corrected by adjusting one or more modification devices of the track or the coating and developing system tool, such as modifying the baking temperature of the baking tool of the track or the coating and developing system, modifying the developing parameters of the developing tool of the track or the coating and developing system, etc. Similarly, among them, for example, the lithography processing systems 400a, 400b include an etching tool, and errors can be corrected by adjusting one or more modification devices of the etching tool, such as modifying the etching parameters (such as etching agent type, etching rate, etc.). Similarly, among them, for example, the lithography processing systems 400a, 400b include a planarization tool, and errors can be corrected by adjusting one or more modification devices of the planarization tool, such as modifying the planarization parameters. Similarly, among them, for example, the lithography processing systems 400a, 400b include a deposition tool, and errors can be corrected by adjusting one or more modification devices of the deposition tool, such as modifying the deposition parameters.

[0055] One or more modification devices of the lithography processing systems 400a, 400b can be capable of applying corrections up to a third-order polynomial to errors (such as imaging errors, focus errors, dose errors, etc.).

[0056] The metrology devices 410a, 410b may be configured to obtain measurement results related to wafers patterned by the lithography processing systems 400a, 400b. The metrology devices 410a, 410b may be configured to measure or determine one or more parameters of the patterns printed by the lithography processing systems 400a, 400b (e.g., overlay error, dose, focus, CD, etc.). The metrology devices 410a, 410b may be diffraction-based overlay metrology tools, which may measure, for example, overlay, critical dimension, and / or other parameters. The metrology devices 410a, 410b may be alignment devices used to measure the relative position between two objects (such as between a patterning device and a wafer). The metrology devices 410a, 410b may be level sensors for measuring the position of a surface, such as the height and / or rotational position of a wafer surface. The metrology devices 410a, 410b may be multiple metrology devices, including any combination of these devices.

[0057] The metrology devices 410a, 410b can measure and / or determine one or more values of one or more parameters (e.g., overlay error, CD, focus, dose, etc.) associated with errors in the patterning process. After the metrology devices 410a, 410b complete the measurement or determination, the software applications 420a, 420b generate modification information based on the measurement data (e.g., overlay error, CD, focus, dose, etc.). The software applications 420a, 420b can evaluate the one or more values of the one or more parameters to determine whether they are within tolerance ranges. If not, the software applications 420a, 420b determine modification information to reflect the error by the one or more values of the one or more parameters exceeding the tolerance. The software applications 420a, 420b can use one or more mathematical models to determine the errors that can be corrected by one or more modification devices of the lithography processing systems 400a, 400b, and provide information on one or more parameters (e.g., modification information) for the one or more modification devices of the lithography processing systems 400a, 400b, where the one or more parameters configure the one or more modification devices of the lithography processing systems 400a, 400b to correct the errors (e.g., eliminate or reduce the errors to within the tolerance ranges). One or more mathematical models can define a set of basis functions that fit the data after being parameterized. The one or more mathematical models can include models configured to simulate correctable errors for the lithography processing systems 400a, 400b. The models can specify the modification ranges that one or more modification devices of the lithography processing systems 400a, 400b can perform and determine the correctable errors within the ranges. That is, the ranges can specify the upper limit, lower limit, and / or both of the amount of modification that a particular modification device of the lithography processing systems 400a, 400b can perform.

[0058] Regarding Figure 4 The method described above has many drawbacks. Existing scanner control methods do not know and thus do not consider possible bonding steps with other wafers. Wafers may be bonded together with incompatible or poorly optimized grid / shape / dead die sites. For example, a first wafer may have a bowl-shaped fingerprint with dead (or out-of-spec) dies found at the edges, and a second wafer may have an inverted bowl-shaped fingerprint such that dead dies are found near the center. The bonding of these wafers will be suboptimal and wasteful compared to bonding wafers with similar fingerprints. For bonding use cases, a wafer may be paired with another wafer that has a specific grid that does not necessarily match the grid of the current wafer.

[0059] Now, many methods will be described to improve current manufacturing techniques for wafer-to-wafer bonding that combines two or more wafers together. The methods include the following:

[0060] ● Overlap feedforward correction of bonding fingerprints caused by the wafer bonding process;

[0061] ● Co-optimization of the correction capabilities of scanner and wafer bonder control capabilities;

[0062] ● Application of a reference scanner monitoring wafer for grid matching of wafers to be bonded;

[0063] · Yield-aware correction and prediction by applying computational metrology methods;

[0064] ● Diffraction-based bonding alignment methods and associated marker structures.

[0065] Figure 5 is a flowchart that illustrates an example of the first four of these concepts in a single process. However, it should be understood that all five of these concepts can be implemented individually, and / or the methods disclosed herein can include any two or more in any combination. Now each concept will be described individually. Figure 5 The flowchart of is based on Figure 4 The flowchart of, and the same elements have the same reference numerals and thus will not have to be described additionally. As Figure 5 represented in, the bonding device 440 can have an associated bonding metrology tool 450 and a bonding software application 460. As before, the bonding metrology tool 450 can be separate from other metrology tools in the figure, or the same metrology tool can be represented by any two or all three of the metrology tools 450, 410a, 410b. Similarly, the software application 460 can be the same as one or both of the software applications 420a, 420b (or run on the same device), and can run on any of the devices represented in the figure and / or one or more separate processing devices (not shown). It should also be noted that the following description describes the bonding process as bonding two wafers. However, these concepts equally apply to bonding more than two wafers, and thus any reference to terms such as "wafer pair" can be understood to cover a set of more than 2 wafers (which are bonded together).

[0066] Similar to Figure 4 the lithography unit LC1 and the lithography unit LC2 can be the same lithography unit, can be different lithography units but include one or more common tools and elements, or can have a completely different set of devices and tools, even completely different lithography units located at different sites or fabs.

[0067] Overlap feedforward correction of bonding fingerprints caused by the wafer bonding process

[0068] In this embodiment, it is proposed to measure the cross-wafer parameter (e.g., overlap) fingerprint after bonding and use this fingerprint as an input to determine corrections or optimizations to the bonding process for use in bonding subsequent wafers. For example, after bonding the first wafer W1 and the second wafer W2, the fingerprint can be measured by a metrology tool 450 and corrections or bonding optimizations can be determined by a software application 460 to bond the third wafer W3 and the fourth wafer W4. The corrections can also be determined based on the individual fingerprints of each wafer (e.g., as measured by fingerprints 410a, 410b), such that the software application infers the bonding tool fingerprint contribution from the final bonded fingerprint and the two pre-bond wafer fingerprints. Then, the software application 460 can actively actuate the bonding tool 440 (e.g., by corrections and / or optimizations) to optimize the overlap for bonding the next wafer pair. Thus, this concept can be represented as a loop of elements 440, 450, 460 and data feedforward from metrology devices 410a, 410b to the software application 460. Figure 5 In an embodiment, the method can be implemented within and by an APC control loop (e.g.,

[0069] the loop LP2). In an embodiment, by considering a larger set of historical overlap data (pre-bond and post-bond fingerprints), the feedforward can be more comprehensive (e.g., by an APC controller or otherwise), for example, to prevent unstable control (e.g., where the fingerprint data of the immediately previous wafer pair does not typically represent the process). Figure 3

[0070] Co-optimization of the calibration capabilities of scanner and wafer bonder control capabilities

[0071] Based on knowledge of the combined tool fingerprints (e.g., using the method described in the previous embodiment), a co-optimized correction for one or both of the scanner fingerprints and the combined tool fingerprint can be determined. Thus, the co-optimization can determine one or two exposure processes for each wafer pair to be bonded, as well as a co-optimized correction for the bonding process, which together minimize the overlap of the wafers ultimately being bonded. The co-optimization can also include corrections for other tools (such as etch tools) which also contribute their own fingerprint. It can be understood that, for example, such a co-optimization method may actually worsen the overlap of one or both of the unbonded wafers (or even, die-in-spec), but in a sense minimize the overlap across the bonded wafers and / or maximize the die-in-spec of the bonded wafers. Any co-optimization strategy can be used, including die-in-spec co-optimization, max-abs optimization, least squares co-optimization, or any other suitable optimization. The co-optimization concept is described, for example, in US2018 / 0252998 and WO2019 / 110261 (both incorporated herein by reference). Any co-optimization concept described herein, but extended to the bonding process, is contemplated in this embodiment.

[0072] For example, the co-optimization can include controlling the bonding tool and one or two scanner fingerprints such that the scanner correction pre-corrects for the bonding tool contribution to the overall overlap fingerprint of the bonded wafers. For example, such an optimization can include finding scanner and / or bonding tool (and / or etch tool or other tool) corrections that minimize the difference between the sum of the first wafer (before bonding) fingerprint and the bonding tool fingerprint and the second wafer (before bonding) fingerprint (for the wafer pair to be bonded for the first and second wafers). The co-optimization can also include co-optimizing the patterning device or mask pattern used to pattern the first and / or second wafers (e.g., via a mask pattern forming device).

[0073] Such co-optimization can be based on the correction capabilities of the relevant tools (e.g., scanners, bonding tools, and / or etching tools) to distribute the correction over these tools to achieve the minimum non-correctable error (NCE) of the parameter of interest (e.g., overlay); for example, using a pattern fidelity control (PEF)-type method. This distribution between the scanner and the bonding (and possibly other tools) correction capabilities can be based not only on the type of correction capabilities (e.g., per spatial frequency, order, field), but also on the range of such correction capabilities. By way of specific example, by adding an offset to the scanner actuation, the resulting fingerprint can be made closer to the center of the correction range of the bonding tool (and vice versa). Such a concept is described, for example, in the aforementioned US2018 / 0252998.

[0074] In such an embodiment, the co-optimization can include: determining (e.g., using one or more mathematical models) the errors that can be corrected by one or more devices of the lithography processing systems 400a, 400b and / or the bonding tool 440; and adding an offset (e.g., an intentional error) to a process performed by one of these devices (or to the reticle pattern itself). For example, the offset may cause an error that cannot be corrected by the devices of the lithography processing systems 400a, 400b or the bonding tool 440 to be transformed into an error that can be corrected by one or more other devices of the lithography processing systems 400a, 400b, the bonding tool 440, and / or the reticle pattern. As an example of such a transformation, an error with an uncorrectable spatial resolution for a particular device and / or the bonding tool 440 of one or both of the lithography processing systems 400a, 400b can be corrected by adding an additional error such that the total error has a spatial resolution that can be corrected by the devices of one or both of the lithography processing systems 400a, 400b and / or the bonding tool 440. In an embodiment, the added error can be distributed (e.g., by a reticle modification tool) among the multiple relevant devices and / or the reticle pattern.

[0075] The co-optimization can further include: determining a control selection scheme for one or both of the first lithography processing system 400a and the lithography processing system 400b from a first control grid associated with the first lithography processing system 400a (e.g., a first control grid measured using a scatterometer and / or an alignment sensor) and a second control grid associated with the second lithography processing system 400b (e.g., a second control grid measured using a scatterometer and / or an alignment sensor) to optimize the matching of the first control grid and the second control grid.

[0076] Reference scanner monitoring wafer for grid matching of wafers to be bonded

[0077] In the foregoing in connection withFigure 3 (Loop LP1) depicts the concept of using a monitoring wafer for scanner stability monitoring. A similar method is proposed for matching the control grids of each wafer in a wafer pair (or a larger set of wafers). As previously described, the first wafer and the second wafer can be from different scanners 400a, 400b. These different scanners can be located in different fabs and can include completely different systems or platforms (e.g., one can be an EUV scanner and the other can be a DUV scanner). Thus, the scanners can include completely different control and alignment strategies and can therefore have different, incompatible control grid definitions. Although such scanner grid differences can be budgeted in the overall overlay budget for wafer bonding, their impact can be reduced or minimized by using a common grid definition.

[0078] In a first implementation, this can be achieved by using matching or replicated monitoring wafers (such as those already described). A suitable processing module (e.g., a module such as stability module 300, which can be represented by software application 460 in Figure 5 can calculate the difference (as a difference set or correction set) between the golden reference wafer exposed on each scanner and the standard monitoring wafer. The individual monitoring wafers plus the difference set will be matched to define a common grid, which can be used as the control grid for the bonding process by bonding tool 440.

[0079] Figure 6 illustrates a flow of a post-bond lithography correction for determining the grid delta (δ) (grid difference) between the grids of bonded wafers using the grid delta (δ) (grid difference) of the monitoring wafer grid. After bonding and grinding / thinning the top silicon substrate, the post-bond lithography layer can be the target for overlay improvement. Such a method controls the delta (δ) / drift of the wafers in the wafer stack relative to the monitoring wafer grid by controlling the grids in the wafer stack. The method assumes that there is a single set of matched monitoring wafers for each fab or scanner involved in manufacturing the wafers for the wafer stack and for post-bond lithography. Alternatively, if this is not possible or not feasible, the calculated delta (δ) grid (correction set) between the monitoring wafers can be added to the process flow (e.g., at step 620 of the illustrated flow).

[0080] Step 600a involves the first fab FAB A, which includes the first scanner TL A on which the first wafer W1 will be processed. A monitoring wafer (e.g., from a matching group) already has a monitoring wafer grid MWG exposed thereon AAfter that, the scanner TL A is used to perform a lithography step on the monitoring wafer, thereby applying its corresponding scanner grid SG on the monitoring wafer AA Then, the monitoring wafer is measured to obtain the overlap fingerprint OVL obtained from the two grids AA Based on this, the correction grid CG is determined AA (e.g., as the inverse of the scanner grid SG AA )

[0081] Step 600b relates to the second fab FAB B, which includes a second scanner TL X on which the second wafer W2 will be processed. The monitoring wafer (e.g., from the matching group) already has a monitoring wafer grid MWG exposed thereon B After that, the scanner TL X is used to perform a lithography step on the monitoring wafer, thereby applying its corresponding scanner grid SG on the monitoring wafer BX Then, the monitoring wafer is measured to obtain the overlap fingerprint OVL obtained from the two grids BX Based on this, the correction grid CG is determined BX (e.g., as the inverse of the scanner grid SG BX )

[0082] Step 610 relates to the third fab FAB C, which includes a third scanner TL Y on which a wafer stack WS including the bonded wafer pair W1, W2 will be processed in a post-bond lithography step. The monitoring wafer (e.g., from the matching group) already has a monitoring wafer grid MWG exposed thereon C After that, the scanner TL C is used to perform a lithography step on the monitoring wafer, thereby applying its corresponding scanner grid SG on the monitoring wafer CY Then, the monitoring wafer is measured to obtain the overlap fingerprint OVL obtained from the two grids CY Based on this, the correction grid CG is determined CY (e.g., as the inverse of the scanner grid SG CY )

[0083] At step 620, the combined scanner correction grid CG AA is determined from the correction grids CG BX 、CG CY determined in the previous steps Bond . For example, the combined scanner correction grid CG Bond can be determined as the correction grid CG AA 、CGBX and CG CY combination (e.g., and). Thus, the combined scanner correction grid CG Bond can be determined as the combination of the inverses of the scanner grids (e.g., and) (e.g., -SG AA , -SG BX , -SG CY combination). The combined scanner correction grid CG Bond may also include the contribution of one or more calculated delta (δ) grids from the respective correction grids in the case of monitor wafers that were not properly matched when determining the correction grid. When using scanner TL Y for post-bond lithography, the combined scanner correction grid CG Bond can be applied when processing the wafer stack at the third fab FAB C. This can be achieved by adding the combined scanner correction grid CG Bond to the stability module control loop at the third fab FAB C or by adding the combined scanner correction grid CG Bond to the stability module control loop at the third fab FAB C via an external interface (e.g., controlled by a user at the third fab).

[0084] In this way, scanner grid drift (for scanners TL A, TL X, TL Y) is accounted for by updating the combined scanner correction grid CG Bond at the same frequency as the scanner correction grids in each individual fab (e.g., every few days). It will be readily understood that the method can be extended to include post-bond lithography steps on bonded stacks of more than two wafers.

[0085] Yield-aware calibration and prediction by applying computational metrology methods

[0086] This embodiment includes performing computational metrology to increase the in-spec die of the bonded die. Such a method may include using or defining a software tool (which may be represented by software application 460 in Figure 5 ).

[0087] The "in-spec die" optimization aims to maximize the number of dies within the specification, rather than the overall or average residual across the substrate. Thus, the "in-spec die" optimization uses prior knowledge of the product (die layout) when optimizing process parameters. Least squares optimization typically treats each site equally, regardless of die layout. Thus, least squares optimization may prefer a correction that "only" results in four sites out of specification but each site is in a different die, rather than having seven sites out of specification but only affecting two dies (e.g., four defects in one die and three defects in another die). However, since only a single defect will cause the chip to be defective, maximizing the number of defect-free dies (i.e., in-spec chips) is ultimately more important than only minimizing the number of defects per substrate or the average residual.

[0088] One type of in-spec die optimization can include per-die maximum absolute value (max abs) optimization. Such max abs optimization can minimize the maximum deviation of the performance parameter from the control target. This will produce a solution but does not prevent dies from going out of specification (only tries to minimize the number of in-spec dies). Another in-spec die strategy can include a constraint-limiting strategy, where the objective (goal) is formulated to include adding constraints to the optimization problem, e.g., such that one or more parameters or metrics are constrained within a range so that they are not allowed to go out of specification. Of course, there are other constraints, such as object constraints of the system, such as field size and constraints that can vary per field, slit width and constraints that can vary per slit, actuation constraints on how the stage can physically move, etc.

[0089] In an embodiment, in-spec die optimization can be further improved by using a "failed die" database. Such a database is dynamically maintained and records all instances where a die is considered to have or is estimated to have at least one defect (e.g., using prior yield data, data from other lithography processes, and / or defocus estimation maps) such that it is considered invalid (defective). Then, such invalid dies can be further sacrificed in the optimization. In a bonding tool, this can include minimizing the number of good dies bonded to invalid dies (which effectively wastes the unbonded good dies), and / or maximizing the number of invalid dies (and / or edge dies) bonded together. In cases where such optimization includes scanner co-optimization, invalid die sacrifice can also be achieved by attributing a very large or infinite process window (beyond its actual working limit) to the invalid die, in order to provide greater flexibility for the optimization or control of other dies before bonding (e.g., during patterning and / or etching processes). Thus, this can reduce the likelihood of defects in another die during the optimization of the same layer or consecutive layers, thereby further maximizing the number of in-spec dies.

[0090] The method of this embodiment may include taking wafer characteristics (grids / shape / inactive dies (e.g., from leveling and / or alignment data)) as input and calculating the combination (e.g., wafer pairs) that provides the overall highest yield. This is a specific example of using yield prediction techniques (yield-aware correction). Additionally, correction capabilities and individual bonding tool fingerprints can be considered to provide an optimal routing: e.g., which wafers should be sent to which bonding tool and / or which control options should be used for the bonding process.

[0091] The process flow can be optimized to identify the specific threads (combinations of tools for manufacturing a particular die) associated with higher yield solutions, as predicted by the wafer pair selection method / software described above. Such yield predictions can be further extended to identify hot spot locations (locations of critical features with narrow process windows, which often limit the process window of the process). This can provide data for guiding inspections (e.g., electrical testing) and / or yield predictions and / or inactive die identification.

[0092] Diffraction-based bonding alignment method and associated marker structures

[0093] Current image-based markers (e.g., box-in-box) used to align wafers for bonding do not allow measurement of overlap with the desired accuracy. Thus, compound diffraction markers are proposed for wafer alignment during the bonding process. Associated methods may include providing a first component or element of the compound marker on a first wafer in a wafer pair and providing a second component or element of the compound marker on a second wafer in the pair. Then, a scatterometer-based metrology tool, such as any current metrology tool for measuring overlap (e.g., a tool that measures structural asymmetry by measuring intensity asymmetry in complementary higher orders (e.g., +1, -1) of diffraction), can be used to read / measure the combined compound marker.

[0094] As an example, WO2015185166A1 describes how to use diffraction-based markers on wafers to measure and control lithography overlap performance. Here, the metrology does not involve the relative displacement of a first structure or grating in a resist and a second structure or grating in a base layer to determine overlap performance in lithography, but rather involves the measurement of the relative displacement between structures or gratings defined by two entities on a single wafer (e.g., after etching) to control bonding overlap performance.

[0095] Figure 7The figure shows a composite diffraction marker or target for bonding metrology. The composite diffraction marker or target includes a first structure or grating G1 on a first wafer W1 of a bonded pair and a second grating G2 on a second wafer W2 of the bonded pair. It should be noted that the first wafer W1 is inverted with respect to the second wafer W2; thus, these gratings are mirror images such that their interference can be used to determine bonding alignment or bonding overlap. After bonding, the two layers including these gratings (or the layers on these gratings) are in contact, and the marker can be measured by measuring the relative displacement X of these gratings. Note that the marker design can include many layers, and all layers can be referenced.

[0096] The relative positions of gratings G1 and G2 can be such that an intentional bias is defined or limited to help distinguish intensity asymmetries due to misalignments (as known in the overlap scenario) from other asymmetry contributions (e.g., processing asymmetries in one or both gratings).

[0097] The wavelength of the radiation of the metrology tool for measurement should be such that the wafer is sufficiently transparent to the radiation (e.g., one or more wavelengths in the infrared region can be used). Using such a wavelength that is transparent to the substrate, metrology can be performed immediately after the wafers have been contacted, thus allowing for quick rework in case of insufficient performance.

[0098] On a suitable metrology platform (e.g., as Figure 2 illustrated), these markers can be used to measure high-density overlap fingerprints because these small markers can be distributed on the wafer at any density. These markers can be oriented to measure overlap in both X and Y (in the substrate plane).

[0099] In some cases, measurements (e.g., unidirectional) can be performed on metal lines as long as these metal lines have the same pitch and are located at the same positions on both wafers. Thus, for this case, no additional metrology space is required.

[0100] Optionally, the cover film can be adjusted to obtain optimal contrast accuracy.

[0101] It can be seen that the diffraction-based metrology method described here will achieve better (by several orders of magnitude) overlap control in overlap metrology performance compared to the current standard image-based method.

[0102] Additionally, such markers can be used to measure the local distance in the Z - direction between marker components based on additional diffraction characteristics (to verify successful bonding). This can include inferring this local distance in the Z - direction between these marker components based on a (multicolor) diffraction spectrum or other measurement signals. This involves the fact that, using diffraction - based measurement, the distance between two gratings has a significant impact on the echo signal. The expected signal is known (or can be inferred) from the film thickness measurement before bonding and CMP control. Any deviation from this expected signal can be used to determine the actual film thickness between these markers. This method can be used to determine the entire interface. In a more extreme case where the bonding fails at the marker site, due to air bubbles that would be trapped between the layers, the signal will be very different from the expected signal. This can be used to indicate the presence of voids during the bonding process.

[0103] Additional embodiments are disclosed by the aspects numbered below:

[0104] 1. A method for controlling a process of manufacturing a semiconductor device, the method comprising:

[0105] obtaining bonded - substrate measurement data, the bonded - substrate measurement data including data related to measurements performed on a bonded substrate, the bonded substrate including two or more patterned substrates bonded together; and

[0106] determining a correction to a bonding step based on the bonded - substrate measurement data, the bonding step being performed to bond two or more subsequent substrates.

[0107] 2. The method according to aspect 1, wherein the bonded - substrate measurement data includes overlap data, and the correction is for maximizing the overlap of the bonded substrate and / or die within specification.

[0108] 3. The method according to aspect 1 or 2, wherein the step of determining the correction includes:

[0109] obtaining first measurement data related to a first substrate before bonding;

[0110] obtaining second measurement data related to a second substrate before bonding; and

[0111] determining bonding - process contribution data based on the bonded - substrate measurement data, the first measurement data, and the second measurement data, the bonding - process contribution data describing the contribution to measurement data resulting from the bonding process and / or the bonding equipment used for the bonding process.

[0112] 4. The method according to aspect 1, 2, or 3, wherein the step of determining the correction includes: determining the correction based on the combined substrate measurement data and historical combined substrate measurement data obtained from additional previously measured combined substrates.

[0113] 5. The method according to any one of aspects 1 to 4, wherein the step of determining the correction includes: determining a common optimization correction for the bonding step and for any one of the patterning processes in the patterning process for manufacturing the two or more patterned substrates before the bonding step.

[0114] 6. The method according to aspect 5, wherein the common optimization correction for any one of the patterning processes in the patterning process includes a common optimization correction for one or more of the following:

[0115] The lithographic exposure process of any one of the patterning processes in the patterning process;

[0116] The patterning device patterning process for defining the pattern on the patterning device used in any one of the patterning processes in the patterning process; or

[0117] The etching process of any one of the patterning processes in the patterning process.

[0118] 7. The method according to aspect 6, wherein the common optimization correction is determined based on the correction capabilities of one or more relevant tools used in the process.

[0119] 8. The method according to aspect 7, wherein the common optimization correction is determined based on the available range of the correction capabilities.

[0120] 9. The method according to aspect 7 or 8, wherein the optimized correction allocates the correction on these tools to achieve the minimum uncorrectable error of the parameter of interest, such as overlay.

[0121] 10. The method according to any one of aspects 5 to 9, wherein the co - optimization includes: determining control actions and / or settings for any one of the patterning processes according to the measurement data related to each of the two or more patterned substrates to optimize the matching of the control grids associated with the two or more patterned substrates.

[0122] 11. The method according to any of the preceding aspects, including:

[0123] Determining an optimal pairing or grouping of the substrates for the bonding step based on substrate characteristics, the substrate characteristics including one or more of the following:

[0124] The location of defective die on each substrate,

[0125] Control grid,

[0126] Substrate shape.

[0127] 12. The method according to aspect 11, wherein said determining the optimal pairing or grouping comprises: predicting the yield of the paired or grouped substrates; and selecting the optimal pairing that maximizes the yield.

[0128] 13. The method according to aspect 12, wherein the result of the predicted yield is used to identify critical sites with more stringent process control limits.

[0129] 14. The method according to aspect 11, 12 or 13, further comprising: considering the characteristics of each bonding tool that can be used in the bonding step; and determining and allocating a bonding tool and / or a control configuration for the bonding tool for each substrate pair or substrate group based on one or both of the characteristics of the substrates or the processing history of each substrate.

[0130] 15. The method according to aspect 14, wherein the method further determines a preferred routing for each substrate by available equipment for some or all of the processing steps in the corresponding patterning process to be used on each substrate.

[0131] Additional embodiments are disclosed by the aspects numbered below:

[0132] 1. A method for controlling a process of manufacturing semiconductor devices, the method comprising:

[0133] Determining a common optimization correction for a bonding step performed to bond two or more substrates and any one of the patterning processes used to fabricate two or more patterned substrates prior to the bonding step.

[0134] 2. The method according to aspect 1, wherein the common optimization correction for any one of the patterning processes comprises a common optimization correction for one or more of the following:

[0135] The lithographic exposure process of any one of the patterning processes;

[0136] The patterning device patterning process for defining a pattern on a patterning device used in any one of the patterning processes; or

[0137] The etching process of any one of the patterning processes.

[0138] 3. The method according to aspect 2, wherein the co-optimized correction is determined based on the calibration capabilities of one or more relevant tools used in the process.

[0139] 4. The method according to aspect 3, wherein the co-optimized correction is determined based on the available range of the calibration capabilities.

[0140] 5. The method according to aspect 3 or 4, wherein the optimized correction allocates the correction on these tools to achieve the minimum uncorrectable error of the parameter of interest, such as overlap.

[0141] 6. The method according to any one of aspects 1 to 5, wherein the co-optimization includes: determining control actions and / or settings for any of the patterning processes in the patterning process according to metrology data related to each of the two or more patterned substrates to optimize the matching of the control grids associated with the two or more patterned substrates.

[0142] 7. The method according to any of the foregoing aspects, including:

[0143] Determining an optimal pairing or grouping of substrates for the bonding step based on substrate characteristics, the substrate characteristics including one or more of the following:

[0144] The location of defective die on each substrate,

[0145] Control grid,

[0146] Substrate shape.

[0147] 8. The method according to aspect 7, wherein the determining the optimal pairing or grouping includes: predicting the yield of the paired or grouped substrates; and selecting the optimal pairing that maximizes the yield.

[0148] 9. The method according to aspect 8, wherein the result of the predicted yield is used to identify critical sites with more stringent process control limits.

[0149] 10. The method according to aspect 7, 8 or 9, further including: considering the characteristics of each bonding tool that can be used for the bonding step; and determining and allocating a bonding tool and / or a control selection scheme for the bonding tool for each substrate pair or substrate group based on one or both of the substrate characteristics or the processing history of each substrate.

[0150] 11. The method according to aspect 10, wherein the method further determines a preferred routing for each substrate by the available equipment in some or all of the processing steps of the corresponding patterning process used on each substrate.

[0151] Additional embodiments are disclosed by the numbered aspects below:

[0152] 1. A method for controlling a process of manufacturing a semiconductor device, the method comprising:

[0153] Determining an optimal pairing or grouping of substrates for a bonding step based on substrate characteristics, the bonding step being performed to bond two or more substrates, the substrate characteristics including two or more of the following:

[0154] The location of defective die on each substrate,

[0155] Control grid,

[0156] Substrate shape.

[0157] 2. The method according to aspect 1, wherein the determining the optimal pairing or grouping includes: predicting the yield of the paired or grouped substrates; and selecting the optimal pairing that maximizes the yield.

[0158] 3. The method according to aspect 2, wherein the result of the predicted yield is used to identify critical areas where process control is more stringent.

[0159] 4. The method according to aspect 1, 2 or 3, further comprising: considering the characteristics of each bonding tool that can be used for the bonding step; and determining and allocating a bonding tool and / or a control option for the bonding tool for each substrate pair or substrate group based on one or both of the substrate characteristics or the processing history of each substrate.

[0160] 5. The method according to aspect 4, wherein the method further determines a preferred routing for each substrate by available equipment in some or all of the processing steps of the corresponding patterning process used on each substrate.

[0161] Additional embodiments are disclosed by the numbered aspects below:

[0162] 1. A method for determining the alignment of a bonded substrate stack, the bonded substrate stack including at least a first substrate and a second substrate, the method comprising:

[0163] Irradiating a composite alignment structure, the composite alignment structure including a first diffraction structure on the first substrate and a second diffraction structure on the second substrate;

[0164] Determining the relative alignment of the first substrate and the second substrate based on the diffraction orders obtained from the irradiation of the composite structure.

[0165] 2. The method according to aspect 1, wherein the determining step comprises: determining the alignment based on an intensity difference between complementary higher diffraction orders obtained from the irradiation of the composite structure.

[0166] 3. The method according to aspect 1 or 2, wherein the first diffraction structure comprises a first etched periodic structure and the second diffraction structure comprises a second etched periodic structure.

[0167] 4. The method according to aspect 1 or 2, wherein each of the first diffraction structure and the second diffraction structure comprises a plurality of metal lines.

[0168] 5. The method according to any of the preceding aspects, wherein the first substrate and the second substrate are bonded together, wherein one of the substrates is inverted with respect to the other substrate and the corresponding diffraction structure of the one substrate is inverted with respect to the other substrate.

[0169] 6. The method according to any of the preceding aspects, wherein the first substrate and the second substrate are substantially transparent to the irradiation used in the irradiation step.

[0170] 7. The method according to any of the preceding aspects, comprising: determining a description of a relative alignment as a function of a position on the bonded substrate stack based on a plurality of the composite alignment structures.

[0171] 8. The method according to any of the preceding aspects, comprising: measuring a local distance in a direction perpendicular to the substrate plane between the first diffraction structure and the second diffraction structure based on diffraction characteristics from the composite alignment structure relative to desired diffraction characteristics to quantify a bonding quality.

[0172] Additional embodiments are disclosed by the aspects numbered below:

[0173] 1. A bonded substrate stack, the bonded substrate stack comprising at least a first substrate and a second substrate, wherein

[0174] the first substrate comprises a first diffraction structure and the second substrate comprises a second diffraction structure, the first diffraction structure and the diffraction structure being positioned to form a composite alignment structure on the first substrate and the second substrate, from which the relative alignment of the first substrate and the second substrate can be measured.

[0175] 2. The bonded substrate stack according to aspect 1, wherein the first diffraction structure comprises a first etched periodic structure and the second diffraction structure comprises a second etched periodic structure.

[0176] 3. The bonded substrate stack according to aspect 1, wherein each of the first diffraction structure and the second diffraction structure includes a plurality of metal lines.

[0177] 4. The bonded substrate stack according to any one of the preceding aspects, wherein the first substrate and the second substrate are bonded together, and one of the substrates is inverted relative to the other substrate and the corresponding diffraction structure of the one substrate is inverted relative to the other substrate.

[0178] 5. The bonded substrate stack according to any one of the preceding aspects, including a plurality of the composite alignment structures, the composite alignment structures being formed by a plurality of first diffraction structures and second diffraction structures within the scope of the corresponding substrate surface.

[0179] Additional embodiments are disclosed by the list of aspects numbered below:

[0180] 1. A method for controlling a process of manufacturing a semiconductor device, the method comprising:

[0181] Obtaining first monitoring data from cyclic monitoring of the stability control of a first lithography apparatus for a first patterning process of patterning a first substrate, the first monitoring data defining a first control grid;

[0182] Obtaining second monitoring data from cyclic monitoring of the stability control of a second lithography apparatus for a second patterning process of patterning a second substrate, the second monitoring data defining a second control grid; and

[0183] Based on the first monitoring data and the second monitoring data, determining a common control grid definition for a bonding step for bonding the first substrate and the second substrate to obtain a bonded substrate.

[0184] 2. The method according to aspect 1, wherein the first monitoring data includes an associated first difference data set that customizes the first monitoring data for the first lithography apparatus relative to a common reference monitoring data set, and the second monitoring data includes an associated second difference data set that customizes the second monitoring data for the second lithography apparatus relative to the common reference monitoring data set.

[0185] 3. The method according to aspect 1 or 2, wherein the step of determining a common control grid definition includes: determining a common control grid definition that optimizes the parameters of interest of the bonded substrate and / or the die within the specifications.

[0186] 4. The method according to any one of the preceding aspects, including:

[0187] Third monitoring data is obtained based on cyclic monitoring for stability control of a third lithography apparatus for a third patterning process for patterning a bonded first and second substrate in a post-lithography step, the third monitoring data defining a third control grid;

[0188] A first correction grid is determined based on the first monitoring data, a second correction grid is determined based on the second monitoring data, and a third correction grid is determined based on the third monitoring data; and

[0189] Using the third lithography apparatus to determine a post-bond correction for a subsequent post-bond metrology of a stack including a first substrate processed on the first lithography apparatus and a second substrate processed on the second apparatus.

[0190] 5. The method according to aspect 4, wherein:

[0191] The first monitoring data, the second monitoring data, and the third monitoring data are each obtained using a respective monitoring substrate, each of these monitoring substrates having been matched such that the first control grid, the second control grid, and the third control grid are all matched; or

[0192] The determining of the post-bond correction further includes: using an additional correction set to match the first control grid, the second control grid, and the third control grid.

[0193] 6. The method according to aspect 4 or 5, wherein the first correction grid, the second correction grid, and the third correction grid include inverse grids of a first lithography apparatus grid applied by the first lithography apparatus, a second lithography apparatus grid applied by the second lithography apparatus, and a third lithography apparatus grid applied by the third lithography apparatus, respectively.

[0194] 7. The method according to any one of the preceding aspects, wherein the bonding step includes bonding more than two substrates together, each of the additional substrates including associated monitoring data defining a control grid, and the step of determining a common control grid definition includes determining a common control grid definition for all the substrates based on all the associated monitoring data.

[0195] 8. The method according to any one of the preceding aspects, further comprising:

[0196] Obtaining bonded substrate metrology data including data related to metrology performed on the bonded substrate; and

[0197] Determining a correction for the performance of the bonding step on subsequent substrates based on the bonded substrate metrology data.

[0198] 9. The method according to aspect 8, wherein the combined substrate measurement data includes overlay data, and the correction is for maximizing the overlay of the combined substrate and / or the in-specification die.

[0199] 10. The method according to aspect 8 or 9, wherein the step of determining the correction includes:

[0200] obtaining first measurement data related to the first substrate before bonding;

[0201] obtaining second measurement data related to the second substrate before bonding; and

[0202] determining bonding process contribution data according to the combined substrate measurement data, the first measurement data, and the second measurement data, the bonding process contribution data describing the contribution to the measurement data obtained from the bonding process and / or the bonding equipment used for the bonding process.

[0203] 11. The method according to aspect 10, wherein the step of determining the correction includes: determining the correction based on the combined substrate measurement data and historical combined substrate measurement data obtained from additional earlier measured combined substrates.

[0204] 12. The method according to any one of aspects 8 to 11, wherein the step of determining the correction includes: determining a common optimization correction for the bonding step and for one or both of the first patterning process and the second patterning process.

[0205] 13. The method according to aspect 12, wherein the common optimization correction for the first patterning process and / or the second patterning process includes a common optimization correction for one or more of the following:

[0206] the lithographic exposure process of the first patterning process and / or the second patterning process;

[0207] the patterning device patterning process for defining the pattern on the patterning device used in the first patterning process and / or the second patterning process; or

[0208] the etching process of the first patterning process and / or the second patterning process.

[0209] 14. The method according to aspect 12 or 13, wherein the common optimization correction is determined based on the correction capabilities of one or more relevant tools or equipment used in the process.

[0210] 15. The method according to aspect 14, wherein the co-optimized correction is determined based on the available range of the correction ability.

[0211] 16. The method according to aspect 14 or 15, wherein the optimized correction allocates the correction on these tools or devices to achieve the minimum uncorrectable error of the parameter of interest.

[0212] 17. The method according to aspect 16, wherein the parameter of interest is overlap.

[0213] 18. The method according to any one of aspects 9 to 17, wherein the co-optimization includes: determining control actions and / or settings for one or both of the first patterning process and the second patterning process based on the first measurement data and the second measurement data to optimize the matching of the first control grid and the second control grid.

[0214] 19. The method according to any one of the foregoing aspects, comprising:

[0215] determining an optimal pairing or grouping of substrates for the bonding step based on substrate characteristics, the substrate characteristics including one or more of the following:

[0216] the location of defective die on each substrate,

[0217] control grid,

[0218] substrate shape.

[0219] 20. The method according to aspect 19, wherein the determining the optimal pairing or grouping includes: predicting the yield of the paired or grouped substrates; and selecting the optimal pairing that maximizes the yield.

[0220] 21. The method according to aspect 20, wherein the result of the predicted yield is used to identify critical sites where process control limitations are more stringent.

[0221] 22. The method according to aspect 19, 20 or 21, further comprising: considering the characteristics of each bonding tool that can be used for the bonding step; and allocating a bonding tool and / or a control selection scheme for the bonding tool to each substrate pair or substrate group based on one or both of the substrate characteristics or the processing history of each substrate.

[0222] 23. The method according to aspect 22, wherein the method further determines a preferred routing for each substrate through the available equipment in some or all of the processing steps of the corresponding patterning process used on each substrate.

[0223] 24. The method according to any one of the foregoing aspects, comprising: performing the bonding step based on the common grid definition.

[0224] 25. The method according to aspect 24, comprising:

[0225] determining the alignment of a subsequent bonded substrate stack by:

[0226] irradiating a composite alignment structure comprising a first diffraction structure on a first substrate and a second diffraction structure on a second substrate; and

[0227] determining the relative alignment of the first substrate and the second substrate based on the diffraction orders obtained from the irradiation of the composite structure.

[0228] 26. The method according to aspect 25, wherein the determining step comprises: determining the alignment based on the intensity difference between complementary higher diffraction orders obtained from the irradiation of the composite structure.

[0229] 27. The method according to aspect 25 or 26, wherein the first diffraction structure comprises a first etched periodic structure and the second diffraction structure comprises a second etched periodic structure.

[0230] 28. The method according to aspect 25 or 26, wherein each of the first diffraction structure and the second diffraction structure comprises a plurality of metal lines.

[0231] 29. The method according to any one of aspects 22 to 28, wherein the first substrate and the second substrate are bonded together, wherein one of the substrates is inverted relative to the other substrate and the corresponding diffraction structure of the one substrate is inverted relative to the other substrate.

[0232] 30. The method according to any one of aspects 22 to 29, wherein the first substrate and the second substrate are substantially transparent to the irradiation used in the irradiation step.

[0233] 31. The method according to any one of aspects 22 to 30, comprising: determining a description of the relative alignment as a function of position on the bonded substrate stack based on a plurality of the composite alignment structures.

[0234] 32. The method according to any one of aspects 22 to 31, comprising: measuring a local distance in a direction perpendicular to the substrate plane between the first diffraction structure and the second diffraction structure based on the diffraction characteristics from the composite alignment structure relative to desired diffraction characteristics to quantify the bonding quality.

[0235] 33. A lithographic apparatus configured to provide a product structure to a substrate in a lithographic process and a bonding apparatus configured to bond the processed substrate, the lithographic apparatus further comprising a processor operable to optimize control of the lithographic apparatus and / or the bonding apparatus during a manufacturing process by performing the method according to any of the preceding aspects.

[0236] 34. A computer program comprising program instructions operable to perform the method according to any one of aspects 1 to 32 when run on a suitable device.

[0237] 35. A non-transitory computer program carrier comprising the computer program according to aspect 34.

[0238] Further embodiments are disclosed by the list of aspects numbered below:

[0239] 1. A method for controlling a process of manufacturing a semiconductor device, the method comprising:

[0240] obtaining a first control grid associated with a first lithographic apparatus for a first patterning process for patterning a first substrate;

[0241] obtaining a second control grid associated with a second lithographic apparatus for a second patterning process for patterning a second substrate; and

[0242] determining, based on the first control grid and the second control grid, a common control grid definition for a bonding step for bonding the first substrate and the second substrate to obtain a bonded substrate.

[0243] 2. The method according to aspect 1, wherein the first control grid is defined based on first monitoring data from cyclic monitoring of stability control of the first lithographic apparatus, and the second control grid is defined based on second monitoring data from cyclic monitoring of stability control of the second lithographic apparatus.

[0244] 3. The method according to aspect 2, wherein the first monitoring data comprises an associated first difference data set customizing the first monitoring data for the first lithographic apparatus relative to a common reference monitoring data set, and the second monitoring data comprises an associated second difference data set customizing the second monitoring data for the second lithographic apparatus relative to the common reference monitoring data set.

[0245] 4. The method according to aspect 1, 2 or 3, wherein the step of determining the common control grid definition includes: determining a common control grid definition that optimizes the parameters and / or specifications of interest of the bonded substrate for the die within.

[0246] 5. The method according to any one of aspects 1 to 4, including:

[0247] Obtaining a third control grid of a third lithography apparatus for a third patterning process for patterning the bonded substrate in a post-bond lithography step;

[0248] Determining a first correction grid based on the first control grid, a second correction grid based on the second control grid, and a third correction grid based on the third control grid; and

[0249] Using the third lithography apparatus to determine a post-bond correction for a subsequent post-bond measurement on a stack including a first substrate processed on the first lithography apparatus and a second substrate processed on the second apparatus.

[0250] 6. The method according to aspect 2, including:

[0251] Obtaining third monitoring data based on cyclic monitoring of the stability control of a third lithography apparatus for a third patterning process for patterning the bonded first and second substrates in a post-bond lithography step, the third monitoring data defining a third control grid;

[0252] Determining a first correction grid based on the first monitoring data, a second correction grid based on the second monitoring data, and a third correction grid based on the third monitoring data; and

[0253] Using the third lithography apparatus to determine a post-bond correction for a subsequent post-bond measurement on a stack including a first substrate processed on the first lithography apparatus and a second substrate processed on the second apparatus.

[0254] 7. The method according to aspect 6, wherein:

[0255] The first monitoring data, the second monitoring data, and the third monitoring data are each obtained using a respective monitoring substrate, each of these monitoring substrates having been matched such that the first control grid, the second control grid, and the third control grid are all matched; or

[0256] The determining of the post-bond correction further includes: using an additional correction set to match the first control grid, the second control grid, and the third control grid.

[0257] 8. The method according to aspect 6 or 7, wherein the first correction grid, the second correction grid, and the third correction grid comprise inverse grids of a first lithography apparatus grid applied by the first lithography apparatus, a second lithography apparatus grid applied by the second lithography apparatus, and a third lithography apparatus grid applied by the third lithography apparatus, respectively.

[0258] 9. The method according to any one of aspects 2 to 8, wherein the bonding step comprises bonding together more than two substrates, each of the additional substrates comprising associated monitoring data defining a control grid, and the step of determining a common control grid definition comprises determining a common control grid definition for all of the substrates based on all of the associated monitoring data.

[0259] 10. The method according to any one of the preceding aspects, further comprising:

[0260] obtaining bonded substrate metrology data, the bonded substrate metrology data comprising data related to metrology performed on the bonded substrate; and

[0261] determining a correction to the performance of the bonding step on subsequent substrates based on the bonded substrate metrology data.

[0262] 11. The method according to aspect 10, wherein the bonded substrate metrology data comprises overlay data, and the correction is for maximizing the overlay of the bonded substrate and / or the in-specification die.

[0263] 12. The method according to aspect 10 or 11, wherein the step of determining the correction comprises:

[0264] obtaining first metrology data related to the first substrate prior to bonding;

[0265] obtaining second metrology data related to the second substrate prior to bonding; and

[0266] determining bonding process contribution data based on the bonded substrate metrology data, the first metrology data, and the second metrology data, the bonding process contribution data describing the contribution to the metrology data resulting from the bonding process and / or the bonding apparatus used for the bonding process.

[0267] 13. The method according to aspect 12, wherein the step of determining the correction comprises: determining the correction based on the bonded substrate metrology data and historical bonded substrate metrology data obtained from additional earlier measured bonded substrates.

[0268] 14. The method according to any one of aspects 10 to 13, wherein the step of determining the correction includes: determining a common optimization correction for the bonding step and for one or both of the first patterning process and the second patterning process.

[0269] 15. The method according to aspect 14, wherein the common optimization correction for the first patterning process and / or the second patterning process includes a common optimization correction for one or more of the following:

[0270] The lithographic exposure process of the first patterning process and / or the second patterning process;

[0271] The patterning device patterning process for defining the pattern on the patterning device used in the first patterning process and / or the second patterning process; or

[0272] The etching process of the first patterning process and / or the second patterning process.

[0273] 16. The method according to aspect 14 or 15, wherein the common optimization correction is determined based on the correction capabilities of one or more relevant tools or devices used in the process.

[0274] 17. The method according to aspect 16, wherein the common optimization correction is determined based on the available range of the correction capabilities.

[0275] 18. The method according to aspect 16 or 17, wherein the optimized correction distributes the correction on these tools or devices to achieve the minimum uncorrectable error of the parameter of interest.

[0276] 19. The method according to aspect 18, wherein the parameter of interest is overlay.

[0277] 20. The method according to any one of aspects 11 to 19, wherein the co-optimization includes: determining control actions and / or settings for one or both of the first patterning process and the second patterning process according to the first measurement data and the second measurement data to optimize the matching of the first control grid and the second control grid.

[0278] 21. The method according to any one of the foregoing aspects, including:

[0279] Determining an optimal pairing or grouping of the substrates for the bonding step based on substrate characteristics, the substrate characteristics including one or more of the following:

[0280] The location of defective die on each substrate,

[0281] Control grid,

[0282] Substrate shape

[0283] 22. The method according to aspect 21, wherein determining the optimal pairing or grouping includes: predicting the yield of the paired or grouped substrates; and selecting the optimal pairing that maximizes the yield.

[0284] 23. The method according to aspect 22, wherein the result of the predicted yield is used to identify critical areas with more stringent process control limitations.

[0285] 24. The method according to aspect 21, 22 or 23, further comprising: considering the characteristics of each bonding tool that can be used in the bonding step; and assigning a bonding tool and / or a control selection scheme for the bonding tool to each substrate pair or substrate group based on one or both of the substrate characteristics or the processing history of each substrate.

[0286] 25. The method according to aspect 24, wherein the method further determines a preferred routing for each substrate by available equipment in some or all of the processing steps of the corresponding patterning process to be used on each substrate.

[0287] 26. The method according to any one of the foregoing aspects, comprising: performing the bonding step based on the common grid definition.

[0288] 27. The method according to aspect 26, comprising:

[0289] determining the alignment of the subsequent bonded substrate stack by:

[0290] irradiating a composite alignment structure that includes a first diffraction structure on the first substrate and a second diffraction structure on the second substrate; and

[0291] determining the relative alignment of the first substrate and the second substrate based on the diffraction orders obtained from the irradiation of the composite structure.

[0292] 28. The method according to aspect 27, wherein the determining step includes: determining the alignment based on the intensity difference between complementary higher diffraction orders obtained from the irradiation of the composite structure.

[0293] 29. The method according to aspect 27 or 28, wherein the first diffraction structure includes an etched first periodic structure, and the second diffraction structure includes an etched second periodic structure.

[0294] 30. The method according to aspect 27 or 28, wherein each of the first diffraction structure and the second diffraction structure comprises a plurality of metal lines.

[0295] 31. The method according to any one of aspects 24 to 30, wherein the first substrate and the second substrate are bonded together, wherein one of the substrates is inverted relative to the other substrate and the corresponding diffraction structure of the one substrate is inverted relative to the other substrate.

[0296] 32. The method according to any one of aspects 24 to 31, wherein the first substrate and the second substrate are substantially transparent to the irradiation used in the irradiation step.

[0297] 33. The method according to any one of aspects 24 to 32, comprising: determining a description of relative alignment as a function of position on the bonded substrate stack based on the plurality of composite alignment structures.

[0298] 34. The method according to any one of aspects 24 to 33, comprising: measuring a local distance in a direction perpendicular to the substrate plane between the first diffraction structure and the second diffraction structure based on diffraction characteristics from the composite alignment structure relative to desired diffraction characteristics to quantify the bonding quality.

[0299] As used in relation to the lithographic apparatus, the terms “radiation” and “beam” encompass all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., having a wavelength of or about 365 nm, 355 nm, 248 nm, 193 nm, 157 nm or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 5 nm to 20 nm), as well as particle beams, such as ion beams or electron beams.

[0300] Where context allows, the term “lens” may represent any one or combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic and electrostatic optical components.

[0301] The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, without departing from the general concept of the invention and without undue experimentation, readily modify and / or adapt, for example, the various applications of these specific embodiments by applying knowledge within the scope of the art. Therefore, such adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It is to be understood that the language or terminology herein is for the purpose of description by way of example and not of limitation, and thus the terminology or language in this specification should be interpreted by those skilled in the art in light of the teachings and guidance.

[0302] The breadth and scope of the present invention should not be limited by any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for controlling a process of manufacturing a semiconductor device, the method comprising: Obtaining a first control grid associated with a first lithography apparatus, the first lithography apparatus being used in a first patterning process for patterning a first substrate; Obtaining a second control grid associated with a second lithography apparatus, the second lithography apparatus being used in a second patterning process for patterning a second substrate; Based on the first control grid and the second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and the second substrate to obtain a bonded substrate; Obtaining bonded substrate metrology data, the bonded substrate metrology data including data related to metrology performed on the bonded substrate; And Based on the bonded substrate metrology data, determining a correction for the performance of the bonding step on subsequent substrates, wherein determining the correction includes: determining a common optimization correction for the bonding step and for one or both of the first patterning process and the second patterning process.

2. The method according to claim 1, wherein The first control grid is defined based on first monitoring data from cyclic monitoring of the stability control of the first lithography apparatus, and the second control grid is defined based on second monitoring data from cyclic monitoring of the stability control of the second lithography apparatus.

3. The method according to claim 2, wherein The first monitoring data includes an associated first difference data set that customizes the first monitoring data for the first lithography apparatus relative to a common reference monitoring data set, and the second monitoring data includes an associated second difference data set that customizes the second monitoring data for the second lithography apparatus relative to the common reference monitoring data set.

4. The method according to claim 1, 2 or 3, wherein, The step of determining a common control grid definition includes: determining a common control grid definition that optimizes the parameters of interest of the bonded substrate and / or the die within the specifications.

5. The method according to claim 1, comprising: Obtaining a third control grid of a third lithography apparatus, the third lithography apparatus being used in a third patterning process for patterning the bonded substrate in a post-bond lithography step; Determining a first correction grid according to the first control grid, determining a second correction grid according to the second control grid, and determining a third correction grid according to the third control grid; and Using the third lithography apparatus to determine a post-bond correction for subsequent post-bond metrology on a stack including the first substrate processed on the first lithography apparatus and the second substrate processed on the second apparatus.

6. The method according to claim 2, comprising: Obtaining third monitoring data from cyclic monitoring of the stability control of a third lithography apparatus, the third lithography apparatus being used in a third patterning process for patterning the bonded first and second substrates in a post-bond lithography step, the third monitoring data defining a third control grid; Determine a first correction grid based on the first monitoring data, determine a second correction grid based on the second monitoring data, and determine a third correction grid based on the third monitoring data; and Use the third lithography apparatus to determine a post-bond correction for subsequent post-bond metrology on a stack, the stack including a first substrate processed on the first lithography apparatus and a second substrate processed on the second apparatus.

7. The method according to claim 6, wherein: The first monitoring data, the second monitoring data, and the third monitoring data are each obtained using a respective monitoring substrate, and each of these monitoring substrates has been matched such that the first control grid, the second control grid, and the third control grid are all matched; or Determining the post-bond correction further includes: using an additional correction set to match the first control grid, the second control grid, and the third control grid.

8. The method according to claim 1, wherein, The bonded substrate metrology data includes overlay data, and the correction is used to maximize the overlay of the bonded substrate and / or the in-specification die.

9. The method according to claim 1, wherein The step of determining the correction includes: Obtaining first metrology data related to the first substrate before bonding; Obtaining second metrology data related to the second substrate before bonding; and Determining bonded process contribution data based on the bonded substrate metrology data, the first metrology data, and the second metrology data, the bonded process contribution data describing the contribution to the metrology data obtained from the bonding process and / or the bonding apparatus used for the bonding process.

10. The method according to claim 1, including: Determining an optimal pairing or grouping of substrates for the bonding step based on substrate characteristics, the substrate characteristics including one or more of the following: The location of defective die on each substrate, The control grid, The substrate shape.

11. The method according to claim 1, including: Performing the bonding step based on the common grid definition.

12. The method according to claim 11, including: Determining the alignment of a subsequent bonded substrate stack by irradiating a composite alignment structure and determining the relative alignment of the first substrate and the second substrate based on diffraction orders obtained from the irradiation of the composite structure, the composite alignment structure including a first diffraction structure on the first substrate and a second diffraction structure on the second substrate.

13. The method according to claim 12, wherein, The first diffraction structure includes a first etched periodic structure, and the second diffraction structure includes a second etched periodic structure.

14. A computer program product including program instructions that are executable to perform the following steps: Obtaining a first control grid associated with a first lithography apparatus used for a first patterning process of patterning a first substrate; Obtaining a second control grid associated with a second lithography apparatus used for a second patterning process of patterning a second substrate; Based on the first control grid and the second control grid, determine a common control grid definition for a bonding step for bonding the first substrate and the second substrate to obtain a bonded substrate; Obtain bonded substrate measurement data, the bonded substrate measurement data including data related to measurements performed on the bonded substrate; and Based on the bonded substrate measurement data, determine a correction for the execution of the bonding step on subsequent substrates, wherein determining the correction includes: determining a common optimization correction for the bonding step and for one or both of the first patterning process and / or the second patterning process.

15. A non-transitory computer program carrier comprising the computer program product according to claim 14.

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