Display panel and display device

Abstract

A display panel and a display device. The display panel includes: a substrate (BS); a pixel unit (101) located on the substrate (BS), including a pixel circuit (10) and a light-emitting element (20), the pixel circuit (10) being configured to drive the light-emitting element (20), the pixel circuit (10) being closer to the substrate (BS) than the light-emitting element (20), the pixel circuit (10) including a driving transistor (T1); a data line (DT) configured to provide a data signal to the pixel circuit (10); a connection element (CE0), the light-emitting element (20) being connected to the pixel circuit (10) through the connection element (CE0), the connection element (CE0) including a shielding portion (CEs); and a connection line (CL) connected to the gate (T10) of the driving transistor (T1); the data line (DT) includes two adjacent data lines (DT), the shielding portion (CEs) is located between the two adjacent data lines (DT), and the orthographic projection of the connection line (CL) on the substrate (BS) at least partially overlaps the orthographic projection of the shielding portion (CEs) on the substrate (BS).

Description

[0001] Cross-reference to Related Applications

[0002] For all purposes, this patent application claims the priority of PCT Patent Application No. PCT / CN2020 / 140199 filed on December 28, 2020, and the content disclosed in the above PCT patent application is hereby incorporated by reference in its entirety as part of the embodiments of the present disclosure. Technical Field

[0003] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0004] With the continuous development of display technology, Active-Matrix Organic Light-Emitting Diode (AMOLED) display technology has been increasingly applied to display devices such as mobile phones, tablet computers, and digital cameras due to its advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, and high response speed. Summary of the Invention

[0005] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0006] On the one hand, at least one embodiment of the present disclosure provides a display panel, including: a substrate; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor and a threshold compensation transistor, a first pole of the threshold compensation transistor being connected to a second pole of the driving transistor, a second pole of the threshold compensation transistor being connected to a gate of the driving transistor; a first power supply line configured to provide a first power supply voltage to the pixel circuit; a stopper electrically connected to the first power supply line; and a first conductive structure connected to the gate of the driving transistor, wherein the threshold compensation transistor includes a first channel and a second channel, the first channel and the second channel being connected by a conductive connection portion; a positive projection of the stopper on the substrate at least partially overlaps a positive projection of the conductive connection portion on the substrate; a positive projection of the first conductive structure on the substrate at least partially overlaps a positive projection of the stopper on the substrate; and an area of a portion of the stopper overlapping the first conductive structure in a positive projection on the substrate is greater than an area of a portion of the stopper overlapping the conductive connection portion in a positive projection on the substrate.

[0007] For example, in some embodiments of the present disclosure, materials of the first conductive structure and the conductive connection portion are the same.

[0008] For example, in some embodiments of the present disclosure, the material of the first conductive structure includes a conductive material obtained by doping a semiconductor material.

[0009] For example, in some embodiments of the present disclosure, the display panel further includes a connection line, and the first conductive structure is connected to the gate of the driving transistor through the connection line.

[0010] For example, in some embodiments of the present disclosure, the material of the first conductive structure is different from the material of the connection line.

[0011] For example, in some embodiments of the present disclosure, the connection line is in contact with the gate of the driving transistor and the first conductive structure respectively.

[0012] For example, in some embodiments of the present disclosure, the first conductive structure, the connection line, and the gate of the driving transistor constitute the gate signal portion of the driving transistor.

[0013] For example, in some embodiments of the present disclosure, the pixel circuit further includes a first reset transistor, a second pole of the first reset transistor is connected to the gate of the driving transistor, and the first conductive structure is multiplexed as the second pole of the first reset transistor.

[0014] For example, in some embodiments of the present disclosure, the display panel further includes a first reset control signal line and a first initialization signal line, a gate of the first reset transistor is connected to the first reset control signal line, a first pole of the first reset transistor is connected to the first initialization signal line, and a positive projection of the first pole of the first reset transistor on the substrate at least partially overlaps a positive projection of the stopper on the substrate.

[0015] For example, in some embodiments of the present disclosure, the display panel further includes a data line and a second conductive structure, the data line is configured to provide a data signal to the pixel circuit, the data line is connected to the second conductive structure, and a positive projection of the stopper on the substrate at least partially overlaps a positive projection of the second conductive structure on the substrate.

[0016] For example, in some embodiments of the present disclosure, an area of a positive projection on the substrate of a portion of the stopper overlapping with the second conductive structure is larger than an area of a positive projection on the substrate of a portion of the stopper overlapping with the conductive connection portion.

[0017] For example, in some embodiments of the present disclosure, an area of a positive projection on the substrate of a portion of the stopper overlapping with the first conductive structure is larger than an area of a positive projection on the substrate of a portion of the stopper overlapping with the second conductive structure.

[0018] For example, in some embodiments of the present disclosure, the positive projection of the stopper on the substrate overlaps at least partially with the positive projection of the data line on the substrate.

[0019] For example, in some embodiments of the present disclosure, the display panel further includes a gate line, the gate of the threshold compensation transistor is connected to the gate line, the pixel circuit further includes a data writing transistor, a first pole of the data writing transistor is connected to the data line, a second pole of the data writing transistor is connected to a first pole of the driving transistor, the gate of the data writing transistor is connected to the gate line, and the second conductive structure is reused as the first pole of the data writing transistor.

[0020] For example, in some embodiments of the present disclosure, the display panel further includes a first connection electrode, and the data line is connected to the second conductive structure through the first connection electrode.

[0021] For example, in some embodiments of the present disclosure, the data line, the first connection electrode, and the second conductive structure form a data signal portion.

[0022] For example, in some embodiments of the present disclosure, the pixel unit includes a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit and the second pixel unit are adjacent in a first direction, the first pixel unit and the third pixel unit are adjacent in a second direction, and the first direction intersects with the second direction; the data line includes a first data line, a second data line, and a third data line. The first data line is configured to provide a first data signal to the pixel circuit of the first pixel unit; the second data line is configured to provide a second data signal to the pixel circuit of the second pixel unit, the third data line is configured to provide a third data signal to the pixel circuit of the third pixel unit, and the third data line is located between the first data line and the second data line; the positive projection of the stopper on the substrate overlaps at least partially with the positive projection of the third data line on the substrate.

[0023] For example, in some embodiments of the present disclosure, the stopper is located between the first data line and the second data line.

[0024] For example, in some embodiments of the present disclosure, in a direction perpendicular to the substrate, the stopper is located between the second conductive structure and the third data line.

[0025] For example, in some embodiments of the present disclosure, the positive projection of the second conductive structure on the substrate overlaps at least partially with the positive projection of the third data line on the substrate.

[0026] For example, in some embodiments of the present disclosure, the display panel further includes a connection element. The light-emitting element is connected to the pixel circuit through the connection element. The connection element includes a shielding portion. The data line includes two adjacent data lines. The shielding portion is located between the two adjacent data lines. The orthographic projection of the connection line on the substrate at least partially overlaps with the orthographic projection of the shielding portion on the substrate.

[0027] For example, in some embodiments of the present disclosure, the connection element further includes a second connection electrode. The pixel circuit is connected to the second connection electrode. The second connection electrode is connected to the shielding portion. The shielding portion is connected to the light-emitting element.

[0028] For example, in some embodiments of the present disclosure, the pixel unit further includes a fourth pixel unit. The fourth pixel unit is adjacent to the second pixel unit in the second direction. The fourth pixel unit is adjacent to the third pixel unit in the first direction. The data line further includes a fourth data line. The fourth data line is configured to provide a fourth data signal to the pixel circuit of the fourth pixel unit. The orthographic projection of the stopper on the substrate at least partially overlaps with the orthographic projection of the fourth data line on the substrate.

[0029] For example, in some embodiments of the present disclosure, the stopper has a first edge. The first edge overlaps with the fourth data line. The angle between the first edge and the fourth data line is greater than zero and less than 90°.

[0030] For example, in some embodiments of the present disclosure, the stopper has a second edge. The second edge overlaps with the third data line. The angle between the second edge and the third data line is greater than zero and less than 90°.

[0031] For example, in some embodiments of the present disclosure, the fourth data line is located between the third data line and the second data line.

[0032] For example, in some embodiments of the present disclosure, the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit form a repeating unit.

[0033] For example, in some embodiments of the present disclosure, the stopper includes a first portion, a second portion, and a third portion. The first portion extends in the first direction. The second portion extends in the second direction. The third portion extends in the first direction. The first portion and the third portion are connected by the second portion. The first portion and the second portion form an inverted T-shaped structure.

[0034] For example, in some embodiments of the present disclosure, the first part, the second part, and the third part are located on the same layer and are of an integral structure.

[0035] For example, in some embodiments of the present disclosure, the pixel circuit further includes a storage capacitor. A first pole of the storage capacitor is connected to a gate of the driving transistor, and a second pole of the storage capacitor is connected to the first power supply line.

[0036] For example, in some embodiments of the present disclosure, the display panel further includes a second reset control signal line and a second initialization signal line. The pixel circuit further includes a second reset transistor. A gate of the second reset transistor is connected to the second reset control signal line, a first pole of the second reset transistor is connected to the second initialization signal line, and a second pole of the second reset transistor is connected to a first pole of the light-emitting element.

[0037] For example, in some embodiments of the present disclosure, the display panel further includes a light-emitting control signal line. The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. A gate of the first light-emitting control transistor is connected to the light-emitting control signal line, a first pole of the first light-emitting control transistor is connected to a first power supply terminal, and a second pole of the first light-emitting control transistor is connected to a first pole of the driving transistor; a gate of the second light-emitting control transistor is connected to the light-emitting control signal line, a first pole of the second light-emitting control transistor is connected to a second pole of the driving transistor, and a second pole of the second light-emitting control transistor is connected to a first pole of the light-emitting element.

[0038] At least one embodiment of the present disclosure further provides a display device, including any one of the above display panels.

[0039] On the other hand, at least one embodiment of the present disclosure provides a display panel, including: a substrate; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit being closer to the substrate than the light-emitting element, the pixel circuit including a driving transistor; a data line configured to provide a data signal to the pixel circuit; a connection element, the light-emitting element being connected to the pixel circuit through the connection element, the connection element including a shielding portion; and a connection line connected to a gate of the driving transistor; the data line includes two adjacent data lines, the shielding portion is located between the two adjacent data lines, and a positive projection of the connection line on the substrate at least partially overlaps a positive projection of the shielding portion on the substrate.

[0040] For example, in some embodiments of the present disclosure, a positive projection of the shielding portion on the substrate is larger than a positive projection of the connection line on the substrate.

[0041] For example, in some embodiments of the present disclosure, a positive projection of the gate of the driving transistor on the substrate partially overlaps a positive projection of the shielding portion on the substrate, and an area of an overlapping portion between the shielding portion and the gate of the driving transistor is smaller than an area of the gate of the driving transistor.

[0042] For example, in some embodiments of the present disclosure, the two adjacent data lines are arranged along a first direction, and the data line extends along a second direction.

[0043] For example, in some embodiments of the present disclosure, a dimension of the gate of the driving transistor in the first direction is greater than a dimension of the shielding portion in the first direction; a dimension of the shielding portion in the second direction is greater than a dimension of the gate of the driving transistor in the second direction.

[0044] For example, in some embodiments of the present disclosure, the connection line contacts the gate of the driving transistor.

[0045] For example, in some embodiments of the present disclosure, the data line and the shielding portion are located in the same layer, and an extending direction of the shielding portion is the same as an extending direction of the data line.

[0046] For example, in some embodiments of the present disclosure, the display panel further includes a first conductive structure, the connection line is connected to the first conductive structure, and a positive projection of the shielding portion on the substrate at least partially overlaps a positive projection of the first conductive structure on the substrate.

[0047] For example, in some embodiments of the present disclosure, the pixel circuit further includes a first reset transistor, a second pole of the first reset transistor is connected to the gate of the driving transistor, and the first conductive structure is multiplexed as the second pole of the first reset transistor.

[0048] For example, in some embodiments of the present disclosure, the display panel further includes a first reset control signal line and a first initialization signal line, a gate of the first reset transistor is connected to the first reset control signal line, and a first pole of the first reset transistor is connected to the first initialization signal line.

[0049] For example, in some embodiments of the present disclosure, the first reset transistor includes a first channel and a second channel, the first channel and the second channel of the first reset transistor are connected by a conductive connection portion, and a positive projection of the shielding portion on the substrate partially overlaps a positive projection of the conductive connection portion of the first reset transistor on the substrate.

[0050] For example, in some embodiments of the present disclosure, the display panel further includes a second initialization signal line. Among them, the first initialization signal line and the second initialization signal line are respectively disposed on opposite sides of the gate of the driving transistor, and the positive projection of the shielding portion on the substrate partially overlaps with the positive projection of the second initialization signal line on the substrate.

[0051] For example, in some embodiments of the present disclosure, the display panel further includes a first power supply line and a stopper. Among them, the first power supply line is configured to provide a first power supply voltage to the pixel circuit, the stopper is electrically connected to the first power supply line, and the positive projection of the first conductive structure on the substrate at least partially overlaps with the positive projection of the stopper on the substrate.

[0052] For example, in some embodiments of the present disclosure, the display panel further includes a second conductive structure. The data line is connected to the second conductive structure, and the positive projection of the stopper on the substrate at least partially overlaps with the positive projection of the second conductive structure on the substrate.

[0053] For example, in some embodiments of the present disclosure, the display panel further includes a gate line. The gate line intersects and is insulated from the data line. The gate line is configured to provide a scan signal to the pixel circuit. The pixel circuit further includes a threshold compensation transistor. A first pole of the threshold compensation transistor is connected to a second pole of the driving transistor, a second pole of the threshold compensation transistor is connected to the gate of the driving transistor; the gate of the threshold compensation transistor is connected to the gate line; the gate of the driving transistor is connected to the second pole of the threshold compensation transistor through the connection line. The threshold compensation transistor includes a first channel and a second channel, and the first channel and the second channel are connected through a conductive connection portion; the positive projection of the stopper on the substrate at least partially overlaps with the positive projection of the conductive connection portion of the threshold compensation transistor on the substrate.

[0054] For example, in some embodiments of the present disclosure, the area of the positive projection on the substrate of the portion of the stopper overlapping with the first conductive structure is larger than the area of the positive projection on the substrate of the portion of the stopper overlapping with the conductive connection portion of the threshold compensation transistor.

[0055] For example, in some embodiments of the present disclosure, the material of the first conductive structure is different from the material of the connection line.

[0056] For example, in some embodiments of the present disclosure, the pixel unit includes two adjacent pixel units in the same column, and two adjacent data lines are respectively connected to the two pixel units.

[0057] For example, in some embodiments of the present disclosure, the display panel further includes a second reset control signal line, the pixel circuit further includes a second reset transistor, a gate of the second reset transistor is connected to the second reset control signal line, a first pole of the second reset transistor is connected to the second initialization signal line, and a second pole of the second reset transistor is connected to a first pole of the light-emitting element.

[0058] For example, in some embodiments of the present disclosure, the pixel circuit further includes a first power supply terminal and a storage capacitor, a first pole of the storage capacitor is connected to a gate of the driving transistor, and a second pole of the storage capacitor is connected to the first power supply terminal.

[0059] For example, in some embodiments of the present disclosure, the pixel circuit further includes a data writing transistor, a gate of the data writing transistor is connected to the gate line, a first pole of the data writing transistor is connected to the data line, and a second pole of the data writing transistor is connected to a first pole of the driving transistor.

[0060] For example, in some embodiments of the present disclosure, the display panel further includes a light-emitting control signal line, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, a gate of the first light-emitting control transistor is connected to the light-emitting control signal line, a first pole of the first light-emitting control transistor is connected to the first power supply terminal, and a second pole of the first light-emitting control transistor is connected to a first pole of the driving transistor; a gate of the second light-emitting control transistor is connected to the light-emitting control signal line, a first pole of the second light-emitting control transistor is connected to a second pole of the driving transistor, and a second pole of the second light-emitting control transistor is connected to a first pole of the light-emitting element.

[0061] For example, in some embodiments of the present disclosure, the data line has a first portion and a second portion, a distance between the first portions of two adjacent data lines is greater than a distance between the second portions of the two adjacent data lines, and the shielding portion is located between the second portions of the two adjacent data lines.

[0062] For example, in some embodiments of the present disclosure, the second portions of the two adjacent data lines are respectively close to the first light-emitting control transistor and the second light-emitting control transistor, and the storage capacitor is located between the first portions of the two adjacent data lines.

[0063] For example, in some embodiments of the present disclosure, the connection element further includes a connection electrode, the connection electrode is connected to the pixel circuit, and the light-emitting element is connected to the connection electrode through the shielding portion.

[0064] At least one embodiment of the present disclosure further provides a display device, including any of the above display panels. Brief Description of the Drawings

[0065] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0066] Figure 1 It is a schematic diagram of a 7T1C pixel circuit;

[0067] Figure 2 is Figure 1 the timing diagram of the pixel circuit shown;

[0068] Figure 3 It is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the present disclosure;

[0069] Figure 4 It is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0070] Figure 5 It is a schematic diagram of forming an active layer, a source electrode, and a drain electrode of a thin film transistor in a display panel provided by an embodiment of the present disclosure;

[0071] Figure 6 It is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0072] Figure 7 It is a plan view of a display panel after forming the second conductive pattern layer provided by an embodiment of the present disclosure;

[0073] Figure 8 It is a plan view of a via formed in at least one of a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer in a display panel provided by an embodiment of the present disclosure;

[0074] Figure 9 It is a plan view of a display panel after forming a via in at least one of a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer provided by an embodiment of the present disclosure;

[0075] Figure 10 It is a plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0076] Figure 11 It is a plan view of a display panel after forming the third conductive pattern layer provided by an embodiment of the present disclosure;

[0077] Figure 12A plan view of a via formed in a passivation layer and a first planarization layer in a display panel provided by an embodiment of the present disclosure;

[0078] Figure 13 A plan view of a display panel provided by an embodiment of the present disclosure after a via is formed in a passivation layer and a first planarization layer;

[0079] Figure 14 A plan view of a fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0080] Figure 15 A plan view of a display panel provided by an embodiment of the present disclosure after a fourth conductive pattern layer is formed;

[0081] Figure 16A A plan view of a fourth conductive pattern layer in a display panel provided by another embodiment of the present disclosure;

[0082] Figure 16B A plan view of a display panel provided by another embodiment of the present disclosure after a fourth conductive pattern layer is formed;

[0083] Figure 17 A plan view of a display panel provided by another embodiment of the present disclosure after a fourth conductive pattern layer is formed;

[0084] Figure 18 A partial cross-sectional view of a display panel provided by an embodiment of the present disclosure ( Figure 17 a cross-sectional view taken along line AB);

[0085] Figure 19 A partial plan view of a display panel provided by an embodiment of the present disclosure;

[0086] Figure 20 A partial cross-sectional view of a display panel provided by an embodiment of the present disclosure ( Figure 19 a cross-sectional view taken along line CD); and

[0087] Figure 21 A pixel circuit diagram of a repeating unit of a display panel provided by an embodiment of the present disclosure. Detailed Description of the Embodiments

[0088] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0089] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms "connect" or "couple" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0090] Currently, there is a large demand for high frame rate AMOLED display panels in the market. For example, the Dual Data scheme can achieve a 120Hz drive while ensuring the display effect.

[0091] Figure 1 It is a schematic diagram of a 7T1C pixel circuit. Figure 2 is Figure 1 The working timing diagram of the pixel circuit shown. Figure 1 The pixel circuit shown can be a pixel circuit of a common low temperature poly-silicon (LTPS) AMOLED in the related art.

[0092] Figure 1 It shows the pixel circuit of a pixel unit of the display panel. As Figure 1 shown, the pixel unit 101 includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes six switching transistors (T2 - T7), a driving transistor T1, and a storage capacitor Cst. The six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 20 includes a first electrode 201, a second electrode 202, and a light-emitting functional layer located between the first electrode 201 and the second electrode 202. For example, the first electrode 201 is an anode, and the second electrode 202 is a cathode. Generally, the threshold compensation transistor T3 and the first reset transistor T6 adopt the dual-gate TFT method to reduce leakage.

[0093] As Figure 1As shown, the display panel includes gate lines GT, data lines DT, a first power supply terminal VDD, a second power supply terminal VSS, an emission control signal line EML, an initialization signal line INT, a first reset control signal line RT1, a second reset control signal line RT2, etc. The first power supply terminal VDD is configured to provide a constant first voltage signal ELVDD to the pixel unit 101, the second power supply terminal VSS is configured to provide a constant second voltage signal ELVSS to the pixel unit 101, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The gate lines GT are configured to provide scan signals SCAN to the pixel unit 101, the data lines DT are configured to provide data signals DATA (data voltages VDATA) to the pixel unit 101, the emission control signal line EML is configured to provide an emission control signal EM to the pixel unit 101, the first reset control signal line RT1 is configured to provide a reset control signal RESET to the pixel unit 101, the second reset control signal line RT1 is configured to provide a scan signal SCAN to the pixel unit 101, and the initialization signal line INT is configured to provide an initialization signal Vinit to the pixel unit 101. For example, the initialization signal Vinit is a constant voltage signal, and its magnitude can, for example, be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vinit can be less than or equal to the second voltage signal ELVSS. For example, the initialization signal line INT includes a first initialization signal line INT1 and a second initialization signal line INT2. For example, the first initialization signal line INT1 is configured to provide an initialization signal Vinit1 to the pixel unit 101, and the second initialization signal line INT1 is configured to provide an initialization signal Vinit2 to the pixel unit 101. For example, in some embodiments, the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal and are both Vinit.

[0094] As Figure 1 shown, the driving transistor T1 is electrically connected to the light-emitting element 20 and outputs a driving current to drive the light-emitting element 20 to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS.

[0095] For example, the light-emitting element 20 is an organic light-emitting diode (OLED), and the light-emitting element 20 emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit 10. For example, one pixel includes a plurality of pixel units. One pixel can include a plurality of pixel units that emit different colors of light. For example, one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto. The number of pixel units included in one pixel and the light-emitting situation of each pixel unit can be determined as needed.

[0096] For example, as Figure 1 shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first pole T21 of the data writing transistor T2 is connected to the data line DT, and the second pole T22 of the data writing transistor T2 is connected to the first pole T11 of the driving transistor T1.

[0097] For example, as Figure 1 shown, the pixel circuit 10 further includes a threshold compensation transistor T3. The gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, the first pole T31 of the threshold compensation transistor T3 is connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0098] For example, as Figure 1 shown, the display panel further includes a light emission control signal line EML. The pixel circuit 10 further includes a first light emission control transistor T4 and a second light emission control transistor T5. The gate T40 of the first light emission control transistor T4 is connected to the light emission control signal line EML, the first pole T41 of the first light emission control transistor T4 is connected to the first power supply terminal VDD, and the second pole T42 of the first light emission control transistor T4 is connected to the first pole T11 of the driving transistor T1; the gate T50 of the second light emission control transistor T5 is connected to the light emission control signal line EML, the first pole T51 of the second light emission control transistor T5 is connected to the second pole T12 of the driving transistor T1, and the second pole T52 of the second light emission control transistor T5 is connected to the first pole 201 of the light emitting element 20.

[0099] As Figure 1 shown, a first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. A second reset transistor T7 is connected to the first pole 201 of the light emitting element 20 and is configured to reset the first pole 201 of the light emitting element 20. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first pole 201 of the light emitting element 20 through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected to be input with the same initialization signal, but not limited thereto. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be insulated from each other and are configured to be input with signals respectively.

[0100] For example, as Figure 1As shown, the first pole T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second pole T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first pole T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second pole T72 of the second reset transistor T7 is connected to the first pole 201 of the light-emitting element 20. For example, as Figure 1 As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RT1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RT2.

[0101] As Figure 1 As shown, the first power supply terminal VDD is configured to supply a first voltage signal ELVDD to the pixel circuit 10; the pixel circuit further includes a storage capacitor Cst, the first pole Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD.

[0102] For example, as Figure 1 As shown, the display panel further includes a second power supply terminal VSS, and the second power supply terminal VSS is connected to the second pole 201 of the light-emitting element 20.

[0103] As Figure 2 As shown, in a frame display period, the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light-emitting stage t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset. When the scan signal SCAN is at a low level, the first pole 201 (for example, the anode) of the light-emitting element 20 is reset. For example, as Figure 1 As shown, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and at the same time, the threshold voltage Vth of the driving transistor T1 is obtained, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; when the light-emitting control signal line EML is at a low level, the light-emitting element 20 emits light, and the voltage of the first node N1 (the gate signal part of the driving transistor) is maintained (the light-emitting stability of the light-emitting element 20) by the storage capacitor Cst. During the driving process of the pixel circuit 10, in the light-emitting stage, the storage capacitor is used to hold the voltage signal so that the potential of its signal holding end is kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a driving current, and further driving the light-emitting element 20 to emit light.

[0104] As Figure 2 As shown, in the reset stage t1, the light-emitting control signal EM is set to the off voltage, the reset control signal RESET is set to the on voltage, and the scan signal SCAN is set to the off voltage.

[0105] As Figure 2 shown, during the data writing and threshold compensation phase and the second reset phase t2, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the on voltage.

[0106] As Figure 2 shown, during the light emission phase t3, the light emission control signal EM is set to the on voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the off voltage.

[0107] As Figure 2 shown, both the first voltage signal ELVDD and the second voltage signal ELVSS are constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0108] For example, in the embodiments of the present disclosure, the on voltage refers to the voltage that can turn on the first and second poles of the corresponding transistor, and the off voltage refers to the voltage that can turn off the first and second poles of the corresponding transistor. When the transistor is a P-type transistor, the on voltage is a low voltage (e.g., 0V), and the off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the on voltage is a high voltage (e.g., 5V), and the off voltage is a low voltage (e.g., 0V). Figure 2 The drive waveforms shown are all described by taking the P-type transistor as an example. For example, the on voltage is a low voltage (e.g., 0V), and the off voltage is a high voltage (e.g., 5V), but it is not limited thereto.

[0109] Please refer to Figure 1 and Figure 2 simultaneously. During the first reset phase t1, the light emission control signal EM is the off voltage, the reset control signal RESET is the on voltage, and the scan signal SCAN is the off voltage. At this time, the first reset transistor T6 is in the conducting state, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, and the second light emission control transistor T5 are in the off state. The first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the drive transistor T1 and is stored by the storage capacitor Cst, resetting the drive transistor T1 and erasing the data stored during the previous (previous frame) light emission.

[0110] During the data writing, threshold compensation, and second reset phase t2, the emission control signal EM is at the off voltage, the reset control signal RESET is at the off voltage, and the scan signal SCAN is at the on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in the conducting state, the second reset transistor T7 is in the conducting state, and the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first electrode 201 of the light-emitting element 20 to reset the light-emitting element 20. The first emission control transistor T4, the second emission control transistor T5, and the first reset transistor T6 are in the off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1. That is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 conducts to connect the driving transistor T1 into a diode structure, whereby the gate of the driving transistor T1 can be charged. After the charging is completed, the gate voltage of the driving transistor T1 is VDATA + Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1. That is, the threshold compensation transistor T3 receives the scan signal SCAN and compensates the threshold voltage for the gate voltage of the driving transistor T1 according to the scan signal SCAN. In this stage, the voltage difference across the storage capacitor Cst is ELVDD - VDATA - Vth.

[0111] During the light-emitting phase t3, the emission control signal EM is at the on voltage, the reset control signal RESET is at the off voltage, and the scan signal SCAN is at the off voltage. The first emission control transistor T4 and the second emission control transistor T5 are in the conducting state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first emission control transistor T4. The gate voltage of the driving transistor T1 remains at VDATA + Vth. The light-emitting current I flows into the light-emitting element 20 through the first emission control transistor T4, the driving transistor T1, and the second emission control transistor T5, and the light-emitting element 20 emits light. That is, the first emission control transistor T4 and the second emission control transistor T5 receive the emission control signal EM and control the light-emitting element 20 to emit light according to the emission control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0112] K(Vgs - Vth) 2 = K(VDATA + Vth - ELVDD - Vth) 2 = K(VDATA - ELVDD) 2

[0113] Among them, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source of the driving transistor T1 (i.e., the first pole of the driving transistor T1 in this embodiment).

[0114] It can be seen from the above formula that the current flowing through the light-emitting element 20 is independent of the threshold voltage of the driving transistor T1. Therefore, this pixel circuit compensates well for the threshold voltage of the driving transistor T1.

[0115] For example, the ratio of the duration of the light-emitting stage t3 to the display period of one frame can be adjusted. In this way, the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the display period of one frame. For example, the ratio of the duration of the light-emitting stage t3 to the display period of one frame is adjusted by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.

[0116] For example, the embodiments of the present disclosure are not limited to Figure 1 the specific pixel circuit shown. Pixel circuits that can achieve compensation for the driving transistor can be adopted. Other setting methods that can be easily thought of by those of ordinary skill in the art without creative efforts based on the description and teaching of the present disclosure for this implementation manner all fall within the protection scope of the present disclosure.

[0117] The following will be described in conjunction with Figures 3 to 21 the display panel provided by the embodiments of the present disclosure. Figure 3 is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the present disclosure. Figure 4 is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 5 is a schematic diagram of an active layer, a source electrode, and a drain electrode for forming a thin-film transistor in a display panel provided by an embodiment of the present disclosure. Figure 6 is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 7 is a plan view after forming the second conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 8 is a plan view of a via formed in at least one of a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer in a display panel provided by an embodiment of the present disclosure. Figure 9 is a plan view after forming a via in at least one of a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer in a display panel provided by an embodiment of the present disclosure. Figure 10A plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 11 A plan view of a display panel after forming a third conductive pattern layer provided by an embodiment of the present disclosure. Figure 12 A schematic plan view of a via formed in a passivation layer and a first planarization layer in a display panel provided by an embodiment of the present disclosure. Figure 13 A schematic plan view of a display panel after forming a via in a passivation layer and a first planarization layer provided by an embodiment of the present disclosure. Figure 14 A plan view of a fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 15 A schematic plan view of a display panel after forming a fourth conductive pattern layer provided by an embodiment of the present disclosure. Figure 16A A plan view of a fourth conductive pattern layer in a display panel provided by another embodiment of the present disclosure. Figure 17 A schematic plan view of a display panel after forming a fourth conductive pattern layer provided by another embodiment of the present disclosure. Figure 18 A partial cross-sectional view of a display panel provided by an embodiment of the present disclosure ( Figure 17 a cross-sectional view taken along line AB). Figure 19 A partial plan view of a display panel provided by an embodiment of the present disclosure. Figure 20 A partial cross-sectional view of a display panel provided by an embodiment of the present disclosure ( Figure 19 a cross-sectional view taken along line CD). Figure 21 A pixel circuit diagram of a repeating unit of a display panel provided by an embodiment of the present disclosure.

[0118] Figures 5 to 17 And Figure 19 shows a first direction X and a second direction Y, and the second direction Y intersects the first direction X. For example, in the embodiments of the present disclosure, the first direction X is perpendicular to the second direction Y as an example. For example, the first direction X is the row direction of pixel units, and the second direction Y is the column direction of pixel units. Both the first direction X and the second direction Y are parallel to the substrate BS. For example, the first direction X is perpendicular to the second direction Y. Figure 17 And Figure 19 shows a third direction Z, and the third direction Z is perpendicular to the substrate BS. The third direction Z is perpendicular to the first direction X and perpendicular to the second direction Y.

[0119] In the embodiments of the present disclosure, for clarity of illustration, in the plan view, the insulating layer is shown in the form of a via, the insulating layer itself is subjected to a transparency treatment, and the first conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer, and the fourth conductive pattern layer are subjected to a semi-transparency treatment.

[0120] Figure 3shows a semiconductor pattern SCP, Figure 4 shows a first conductive pattern layer LY1. For example, a first gate insulating layer (first gate insulating layer GI1, refer to Figure 18 ) is provided between the first conductive pattern layer LY1 and the semiconductor pattern SCP. For example, the semiconductor pattern SCP and subsequent various components are formed on a substrate. As Figure 4 shown, the first conductive pattern layer LY1 includes a first reset control signal line RT1, a gate line GT, a first pole Ca of a storage capacitor Cst (gate T10 of a driving transistor T1), a light emission control signal line EML, and a second reset control signal line RT2. Using the first conductive pattern layer LY1 as a mask, the semiconductor pattern SCP is doped so that the area of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 retains semiconductor characteristics, forming an active layer ACT (see Figure 5 ), while the area of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 is made conductive, forming the source and drain of a thin film transistor. As shown in 5, the active layer ACT formed after partial conduction of the semiconductor pattern SCP is shown. For example, in an embodiment of the present disclosure, the gate line GT of this stage is connected to the reset control signal line of the next stage. For example, the gate line GT and the second reset control signal line RT2 can be electrically connected to input the same signal at the same time.

[0121] As Figure 4 and Figure 5 shown, the first reset control signal line RT1, the gate line GT, the light emission control signal line EML, and the second reset control signal line RT2 all extend along the first direction X.

[0122] For example, as Figure 5As shown, during the fabrication of the display panel, a self-alignment process is adopted. Using the first conductive pattern layer LY1 as a mask, the semiconductor pattern layer SCP is conductorized. For example, the semiconductor pattern layer SCP is heavily doped using an ion implantation process, so that the portions of the semiconductor pattern layer SCP not covered by the first conductive pattern layer LY1 are conductorized, forming the source regions (first poles T11) and drain regions (second poles T12) of the driving transistor T1, the source regions (first poles T21) and drain regions (second poles T22) of the data writing transistor T2, the source regions (first poles T31) and drain regions (second poles T32) of the threshold compensation transistor T3, the source regions (first poles T41) and drain regions (second poles T42) of the first light-emitting control transistor T4, the source regions (first poles T51) and drain regions (second poles T52) of the second light-emitting control transistor T5, the source regions (first poles T61) and drain regions (second poles T62) of the first reset transistor T6, and the source regions (first poles T71) and drain regions (second poles T72) of the second reset transistor T7. The portions of the semiconductor pattern layer SCP covered by the first conductive pattern layer L1 retain semiconductor characteristics, forming the channel regions T13 of the driving transistor T1, the channel regions T23 of the data writing transistor T2, the channel regions T33 of the threshold compensation transistor T3, the channel regions T43 of the first light-emitting control transistor T4, the channel regions T53 of the second light-emitting control transistor T5, the channel regions T63 of the first reset transistor T6, and the channel regions T73 of the second reset transistor T7. The channel regions of each transistor form the active layer ACT (refer to Figure 5 ).

[0123] For example, as Figure 5 shown, the second pole T72 of the second reset transistor T7 and the second pole T52 of the second light-emitting control transistor T5 are integrally formed; the first pole T51 of the second light-emitting control transistor T5, the second pole T12 of the driving transistor T1, and the first pole T31 of the threshold compensation transistor T3 are integrally formed; the first pole T11 of the driving transistor T1, the second pole T22 of the data writing transistor T2, and the second pole T42 of the first light-emitting control transistor T4 are integrally formed; the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed.

[0124] For example, the channel region (active layer) of the transistor adopted in the embodiments of the present disclosure can be single-crystalline silicon, polycrystalline silicon (such as low-temperature polycrystalline silicon), or metal oxide semiconductor materials (such as IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin-film transistors, that is, the channel material of the transistor is metal oxide semiconductor material (such as IGZO, AZO, etc.). The metal oxide semiconductor thin-film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0125] For example, the transistors adopted in the embodiments of the present disclosure can include various structures, such as top-gate type, bottom-gate type, or double-gate structure. In some embodiments, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double-gate thin-film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0126] For example, as Figure 5 shown, a part of the light emission control signal line EML serves as the gate T40 of the first light emission control transistor T4, a part of the light emission control signal line EML serves as the gate T50 of the second light emission control transistor T5, the gate T60 of the first reset transistor T6 is a part of the first reset control signal line RT1, the gate T70 of the second reset transistor T7 is a part of the second reset control signal line RT2, the gate T20 of the data writing transistor T2 is a part of the gate line GT, and the gate T30 of the threshold compensation transistor T3 is a part of the gate line GT.

[0127] As Figure 5 shown, the threshold compensation transistor T3 is a double-gate transistor. The threshold compensation transistor T3 includes a first channel T331 and a second channel T332, and the first channel T331 and the second channel T332 are connected by a first conductive connection portion CP1. As Figure 5 shown, the first reset transistor T6 is a double-gate transistor. The first reset transistor T6 includes a first channel T631 and a second channel T632, and the first channel T631 and the second channel T632 are connected by a second conductive connection portion CP2.

[0128] Figure 6 shows the second conductive pattern layer LY2. For example, a second gate insulating layer (second gate insulating layer GI2, refer to Figure 18 ) is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes a stopper BK, a first initialization signal line INT1, a second initialization signal line INT2, and the second pole Cb of the storage capacitor Cst. For example, refer toFigure 6 , the first initialization signal line INT1 extends along the first direction X, and the second initialization signal line INT2 extends along the first direction X. The first initialization signal line INT1 and the second initialization signal line INT2 are arranged along the second direction Y. As Figure 6 shown, the first initialization signal line INT1 and the second initialization signal line INT2 are located on both sides of the second pole Cb of the storage capacitor Cst, the first initialization signal line INT1 and the second initialization signal line INT2 are located on both sides of the stopper BK, and the second pole Cb of the storage capacitor Cst and the stopper BK are provided between the first initialization signal line INT1 and the second initialization signal line INT2. As Figure 6 shown, the first initialization signal line INT1, the stopper BK, the second pole Cb of the storage capacitor Cst, and the second initialization signal line INT2 are arranged in sequence along the second direction Y. The stopper BK is electrically connected to the first power supply line VDD1 so that the first power supply line VDD1 provides a constant voltage for the stopper BK.

[0129] As Figure 7 shown, the positive projection of the stopper BK on the substrate at least partially overlaps with the positive projection of the first conductive connection portion CP1 on the substrate. That is, the stopper BK is configured to block the first conductive connection portion CP1 between the two channels of the threshold compensation transistor T3, and the stopper BK and the first conductive connection portion CP1 form a capacitor (stable capacitor) to avoid leakage current generated by the threshold compensation transistor T3 and avoid affecting the display effect. As Figure 7 shown, in the plan view, the stopper BK and the first conductive connection portion CP1 partially overlap.

[0130] As Figure 7 shown, in the plan view, the first initialization signal line INT1 and the second conductive connection portion CP2 partially overlap, and a capacitor (stable capacitor) is formed between the first initialization signal line INT1 and the second conductive connection portion CP2 to avoid leakage current generated by the first reset transistor T6 and avoid affecting the display effect.

[0131] For example, in the embodiments of the present disclosure, the partial overlap of element A and element B may refer to that a part of element A overlaps with element B, a part of element B overlaps with element A, or a part of element A overlaps with a part of element B. Element A and element B are two different elements.

[0132] As Figure 7 shown, the gate line GT extends along the first direction X, the first reset control signal line RT1 extends along the first direction X, and the stopper BK is located between the gate line GT and the first reset control signal line RT1. Thus, the position of the stopper BK in the second direction Y is defined.

[0133] As Figure 6 and Figure 7As shown, the stopper BK includes a first part BKa, a second part BKb, and a third part BKc. The first part BKa extends along a first direction X, the second part BKb extends along a second direction Y, and the third part BKc extends along the first direction X. The first part BKa and the third part BKc are connected by the second part BKb, and the first part BKa and the second part BKb form an inverted T-shaped structure. For example, the third part BKc has a T-shaped structure. For example, as Figure 6 shown, the first part BKa, the second part BKb, and the third part BKc are located on the same layer and are of an integral structure. This will be introduced later Figure 6 and Figure 7 the functions of the respective parts of the stopper having the shape shown.

[0134] As Figure 5 , Figure 7 and Figure 15 shown, the display panel includes a first conductive structure CDT1. The first conductive structure CDT1 is connected to the gate T10 of the driving transistor T1. The orthographic projection of the first conductive structure CDT1 on the substrate at least partially overlaps with the orthographic projection of the stopper BK on the substrate, so that the stopper BK shields the parasitic capacitance between the gate signal part PT1 of the driving transistor (including the gate T10 of the driving transistor T1 and the first conductive structure CDT1) and the data line, reduces the coupling effect, and alleviates the longitudinal crosstalk. Refer to Figure 15 and Figure 6 , the orthographic projection of the first conductive structure CDT1 on the substrate at least partially overlaps with the orthographic projection of the third part BKc of the stopper BK on the substrate.

[0135] For example, the material of the first conductive structure CDT1 is the same as the material of the first conductive connection part CP1. For example, the first conductive structure CDT1 and the first conductive connection part CP1 can be made from the same film layer by the same process.

[0136] For example, the material of the first conductive structure CDT1 includes a conductive material obtained by doping a semiconductor material. For example, the material of the first conductive structure CDT1 includes a conductive material obtained by doping polysilicon, but is not limited thereto.

[0137] For example, as Figure 5 , Figure 7 and Figure 15 shown, the first conductive structure CDT1 is multiplexed as the second pole T62 of the first reset transistor T6. Then, the orthographic projection of the second pole T62 of the first reset transistor T6 on the substrate at least partially overlaps with the orthographic projection of the stopper BK on the substrate. In the embodiments of the present disclosure, the case where the first conductive structure CDT1 is used as the second pole T62 of the first reset transistor T6 is taken as an example for illustration.

[0138] For example, as Figure 5, Figure 7 and Figure 15 As shown in Figure 7 and Figure 15 , in the plan view, the first pole T61 of the first reset transistor T6 partially overlaps with the stopper BK, that is, the orthographic projection of the first pole T61 of the first reset transistor T6 on the substrate overlaps at least partially with the orthographic projection of the stopper BK on the substrate. This setting can increase the area of the stopper, making it play a better shielding role.

[0139] For example, referring to Figure 16A and Figure 16B , the data line DT has a first part P01 and a second part P02. The pitch SP1 between the first parts P01 of two adjacent data lines DT is greater than the pitch SP2 between the second parts P02 of two adjacent data lines DT. The shielding part CEs is located between the second parts P02 of two adjacent data lines DT. As shown in Figure 16A and Figure 16B , the shielding part CEs is also located between the first parts P01 of two adjacent data lines DT. Figure 16A and Figure 16B As shown in Figure 16A and Figure 16B , the shielding part CEs is also located between the first parts P01 of two adjacent data lines DT.

[0140] For example, as shown in Figure 16B , the second parts P02 of two adjacent data lines DT are respectively close to the first light-emitting control transistor T4 and the second light-emitting control transistor T5, and the storage capacitor Cst is located between the first parts P01 of two adjacent data lines DT.

[0141] The second parts P02 of two adjacent data lines DT can also be referred to as narrowing parts. As shown in Figure 16B , two adjacent data lines DT are narrowed at the first light-emitting control transistor T4 and the second light-emitting control transistor T5, and are not narrowed at the storage capacitor Cst. Figure 16B As shown in Figure 16B , two adjacent data lines DT are narrowed at the first light-emitting control transistor T4 and the second light-emitting control transistor T5, and are not narrowed at the storage capacitor Cst.

[0142] Referring to Figure 17 , in order to play a better shielding role, the orthographic projection of the shielding part CEs on the substrate overlaps at least partially with the orthographic projection of the first conductive structure CDT1 on the substrate.

[0143] Referring to Figure 5 and Figure 17 , the orthographic projection of the shielding part CEs on the substrate overlaps partially with the orthographic projection of the second conductive connection part CP2 of the first reset transistor T6 on the substrate. For example, referring to Figure 5 , Figure 14 , Figure 15 and Figure 17, the orthographic projection of the shielding part CEs in the first pixel unit 101a on the substrate partially overlaps with the orthographic projection of the second conductive connection part CP2 of the first reset transistor T6 in the third pixel unit 101c on the substrate. That is, the orthographic projection of the shielding part CEs in a pixel unit 101 on the substrate partially overlaps with the orthographic projection of the second conductive connection part CP2 of the first reset transistor T6 in the pixel unit in the same column in the next row on the substrate.

[0144] Reference Figures 14 to 16A , taking Figure 15 the stopper BK in the upper left corner as an example, the stopper BK overlaps with the first conductive connection part CP1 of the threshold compensation transistor T3 of the second pixel unit 101b to form a stable capacitor to reduce leakage current.

[0145] As Figure 7 shown, the area A1 of the orthographic projection of the part of the stopper BK overlapping with the first conductive structure CDT1 (the second pole T62 of the first reset transistor T6) on the substrate is larger than the area A0 of the orthographic projection of the part of the stopper BK overlapping with the first conductive connection part CP1 on the substrate. That is, the area A1 of the orthographic projection of the overlapping part of the stopper BK and the first conductive structure CDT1 on the substrate is larger than the area A0 of the orthographic projection of the overlapping part of the stopper BK and the first conductive connection part CP1 on the substrate.

[0146] As Figure 10 shown, the third conductive pattern layer LY3 includes a power supply connection line VDD0, connection electrodes CEa, CEb, CEc, CEd (the second connection electrode CEd), and CEe (the first connection electrode CEe). An interlayer insulating layer (interlayer insulating layer ILD, refer to Figure 18 ) is provided between the third conductive pattern layer LY3 and the second conductive pattern layer LY2.

[0147] Reference Figures 9 to 11, the power supply connection line VDD0 is electrically connected to the first pole T41 of the first light-emitting control transistor T4 through the via hole H2, the power supply connection line VDD0 is electrically connected to the second pole Cb of the storage capacitor Cst through the via holes H3 and H30, and the power supply connection line VDD0 is electrically connected to the conductive block BK through the via hole H0. One end of the connection electrode CEa is electrically connected to the first initialization signal line INT1 through the via hole H12, and the other end of the connection electrode CEa is connected to the first pole T61 of the first reset transistor T6 through the via hole H11, so that the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line INT1. One end of the connection electrode CEb is electrically connected to the second pole T62 of the first reset transistor T6 through the via hole H22, and the other end of the connection electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole Ca of the storage capacitor Cst) through the via hole H21, so that the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole Ca of the storage capacitor Cst). One end of the connection electrode CEc is electrically connected to the second initialization signal line INT2 through the via hole H32, and the other end of the connection electrode CEc is connected to the first pole T71 of the second reset transistor T7 through the via hole H31, so that the first pole T71 of the second reset transistor T7 is electrically connected to the second initialization signal line INT2. The connection electrode CEd is electrically connected to the second pole T52 of the second light-emitting control transistor T5 through the via hole H40. The connection electrode CEd can be used to be connected to the subsequently formed connection electrode CEf, and then electrically connected to the first electrode 201 of the light-emitting element 20 (refer to Figure 17 ). The connection electrode CEe is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole H5. The connection electrode CEe is used to be connected to the data line.

[0148] Figure 14 shows the fourth conductive pattern layer LY4. The fourth conductive pattern layer LY4 includes a data line DT, a connection electrode CEf, and a first power supply line VDD1. A passivation layer (passivation layer PVX, refer to Figure 18 ) and a first planarization layer (first planarization layer PLN1, refer to Figure 18)。The first power supply line VDD1 is connected to the power supply connection line VDD0 through a via hole H6 that penetrates the passivation layer and the first planarization layer. The connection electrode CEf is connected to the connection electrode CEd through a via hole H7 that penetrates the passivation layer and the first planarization layer. The data line DT is connected to the connection electrode CEe through a via hole H8 that penetrates the passivation layer and the first planarization layer, and is further electrically connected to the first pole T21 of the data writing transistor T2. For example, the connection electrode CEf (the third connection electrode CEf) and the connection electrode CEd (the second connection electrode CEd) form a connection element CE0. For example, the light-emitting element 20 is connected to the pixel circuit 10 through the connection element CE0. For example, the pixel circuit 10 is connected to the connection electrode CEd (the second connection electrode CEd), the connection electrode CEd (the second connection electrode CEd) is connected to the connection electrode CEf (the third connection electrode CEf), and the connection electrode CEf (the third connection electrode CEf) is connected to the light-emitting element 20.

[0149] Figure 14 The first data line DT1, the second data line DT2, the third data line DT3, and the fourth data line DT4 are shown. Figure 14 The positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d are also shown.

[0150] As Figure 14 Figure 16A and Figure 16B shown, the data line DT extends along the second direction Y, and the first data line DT1, the third data line DT3, the fourth data line DT4, and the second data line DT2 are arranged along the first direction X. The fourth data line DT4 is located between the third data line DT3 and the second data line DT2. The first pixel unit 101a and the second pixel unit 101b are in the same row and in adjacent columns, and the third pixel unit 101c and the fourth pixel unit 101d are in the same row and in adjacent columns. The first pixel unit 101a and the third pixel unit 101c are in the same column and in adjacent rows, and the second pixel unit 101b and the fourth pixel unit 101d are in the same column and in adjacent rows. As Figure 15 shown, the data line DT intersects with the gate line GT and is insulated from each other.

[0151] For example, the first power supply line VDD1 is configured to supply a first voltage signal ELVDD to the pixel circuit 10. The first power supply line VDD1 is electrically connected to the stopper BK to provide a constant voltage to the stopper BK. The first power supply line VDD1 is connected to the first power supply terminal VDD, and the second pole Cb of the storage capacitor Cst is connected to the first power supply line VDD1. For example, the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1. Figure 15A plan view showing the structure after forming the fourth conductive pattern layer LY4.

[0152] For example, the first pole T41 of the first light-emitting control transistor T4 is connected to the first power supply terminal VDD through a power supply connection line VDD0 and a first power supply line VDD1 (refer to Figure 10 and Figure 15 ).

[0153] As Figure 5 , Figure 7 and Figure 15 shown, the display panel includes a second conductive structure CDT2, and the orthographic projection of the stopper BK on the substrate at least partially overlaps with the orthographic projection of the second conductive structure CDT2 on the substrate to shield the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoid display abnormalities caused by coupling. For example, in the first pixel unit 101a and the second pixel unit 101b, the stopper BK overlaps with the first conductive connection portion CP1 of the threshold compensation transistor T3 of the second pixel unit 101b and overlaps with the second conductive structure CDT2 of the first pixel unit 101a. For example, the second conductive structure CDT2 has the same material as the first conductive structure CDT1.

[0154] As Figure 5 , Figure 7 and Figure 15 shown, the first pole T21 of the data writing transistor T2 is multiplexed as the second conductive structure CDT2. In the embodiments of the present disclosure, the first pole T21 of the data writing transistor T2 is used as the second conductive structure CDT2 as an example for illustration, but it is not limited thereto.

[0155] As Figure 15 shown, the data line DT, the connection electrode CEe, and the second conductive structure CDT2 form a data signal portion PT2. For example, the data line DT, the connection electrode CEe, and the second conductive structure CDT2 form the same node. For example, the potentials on the data line DT, the connection electrode CEe, and the second conductive structure CDT2 are the same or substantially the same. That is, the potentials at various positions on the data signal portion PT2 are the same or substantially the same. Thus, the stopper BK overlapping with the second conductive structure CDT2 can shield the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoid display abnormalities caused by coupling.

[0156] Refer to Figure 7, the area A2 of the orthographic projection on the substrate of the overlapping portion of the stopper BK with the second conductive structure CDT2 (the first pole T21 of the data writing transistor T2) is greater than the area A0 of the orthographic projection on the substrate of the overlapping portion of the stopper BK with the first conductive connection portion CP1. For example, the data line DT is connected to the connection electrode CEe through the via hole H8, and then connected to the second conductive structure CDT2.

[0157] Reference Figure 7 , the area A1 of the orthographic projection on the substrate of the overlapping portion of the stopper BK with the first conductive structure CDT1 is greater than the area A2 of the orthographic projection on the substrate of the overlapping portion of the stopper BK with the second conductive structure CDT2. For example, the area A1 is greater than the area A2, and the area A2 is greater than the area A0. That is, the areas A1, A2, and A0 decrease in sequence, but the embodiments of the present disclosure are not limited thereto.

[0158] Reference Figures 13 to 15 , according to the manufacturing sequence of each layer of the display panel, it can be known that in the direction perpendicular to the substrate, the stopper BK is located between the second conductive structure CDT2 (the first pole T21 of the data writing transistor T2) and the third data line DT3.

[0159] As Figure 15 shown, the orthographic projection of the stopper BK on the substrate partially overlaps with the orthographic projection of the third data line DT3 on the substrate, so that the stopper BK shields the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoids display abnormalities caused by coupling. Reference Figure 15 and Figure 6 , the orthographic projection of the first part BKa of the stopper BK on the substrate partially overlaps with the orthographic projection of the third data line DT3 on the substrate, so that the first part BKa of the stopper BK shields the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoids display abnormalities caused by coupling.

[0160] As Figure 15 shown, in the plan view, one stopper BK corresponds to two pixel units in the same row. As Figure 15 shown, in the plan view, the stopper BK is located between the first data line DT1 and the second data line DT2.

[0161] As Figure 5 , Figure 7 and Figure 15 shown, the orthographic projection of the first pole T21 of the data writing transistor T2 on the substrate at least partially overlaps with the orthographic projection of the third data line DT3 on the substrate.

[0162] Reference Figures 14 to 16B, the stopper BK extends leftward into the first pixel unit 101a adjacent to the second pixel unit 101b, so that the stopper BK has a portion located between the first data line DT1 and the third data line DT3 to shield the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoid display anomalies caused by coupling. The first data line DT1 and the third data line DT3 are two adjacent data lines.

[0163] For example, in the embodiments of the present disclosure, two adjacent elements C mean that the two elements C are adjacent to each other and no element C is provided therebetween, but it does not exclude that other elements other than the element C are also provided between the two adjacent elements C.

[0164] For example, the 120Hz driving scheme adopts a time-division writing method, that is, the data signal is first stored in the storage capacitor, and then the scanning signal is turned on and written into the pixel unit. The interference between the data signals will affect the accurate writing of the data signals and the display effect; the design that the stopper BK extends leftward to play a shielding role can well improve this problem.

[0165] In the conventional technology, the gate T10 of the driving transistor T1 is in a floating state during the light-emitting stage and is held by the storage capacitor Cst. Due to the existence of the parasitic capacitance between the gate and the data line, the data signal jump will be coupled to the gate signal part (the first node N1) of the driving transistor and cannot be restored to the initial state, thus resulting in vertical crosstalk.

[0166] Reference Figures 14 to 16B , the stopper BK extends rightward and overlaps with the first conductive structure CDT1 (the second pole T62 of the first reset transistor T6) of the first pixel unit 101a, covering the signal on the gate T10 of the driving transistor T1 of the first pixel unit 101a, shielding the parasitic capacitance between the gate T10 (the gate signal part PT1 of the driving transistor) of the driving transistor T1 and the data line, reducing the coupling effect, and alleviating the vertical crosstalk.

[0167] In another embodiment, the length of the connection electrode CEf in the second direction Y in the display panel is adjusted, as Figure 16A and Figure 16B shown, the length of the connection electrode CEf in the second direction Y is increased. Figure 16A and Figure 16B The connection electrode CEf shown can be called a shielding part CEs. The shielding part CEs and the connection electrode CEd (the second connection electrode CEd) form a connection element CE0. The shielding part CEs can replace the connection electrode CEf without additional process manufacturing.

[0168] Reference Figure 10 and Figure 11, the other end of the connection electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole Ca of the storage capacitor Cst) through the via H21, and one end of the connection electrode CEb is electrically connected to the second pole T62 of the first reset transistor T6 through the via H22. The connection electrode CEb can also be referred to as the connection line CL. As Figure 11 shown, the gate T10 of the driving transistor T1 is connected to the second pole T32 of the threshold compensation transistor T3 through the connection line CL.

[0169] For example, referring to Figure 10 and Figure 11 , the first conductive structure CDT1 is connected to the gate T10 of the driving transistor T1 through the connection line CL. In other words, the gate T10 of the driving transistor T1 is connected to the first conductive structure CDT1 through the connection line CL. For example, the material of the first conductive structure CDT1 is different from the material of the connection line CL. For example, the material of the connection line CL includes metal.

[0170] For example, as Figure 11 and Figure 18 shown, the connection line CL is in contact with the gate T10 of the driving transistor T1. For example, as Figure 11 and Figure 18 shown, the connection line CL is in contact with the first conductive structure CDT1. That is, both ends of the connection line CL are in contact with the gate T10 of the driving transistor T1 and the first conductive structure CDT1 respectively.

[0171] For example, as Figure 11 shown, the first conductive structure CDT1, the connection line CL, and the gate T10 of the driving transistor T1 constitute the gate signal part PT1 of the driving transistor T1. Thus, the overlap of the stopper BK with the first conductive structure CDT1 can shield the parasitic capacitance between the gate signal part of the driving transistor and the data line, reducing the vertical crosstalk. For example, for example, the first conductive structure CDT1, the connection line CL, and the gate T10 of the driving transistor T1 constitute the same node. For example, the potentials on the first conductive structure CDT1, the connection line CL, and the gate T10 of the driving transistor T1 are the same or substantially the same. That is, the potentials at various positions on the gate signal part PT1 are the same or substantially the same.

[0172] Referring to Figure 16A , Figure 16B and Figure 17 , the shielding part CEs extends along the second direction Y. For example, the extending direction of the shielding part CEs is the same as the extending direction of the data line DT. As Figure 20 shown, the light-emitting element 20 is connected to the pixel circuit 10 through the connection element CE0. In the embodiments of the present disclosure, the extending manner of a component refers to the general trend or direction of the component, and not necessarily all positions of the component extend along the extending direction.

[0173] Reference Figure 16A 、 Figure 16B and Figure 17 , the data line DT and the shielding portion CEs are located on the same layer, and both the data line DT and the shielding portion CEs are located in the fourth conductive pattern layer LY4. The data line DT includes two adjacent data lines DT, the shielding portion CEs is located between the two adjacent data lines DT, and the orthographic projection of the shielding portion CEs on the substrate BS at least partially overlaps with the orthographic projection of the connection line CL on the substrate BS. For example, the two adjacent data lines DT are arranged along the first direction X, and the data line DT extends along the second direction. Reference Figure 16A 、 Figure 16B and Figure 17 , the data line DT includes a first data line DT1 and a third data line DT3, the first data line DT1 and the third data line DT3 are adjacent, and in the first direction X, the shielding portion CEs is located between the first data line DT1 and the third data line DT3. In the embodiments of the present disclosure, that component A and component B are adjacent means that there is no component A and no component B between component A and component B. The shielding portion CEs extends along the second direction and is interposed between two adjacent data lines DT. At positions where the adjacent data lines are relatively close, the shielding effect is more obvious. The embodiments of the present disclosure are described by taking the data line DT and the shielding portion CEs being located on the same layer as an example. In other embodiments, the data line DT and the shielding portion CEs may be located on the same layer or on different layers.

[0174] In the embodiments of the present disclosure, the orthographic projection of the shielding portion CEs on the substrate BS at least partially overlaps with the orthographic projection of the connection line CL on the substrate BS, so that the shielding portion CEs shields the parasitic capacitance between the gate signal portion of the driving transistor and the data line, reducing the longitudinal crosstalk problem.

[0175] For example, a 120Hz driving scheme uses a time-division writing method, that is, the data signal is first stored in the storage capacitor, and then the scanning signal is turned on and written into the pixel unit. The interference between the data signals will affect the accurate writing of the data signals and the display effect. In the embodiments of the present disclosure, the shielding portion CEs is located between two adjacent data lines DT, and the orthographic projection of the connection line CL on the substrate BS at least partially overlaps with the orthographic projection of the shielding portion CEs on the substrate BS, which can well reduce the coupling effect and improve this problem. It should be noted that the shielding portion CEs being located between two adjacent data lines DT describes the setting position of the shielding portion CEs. The shielding portion CEs is located between two adjacent data lines DT, but there is not necessarily a shielding portion CEs between every two adjacent data lines DT. As Figure 16A and Figure 17As shown, the first data line DT1 and the third data line DT3 are adjacent, and the shielding portion CEs is located between the first data line DT1 and the third data line DT3. The fourth data line DT4 and the second data line DT2 are adjacent, and the shielding portion CEs is located between the fourth data line DT4 and the second data line DT2. Although the third data line DT3 and the fourth data line DT4 are adjacent, no shielding portion CEs is provided therebetween.

[0176] For example, as Figure 17 shown, in order to minimize the longitudinal crosstalk, the orthographic projection of the shielding portion CEs on the substrate BS is larger than the orthographic projection of the connection line CL on the substrate BS. For example, the orthographic projection of the shielding portion CEs on the substrate BS covers the orthographic projection of the connection line CL on the substrate BS. For example, in the plan view, the shielding portion CEs covers the connection line CL. As Figure 17 and Figure 18 shown, the main surface of the substrate BS is the surface for fabricating each component, and each component is provided on the main surface of the substrate BS.

[0177] For example, in order to greatly reduce the longitudinal crosstalk, the orthographic projection of the gate T10 of the driving transistor T1 on the substrate BS partially overlaps with the orthographic projection of the shielding portion CEs on the substrate BS, and the area of the overlapping portion between the shielding portion CEs and the gate T10 of the driving transistor T1 is smaller than the area of the gate T10 of the driving transistor T1.

[0178] For example, as Figure 17 shown, the dimension of the gate T10 of the driving transistor T1 in the first direction X is larger than the dimension of the shielding portion CEs in the first direction X; the dimension of the shielding portion CEs in the second direction Y is larger than the dimension of the gate of the driving transistor T1 in the second direction Y.

[0179] For example, as Figure 17 shown, the gate T10 of the driving transistor T1 extends beyond the shielding portion CEs from both sides in the first direction X.

[0180] For example, as Figure 17 shown, the orthographic projection of the shielding portion CEs on the substrate BS overlaps with the orthographic projection of the gate line GT on the substrate BS.

[0181] For example, as Figure 17 shown, the orthographic projection of the gate line GT on the substrate BS partially overlaps with the orthographic projection of the shielding portion CEs on the substrate BS.

[0182] For example, the pixel unit includes two adjacent pixel units located in the same column, and two adjacent data lines DT are respectively connected to the two pixel units. Figure 16AShows the positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d. Figure 16A Shows the first data line DT1, the second data line DT2, the third data line DT3, and the fourth data line DT4. Refer to Figure 16A and Figure 17 , the first data line DT1 is connected to the first pixel unit 101a, the second data line DT2 is connected to the second pixel unit 101b, the third data line DT3 is connected to the third pixel unit 101c, and the fourth data line DT4 is connected to the fourth pixel unit 101d. The first data line DT1 is configured to provide a first data signal to the pixel circuit of the first pixel unit 101a. The second data line DT2 is configured to provide a second data signal to the pixel circuit of the second pixel unit 101b. The third data line DT3 is configured to provide a fourth data signal to the pixel circuit of the third pixel unit 101c. The fourth data line DT4 is configured to provide a fourth data signal to the pixel circuit of the fourth pixel unit 101d.

[0183] For example, referring to Figure 15 , the orthographic projection of the stopper BK on the substrate overlaps with the orthographic projection of the fourth data line DT4 on the substrate.

[0184] For example, referring to Figure 6 , Figure 9 , Figure 11 and Figure 15 , taking the stopper BK located in the first pixel unit 101a and the second pixel unit 101b as an example, the stopper BK has a first edge E1, the first edge E1 overlaps with the fourth data line DT4, and the included angle θ1 between the first edge E1 and the fourth data line DT4 is greater than zero and less than 90°. Or rather, the included angle θ1 between the first edge E1 and the extending direction of the fourth data line DT4 is greater than zero and less than 90°. The extending direction of the fourth data line DT4 is the second direction Y. In other words, the first edge E1 is inclined with respect to the fourth data line DT4. This setting method is beneficial to reducing the overlapping area between the fourth data line DT4 and the stopper BK, reducing the parasitic capacitance, and avoiding affecting the data writing speed of the fourth pixel unit.

[0185] For example, referring to Figure 6 , Figure 9 , Figure 11 and Figure 15, taking the stopper BK located in the first pixel unit 101a and the second pixel unit 101b as an example, the stopper BK has a second edge E2, the second edge E2 overlaps with the third data line DT3, and the included angle θ2 between the second edge E2 and the third data line DT3 is greater than zero and less than 90°. Or rather, the included angle θ2 between the second edge E2 and the extending direction of the third data line DT3 is greater than zero and less than 90°. The extending direction of the third data line DT3 is the second direction Y. In other words, the second edge E2 is inclined with respect to the third data line DT3. This setting method is beneficial to reducing the overlapping area between the third data line DT3 and the stopper BK, reducing the parasitic capacitance, and avoiding affecting the data writing speed of the third pixel unit.

[0186] Reference Figure 14 、 Figure 16A and Figure 21 , the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d form a repeating unit RP. Multiple repeating units RP can form an array. The repeating unit RP is the smallest repeating unit of the display array.

[0187] In Figure 21 , in the same pixel unit, the first reset transistor T6 and the second reset transistor T7 are connected to the same reset control signal line RT to be input with the same reset control signal at the same time, but the embodiments of the present disclosure are not limited thereto.

[0188] In other embodiments, as Figure 1 shown, in the same pixel unit, the first reset transistor T6 and the second reset transistor T7 can also be respectively connected to the first reset control signal line and the second reset control signal line, and the first reset control signal line and the second reset control signal line are insulated from each other to be respectively input with signals. In this case, the first reset transistor T6 and the second reset transistor T7 are input with signals at different times. As described above, the first reset transistor T6 is input with the reset control signal RESET in the first reset stage t1, and the second reset transistor T7 is input with the scan signal SCAN in the data writing, threshold compensation, and second reset stage t2. For example, the gate line GT of this stage is connected to the reset control signal line of the next stage. For example, the gate line GT and the second reset control signal line RT2 can be electrically connected to input the same signal at the same time.

[0189] For example, as Figure 17 shown, the second pole T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 through the connection line CL. As described above, the second pole T62 of the first reset transistor T6 and the second pole T32 of the threshold compensation transistor T3 are integrally formed, so that the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0190] For example, as Figure 17 shown, the positive projection of the shielding portion CEs on the substrate BS at least partially overlaps with the positive projection of the second pole T62 of the first reset transistor T6 on the substrate BS. Similarly, since the second pole T62 of the first reset transistor T6 and the second pole T32 of the threshold compensation transistor T3 are integrally formed, the positive projection of the shielding portion CEs on the substrate BS at least partially overlaps with the positive projection of the second pole T32 of the threshold compensation transistor T3 on the substrate BS.

[0191] For example, as Figure 17 shown, the positive projection of the shielding portion CEs on the substrate BS does not overlap with the positive projection of the stopper BK on the substrate BS, so that the upper end position of the shielding portion CEs in the second direction Y is defined.

[0192] For example, referring to Figure 9 and Figure 17 , the first initialization signal line INT1 and the second initialization signal line INT2 are respectively arranged on opposite sides of the gate T10 of the driving transistor T1, and the positive projection of the shielding portion CEs on the substrate BS at least partially overlaps with the positive projection of the second initialization signal line INT2 on the substrate BS.

[0193] Furthermore, for example, the positive projection of the shielding portion CEs on the substrate BS at least partially overlaps with the positive projection of the second conductive connection portion CP2 of the pixel unit in the next row on the substrate BS, so that a capacitor is formed between the second conductive connection portion CP2 and the shielding portion CEs. This capacitor serves as a stabilizing capacitor and functions to reduce the leakage current of the first reset transistor T6.

[0194] For example, referring to Figure 15 and Figure 17 , the positive projection of the shielding portion CEs and the first initialization signal line INT1 on the substrate BS do not overlap.

[0195] For example, referring to Figure 15 , the first reset control signal line RT1 and the second reset control signal line RT2 are respectively arranged on opposite sides of the gate T10 of the driving transistor T1. Referring to Figure 17 , the positive projection of the second reset control signal line RT2 on the substrate BS and the positive projection of the shielding portion CEs on the substrate BS do not overlap. Thus, the lower end position of the shielding portion CEs in the second direction Y is defined.

[0196] For example, referring to Figure 15 and Figure 17, the orthographic projection of the first reset control signal line RT1 on the substrate BS and the orthographic projection of the shielding portion CEs on the substrate BS do not overlap.

[0197] For example, referring to Figure 15 , the first reset control signal line extends along the first direction X, and the second reset control signal line extends along the first direction X.

[0198] In Figure 14 , each connection electrode CEf is connected to a light-emitting element, that is, each connection electrode CEf corresponds to a pixel unit 101. In Figure 16A , each shielding portion CEs is connected to a light-emitting element, that is, each shielding portion CEs corresponds to a pixel unit 101.

[0199] For example, referring to Figure 5 , the orthographic projections of the first gate T601 and the second gate T602 of the first reset transistor T6 on the substrate BS overlap with the orthographic projections of the first channel T631 and the second channel T632 of the first reset transistor T6 on the substrate BS, respectively.

[0200] For example, as Figure 11 and Figure 13 shown, the first power supply line VDD1 is connected to the second pole Cb of the storage capacitor Cst through the power supply connection line VDD0.

[0201] In the conventional technology, the threshold compensation transistor T3 is a double-gate transistor. The intermediate node (the first conductive connection portion CP1) of the threshold compensation transistor T3 is disturbed by the jump of the scan signal. The voltage increases at the moment when the scan signal is turned off, and the leakage to the gate of the driving transistor T1 is aggravated, which will cause the Flicker problem.

[0202] For example, referring to Figure 13 and Figure 15 , in order to reduce the leakage of the threshold compensation transistor T3, the orthographic projection of the stopper BK on the substrate BS and the orthographic projection of the first conductive connection portion CP1 on the substrate BS overlap at least partially. A stable capacitor is formed between the stopper BK and the first conductive connection portion CP1. Increasing the parasitic capacitance between the intermediate node of the threshold compensation transistor T3 and the first voltage signal ELVDD can reduce the disturbance amount and improve the leakage problem.

[0203] A pixel circuit is formed on the substrate, and a display panel as shown in Figure 15 or Figure 17 is formed. On the basis of the display panel shown in Figure 15 or Figure 17 , a light-emitting element is further formed to obtain a display panel that can perform display. Thus, the pixel circuit is closer to the substrate than the light-emitting element. As Figure 20As shown, the pixel circuit 10 is closer to the substrate BS than the light-emitting element 20.

[0204] For example, Figure 18 is Figure 17 a cross-sectional view along line AB in. Figure 19 The first electrode 201 of the light-emitting element 20 is shown. Figure 17 This is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Figure 19 The film layer above the first electrode 201 of the light-emitting element is omitted in. The layers above the first electrode 201 of the light-emitting element 20 can be referred to the cross-sectional view. Of course, the setting position and shape of the first electrode 201 of the light-emitting element are not limited to Figure 19 As shown, those skilled in the art can adjust the setting position and shape of the first electrode 201 of the light-emitting element as needed.

[0205] Referring to Figure 18 and Figure 20 , the buffer layer BL is located on the substrate BS, the isolation layer BR is located on the buffer layer BL, the channel region, source and drain of the transistor are located on the isolation layer BR, a first gate insulating layer GI1 is formed on the channel region, source and drain of the transistor, a first conductive pattern layer LY1 is located on the first gate insulating layer GI1, a second gate insulating layer GI2 is located on the first conductive pattern layer LY1, a second conductive pattern layer LY2 is located on the second gate insulating layer GI2, an interlayer insulating layer ILD is located on the second conductive pattern layer LY2, a third conductive pattern layer LY3 is located on the interlayer insulating layer ILD, a passivation layer PVX is located on the first conductive pattern layer LY, a first planarization layer PLN1 is located on the passivation layer PVX, and a fourth conductive pattern layer LY4 is located on the first planarization layer PLN1.

[0206] Referring to Figure 20 , a second planarization layer PLN2 is located on the fourth conductive pattern layer LY4, the first electrode 201 of the light-emitting element 20 is located on the second planarization layer PLN2, the pixel definition layer PDL and the spacer PS are located on the second planarization layer PLN2, the pixel definition layer PDL has an opening OPN, and the opening OPN is configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit. The spacer PS is configured to support the fine metal mask when forming the light-emitting functional layer 203.

[0207] For example, the opening OPN is the light-emitting area of the pixel unit. The light-emitting functional layer 203 is located above the first electrode 201 of the light-emitting element 20, the second electrode 202 of the light-emitting element 20 is located on the light-emitting functional layer 203, and a packaging layer CPS is provided on the light-emitting element 20. The packaging layer CPS includes a first packaging layer CPS1, a second packaging layer CPS2, and a third packaging layer CPS3. For example, the first packaging layer CPS1 and the third packaging layer CPS3 are inorganic material layers, and the second packaging layer CPS2 is an organic material layer. For example, the first electrode 201 is the anode of the light-emitting element 20, and the second electrode 202 is the cathode of the light-emitting element 20, but it is not limited thereto.

[0208] As Figure 19 and Figure 20 shown, the first electrode 201 of the light-emitting element 20 is connected to the shielding portion CEs (connection electrode CEf) through a via hole H9 penetrating the second planarization layer PLN2.

[0209] For example, the light-emitting element 20 includes an organic light-emitting diode. The light-emitting functional layer 203 is located between the second electrode 202 and the first electrode 201. The second electrode 202 is located on the side of the first electrode 201 away from the substrate BS, and the light-emitting functional layer 203 includes at least a light-emitting layer, and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0210] As Figure 6 and Figure 18 shown, the second electrode Cb of the storage capacitor has an opening OPN1, and the setting of the opening OPN1 facilitates the connection of the connection electrode CEb to the gate T10 of the driving transistor T1.

[0211] For example, the transistors in the pixel circuit of the embodiments of the present disclosure are all thin-film transistors. For example, the first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, and the fourth conductive pattern layer LY4 are all made of metal materials. For example, the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto. For example, the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are formed of materials such as titanium and aluminum, but are not limited thereto. For example, the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are respectively structures formed by three sub-layers of Ti / AL / Ti, but are not limited thereto. For example, the substrate can be a glass substrate or a polyimide substrate, but is not limited thereto and can be selected according to needs. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, and the spacer PS are all made of insulating materials. The materials of the first electrode 201 and the second electrode 202 of the light-emitting element can be selected according to needs. In some embodiments, the first electrode 201 can be at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode 201 can have a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode 202 can be a metal with a low work function and can be at least one of magnesium and silver, but is not limited thereto.

[0212] In the display panel provided by the embodiments of the present disclosure, the stopper BK having the structure shown in Figure 6 may not be provided. Of course, the shielding portion CEs shown in Figure 16A may also not be provided. For example, in some embodiments, the stopper BK is not provided, or a stopper having other shapes or structures is provided. For example, in some embodiments, the shielding portion CEs is not provided, but a connecting electrode CEf shown in Figure 14 is provided.

[0213] The display panel provided by the embodiments of the present disclosure can be fabricated according to the structure of the display panel. The following lists a feasible fabrication method. It should be noted that the fabrication method of the display panel provided by the embodiments of the present disclosure is not limited to the following method.

[0214] The fabrication method will be described with reference to the previous drawings. The fabrication method of the display panel provided by the embodiments of the present disclosure includes the following steps.

[0215] Step S1: Form a buffer layer BL on the substrate.

[0216] Step S2: Form an isolation layer BR on the buffer layer BL.

[0217] Step S3: Form a semiconductor pattern SCP on the isolation layer BR.

[0218] Step S4: Form a first gate insulating layer GI1 on the semiconductor pattern SCP.

[0219] Step S5: Form a first conductive thin film on the first gate insulating layer GI1, and pattern the first conductive thin film to form a first conductive pattern layer LY1.

[0220] Step S6: Use the first conductive pattern layer LY1 as a mask to dope the semiconductor pattern SCP to form the active layer ACT, source electrode, and drain electrode of the transistor.

[0221] Step S7: Form a second gate insulating layer GI2.

[0222] Step S8: Form a second conductive thin film on the second gate insulating layer GI2, and pattern the second conductive thin film to form a second conductive pattern layer LY2.

[0223] Step S9: Form an interlayer insulating layer ILD on the second conductive pattern layer LY2.

[0224] Step S10: Form vias in at least one of the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD (refer to Figure 8 ).

[0225] Step S11: Form a third conductive thin film on the interlayer insulating layer ILD, and pattern the third conductive thin film to form a third conductive pattern layer LY3. The components in the third conductive pattern layer LY3 are respectively connected to the components in the second conductive pattern layer LY2 and the source electrode and drain electrode of the transistor through vias.

[0226] Step S12: Form a passivation layer PVX and a first planarization layer PLN1.

[0227] Step S13: Form vias in the passivation layer PVX and the first planarization layer PLN1 (refer to Figure 12 ).

[0228] Step S14: Form a fourth conductive thin film on the first planarization layer PLN1, and pattern the fourth conductive thin film to form a fourth conductive pattern layer LY4. The components in the fourth conductive pattern layer LY4 can be connected to the components in the third conductive pattern layer LY3 through the vias in the passivation layer PVX and the first planarization layer PLN1.

[0229] Step S15: Form a first electrode 201 of the light-emitting element 20 on the fourth conductive pattern layer LY4.

[0230] Step S16: Form a pixel definition layer PDL and spacers PS.

[0231] Step S17: Form the light-emitting functional layer 203 of the light-emitting element 20.

[0232] Step S18: Form the second electrode 202 of the light-emitting element 20.

[0233] Step S19: Form the encapsulation layer CPS.

[0234] At least one embodiment of the present disclosure further provides a display device, including any one of the above display panels. For example, the display device includes an OLED or a product with high frame rate driving including an OLED. For example, the display device includes any product or component with a display function such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc. containing the above display panel.

[0235] The above takes the pixel circuit of 7T1C as an example for illustration, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, and the embodiments of the present disclosure do not limit this.

[0236] In the embodiments of the present disclosure, elements located in the same layer may be formed by the same film layer through the same patterning process. For example, elements located in the same layer may be located on the surface of the same element away from the substrate.

[0237] It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is enlarged. It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, the element may be "directly" on or under the other element, or there may be intermediate elements.

[0238] In the embodiments of the present disclosure, the patterning or patterning process may only include a lithography process, or include a lithography process and an etching step, or may include other processes for forming a predetermined pattern such as printing and inkjet. The lithography process refers to a process including film formation, exposure, development, etc., and uses photoresist, a mask, an exposure machine, etc. to form a pattern. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0239] Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0240] As described above, this is only a specific embodiment of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: a substrate substrate; a pixel unit located on the substrate substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit being closer to the substrate substrate than the light-emitting element, and the pixel circuit including a driving transistor; a data line configured to provide a data signal to the pixel circuit; a connection element, the light-emitting element being connected to the pixel circuit through the connection element, the connection element including a shielding portion; and a connection line connected to the gate of the driving transistor, wherein the data line includes two adjacent data lines, the shielding portion is located between the two adjacent data lines, and at least a part of the orthographic projection of the connection line on the substrate substrate overlaps with the orthographic projection of the shielding portion on the substrate substrate.

2. The display panel according to claim 1, wherein, The orthographic projection of the shielding portion on the substrate substrate is larger than the orthographic projection of the connection line on the substrate substrate.

3. The display panel according to claim 1, wherein, The orthographic projection of the gate of the driving transistor on the substrate substrate partially overlaps with the orthographic projection of the shielding portion on the substrate substrate, and the area of the overlapping portion of the shielding portion and the gate of the driving transistor is smaller than the area of the gate of the driving transistor.

4. The display panel according to claim 1, wherein, The two adjacent data lines are arranged along a first direction, and the data line extends along a second direction.

5. The display panel according to claim 4, wherein, The dimension of the gate of the driving transistor in the first direction is larger than the dimension of the shielding portion in the first direction; The dimension of the shielding portion in the second direction is larger than the dimension of the gate of the driving transistor in the second direction.

6. The display panel according to any one of claims 1-5, wherein, The connection line is in contact with the gate of the driving transistor.

7. The display panel according to any one of claims 1-5, wherein, The data line and the shielding portion are located in the same layer, and the extending direction of the shielding portion is the same as the extending direction of the data line.

8. The display panel according to any one of claims 1-5 further includes a first conductive structure, wherein, The connection line is connected to the first conductive structure, and at least a part of the orthographic projection of the shielding portion on the substrate substrate overlaps with the orthographic projection of the first conductive structure on the substrate substrate.

9. The display panel according to claim 8, wherein, The pixel circuit further includes a first reset transistor, a second pole of the first reset transistor is connected to the gate of the driving transistor, and the first conductive structure is multiplexed as the second pole of the first reset transistor.

10. The display panel according to claim 9 further includes a first reset control signal line and a first initialization signal line, wherein, The gate of the first reset transistor is connected to the first reset control signal line, and the first pole of the first reset transistor is connected to the first initialization signal line.

11. The display panel according to claim 9 or 10, wherein, The first reset transistor includes a first channel and a second channel, the first channel and the second channel of the first reset transistor are connected through a conductive connection portion, and the orthographic projection of the shielding portion on the substrate substrate partially overlaps with the orthographic projection of the conductive connection portion of the first reset transistor on the substrate substrate.

12. The display panel according to claim 10 further includes a second initialization signal line, wherein, The first initialization signal line and the second initialization signal line are respectively arranged on opposite sides of the gate of the driving transistor, and the orthographic projection of the shielding portion on the substrate substrate partially overlaps with the orthographic projection of the second initialization signal line on the substrate substrate.

13. The display panel according to claim 8 further includes a first power line and a stopper, wherein, The first power supply line is configured to supply a first power supply voltage to the pixel circuit. The stopper is electrically connected to the first power supply line. The positive projection of the first conductive structure on the substrate at least partially overlaps with the positive projection of the stopper on the substrate.

14. The display panel according to claim 13 further includes a second conductive structure, wherein, The data line is connected to the second conductive structure. The positive projection of the stopper on the substrate at least partially overlaps with the positive projection of the second conductive structure on the substrate.

15. The display panel according to claim 13, further comprising a gate line, wherein the gate line intersects with the data line and is insulated from each other, and the gate line is configured to supply a scan signal to the pixel circuit. The pixel circuit further includes a threshold compensation transistor. A first pole of the threshold compensation transistor is connected to a second pole of the driving transistor. A second pole of the threshold compensation transistor is connected to a gate of the driving transistor. The gate of the threshold compensation transistor is connected to the gate line. The gate of the driving transistor is connected to the second pole of the threshold compensation transistor through the connection line. The threshold compensation transistor includes a first channel and a second channel, and the first channel and the second channel are connected by a conductive connection portion. The positive projection of the stopper on the substrate at least partially overlaps with the positive projection of the conductive connection portion of the threshold compensation transistor on the substrate.

16. The display panel according to claim 15, wherein, The area of the positive projection on the substrate of the portion of the stopper overlapping with the first conductive structure is larger than the area of the positive projection on the substrate of the portion of the stopper overlapping with the conductive connection portion of the threshold compensation transistor.

17. The display panel according to claim 13, wherein, The material of the first conductive structure is different from the material of the connection line.

18. The display panel according to any one of claims 1-5, wherein, The pixel unit includes two adjacent pixel units in the same column, and two adjacent data lines are respectively connected to the two pixel units.

19. The display panel according to claim 12 further includes a second reset control signal line, wherein, The pixel circuit further includes a second reset transistor. The gate of the second reset transistor is connected to the second reset control signal line. A first pole of the second reset transistor is connected to the second initialization signal line. A second pole of the second reset transistor is connected to a first pole of the light-emitting element.

20. The display panel according to claim 15, wherein, The pixel circuit further includes a first power supply terminal and a storage capacitor. A first pole of the storage capacitor is connected to the gate of the driving transistor, and a second pole of the storage capacitor is connected to the first power supply terminal.

21. The display panel according to claim 20, wherein, The pixel circuit further includes a data writing transistor. The gate of the data writing transistor is connected to the gate line. A first pole of the data writing transistor is connected to the data line. A second pole of the data writing transistor is connected to a first pole of the driving transistor.

22. The display panel according to claim 20 further includes a light emission control signal line, wherein, The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The gate of the first light-emitting control transistor is connected to the light-emitting control signal line. A first pole of the first light-emitting control transistor is connected to the first power supply terminal. A second pole of the first light-emitting control transistor is connected to a first pole of the driving transistor. The gate of the second light-emitting control transistor is connected to the light-emitting control signal line, the first pole of the second light-emitting control transistor is connected to the second pole of the driving transistor, and the second pole of the second light-emitting control transistor is connected to the first pole of the light-emitting element.

23. The display panel according to claim 22, wherein, The data line has a first portion and a second portion, the distance between the first portions of two adjacent data lines is greater than the distance between the second portions of the two adjacent data lines, and the shielding portion is located between the second portions of the two adjacent data lines.

24. The display panel according to claim 23, wherein, The second portions of the two adjacent data lines are respectively close to the first light-emitting control transistor and the second light-emitting control transistor, and the storage capacitor is located between the first portions of the two adjacent data lines.

25. The display panel according to any one of claims 1-5, wherein, The connection element further includes a connection electrode, the connection electrode is connected to the pixel circuit, and the light-emitting element is connected to the connection electrode through the shielding portion.

26. The display panel according to any one of claims 1-5, wherein, The pixel circuit further includes a first power supply terminal and a storage capacitor. The first pole of the storage capacitor is connected to the gate of the driving transistor, and the second pole of the storage capacitor is connected to the first power supply terminal.

27. The display panel according to claim 26, further comprising a gate line, wherein the gate line intersects with the data line and is insulated from each other, the gate line is configured to provide a scanning signal to the pixel circuit, the pixel circuit further includes a data writing transistor, the gate of the data writing transistor is connected to the gate line, the first pole of the data writing transistor is connected to the data line, and the second pole of the data writing transistor is connected to the first pole of the driving transistor.

28. The display panel according to claim 26 further includes a light emission control signal line, wherein, The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The gate of the first light-emitting control transistor is connected to the light-emitting control signal line, the first pole of the first light-emitting control transistor is connected to the first power supply terminal, and the second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor; The gate of the second light-emitting control transistor is connected to the light-emitting control signal line, the first pole of the second light-emitting control transistor is connected to the second pole of the driving transistor, and the second pole of the second light-emitting control transistor is connected to the first pole of the light-emitting element.

29. The display panel according to claim 28, wherein, The data line has a first portion and a second portion, the distance between the first portions of two adjacent data lines is greater than the distance between the second portions of the two adjacent data lines, and the shielding portion is located between the second portions of the two adjacent data lines.

30. The display panel according to claim 29, wherein, The second portions of the two adjacent data lines are respectively close to the first light-emitting control transistor and the second light-emitting control transistor, and the storage capacitor is located between the first portions of the two adjacent data lines.

31. A display device, comprising the display panel according to any one of claims 1-30.

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