Switchable channel direction between host system and memory system

Abstract

This application relates to switchable lane directions between a host system and a memory system. A host system can communicate with a memory system using a set of lanes, where each lane can send information (e.g., commands, operations, data) in a particular direction. In some cases, the host system and memory system can support one or more switchable lanes, where both systems include transmit and receive modules for the lanes. The host system and the memory system can switch the direction configured for a lane according to bandwidth conditions associated with a particular direction meeting a threshold for reconfiguring the lane. Switching the lane direction can increase the supported bandwidth in a particular direction, e.g., from the host system to the memory system (e.g., in a "write-optimized" configuration) or from the memory system to the host system (e.g., in a "read-optimized" configuration).

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 240,927, filed April 26, 2021, entitled “Switchedable Lane Directions Between a Host System and a Memory System,” which is assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to switchable channel directions between host systems and memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods, even without external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory system including a controller configured such that the apparatus: communicates with a host system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system; determines, at least in part, based on one or both of a first bandwidth supported by the set of channels for the first direction or a second bandwidth supported by the set of channels for the second direction, whether a bandwidth condition associated with one or both of the first direction or the second direction satisfies a threshold for reconfiguring channels in the set of channels; and switches the direction configured for the channels, at least in part based on determining that the bandwidth condition associated with one or both of the first direction or the second direction satisfies the threshold.

[0007] Describe another device. The device may include: a host system including a controller configured to couple with a memory system, wherein the controller is configured such that the device: communicates with the memory system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system; receives from the memory system an indication of a request to reconfigure the set of channels to support additional bandwidth in the first direction or the second direction; and switches the direction of channel configuration in the set of channels based at least in part on the request to reconfigure the set of channels to support the additional bandwidth in the first direction or the second direction.

[0008] Describe another device. The device may include: a memory system including a memory system controller; and a link including a first channel between the memory system controller and a host system controller, wherein the first channel is configurable to send information to the host system controller at least in part based on activating a transmission module at the memory system controller and is configurable to receive information from the host system controller at least in part based on activating a receiving module at the memory system controller. Attached Figure Description

[0009] Figure 1 and 2 This document describes an example of a system that supports switchable channel direction between the host system and the memory system, based on the examples disclosed herein.

[0010] Figure 3A , 3BAnd 3C specification examples of channel configuration supporting switchable channel direction between host system and memory system based on the examples disclosed herein.

[0011] Figure 4 This document describes an example of a process flow that supports switchable channel directions between the host system and the memory system, based on the examples disclosed herein.

[0012] Figure 5 A block diagram illustrating a memory system that supports switchable channel direction between the host system and the memory system, based on the examples disclosed herein.

[0013] Figure 6 A block diagram illustrating a host system that supports switchable channel direction between the host system and the memory system, based on the examples disclosed herein.

[0014] Figure 7 and 8 The flowchart illustrates one or more methods for supporting switchable channel directions between a host system and a memory system, based on the examples disclosed herein. Detailed Implementation

[0015] A host system can use a set of channels to communicate with a memory system to transmit information. Each channel can be configured to send information in a specific direction. For example, a channel can be configured as a transmit (Tx) to receive (Rx) channel from a first system to a second system (e.g., host system to memory system) or a Tx to Rx channel from the first system to the second system (e.g., memory system to host system). In some cases, the host system and the memory system can be configured with symmetrical channel configurations (e.g., the number of Tx to Rx channels from the memory system is the same as the number of Tx to Rx channels from the host system). However, the communication traffic between the two systems, such as the host system and the memory system, may not be symmetrical between the host system and the memory system. For example, due to the amount of commands, such as read commands or write commands, issued by the host system, the command-based bandwidth in the first direction (e.g., from the host system or from the memory system) may exceed the channel capacity and may be relatively high, while the command-based bandwidth in the second direction may not exceed the channel capacity and may be relatively low (e.g., below a bandwidth threshold). This configuration may inefficiently utilize the capacity supported by the channels and may introduce latency in the first direction. For example, the channel capacity in the first direction may be saturated, causing information to back up for transmission in the first direction, while the amount of information transmitted in the second direction may be less than the channel capacity, leaving one or more channels configured in the second direction idle or underutilized.

[0016] To support improved efficiency in channel usage between the host system and the memory system, the host system and the memory system may use one or more switchable channels. Switchable channels may be switchable based on the signaling direction carried by the channel, making the channel operable as a Tx-to-Rx channel from the host system or a Tx-to-Rx channel from the memory system. Each of the host system and the memory system may include a transmission module and a receiving module for the channel to support the switching capability. The host system, the memory system, or both may determine whether to dynamically switch the direction of the switchable channel in response to specific bandwidth conditions. For example, if the bandwidth condition associated with a first direction (e.g., from the memory system to the host system) meets a threshold (e.g., exceeds a bandwidth threshold), then one or more of the systems may reconfigure the switchable channel to operate as a Tx-to-Rx channel (e.g., from the memory system). Due to the switching, in this example, a set of channels can support additional capacity from the memory system to the host system—thereby improving throughput and alleviating information backlog in the first direction. In some instances, this configuration may be referred to as a "read-optimized" configuration (e.g., increased bandwidth available for reading data from the memory system). Alternatively, if the bandwidth conditions associated with the second direction (e.g., from the host system to the memory system) meet a threshold, the system can reconfigure the switchable channel to operate as a Tx-to-Rx channel (e.g., from the host system), thereby supporting additional throughput and alleviating information backlog in the second direction. In some instances, this configuration may be referred to as a "write-optimized" configuration (e.g., increased bandwidth available for writing data to the memory system).

[0017] Firstly, in reference Figure 1 and 2 The features of this disclosure are described in the context of systems and apparatuses. The features of this disclosure are further described in reference to [reference 1]. Figure 3A , 3B The channel configurations of 3C and 4 are described in the context of the process flow for dynamically switching channel configurations. These and other features of this disclosure are derived from references. Figures 5 to 8 The device diagrams and flowcharts relating to the switchable channel direction between the host system and the memory system are further illustrated and described in the context of the device diagrams and flowcharts.

[0018] Figure 1 This document describes an example of a system 100 that supports switchable channel direction between a host system and a memory system, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110. The host system 105 and the memory system 110 can be coupled using a set of channels 125.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital Storage (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or any other computing device containing memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, host system 105 may use memory system 110 to write data to and read data from memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM slot interfaces supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface of each memory device 130 included in memory system 110 or via a corresponding physical host interface of each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] In some instances, the physical host interface may include one or more links, channels 125, or combinations thereof. Links may support bidirectional communication between host system 105 and memory system 110. Each link may be an interconnection of channels 125 (e.g., a pair of channels 125), and each channel 125 may support unidirectional communication from host system 105 to memory system 110 or from memory system 110 to host system 105. For example, channel 125 may include a transmission module, a receiving module, and a line, which is a point-to-point interconnect between the transmission and receiving modules and is capable of transmitting information (e.g., as a signal). As illustrated, host system 105 and memory system 110 may be coupled using a first link including channels 125-a and 125-b and a second link including channels 125-c and 125-d. In some cases, channel 125 may be an instance of an M-PHY channel (e.g., a physical layer protocol supporting data communication for mobile multimedia devices). Each channel 125 may support bandwidth capacity in a specific direction. As an example, channel 125 can support 20 gigabits per second, which corresponds to 2 gigabits per second (GB / s) of available information (e.g., data) after decoding. Therefore, a host system 105 and a memory system 110 configured with two links (each containing a pair of unidirectional channels 125 in opposite directions) can concurrently support approximately 4 GB / s of data communication in each direction.

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain memory cells of the same or different types.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may generally be referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate said commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, discard item collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic that performs the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be used within local memory 120 for subsequent retrieval of host system 105 or manipulation (e.g., updates) by host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0029] although Figure 1 An example of memory system 110 has been described as including memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, in some cases, one or more functions attributed herein to memory system controller 115 may be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115 or perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As explained, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information per cell, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information per cell, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information per cell, a three-level cell (TLC) when configured to store three bits of information per cell, a four-level cell (QLC) when configured to store four bits of information per cell, or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity to support circuitry.

[0034] In some cases, plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0036] For some NAND architectures, a memory cell can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Therefore, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing page 175 has been erased.

[0037] System 100 may include any number of non-transitory computer-readable media supporting switchable channel directions between host system 105 and memory system 110. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if such instructions are executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), they may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0038] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include one or more memory arrays and associated circuitry, for example, in combination with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] Host system 105 can use one or more of channels 125 to transmit commands, operations, data, or other messages to the memory system. However, in some cases, host system 105 and memory system 110 may inefficiently utilize the bandwidth supported by channels 125. For example, one or more channels 125 may have data transfer capacity that is unused for a portion of the time (e.g., left idle) (e.g., if the bandwidth is not currently in use). Alternatively, if the full capacity of channels 125 in a particular direction is utilized, information may back up (e.g., at host system 105 or memory system 110). For example, if host system 105 performs significantly more write operations than read operations or significantly more read operations than write operations (e.g., greater than a threshold ratio), then channel 125 utilization may be inefficient.

[0040] To effectively utilize the bandwidth supported by channel 125, system 100 may use one or more switchable channels 125. Switchable channels 125 can be configured to switch directions. In some cases, switching the direction of channel 125 can switch the link from supporting bidirectional transmission to supporting unidirectional transmission. Switching the direction of channel 125 (e.g., from a first direction to a second direction) can increase the bandwidth in the second direction. Host system 105, memory system 110, or both may dynamically trigger direction switching for channel 125 in response to one or more factors, such as bandwidth conditions. For example, if the bandwidth from host system 105 to memory system 110 meets a threshold condition (e.g., exceeds a threshold), then host system 105 and memory system 110 may switch channel 125 to support Tx to Rx from host system 105. For example, using... Figure 1 As described in the channel configuration, the set of channels 125 between host system 105 and memory system 110 can support 4 GB / s data communication in each direction. To support additional bandwidth from host system 105 to memory system 110, system 100 can switch the direction of channel 125-c, such that three channels 125 are from host system 105 to memory system 110 and one channel is from memory system 110 to host system 105. Therefore, the set of channels 125 can support 6 GB / s data communication from host system 105 to memory system 110. Alternatively, if the bandwidth from memory system 110 to host system 105 meets a threshold condition (e.g., exceeds a threshold), then host system 105 and memory system 110 can switch channels 125 (e.g., channel 125-d) to support Tx to Rx from memory system 110. By dynamically switching the channel direction in response to bandwidth conditions, the host system 105 and the memory system 110 can effectively utilize the total bandwidth supported by the channel 125, improve throughput in a specific direction in response to specific bandwidth conditions, and reduce information backlog and corresponding latency between the host system 105 and the memory system 110.

[0041] Figure 2 This document describes an example of system 200 that supports switchable channel direction between a host system and a memory system, based on the examples disclosed herein. System 200 may be used as a reference. Figure 1 The described system 100 or an example thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 when requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement reference Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0042] Memory system 210 may include memory device 240 to store data transferred between memory system 210 and host system 205, for example, in response to receiving an access command from host system 205, as described herein. Memory device 240 may include references Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point memory, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0043] Memory system 210 may include memory controller 230 to control the direct delivery of data to and from memory device 240, for example, for storing data, retrieving data, and determining memory locations where data is stored and retrieved. Memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, memory controller 230 may implement a reference... Figure 1 The aspects of the local memory 135 described.

[0044] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to move data between the host system 205 and the memory device 240, for example, as shown by data path 250, and can be collectively referred to as the data path components.

[0045] Using buffer 225 to temporarily store data during transmission allows data to be buffered as commands being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, buffered data can be stored or transmitted (or both). Buffer 225 may include relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow data to be quickly stored in and retrieved from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0046] Temporary storage of data within buffer 225 can refer to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it can be overwritten with data from an additional access command). Additionally, buffer 225 can be a non-cached buffer. That is, data may not be read directly from buffer 225 by the host system 205. For example, a read command can be added to a queue without requiring an address to be matched to an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0047] The memory system 210 may additionally include a memory system controller 215 to execute commands received from the host system 205 and control data path components during data movement. The memory system controller 215 may be a reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0048] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, if more than one access command from host system 205 is processed concurrently by memory system 210. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and memory controller 230, respectively. However, if queues are used, they can be located anywhere within memory system 210.

[0049] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may be transferred via data path component using data path 250 instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path component via bus 235 (e.g., using a memory system 210-specific protocol).

[0050] If host system 205 transmits an access command to memory system 210, the command may be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered the front end of memory system 210. Upon receiving each access command, interface 220 may, for example, pass the command to memory system controller 215 via bus 235. In some cases, each command may be added to command queue 260 via interface 220 to pass the command to memory system controller 215.

[0051] The memory system controller 215 can determine that an access command has been received in response to communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving the command from command queue 260. After, for example, the command is retrieved from command queue 260 by memory system controller 215, the command can be removed from command queue 260. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0052] Once it is determined that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0053] In either case, the memory system controller 215 may use buffer 225 to temporarily store data received from or sent to the host system 205. Buffer 225 can be considered as an intermediate layer of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in buffer 225) may be performed by hardware (e.g., dedicated circuitry) in interface 220, buffer 225, or memory controller 230.

[0054] In order to process a write command received from host system 205, memory system controller 215 may determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the write command, for example via firmware (e.g., controller firmware).

[0055] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 may be moved to buffer queue 265 by memory system controller 215 and may be held in buffer queue 265, while associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating the location in buffer 225 where the data associated with each command is stored may be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205, and at least a portion of the access commands can be processed concurrently.

[0056] If buffer 225 has sufficient space to store the write data, then memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "transfer ready" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). As interface 220 sequentially receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0057] Once written data is stored in buffer 225 via interface 220, the data can be transferred out of buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that data transfer to memory device 240 has been completed.

[0058] In some cases, storage queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands (e.g., via bus 235) from buffer queue 265 to storage queue 270 for processing. Storage queue 270 may contain entries for each access command. In some instances, storage queue 270 may additionally include: a buffer pointer (e.g., an address) indicating the location in buffer 225 where the data associated with the command is stored; and a storage pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, storage controller 230 can obtain the location within buffer 225 from which data is obtained, either from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 can manage the location within memory device 240 to store data (e.g., perform wear leveling, discarded item collection, and the like). Entries may be added to storage queue 270, for example, by memory system controller 215. The entry can be removed from the storage queue 270 after the data transfer is completed, for example by the storage controller 230 or the memory system controller 215.

[0059] In order to process a read command received from host system 205, memory system controller 215 may again determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the read command, for example via firmware (e.g., controller firmware).

[0060] In some cases, buffer queue 265 can be used to assist in buffering data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, then memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235 whether data transfer to buffer 225 has been completed.

[0061] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of the data retrieved from the buffer 225 or the storage queue 270 within the memory device 240. In some cases, the storage controller 230 can obtain the location of the data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of the data stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0062] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0063] The memory system controller 215 can execute received commands in a sequence (e.g., first-in-first-out, according to the order of command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to be moved in and out of buffer 225, as described above. As the data moves into and is stored in buffer 225, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), then the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, then the address where the data associated with that command was previously stored can be used to store the data associated with the new command.

[0064] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, discard item collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0065] System 200 may support a switchable channel between host system 205 and memory system 210. For example, a channel may be an instance of wires or traces between one or more pins of the host system controller and one or more pins of the memory system controller 215 (or interface 220). The channel may connect to modules at the host system controller (e.g., at two signaling pins) and modules at the memory system controller 215 (e.g., at two signaling pins). For non-switchable channels, such modules may be static; for example, a channel between a transmission module at the host system controller and a receiving module at the memory system controller 215 supports Tx to Rx from host system 205, while a channel between a receiving module at the host system controller and a transmission module at the memory system controller 215 supports Tx to Rx from memory system 210. In contrast, each of the host system controller and memory system controller 215 may include both a transmission module and a receiving module for switchable channels. The host system controller and memory system controller 215 may activate one module and deactivate another module to transmit information in a specific direction via the channel. For example, the host system controller, memory system controller 215, or both may include logic or switches to switch between a transmission module (e.g., where the receiving module is deactivated at the controller) at an active (e.g., powered or otherwise energized) controller and a receiving module (e.g., where the transmission module is deactivated at the controller) at an active controller. As described herein, the transmission and receiving modules may be instances of hardware components (e.g., M-PHY transmission hardware and M-PHY receiving hardware), software components, firmware components, logic, or any combination thereof.

[0066] In some instances, channels may be grouped into pairs, referred to as links 245. Links 245 may be between the host system controller and interface 220 (e.g., links 245-a and 245-b), between the host system controller and memory system controller 215 (e.g., links 245-c and 245-d), or a combination thereof. For non-switchable channels, link 245 may comprise a pair of unidirectional channels in opposite directions, enabling bidirectional communication between host system 205 and memory system 210. However, for switchable channels, link 245 may comprise a pair of unidirectional channels with switchable directions (e.g., controlled by commands, operations, or logic at host system 205, memory system 210, or both). Therefore, a link 245 with a switchable channel can support bidirectional communication between the host system 205 and the memory system 210 (e.g., link 245-c), unidirectional communication from the host system 205 to the memory system 210 (e.g., link 245-d), and unidirectional communication from the memory system 210 to the host system 205 (e.g., link 245-b), depending on the current direction of the channel within the link 245. In some instances, the system 200 may support one link 245 with a non-switchable channel (e.g., link 245-a) and one or more links 245 with switchable channels, such that the system 200 maintains at least one channel in each direction.

[0067] Figure 3A This document describes an example of a channel configuration 300-a that supports switchable channel direction between a host system and a memory system, based on the examples disclosed herein. Channel configuration 300-a couples a host system 305-a to a memory system 310-a, wherein the host system 305-a, the memory system 310-a, or both may be referenced. Figure 1 and 2 The description corresponds to an example of a system. Channel configuration 300-a may contain two links, each with two channels. However, in some instances, channel configuration 300-a may support any number of links, channels, or both between host system 305-a and memory system 310-a.

[0068] Channel configuration 300-a can support links with non-switchable channels. For example, channel configuration 300-a can maintain a Tx-to-Rx channel 315-a from the host system 305-a and a Tx-to-Rx channel 320-a from the memory system 310-a. In some instances, such channels may be non-switchable due to hardware configuration. For example, the Tx-to-Rx channel 315-a from the host system 305-a can be connected to the transmission module 330-a at the host system controller and the receiver module 335-a at the memory system controller. Similarly, the Tx-to-Rx channel 320-a from the memory system 310-a can be connected to the transmission module 330-b at the memory system controller and the receiver module 335-b at the host system controller. Therefore, the transmission module 330 and the receiver module 335 can define the direction of the non-switchable channel. Alternatively, in some other instances, such channels may be non-switchable depending on logic or policy at host system 305-a, memory system 310-a, or both. For example, host system 305-a, memory system 310-a, or both may be operable such that at least one link is maintained with a non-switchable channel, such that host system 305-a and memory system 310-a maintain non-zero bandwidth capacity in each direction. In some cases, host system 305-a, memory system 310-a, or both may use non-switchable channels to transmit operations, commands, or other information related to configuring switchable channel 325.

[0069] Channel configuration 300-a may additionally support links with switchable channels 325. For example, channel configuration 300-a may include switchable channels 325-a and 325-b. The host system controller and memory system controller may include transmission and reception modules 340 at each end of the switchable channels 325. For example, switchable channel 325-a may be connected to transmission and reception modules 340-a at the host system controller and transmission and reception modules 340-b at the memory system controller. Similarly, switchable channel 325-b may be connected to transmission and reception modules 340-c at the host system controller and transmission and reception modules 340-d at the memory system controller.

[0070] To configure switchable channel 325-a as a Tx-to-Rx channel 315 originating from host system 305-a, the host system controller can activate the transmission module of transmission and reception module 340-a and deactivate its reception module, and the memory system controller can activate the reception module of transmission and reception module 340-b and deactivate its transmission module. Activating the transmission module at the host system controller and activating the reception module at the memory system controller allows electronic flow from host system 305-a to memory system 310-a, thereby supporting signaling of information (e.g., data, commands) from host system 305-a to memory system 310-a. Alternatively, to configure switchable channel 325-a as a Tx-to-Rx channel 320 originating from memory system 310-a, the host system controller can deactivate the transmission module of transmission and reception module 340-a and activate its reception module, and the memory system controller can deactivate the reception module of transmission and reception module 340-b and activate its transmission module. Activating the transmission module at the memory system controller and the receiving module at the host system controller allows electronics to flow from the memory system 310-a to the host system 305-a, thereby supporting signaling of information (e.g., data, responses) from the memory system 310-a to the host system 305-a.

[0071] Other systems may use non-switchable channels with a symmetrical configuration, possessing a constant bandwidth capacity in each direction. However, bandwidth usage can be asymmetrical and vary over time. Fluctuations in bandwidth usage can cause one or more channels to be idle for periods between bursts of transmitted information (e.g., data, commands, responses, or other information). For example, to execute a set of read commands, a memory system may send data to a host system at a threshold data rate (e.g., the maximum supported data rate or other data rates) supported by the channel configuration. If the memory system is processing read commands instead of write commands (or is processing write commands for a relatively small amount of data) during a period of time, then the channel sending data from the memory system to the host system may be full, while one or more channels supporting data transfer from the host system to the memory system may be idle. Similarly, if the memory system is processing write commands instead of read commands (or is processing read commands for a relatively small amount of data) during a period of time, then the channel sending data from the host system to the memory system may be full, while one or more channels supporting data transfer from the memory system to the host system may be idle. Therefore, such systems may inefficiently utilize the bandwidth capacity of the channels.

[0072] In contrast, channel configuration 300-a can dynamically adjust the bandwidth capacity in a specific direction by switching channel directions in response to the type of work performed by memory system 310-a (e.g., reading or writing data). Depending on the current bandwidth conditions between host system 305-a and memory system 310-a, the switchable channel configuration can support potential increases in channel bandwidth and correspondingly increase throughput in either direction (e.g., without increasing the number of channels or pins between host system 305-a and memory system 310-a). For example, in response to current bandwidth conditions, such as by utilizing the entire group of channels more frequently due to switching, the transmission bandwidth at a threshold transmission rate (e.g., the maximum supported speed) can be adjusted for a specific direction.

[0073] In some instances, the UniPro protocol operates as the management layer for a channel (e.g., an M-PHY channel) between host system 305-a and memory system 310-a (e.g., containing a UFS device). UniPro can use the channel's capabilities to configure the channel between host system 305-a and memory system 310-a and control data flow across the channel. To support switchable channels, UniPro may additionally include a channel switching control mechanism that can monitor one or more bandwidth triggers from memory system 310-a (e.g., memory device, memory system controller, buffer), host system 305-a (e.g., host system controller, buffer), or a combination thereof. If a bandwidth trigger is detected (e.g., via memory system 310-a, host system 305-a, or both), memory system 310-a, host system 305-a, or both may request UniPro to switch the channel direction to increase bandwidth capacity in a specific direction. To switch channel directions, UniPro can deactivate switchable channel 325, switch the direction of both host system 305-a and memory system 310-a (e.g., by switching the active module of transmit and receive module 340), and reactivate switchable channel 325. In some instances, even when deactivating and reconfiguring the switchable channel, UniPro can maintain a non-switchable channel group to support communication between host system 305-a and memory system 310-a in both directions. In some cases, channel switching may correspond to a specific duration, a specific set of tasks, or a combination thereof. After the duration expires, the set of tasks completes, or both, UniPro can switch the channel direction back to the default channel direction. In some instances, the default channel configuration may be a symmetrical channel configuration (e.g., where switchable channels 325-a and 325-b transmit data in opposite directions).

[0074] The UniPro or another management layer for the switchable channel 325 can support any number of bandwidth triggers to trigger direction switching of one or more channels. In some instances, the system (e.g., memory system 310-a, host system 305-a, or both) can trigger channel direction switching in response to the amount of data ready to transmit or receive meeting a threshold data amount. Alternatively, the system can trigger switching in response to the data rate for a direction meeting a saturation threshold (e.g., if the channel currently configured to transmit data in said direction is full or transmitting at a threshold data rate). In some instances, the system can trigger switching in response to detecting a backlog of data in the buffer, for example, due to retrieving data at a rate faster than the rate at which data can be transmitted via the channel group. In some cases, detecting a backlog may involve determining whether the amount of data currently in the buffer meets a threshold data amount or whether the rate at which data is added to the buffer meets a threshold data rate. Alternatively, the system can trigger switching in response to detecting the ability to transmit or receive additional information in a particular direction. For example, if the system detects one or more idle channels in the first direction and the bandwidth in the second direction meets the bandwidth threshold, the system can trigger a channel direction switch for the one or more idle channels.

[0075] In some instances, the host system 305-a or the memory system 310-a can control channel switching. For example, the system can trigger channel reconfiguration to switch the channel direction. If the host system 305-a triggers the switching, it can transmit an instruction to the memory system 310-a to reconfigure the channel direction, causing the channel direction to switch at both ends of the channel. Similarly, if the memory system 310-a triggers the switching, it can transmit an instruction to the host system 305-a to reconfigure the channel direction.

[0076] In some other instances, host system 305-a can control channel switching, while memory system 310-a can request or otherwise indicate the availability of performing a channel direction switch. Both host system 305-a and memory system 310-a can support sending messages to indicate information related to switchable channel directions. For example, to perform a read operation, host system 305-a can send a command UFS Protocol Information Unit (UPIU) indicating a read operation for a set of data. Memory system 310-a can respond with one or more data items in the UPIU, where each data item in the UPIU contains a portion of the set of data. In some cases, the data in the UPIU may contain indicators (e.g., fields, flags) for memory system 310-a indicating a request for a channel direction switch. For example, if memory system 310-a sets a flag, the flag setting indicates that memory system 310-a is requesting a "read optimization" configuration (e.g., at least one switchable channel 325 is switched to a Tx-to-Rx channel 320 from memory system 310-a). Memory system 310-a can set the flag in response to a detected bandwidth trigger. Host system 305-a can receive data from the UPIU, determine whether the flag is set (e.g., whether the flag is set or not), and determine to perform a channel direction switch. For example, host system 305-a can trigger a channel direction switch at the host system controller and can transmit an indication to memory system 310-a to correspondingly reconfigure the channel direction at the memory system controller.

[0077] Alternatively, to perform a write operation, host system 305-a may send a command UPIU indicating a write operation to memory system 310-a. Memory system 310-a may respond with one or more transfer-ready (RTT) UPIUs, each RTT UPIU indicating a portion of data to be sent by host system 305-a (e.g., in a data output UPIU). In some cases, the RTT UPIU may contain an indicator (e.g., a field, a flag) for memory system 310-a to indicate a request for a channel direction switch. For example, if memory system 310-a sets a flag, the flag setting may indicate that memory system 310-a is requesting a "write-optimized" configuration (e.g., where at least one switchable channel 325 is switched to a Tx-to-Rx channel 315 from host system 305-a). Memory system 310-a may set the flag in response to the detection of a bandwidth trigger. The host system 305-a can receive the RTT UPIU, determine that the flag is set, and determine to perform a channel direction switch. For example, the host system 305-a can trigger a channel direction switch at the host system controller and can transmit a corresponding instruction to the memory system 310-a to reconfigure the channel direction at the memory system controller.

[0078] Figure 3B This document describes an example of a channel configuration 300-b that supports switchable channel direction between a host system and a memory system, based on the examples disclosed herein. Channel configuration 300-b may support a "read-optimized" configuration. For example, channel configuration 300-b may include one or more links with non-switchable channels and one or more links with switchable channels 325. To support additional bandwidth capacity from memory system 310-b to host system 305-b, a larger proportion of switchable channels 325 may be configured as Tx-to-Rx channels 320 from memory system 310-b (e.g., compared to Tx-to-Rx channels 315 configured from host system 305-b). Host system 305-b, memory system 310-b, or both may be referenced. Figure 1 , 2 And instances of the corresponding systems described in 3A.

[0079] In some instances, memory system 310-b can determine whether it is reading data from a memory die or memory device (e.g., a NAND device or other memory device) at a higher data rate than supported by the bandwidth capability from memory system 310-b to host system 305-b. For example, if a symmetrical channel configuration (e.g., where switchable channels 325-c and 325-d transmit data in opposite directions) supports a first data rate from memory system 310-b to host system 305-b, and memory system 310-b is reading data from one or more memory devices at a second data rate greater than the first data rate, then data can accumulate at the buffer of memory system 310-b faster than a buffer can send data to host system 305-b. In some cases, memory system 310-b may send data from the UPIU to host system 305-b to request additional bandwidth in the direction from memory system 310-b to host system 305-b. The host system 305-b can receive data from the UPIU and trigger a channel direction switch to increase the bandwidth capacity from the memory system 310-b to the host system 305-b. For example, the host system controller can switch the direction configured for the switchable channel 325-c. Therefore, the channel configuration 300-b may include one Tx-to-Rx channel 315-b from the host system 305-b and three Tx-to-Rx channels 320 from the memory system 310-b (e.g., Tx-to-Rx channel 320-b from the memory system 310-b, switchable channel 325-c, and switchable channel 325-d). Reconfiguring the channel from a symmetric configuration to a “read-optimized” configuration can increase the bandwidth capacity from memory system 310-b to host system 305-b by approximately 50%, thereby supporting additional data throughput for read operations (e.g., in a “homogeneous” read scenario, where memory system 310-b handles a large number of read operations and relatively few – or none – write operations within a given time period).

[0080] Figure 3C This document describes an example of a channel configuration 300-c that supports switchable channel direction between a host system and a memory system, based on the examples disclosed herein. Channel configuration 300-c can support a "write-optimized" configuration. For example, channel configuration 300-c may include one or more links with non-switchable channels and one or more links with switchable channels 325. To support additional bandwidth capacity from host system 305-c to memory system 310-c, a larger proportion of the switchable channels 325 can be configured as Tx-to-Rx channels 315 from host system 305-c. Host system 305-c, memory system 310-c, or both may be referenced. Figure 1 , 2Examples of the corresponding systems described in 3A and 3B.

[0081] In some instances, memory system 310-c can determine whether it is receiving information (e.g., commands, data) from host system 305-c at a data rate that meets a bandwidth capacity threshold. For example, memory system 310-c may be receiving information from host system 305-c at a data rate currently supported by the bandwidth capacity from host system 305-c to memory system 310-c. In some cases, memory system 310-c may send an RTT UPIU to host system 305-c to request additional bandwidth in the direction from host system 305-c to memory system 310-c. Host system 305-c may receive the RTT UPIU and determine whether to trigger a channel direction switch to increase the bandwidth capacity from host system 305-c to memory system 310-c. In some cases, host system 305-c may trigger a switch if it detects a backlog of information to be sent to memory system 310-c in its buffer. The host system controller can switch the configuration direction for switchable channel 325-f. Therefore, channel configuration 300-c may include one Tx-to-Rx channel 320-c from memory system 310-c and three Tx-to-Rx channels 315 from host system 305-c (e.g., Tx-to-Rx channel 315-c from host system 305-c, switchable channel 325-e, and switchable channel 325-f). Reconfiguring the channels from a symmetric configuration to a "write-optimized" configuration can increase the bandwidth capacity from host system 305-c to memory system 310-c by approximately 50%, thereby supporting additional data throughput for write operations (e.g., in a "homogeneous" write scenario where memory system 310-c handles a large number of write operations and relatively few—or none—read operations within a given time period).

[0082] Figure 4 This describes an example of a process flow 400 that supports switchable channel direction between a host system and a memory system, based on the examples disclosed herein. Process flow 400 can be found in references... Figure 1 and 2 The described system 100 (or one or more components thereof) or system 200 (or one or more components thereof) is implemented. Process flow 400 can support dynamic switching between channel configurations, as referenced. Figure 3A , 3BAnd 3C description. For example, process flow 400 may be implemented by a device (e.g., a host system, a memory system) or a system of devices (e.g., a host system coupled to the memory system). The host system and memory system may dynamically switch channel directions to improve bandwidth utilization of a set of channels between the host system and the memory system, thereby improving the overall performance capabilities of the host system and the memory system. In some cases, the following alternative instances may be implemented, some of which may be performed in a different order than described, or not at all. Additionally or alternatively, operations may include additional features not mentioned below, or additional processes may be added.

[0083] At 405, a set of channels is used to transmit information. For example, information can be transmitted between a memory system and a host system via said set of channels. Each channel can be configured to transmit information in a first direction or a second direction. For example, said set of channels can include a first subset of channels configured to transmit information in the first direction from the memory system to the host system and a second subset of channels configured to transmit information in the second direction from the host system to the memory system.

[0084] At 410, the system (e.g., a host system, a memory system, or both) determines whether the bandwidth conditions for the first direction meet a threshold for reconfiguring the channel direction. For example, the host system may send one or more read commands to the memory system, and the memory system may read data to be sent to the host system from a memory die containing memory devices. If the memory system detects that the amount of data read from the memory die exceeds a first bandwidth supported by the set of channels for the first direction (e.g., based on the data rate and channel bandwidth capacity), then the memory system may determine to trigger a channel switch. For example, if the bandwidth conditions for the first direction meet the threshold, then at 415, the channel direction is switched. The host system and the memory system may reconfigure the channel direction such that the reconfigured channel transmits information in the first direction (e.g., to increase the bandwidth for transmitting data in response to one or more read commands). If the bandwidth conditions for the first direction do not meet the threshold, then the host system and the memory system may avoid reconfiguring the channel for the first direction.

[0085] At 420, the system (e.g., a host system, a memory system, or both) determines whether the bandwidth conditions for the second direction meet a threshold for reconfiguring the channel direction. The bandwidth conditions for the first direction and the bandwidth conditions for the second direction may be the same or different. In some instances, the host system may send data to the memory system as part of a write operation. If the memory system detects that it supports writing data to the memory die at a rate exceeding the second bandwidth supported by the set of channels for the second direction (e.g., based on the data rate and channel bandwidth capacity), then the memory system may determine to trigger a channel switch. For example, if the bandwidth conditions for the second direction meet the threshold, then at 425, the channel direction is switched. The host system and the memory system may reconfigure the channel direction such that the reconfigured channel sends information in the second direction (e.g., to increase the bandwidth for sending data in response to one or more write commands). If the bandwidth conditions for the second direction do not meet the threshold, then the host system and the memory system may avoid reconfiguring the channel for the second direction.

[0086] The host system and memory system can use the set of channels to transmit information, and in some cases, the channels can be reconfigured for different directions. The host system and memory system can continue to track bandwidth conditions and dynamically determine updated channel directions to support different bandwidth capacities in the first and second directions at different times.

[0087] Figure 5 A block diagram 500 illustrates a memory system 520 that supports switchable channel direction between a host system and a memory system, according to an example disclosed herein. The memory system 520 may be used as a reference. Figures 1 to 4 Examples of aspects of the described memory system. Memory system 520 or its various components may be examples of means for performing various aspects of switchable channel directions between a host system and a memory system, as described herein. For example, memory system 520 may include communication component 525, bandwidth condition component 530, channel switching component 535, channel switching indication component 540, read operation component 545, request component 550, write operation component 555, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0088] Communication component 525 may be configured or otherwise support means for communicating with a host system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system. Bandwidth condition component 530 may be configured or otherwise support means for determining, at least in part, whether a bandwidth condition associated with one or both of the first or second direction satisfies a threshold for reconfiguring channels in the set of channels, based on either a first bandwidth supported by the set of channels in the first direction or a second bandwidth supported by the set of channels in the second direction. Channel switching component 535 may be configured or otherwise support means for switching the direction of channel configuration at least in part based on determining that a bandwidth condition associated with one or both of the first or second direction satisfies a threshold.

[0089] In some instances, the channel is configured to transmit information in a second direction from the host system to the memory system. In some instances, to determine whether a bandwidth condition associated with one or both of the first and second directions meets a threshold, the bandwidth condition component 530 may be configured or otherwise supported to include means for determining whether a first bandwidth condition associated with the first direction from the memory system to the host system meets a threshold for reconfiguring the channel. In some instances, to switch the direction configured for the channel, the channel switching component 535 may be configured or otherwise supported to switch the channel from being configured to transmit information in the second direction from the host system to the memory system to being configured to transmit information in the first direction from the memory system to the host system, at least in part based on determining that a first bandwidth condition associated with the first direction meets a threshold.

[0090] In some instances, the read operation component 545 may be configured or otherwise supported to support means for reading data to be transmitted to a host system from a memory die containing a memory device. In some instances, the bandwidth condition component 530 may be configured or otherwise supported to support means for detecting that the amount of data read from the memory die exceeds a first bandwidth supported by the set of channels for the first direction, wherein determining that the first bandwidth condition associated with the first direction satisfies a threshold is at least partially based on the detection. In some instances, the request component 550 may be configured or otherwise supported to support means for sending an instruction to the host system to reconfigure the set of channels to support additional bandwidth in the first direction, wherein switching the direction configured for the channels is at least partially based on the request.

[0091] In some instances, the requested instruction contains data from UPIU.

[0092] In some instances, the channel is configured to transmit information in a first direction from the memory system to the host system. In some instances, to determine whether a bandwidth condition associated with one or both of the first and second directions meets a threshold, the bandwidth condition component 530 may be configured or otherwise support means for determining whether a second bandwidth condition associated with the second direction from the host system to the memory system meets a threshold for reconfiguring the channel. In some instances, to switch the direction configured for the channel, the channel switching component 535 may be configured or otherwise support means for switching the channel from being configured to transmit information in the first direction from the memory system to the host system to being configured to transmit information in the second direction from the host system to the memory system, at least in part based on determining that a second bandwidth condition associated with the second direction meets a threshold.

[0093] In some instances, write operation component 555 may be configured or otherwise supported to include means for receiving data from the host system based on a second bandwidth supported by the set of channels for the second direction. In some instances, bandwidth condition component 530 may be configured or otherwise supported to include means for detecting that the memory system supports writing data to the memory die at a rate exceeding the second bandwidth supported by the set of channels for the second direction, wherein determining that the second bandwidth condition associated with the second direction meets a threshold is at least partially based on the detection. In some instances, request component 550 may be configured or otherwise supported to include means for sending an instruction to the host system to reconfigure the set of channels to support additional bandwidth in the second direction, wherein the direction configured for the channels is at least partially based on the request.

[0094] In some instances, the requested instruction includes RTT UPIU.

[0095] In some instances, the channel switching indication component 540 may be configured or otherwise supported to include a component for receiving an indication from the host system of the direction of switching for a channel configuration, wherein the switching is at least in part based on the received indication.

[0096] In some instances, the channel switching indication component 540 may be configured or otherwise supported as a component for sending an indication to the host system that the direction of the channel configuration is at least partially based on the switching.

[0097] In some instances, to support switching of the direction configured for a channel, the channel switching component 535 may be configured or otherwise support components for activating the transmission module and deactivating the receiver module for the channel at the memory system. In other instances, to support switching of the direction configured for a channel, the channel switching component 535 may be configured or otherwise support components for activating the receiver module and deactivating the transmission module for the channel at the memory system.

[0098] Figure 6 A block diagram 600 illustrates a host system 620 that supports switchable channel direction between a host system and a memory system, according to an example disclosed herein. The host system 620 may be used as a reference. Figures 1 to 4 Examples of aspects of the host system described herein. Host system 620 or its various components may be examples of means for performing various aspects of switchable channel directions between the host system and the memory system, as described herein. For example, host system 620 may include communication component 625, channel switching request component 630, channel switching component 635, channel switching indication component 640, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0099] Communication component 625 may be configured or otherwise supported for communicating with a memory system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system. Channel switching request component 630 may be configured or otherwise supported for receiving from the memory system an indication of a request to reconfigure the set of channels to support additional bandwidth in the first or second direction. Channel switching component 635 may be configured or otherwise supported for switching the direction configured for channels in the set of channels based at least in part on a request to reconfigure the set of channels to support additional bandwidth in the first or second direction.

[0100] In some instances, channels are configured to transmit information in a second direction from the host system to the memory system. In some instances, the request indicates a request to reconfigure the set of channels to support additional bandwidth in a first direction. In some instances, to switch the direction configured for a channel, channel switching component 635 may be configured or otherwise support switching a channel from being configured to transmit information in a second direction from the host system to the memory system to being configured to transmit information in a first direction from the memory system to the host system, at least in part based on a request to reconfigure the set of channels to support additional bandwidth in the first direction.

[0101] In some instances, the requested instruction contains data from UPIU.

[0102] In some instances, channels are configured to transmit information in a first direction from the memory system to the host system. In some instances, the request indicates a request to reconfigure the set of channels to support additional bandwidth in a second direction. In some instances, to switch the direction configured for a channel, channel switching component 635 may be configured or otherwise support switching a channel from being configured to transmit information in the first direction from the memory system to the host system to being configured to transmit information in the second direction from the host system to the memory system, based at least in part on a request to reconfigure the set of channels to support additional bandwidth in the second direction.

[0103] In some instances, the requested instruction includes RTT UPIU.

[0104] In some instances, the channel switching indication component 640 may be configured or otherwise supported as a means for sending an indication to the memory system to switch the direction of the channel configuration at least in part based on the switching.

[0105] Figure 7 The flowchart illustrates a method 700 for supporting switchable channel direction between a host system and a memory system, based on examples disclosed herein. Operation of method 700 can be implemented by the memory system or its components described herein. For example, operation of method 700 can be achieved by referring to... Figures 1 to 5 The described memory system performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0106] At 705, the method may include communicating with a host system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system. Operation 705 may be performed according to the examples disclosed herein. In some instances, aspects of operation 705 may be derived from references... Figure 5 The described communication component 525 is executed.

[0107] At 710, the method may include determining, at least in part, whether a bandwidth condition associated with one or both of the first or second direction satisfies a threshold for reconfiguring channels in the set of channels, based on one or both of a first bandwidth supported by the set of channels for a first direction or a second bandwidth supported by the set of channels for a second direction. For example, a memory system may use a first bandwidth value or a second bandwidth value to determine a threshold for reconfiguring channels and may compare the bandwidth condition with the determined threshold. Operation 710 may be performed according to the examples disclosed herein. In some instances, aspects of operation 710 may be referenced from... Figure 5 The bandwidth condition component 530 described is executed.

[0108] At 715, the method may include switching the direction for the channel configuration based at least in part on (e.g., in response to) determining that a bandwidth condition associated with one or both of the first and second directions satisfies the threshold. Operation 715 may be performed according to the examples disclosed herein. In some instances, aspects of operation 715 may be derived from references... Figure 5 The described channel switching component 535 is executed.

[0109] Aspects of process flow 700 may be implemented by a controller and other components. Alternatively, aspects of process flow 700 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, when executed by a controller (e.g., a memory system controller), the instructions may cause the controller to perform operations of process flow 700.

[0110] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: communicating with a host system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system; determining, at least in part, based on one or both of a first bandwidth supported by the set of channels for the first direction or a second bandwidth supported by the set of channels for the second direction, whether a bandwidth condition associated with one or both of the first or second direction satisfies a threshold for reconfiguring channels in the set of channels; and switching the direction configured for the channels, at least in part based on determining that the bandwidth condition associated with one or both of the first or second direction satisfies the threshold.

[0111] In some instances of the method 700 and apparatus described herein, a channel may be configured to transmit information in a second direction from a host system to a memory system, the determination may include determining that a first bandwidth condition associated with a first direction from the memory system to the host system satisfies a threshold for reconfiguring the channel, and the switching may include switching the channel from being configured to transmit information in the second direction from the host system to the memory system to being configured to transmit information in the first direction from the memory system to the host system, at least in part based on determining that the first bandwidth condition associated with the first direction satisfies the threshold.

[0112] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: reading data from a memory die containing a memory device for transmission to the host system; detecting that the amount of data read from the memory die exceeds a first bandwidth supported by the set of channels for the first direction, wherein determining that the first bandwidth condition associated with the first direction satisfies the threshold may be based at least in part on the detection; and sending an instruction to the host system to reconfigure the set of channels to support additional bandwidth in the first direction, wherein switching the direction configured for the channels may be based at least in part on the request.

[0113] In some instances of the method 700 and device described herein, the requested instruction includes data from the UPIU.

[0114] In some instances of the method 700 and apparatus described herein, a channel may be configured to transmit information in a first direction from a memory system to a host system, the determination may include determining that a second bandwidth condition associated with a second direction from the host system to the memory system satisfies a threshold for reconfiguring the channel, and the switching may include switching the channel from being configured to transmit information in the first direction from the memory system to the host system to being configured to transmit information in the second direction from the host system to the memory system, at least in part based on determining that the second bandwidth condition associated with the second direction satisfies the threshold.

[0115] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving data from the host system according to a second bandwidth supported by the set of channels for the second direction; detecting that the memory system supports writing the data to a memory die at a rate exceeding the second bandwidth supported by the set of channels for the second direction, wherein determining that the second bandwidth condition associated with the second direction satisfies the threshold may be at least partially based on the detection; and sending an instruction to the host system to reconfigure the set of channels to support additional bandwidth in the second direction, wherein switching the direction configured for the channels may be at least partially based on the request.

[0116] In some instances of the method 700 and device described herein, the requested indication includes RTT UPIU.

[0117] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving an indication from a host system to switch the direction of a channel configuration, wherein the switching may be based at least in part on the received indication.

[0118] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for sending an indication to a host system that the direction of the channel configuration can be switched at least in part based on the switching.

[0119] In some instances of the method 700 and apparatus described herein, switching the direction configured for the channel may include operations, features, circuitry, logic, components, or instructions for: activating the transmission module and deactivating the receiving module for the channel in the memory system; or activating the receiving module and deactivating the transmission module for the channel in the memory system.

[0120] Figure 8 The flowchart illustrates a method 800 for supporting switchable channel direction between a host system and a memory system, based on examples disclosed herein. Operation of method 800 can be implemented by the host system or its components described herein. For example, operation of method 800 can be performed by reference to... Figures 1 to 4 The host system described in section 6 performs the functions described herein. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0121] At 805, the method may include communicating with a memory system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system. Operation 805 may be performed according to the examples disclosed herein. In some instances, aspects of operation 805 may be derived from references... Figure 6 The described communication component 625 is executed.

[0122] At 810, the method may include receiving an instruction from the memory system to reconfigure the set of channels to support additional bandwidth in a first or second direction. Operation 810 may be performed according to the examples disclosed herein. In some instances, aspects of operation 810 may be derived from references... Figure 6 The described channel switching request component 630 is executed.

[0123] In 815, the method may include switching the direction of channel configuration for one of the channels based at least in part on (e.g., in response to) a request to reconfigure the set of channels to support additional bandwidth in a first or second direction. Operation 815 may be performed according to the examples disclosed herein. In some instances, aspects of operation 815 may be derived from references... Figure 6 The described channel switching component 635 is executed.

[0124] Aspects of process flow 800 may be implemented by a controller and other components. Alternatively, aspects of process flow 800 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to the host system). For example, when executed by a controller (e.g., a host system controller), the instructions may cause the controller to perform the operation of process flow 800.

[0125] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: communicating with the memory system using a set of channels to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system; receiving from the memory system an indication of a request to reconfigure the set of channels to support additional bandwidth in the first or second direction; and switching the direction of channel configuration in the set of channels based at least in part on the request to reconfigure the set of channels to support the additional bandwidth in the first or second direction.

[0126] In some instances of the method 800 and apparatus described herein, channels may be configured to transmit information in a second direction from a host system to a memory system, the requested instruction requests reconfiguration of the set of channels to support additional bandwidth in a first direction, and the switching may include, at least in part, switching channels from being configured to transmit information in the second direction from the host system to the memory system to being configured to transmit information in the first direction from the memory system to the host system based on a request to reconfigure the set of channels to support additional bandwidth in the first direction.

[0127] In some instances of the method 800 and device described herein, the requested instruction includes data from the UPIU.

[0128] In some instances of the method 800 and apparatus described herein, channels may be configured to transmit information in a first direction from the memory system to the host system, the requested instruction requesting reconfiguration of the set of channels to support additional bandwidth in a second direction, and the switching may include, at least in part, switching channels from being configured to transmit information in the first direction from the memory system to the host system to being configured to transmit information in the second direction from the host system to the memory system based on the request to reconfigure the set of channels to support additional bandwidth in the second direction.

[0129] In some instances of the method 800 and device described herein, the requested indication includes RTT UPIU.

[0130] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for sending an indication to a memory system, at least in part based on the switching, to switch the direction of the channel configuration.

[0131] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0132] Describe another device. The device may include: a memory system including a memory system controller; and a link including a first channel between the memory system controller and a host system controller, wherein the first channel is configured to send information to the host system controller at least in part based on activating a transmission module at the memory system controller, and is configured to receive information from the host system controller at least in part based on activating a receiving module at the memory system controller.

[0133] In some instances of the device, the memory system controller includes logic configured to activate the transmission module and deactivate the receiving module, activate the receiving module and deactivate the transmission module, or both.

[0134] In some instances of the device, the link includes a second channel, wherein the second channel is configurable to send information to the host system controller at least in part based on activating a second transmission module at the memory system controller, and is configurable to receive information from the host system controller at least in part based on activating a second receiving module at the memory system controller.

[0135] In some instances, the device may include a second link comprising a third channel and a fourth channel, the second link being between the memory system controller and the host system controller, wherein the third channel supports sending information to the host system controller using a third transmission module at the memory system controller, and the fourth channel supports receiving information from the host system controller using a third receiving module at the memory system controller.

[0136] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have multiple bit widths.

[0137] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or electrically connected, connected, or coupled) if there is any conductive path between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or electrically connected, connected, or coupled) may be open or closed depending on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0138] The term "coupling" refers to a shift from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0139] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if an open circuit exists between them. For example, if a switch is turned off, the two components separated by the switch positioned between them are isolated from each other. If a controller isolates two components, the controller introduces a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0140] As used in this article, the term “substantially” means that the modified property (e.g., a verb or adjective modified by the term “substantially”) does not need to be absolute but close enough to achieve the property’s advantage.

[0141] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” may be used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0142] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a preceding condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least partially as a result of the occurrence of the preceding condition or action (whether after one or more other intermediate conditions or actions that occur directly after the first condition or action or after it).

[0143] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action is executable, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action is executable, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, such that no other intermediate conditions or actions occur between the previous condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the previous condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" certain other steps, actions, events, or conditions may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" this other condition or action.

[0144] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0145] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0146] The descriptions set forth herein, together with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed description includes specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0147] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0148] The functions described herein can be implemented in hardware or software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0149] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0150] As used herein, the word "or" in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") encompasses the contents of the claims, and indicates a list of items such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0151] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL, or technology (such as infrared, radio, and microwave) is included in the media definition. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0152] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory system including a controller configured to cause the device to: A set of channels is used to communicate with the host system to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system; Whether a bandwidth condition associated with one or both of the first direction or the second direction satisfies a threshold for reconfiguring channels in the set of channels is determined at least in part based on one or both of a first bandwidth supported by the set of channels for the first direction or a second bandwidth supported by the set of channels for the second direction. An instruction to reconfigure the set of channels to support additional bandwidth in the first direction or the second direction is sent, based at least in part on determining that the bandwidth condition associated with one or both of the first direction or the second direction meets the threshold. and The direction configured for the channel is switched at least in part based on the instruction sent in the request.

2. The device according to claim 1, wherein: The channel is configured to transmit information in the second direction from the host system to the memory system; The controller, configured to enable the device to determine whether the bandwidth condition associated with one or both of the first direction or the second direction satisfies the threshold, is configured to enable the device to: Determine that a first bandwidth condition associated with the first direction from the memory system to the host system satisfies the threshold for reconfiguring the channel; and The controller, configured to cause the device to switch the direction configured for the channel, is configured to cause the device to: The channel is switched from being configured to transmit information in the second direction from the host system to the memory system to being configured to transmit information in the first direction from the memory system to the host system, at least in part based on determining that the first bandwidth condition associated with the first direction meets the threshold.

3. The device of claim 2, wherein the controller is further configured such that the device: Reading data from a memory die including a memory device for transmission to the host system; and The detection detects that the amount of data read from the memory die exceeds the first bandwidth supported by the set of channels for the first direction, wherein determining that the first bandwidth condition associated with the first direction satisfies the threshold is at least in part based on the detection, wherein the indication requests a reconfiguration of the set of channels to support additional bandwidth in the first direction.

4. The device of claim 3, wherein the indication of the request includes data in the Universal Flash Storage UFS Protocol Information Unit (UPIU).

5. The device according to claim 1, wherein: The channel is configured to transmit information in the first direction from the memory system to the host system; The controller, configured to enable the device to determine whether the bandwidth condition associated with one or both of the first direction or the second direction satisfies the threshold, is configured to enable the device to: The second bandwidth condition associated with the second direction from the host system to the memory system is determined to satisfy the threshold for reconfiguring the channel; and The controller, configured to cause the device to switch the direction configured for the channel, is configured to cause the device to: The channel is switched from being configured to transmit information in the first direction from the memory system to the host system to being configured to transmit information in the second direction from the host system to the memory system, at least in part based on determining that the second bandwidth condition associated with the second direction meets the threshold.

6. The device of claim 5, wherein the controller is further configured such that the device: Data is received from the host system according to the second bandwidth supported by the set of channels for the second direction; and The detection that the memory system supports writing the data to the memory die at a rate exceeding the second bandwidth supported by the set of channels for the second direction is at least partially based on the detection. The indicated request requests that the set of channels be reconfigured to support additional bandwidth in the second direction.

7. The apparatus of claim 6, wherein the indication of the request includes a Transmission Ready Time (RTT) Universal Flash Storage UFS Protocol Information Unit (UPIU).

8. The device of claim 1, wherein the controller is further configured such that the device: The host system receives an instruction to switch the direction configured for the channel, wherein the switching is at least in part based on the received instruction.

9. The device of claim 1, wherein the controller is further configured such that the device: Sending the direction configured for the channel to the host system is an indication that the switching is at least in part based on the switching.

10. The device of claim 1, wherein the controller configured to cause the device to switch the direction configured for the channel is configured to cause the device to: At the memory system, activate the transmission module and deactivate the receiving module for the channel; or The receiving module is activated and the transmission module is deactivated for the channel in the memory system.

11. An apparatus comprising: A host system including a controller configured to couple with a memory system, wherein the controller is configured to cause the device to: A set of channels is used to communicate with the memory system to transmit information, wherein the set of channels includes a first subset of channels configured to transmit information in a first direction from the memory system to the host system and a second subset of channels configured to transmit information in a second direction from the host system to the memory system; Receive an instruction from the memory system to reconfigure the set of channels to support additional bandwidth in the first or second direction; and The direction of the channel configuration in the set of channels is switched at least in part based on the request to reconfigure the set of channels to support the additional bandwidth in the first or second direction.

12. The device according to claim 11, wherein: The channel is configured to transmit information in the second direction from the host system to the memory system; The request indicates a request to reconfigure the set of channels to support the additional bandwidth in the first direction; and The controller, configured to cause the device to switch the direction configured for the channel, is configured to cause the device to: At least in part based on the request to reconfigure the set of channels to support the additional bandwidth in the first direction, the channels are switched from being configured to transmit information in the second direction from the host system to the memory system to being configured to transmit information in the first direction from the memory system to the host system.

13. The device of claim 12, wherein the indication of the request includes data in the Universal Flash Storage UFS Protocol Information Unit (UPIU).

14. The device according to claim 11, wherein: The channel is configured to transmit information in the first direction from the memory system to the host system; The request indicates a request to reconfigure the set of channels to support the additional bandwidth in the second direction; and The controller, configured to cause the device to switch the direction configured for the channel, is configured to cause the device to: At least in part based on the request to reconfigure the set of channels to support the additional bandwidth in the second direction, the channels are switched from being configured to transmit information in the first direction from the memory system to the host system to being configured to transmit information in the second direction from the host system to the memory system.

15. The apparatus of claim 14, wherein the indication of the request includes a Transmission Ready Time (RTT) Universal Flash Storage UFS Protocol Information Unit (UPIU).

16. The device of claim 11, wherein the controller is further configured such that the device: Send an instruction to the host system to switch the direction configured for the channel, at least in part based on the switching.

17. An apparatus comprising: A memory system, including a memory system controller; and A link, including a first channel between the memory system controller and the host system controller, wherein the first channel is configurable to send information to the host system controller at least in part based on activating a transmission module at the memory system controller, and is configurable to receive information from the host system controller at least in part based on activating a receiving module at the memory system controller, wherein the memory system controller includes logic configured to send an indication requesting reconfiguration of the first channel to support additional bandwidth in a first direction or a second direction.

18. The apparatus according to claim 17, wherein: The memory system controller includes logic configured to activate the transmission module and deactivate the receiving module, activate the receiving module and deactivate the transmission module, or both.

19. The apparatus according to claim 17, wherein: The link includes a second channel, wherein the second channel is configurable to send information to the host system controller at least in part based on activating a second transmission module at the memory system controller, and is configurable to receive information from the host system controller at least in part based on activating a second receiving module at the memory system controller.

20. The apparatus of claim 17, further comprising: The second link includes a third channel and a fourth channel, which are located between the memory system controller and the host system controller. The third channel supports sending information to the host system controller using a third transmission module at the memory system controller, and the fourth channel supports receiving information from the host system controller using a third receiving module at the memory system controller.

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