Dynamic superblock

Abstract

This application relates to dynamic superblocks. In some examples, a superblock can be established across one or more dies of a memory device. A superblock can include one or more blocks from multiple planes of a memory die and can be associated with a first performance cursor or a second performance cursor. The superblock can be established based on one or more criteria, such as a number of available blocks in a plane, a number of access operations performed on one or more blocks in a plane, or other criteria. Establishing a superblock associated with a first performance cursor can allow performance criteria established by a host device to be maintained, while establishing a superblock associated with a second performance cursor can allow garbage collection, wear leveling, and other maintenance operations to be performed on the memory device.

Description

[0001] Cross-references

[0002] This patent application claims the benefit of U.S. Patent Application No. 17 / 241,930, entitled “Dynamic Superblocks,” filed April 27, 2021, by CARIELLO, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves dynamic superblocks. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, either logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of those possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] Describe a device. In some instances, the device may include: a memory comprising a plurality of planes, each comprising a plurality of blocks, each of the plurality of blocks comprising a plurality of non-volatile memory cells; and a controller coupled to the memory and operable to: determine, at least in part, based on one or more commands received from a host device, the creation of a superblock comprising two or more blocks of the memory, wherein the superblock is associated with multi-plane write operations for the memory; select a corresponding block for the superblock from each of at least two of the plurality of planes, at least in part based on the determination of the creation of the superblock; receive data from the host device for writing to the memory; and transmit commands and data to the memory, wherein the commands instruct data to be written in parallel to the corresponding blocks of the superblock.

[0007] Describe a device. In some instances, the device may include: a memory comprising a plurality of planes, wherein each plane includes a plurality of blocks, each comprising a plurality of non-volatile memory cells; and a controller coupled to the memory, wherein the controller is operable to: establish a first superblock associated with a first performance level, the first superblock including a first block from a first plane of the plurality of planes of the memory and a second block from a second plane of the plurality of planes of the memory; establish a second superblock associated with a second performance level, the second superblock including a corresponding block from each of the plurality of planes of the memory; and transmit to the memory a first command and first data for performing a first write operation on the first superblock, and a second command and second data for performing a second write operation on the second superblock.

[0008] A non-transitory computer-readable medium storing code is described. In some instances, the non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of a memory device, cause the memory device to: determine, at least in part, based on one or more commands received from a host device, to establish a superblock comprising a first set of two or more blocks of memory, the memory comprising a plurality of planes, wherein the superblock is associated with multi-plane write operations for the memory; select a corresponding block for the superblock from each of at least two of the plurality of planes, at least in part based on determining to establish the superblock; receive data from the host device for writing to the memory; and transmit commands and data to the memory, wherein the commands instruct data to be written in parallel to the corresponding blocks of the superblock. Attached Figure Description

[0009] Figure 1 This describes an instance of a system that supports dynamic superblocks, based on examples disclosed herein.

[0010] Figure 2 This describes an instance of a system that supports dynamic superblocks, based on examples disclosed herein.

[0011] Figure 3 This document describes an example of a process flow diagram supporting dynamic superblocks, as illustrated in the examples disclosed herein.

[0012] Figure 4 This describes an example of a memory device that supports dynamic superblocks, based on examples disclosed herein.

[0013] Figure 5 This describes an example of a memory device that supports dynamic superblocks, based on examples disclosed herein.

[0014] Figure 6 A block diagram is shown illustrating a memory controller that supports dynamic superblocks, based on examples disclosed herein.

[0015] Figure 7 and 8 The flowchart illustrates one or more methods that support dynamic superblocks, based on examples disclosed herein. Detailed Implementation

[0016] Non-volatile memory devices may comprise multiple dies (e.g., multiple memory dies), each comprising one or more planes. Each plane may contain one or more blocks, and each block may contain one or more memory cells (e.g., one or more non-volatile memory cells, such as NAND memory cells). In managed NAND (e.g., mNAND) devices, the memory cells may be managed by a memory controller. Managed NAND (e.g., mNAND) devices may use multi-plane writes to achieve higher performance across one or more memory dies. For example, a multi-plane write command can write data in parallel to memory cells across various planes of each memory die. In some instances, superblocks may be created for managed NAND devices during manufacturing. A superblock may contain one or more blocks from multiple planes, which can improve performance during multi-plane write operations. Managed NAND devices may maintain a cursor to indicate the current write position of the superblock. However, the number of superblocks that can be generated may be limited due to defects in the memory, as one or more planes may have a large number of bad blocks.

[0017] This document describes techniques for generating and managing dynamic superblocks across multiple memory dies. In some instances, a controller (e.g., an mNAND controller) can be configured to generate and maintain various superblocks on one or more memory dies. For example, the controller may consider the number of available blocks in a plane and / or maintenance operations performed during superblock generation (e.g., garbage collection, wear leveling, etc.). Thus, when a new cursor is opened (e.g., when a superblock is accessed for the first time, or when switching from writing to the first block to writing to the second block), the controller can build superblocks based on the number of available blocks across various planes and can reuse blocks that have been cleared due to garbage collection or other maintenance operations. The controller can also establish and maintain multiple cursors associated with different performance levels. For example, a first cursor (e.g., a fast cursor) can be maintained to support blocks in each plane of the memory, and a slow cursor to support blocks in less than all planes of the memory. A second cursor can be used for maintenance operations across planes because planes with fewer blocks or more blocks with higher cycles can be skipped. Therefore, by creating and maintaining dynamic superblocks associated with different performance levels, maintenance operations can be performed on some blocks without affecting the overall performance of the memory system.

[0018] First, as referenced Figures 1 to 2 The features of this disclosure are described in the context of the system described. (See references...) Figures 3 to 5 Features of this disclosure are described within the context of the flowcharts and memory devices described herein. These and other features of this disclosure are further illustrated by and described with reference to device diagrams and flowcharts relating to, as referenced... Figures 6 to 8 The described dynamic superblock.

[0019] Figure 1 This describes an instance of a system 100 that supports dynamic superblocks, as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing means.

[0022] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data—and other such operations—generally referred to as access operations at the memory device 130. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or operations related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updates) by the host system 105 according to a caching strategy (e.g., reduced latency relative to memory device 130).

[0029] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions belonging to memory system controller 115 herein. Generally, one or more functions belonging to memory system controller 115 herein may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more commonly referred to as a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations can be performed within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased in parallel as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may be updated only after the entire block 170 containing page 175 has been erased.

[0037] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing both valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0038] System 100 may include any number of non-transitory computer-readable media supporting a dynamic superblock. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0039] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system. For instance, memory system controller 115 may establish one or more superblocks on memory die 160. As described herein, a superblock may comprise at least one block 170 from two or more planes of memory die 160. In some instances, a superblock may be associated with a first cursor (e.g., a performance cursor) or a second cursor (e.g., a non-performance cursor).

[0040] To establish a superblock, the memory system controller 115 may determine the number of available blocks in each plane of the memory die 160, or the number of access operations to be performed on the available blocks in each plane of the memory die 160. Based on this determination, the memory system controller 115 may select at least one block 170 from two or more planes of the memory die 160 to be included in the superblock. Therefore, when the memory system controller 115 receives a command (e.g., a write command, a multi-plane write command), the memory system controller 115 may transmit the command and data to the memory device 130-a. The command may instruct data to be written in parallel to the corresponding blocks of the superblock. By establishing and maintaining a dynamic superblock on the memory die 160, maintenance operations can be performed on some blocks 170 without affecting the overall performance of the memory system 110.

[0041] Figure 2 This describes an instance of system 200 that supports dynamic superblocks, as disclosed in this document. System 200 may be as described in the references. Figure 1 An example of system 100 as described in the description or other aspects thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement references Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0042] Memory system 210 may include memory device 240 to store, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205, as described herein. Memory device 240 may include, as referenced... Figure 1The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0043] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described in the reference. Figure 1 The aspects of the local controller 135 described.

[0044] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to translate data between the host system 205 and the memory device 240 (e.g., as shown by data path 250), and may be collectively referred to as the data path components.

[0045] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling bursts of commands, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators or both, to allow for rapid data storage to and retrieval from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0046] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Additionally, buffer 225 may be a non-cached buffer. That is, the host system 205 cannot directly read data from buffer 225. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0047] The memory system 210 may additionally include a memory system controller 215, which executes commands received from the host system 205 and controls data path components when moving data. The memory system controller 215 may be as described in the reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0048] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. This is advantageous, for example, when the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) may be located anywhere within the memory system 210.

[0049] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0050] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0051] The memory system controller 215 can determine that an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving a command from command queue 260. After, for example, the command has been retrieved from command queue 260 by memory system controller 215, the command can be removed from the command queue. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0052] After confirming that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0053] In either case, the memory system controller 215 may use the buffer 225 (in particular) for temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0054] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0055] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the command stream including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where in buffer 225 the data associated with each command will be stored can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0056] If buffer 225 has sufficient space to store the write data, then memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0057] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 and transfer the data to memory device 240 using data path 250. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0058] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain an entry for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where the data associated with the command is stored in buffer 225; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location of data to be retrieved from buffer 225 from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of stored data in memory device 240 (e.g., performing wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0059] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0060] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, then memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 when data transfer to buffer 225 has been completed.

[0061] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location within the memory device 240 from which data is retrieved from, either from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location within the buffer 225 for storing data from the buffer queue 265. In some cases, the storage controller 230 can obtain the location within the buffer 225 for storing data from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0062] Once data has been stored in buffer 225 by storage controller 230, it can be transferred from buffer 225 to host system 205. For example, storage system controller 215 can enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS or eMMC). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 is complete.

[0063] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can move the data corresponding to the command in and out of buffer 225, as discussed above. While the data is moved into and stored in buffer 225, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), then the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, then the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0064] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more adjacent LBAs may correspond to non-adjacent physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0065] In some instances, the memory system controller 215 may establish one or more superblocks on one or more memory dies of the memory device 240. As described herein, a superblock may contain at least one block from two or more planes of the memory die and may be associated with one or more performance levels. For example, a superblock may be associated with a first cursor (e.g., a performance cursor) or a second cursor (e.g., a non-performance cursor). Whether a superblock is associated with a first or second cursor may depend on the performance criteria received from the host system 205.

[0066] To establish a superblock, the memory system controller 215 may determine the number of available blocks in each plane of the memory die of the memory device 240, or the number of access operations to be performed on the available blocks in each plane of the memory die of the memory device 240. Based on this determination, the memory system controller 215 may select at least one block from two or more planes of the memory die to be included in the superblock. Therefore, when the memory system controller 215 receives a command (e.g., a write command, a multi-plane write command), the memory system controller 215 may transmit the command and data to the memory device 240. The command may instruct data to be written in parallel to the corresponding blocks of the superblock.

[0067] Alternatively, the memory system controller 215 may receive performance criteria from the host system 205. For example, the memory system controller 215 may receive sequential write commands from the host system 205 and may create a superblock associated with a first cursor (e.g., a performance cursor) based on the received sequential write commands. In such instances, the superblock may consist of individual blocks from each plane of the memory die, and data associated with sequential write operations may be written to each block, performing multi-plane writes simultaneously.

[0068] In other instances, the memory system controller 215 may not receive performance criteria from the host system 205 and may create a superblock associated with a second cursor (e.g., a non-performance cursor). In such instances, the superblock may consist of individual blocks from each of a subset of planes from the memory die (e.g., at least one plane may not contain any blocks from the superblock), and write operations may partially (or completely) fill each block. By creating and maintaining dynamic superblocks on the memory die of the memory device 240, maintenance operations can be performed on some blocks while still meeting the performance requirements established by the host system 205.

[0069] Figure 3 This describes an example of a process flow diagram 300 supporting dynamic superblocks, as disclosed herein. Process flow diagram 300 illustrates the operation of host device 305 and memory device 310. Memory device 310 may be an example of a managed memory device (e.g., an mNAND memory device) and may include a memory controller 315, memory dies 320-a (e.g., a first memory die 320-a), and memory dies 320-b (e.g., a second memory die 320-b). In some instances, memory device 310 may include any number of memory dies 320. Process flow diagram 300 illustrates the dynamic creation and maintenance of superblocks, which allows memory device 310 to perform maintenance operations on some memory dies 320 (e.g., some blocks of some memory dies 320) while meeting performance criteria established by host device 305.

[0070] As shown in process flow diagram 300, memory controller 315 may receive one or more commands 322 from host device 305. In some instances, command 322 may include read commands, write commands, or other commands, and may include data also received from host device 305 (e.g., for a write command) or associated with said data. Memory controller 315 may buffer the data (e.g., in buffer 225).

[0071] The memory controller 315 may receive a performance criterion 324 associated with command 322. For example, performance criterion 324 may indicate support for sequential write commands (e.g., command 322). In other instances, performance criterion 324 may indicate the rate at which data is to be written to memory device 310, or it may be another type of criterion used to select a first cursor (e.g., a fast cursor, a performance cursor) when creating a new superblock. The performance criterion may be transmitted from host device 305 to memory device 310 via command 322 (e.g., to memory controller 315), or separately from command 322 (e.g., before command 322).

[0072] At 326, the memory controller 315 may determine the creation of a superblock. In some instances, determining the creation of a superblock may involve or be associated with opening a new cursor. As described herein, a cursor may point to a location where data received from the host device 305 is written. Furthermore, a superblock may refer to a logical grouping of blocks managed by firmware (e.g., the firmware of the memory controller 315) within one or more memory dies 320. For example, a superblock may contain at least one block from at least two planes contained in memory die 320-a, memory die 320-b, or both. Therefore, when data (e.g., data associated with writing) is received from the host device 305, the memory controller 315 may write the data in parallel to the blocks contained in the superblock (e.g., using multi-plane writing). In some instances, blocks may be selected for the superblock based on various criteria discussed below.

[0073] The memory controller 315 can manage the superblock based on a first cursor (e.g., a fast cursor, a performance cursor) or a second cursor (e.g., a non-performance cursor). Whether the memory controller 315 manages the superblock based on the first or second cursor may depend on whether any performance criteria are received from the host device 305. For example, if the host device 305 indicates a sequential write command for data 334, then the memory controller 315 may determine to build the superblock based on the first cursor. Alternatively, if the host device 305 does not indicate any performance criteria, then the memory controller 315 may determine to build the superblock based on the second cursor. The memory controller 315 may maintain multiple active cursors (e.g., one performance cursor and one non-performance cursor).

[0074] In some instances, memory controller 315 may determine the creation of a superblock (e.g., at 326) based on the number of available blocks in each plane of memory die 320-a, memory die 320-b, or both. For example, if a plane contains a threshold number of available blocks, then memory controller 315 may (e.g., for a superblock) select blocks within the plane. Available blocks can refer to any block that is not bad or filled with data (e.g., contains no valid data or has been erased). If a plane does not contain a threshold number of available blocks, then memory controller 315 may avoid selecting blocks from a particular plane for a superblock until one or more maintenance operations, such as garbage collection, are performed on the blocks of the plane. Once maintenance operations have been performed on the blocks of the plane, and the plane contains a threshold number of available blocks, those blocks can be included in the subsequently created superblock.

[0075] In other instances, memory controller 315 may determine the creation of a superblock (e.g., at 326) based on the number of access operations performed on available blocks within each plane of memory dies 320-a, 320-b, or both. For example, if the number of access operations performed on the block meets a threshold, memory controller 315 may (e.g., for a superblock) select a block within the plane. The number of access operations may reflect the number of certain access operations, such as program operations and erase operations, and may exclude one or more access operations that may not cause cell degradation, such as read operations. Alternatively, access operations may be associated with a weighting factor, and the number of access operations may be a weighted number (e.g., program or erase operations may be weighted higher than read operations). If the number of access operations performed on a particular block does not meet a threshold (e.g., if the block is used more often than other blocks), memory controller 315 may avoid selecting a block for a superblock until one or more maintenance operations, such as wear leveling, are performed on the blocks of memory die 320. Once maintenance operations are performed on a block (or blocks), and the number of access operations performed on that block meets a threshold for access operations (e.g., relative to other blocks), the block can be included in a subsequently generated superblock.

[0076] Memory controller 315 may transmit signaling 330 to memory dies 320-a and 320-b. In some instances, signaling 330 may be transmitted sequentially or in parallel by memory controller 315 and may be in response to determining the creation of a superblock (e.g., at 326). Signaling 330 may contain the following commands (e.g., read commands, write commands), requests, or other types of communication: for determining the number of available blocks in each plane of memory dies 320-a, memory dies 320-b, or both, or for determining the number of access operations to be performed on the available blocks in each plane of memory dies 320-a, memory dies 320-b, or both. Signaling 330 may return from memory dies 320-a, memory dies 320-b, or both to indicate (e.g., to memory controller 315) the number of access operations to be performed on the available blocks of memory dies 320 or the number of available blocks in each memory die 320. In some instances, signaling 330 may be omitted, and information (e.g., the number of available blocks, the number of access operations performed on available blocks in each plane of memory die 320) may be maintained by memory controller 315.

[0077] At 332, the memory controller 315 may select blocks to be included in the superblock. The memory controller 315 may select blocks based on signaling 330 between the memory controller 315 and memory dies 320-a and 320-b, and whether any performance criteria are received from the host device 305. In some instances, the memory controller 315 may select blocks from a plane containing a threshold number of available blocks and / or blocks that satisfy a threshold number of access operations (e.g., blocks with fewer than the threshold number of access operations). Alternatively or additionally, the number of blocks selected for the superblock may be based on whether any performance criteria are received from the host device 305. That is, if a performance criterion is received, then the memory controller 315 may select blocks for the superblock from each plane of memory dies 320-a and / or memory dies 320-b. In other instances, if no performance criteria are received, then the memory controller 315 may select a smaller number of blocks for the superblock (e.g., one block from each of a subset of the planes of memory dies 320-a and 320-b).

[0078] As the first example, and for reference Figure 4 The memory controller 315 may receive instructions for sequential write operations from the host device 305 (e.g., in performance criterion 324). Figure 4This describes an example of a memory device 400 supporting dynamic superblocks, as disclosed herein. The memory device 400 may include memory dies 405-a (e.g., a first memory die 405-a) and memory dies 405-b (e.g., a second memory die 405-b). In some instances, memory die 405-a may include one or more planes 410, each containing one or more blocks, and memory die 405-b may include one or more planes 415, each containing one or more blocks. Furthermore, each block of memory die 405-a and each block of memory die 405-b may be located within row 417. The memory device 400 may dynamically establish one or more superblocks, which allows the memory device 400 to perform maintenance operations on some memory dies 405 (e.g., some blocks of some memory dies 405) while meeting performance criteria established by the host device. Memory dies 405-a and 405-b can correspond to memory dies 320-a and 320-b, respectively.

[0079] like Figure 4 As shown, memory device 400 may include a first memory die 405-a, which includes planes 410-a to 410-f. Although six (6) planes are described, the first memory die 405-a may contain any number of planes. Each plane of the first memory die 405-a may contain multiple blocks. For simplicity, each plane is described as containing eight (8) blocks associated with rows 417a to 417-h. Although eight (8) blocks are described, the first memory die 405-a may contain any number of blocks, including tens, hundreds, or thousands of blocks. Each block may contain one or more pages (e.g., one or more pages of data) and may be configured to store a certain amount of data, such as 16KB of data.

[0080] In some instances, blocks in the planes of the first memory die 405-a and the second memory die 405-b may be usable, may be contained in a specific superblock, may be associated with maintenance operations, or may be bad blocks. For example, block 420 may be usable, block 425 may be associated with maintenance operations, block 430 may be associated with the first superblock, block 435 may be associated with the second superblock, and block 440 may be a bad block.

[0081] Therefore, as referenced Figure 4As described, memory controller 315 may determine to establish a superblock based on a first cursor (e.g., at 326). The superblock associated with the first cursor may contain blocks 435 from each plane of the respective memory die 405. Block 420 may be available in the superblock as described herein. In some instances, a block may be available due to the type and / or amount of data stored in the corresponding block, the number of access operations performed on the corresponding block, or due to a recent maintenance operation (e.g., garbage collection). For example, a block that does not contain any stored data (or contains a relatively small amount of stored data), a block that has not yet undergone a relatively large number of access operations, or a block that is available because old or invalid data has recently been removed during garbage collection may be available in the superblock. For illustrative purposes, block 420 may be available in subsequent superblocks (such as, referenced in...). Figure 5 In the superblock described.

[0082] In some instances, block 440 may not be usable in a superblock. Block 440 may have deteriorated during manufacturing or other processes, rendering it unusable for storage. However, as described herein, other blocks in the same plane as bad block 440 may be usable in a superblock, thus not unduly limiting the number of superblocks the memory controller can build.

[0083] Therefore, for illustrative purposes, a superblock may contain blocks 435 from each plane of memory die 405-a and from each plane of memory die 405-b. In some instances, although each memory die 405 may contain six (6) planes, memory die 405 may contain any number of planes.

[0084] Alternatively, the memory controller 315 may determine that each plane of each memory die 405 contains a threshold number of available blocks and / or that blocks 435 selected for the superblock are associated with a threshold number of access operations. In some cases, if one or more planes of the memory die 405 do not contain a threshold number of available blocks, or if some blocks are not associated with a threshold number of access operations, then one or more maintenance operations may be performed before the superblock is created.

[0085] Block 430 may be contained within a first superblock associated with a first cursor (e.g., a performance cursor). As described herein, a superblock may be associated with a performance cursor based on one or more performance criteria received from the host device. Furthermore, the superblock associated with a performance cursor may contain a block from each plane of one or more memory dies 405. For example, the first superblock may contain block 430 as listed in Table 1.

[0086]

[0087]

[0088] Table 1

[0089] As a second example, and referring to Figure 4 The memory controller 315 may not receive performance criteria 324 from the host device 305. Therefore, the memory controller 315 may determine to establish a superblock based on a second cursor (e.g., at 326). The superblock associated with the second cursor may contain blocks 435 from each of a subset of the planes of the memory die 405. That is, for illustrative purposes, the superblock may contain a number of blocks 435 less than the total number of planes contained in memory dies 405-a and 405-b. In some instances, although each memory die 405 may contain six (6) planes, the memory die 405 may contain any number of planes.

[0090] When selecting block 435 for the superblock, memory controller 315 may determine that some planes do not contain a threshold number of available blocks and / or that block 430 selected for the superblock does not meet the threshold number of access operations. For example, due to a plane not containing a threshold number of available blocks, or due to available blocks not meeting the threshold number of access operations (e.g., having more than the threshold number of access operations), memory controller 315 may avoid selecting blocks from planes 415-d and 415-e. In some cases, if one or more planes of memory die 405 do not meet the threshold number of available blocks, or if some blocks do not meet the threshold number of access operations, one or more maintenance operations may be performed before the subsequent superblock is built.

[0091] Block 435 may be contained within a second superblock associated with the second cursor (e.g., a non-performance cursor). As described herein, a superblock not associated with a performance cursor may contain a block from a subset of the planes of one or more memory dies 405. For example, the second superblock may contain block 435 as listed in Table 2.

[0092] flat OK 410-a 417-a 410-b 417-a 410-c 417-b 410-d 417-g 410-e 417-d 410-f 417-d 415-a 417-e 415-b 417-c 415-c 417-c 415-d none 415-e none 415-f 417-c

[0093] Table 2

[0094] Therefore, as shown in Table 2, the second superblock may not contain any blocks in planes 415-d or 415-e. Thus, when a write command is received from the host device, data can be written in parallel to each block in the second superblock. In some instances, the amount of data to be written to blocks in the second superblock may be relatively small, such that each block is not completely filled with data. This allows for relatively few write operations, followed by periods of idle time for memory device 400, or periods of synchronization for caches (e.g., caches associated with memory device 400). Furthermore, the superblock associated with the second cursor may allow skipping some planes (e.g., planes 415-d and 415-e) to enable wear leveling or other maintenance operations.

[0095] When a superblock is created, host device 305 may transfer data 334 to memory device 310. Memory controller 315 may buffer the data. Memory controller 315 may transfer signaling 336 to memory dies 320-a and 320-b. In some instances, signaling 336 may be transferred sequentially or in parallel by memory controller 315 and may be in response to receiving data 334 from host device 305. Signaling 336 may include commands (e.g., read commands, write commands), requests, or other types of communication for writing data to the superblock.

[0096] In response to received data, data can be written in parallel to each block of the first superblock. In some instances, data can be written to blocks such that each block is completely filled with data. For example, multiple write commands can be received from the host device, and multiple write operations (e.g., multiple multi-plane write operations) can be performed on each block of the first superblock. After a certain number of write operations (e.g., greater than or equal to one (1)), the superblock may be full. When the superblock is full (e.g., completely filled), the memory controller can open a new cursor corresponding to the new superblock. In some instances, maintenance operations can be performed on one or more blocks of the first superblock after the new cursor (and subsequent superblocks) are opened.

[0097] For example, signaling 336 may include a write command for writing data to a superblock associated with memory dies 320-a and 320-b. Therefore, if the superblock is associated with a first cursor, data can be written in parallel to each block, such that pages of each block are written along with portions of the data. In other instances, if the superblock is associated with a second cursor, a smaller amount of data can be received and written in parallel to the blocks of the superblock, such that each block receives a portion of the data. In either instance (e.g., whether the superblock is associated with the first or second cursor), data can be written evenly across each block of the superblock (e.g., the same number of pages can be written in each block).

[0098] The memory controller 315 may transmit maintenance signaling 340 to memory die 320-a. Maintenance signaling 340 may initiate one or more maintenance operations to be performed at 342. Similarly, the memory controller 315 may transmit maintenance signaling 344 to memory die 320-b, initiating one or more maintenance operations to be performed at 346. In some instances, maintenance operations may be performed on memory dies 320-a and 320-b at any time, and are therefore described as occurring after data has been written to memory dies 320-a and 320-b for illustrative purposes only.

[0099] In some instances, block 425 may undergo or experience maintenance operations. As described herein, maintenance operations may be performed on block 425, such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. In some instances, maintenance operations may be performed on blocks containing old or invalid data, or on blocks associated with a relatively high number of access operations (e.g., blocks that do not contain a threshold number of access operations). Performing maintenance operations makes the associated blocks available for inclusion in subsequent superblocks. For illustrative purposes, it is shown as undergoing or experiencing as referenced. Figure 4 Some of the maintenance operations described in block 425 can be used and / or included in the reference. Figure 5 In the superblock described.

[0100] Maintenance operations performed on memory dies 320-a and 320-b may include operations such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. In some instances, maintenance operations may be performed on blocks containing old or invalid data, or on blocks associated with a relatively small number of access operations (e.g., blocks that meet a threshold number of access operations). Performing maintenance operations makes the associated blocks available for inclusion in subsequent superblocks. For illustrative purposes, and with reference to… Figure 4As described, the memory controller 315 can perform maintenance operations on block 425, thus making block 425 available for inclusion in a subsequent superblock.

[0101] In some instances, the memory controller 315 may initiate one or more maintenance operations on memory die 320-a or memory die 320-b based on the amount of valid data written to the respective blocks. For example, the memory controller 315 may initiate a garbage collection operation on blocks containing a relatively small amount of valid data (e.g., in contrast to blocks with a relatively large amount of valid data). This type of garbage collection operation (e.g., “greedy” garbage collection) may consume less time compared to a garbage collection operation performed on blocks with a relatively large amount of valid data, which can improve the overall efficiency of the memory device 310.

[0102] The memory controller 315 may receive one or more additional commands 348 from the host device 305. In some instances, the commands may include read commands, write commands, or other commands. For example, command 348 may include a sequential write command.

[0103] At 350, memory controller 315 may determine to establish a second superblock. In some instances, determining to establish a superblock may involve or be associated with opening a new cursor. In some instances, the cursor may be opened in response to data written to the superblock via signaling 336. As described herein, memory controller 315 may manage the second superblock based on a first cursor (e.g., a fast cursor, a performance cursor) or a second cursor (e.g., a non-performance cursor). Furthermore, memory controller 315 may determine to establish the second superblock (e.g., at 350) based on the number of available blocks in each plane of memory dies 320-a, 320-b, or both, or based on the number of access operations performed on available blocks in each plane of memory dies 320-a, 320-b, or both. Thus, the second superblock may include blocks that were previously unavailable but became available due to maintenance operations performed at 342 and 346.

[0104] Memory controller 315 may transmit signaling 352 to memory dies 320-a and 320-b. In some instances, signaling 352 may be transmitted sequentially or in parallel by memory controller 315 and may be in response to determining the creation of a second superblock (e.g., at 350). Signaling 352 may contain the following commands (e.g., read commands, write commands), requests, or other types of communication: for determining the number of available blocks in each plane of memory dies 320-a, memory dies 320-b, or both, or for determining the number of access operations to be performed on the available blocks in each plane of memory dies 320-a, memory dies 320-b, or both. Signaling may be returned from memory dies 320-a, memory dies 320-b, or both to indicate (e.g., to memory controller 315) the number of access operations to be performed on the available blocks of memory dies 320 or the number of available blocks in each memory die 320. In some instances, signaling 352 may be omitted, and information (e.g., the number of available blocks, the number of access operations performed on available blocks in each plane of memory die 320) may be maintained by memory controller 315 (e.g., possibly previously read from different locations in memory die 320-a, memory die 320-b, or different memory dies 320).

[0105] At 356, the memory controller 315 can select blocks to be included in the second superblock. The memory controller 315 can select blocks based on signaling 352 communicating with memory dies 320-a and 320-b, and whether any performance criteria are received from the host device 305. In some instances, the memory controller 315 can select blocks from a plane of available blocks that meet a threshold number and / or blocks that meet a threshold number of access operations. Alternatively or additionally, the number of blocks selected for the superblock can be based on whether any performance criteria are received from the host device 305.

[0106] With the help of examples, and reference Figure 5 The memory controller 315 may not receive performance criteria from the host device 305. Figure 5 This describes an example of a memory device 500 supporting dynamic superblocks, as disclosed herein. The memory device 500 may include memory dies 505-a (e.g., a first memory die 505-a) and memory dies 505-b (e.g., a second memory die 505-b), and may illustrate a memory device 400 after which maintenance operations are performed at 342 and 346 and a block is selected for the second superblock at 356 (e.g., memory die 505-a may correspond to memory die 405-a, and memory die 505-b may correspond to memory die 405-b).

[0107] like Figure 5As shown, memory device 500 may include a first memory die 505-a, which includes planes 510-a to 510-f. Although six (6) planes are described, the first memory die 505-a may contain any number of planes. Each plane of the first memory die 505-a may contain multiple blocks. For example, each plane may contain eight (8) blocks associated with rows 517-a to 517-h. Although eight (8) blocks are described, the first memory die 505-a may contain any number of blocks. Each block may contain one or more pages (e.g., one or more pages of data) and may be configured to store a certain amount of data, such as 16KB of data.

[0108] In some instances, blocks in the planes of the first memory die 505-a and the second memory die 505-b may be usable, may be contained in a specific superblock, may be associated with maintenance operations, or may be bad blocks. For example, block 520 may be usable, block 525 may be associated with maintenance operations, block 530 may be associated with the first superblock, block 535 may be associated with the second superblock, and block 540 may be a bad block. In some instances, memory device 500 may be as described in the reference... Figure 4 The described memory device 400 is an example, but has undergone one or more maintenance operations. Furthermore, Figure 5 This can indicate the new superblock created after the maintenance operation was performed.

[0109] As described herein, block 520 may be available in a superblock. In some instances, a block may be available due to the type and / or amount of data stored in the block, the number of access operations performed on the block, or a recent maintenance operation (e.g., garbage collection). For example, a block that does not contain any stored data (or contains a relatively small amount of stored data), a block that has not yet undergone a relatively large number of access operations, or a block that is available because old or invalid data was recently removed during garbage collection may be available in a superblock. For illustrative purposes, block 520 may be available in subsequent superblocks.

[0110] In some instances, block 540 may not be usable in a superblock. Block 540 may have deteriorated during manufacturing or other processes, rendering it unusable for storage. However, as described herein, other blocks in the same plane as bad block 540 may be usable in a superblock, thus not unduly limiting the number of superblocks the memory controller can build.

[0111] As the first example, and for reference Figure 5The memory controller 315 may receive instructions for sequential write operations from the host device 305 and may determine to create a superblock based on a first cursor (e.g., at 350). Block 530 may be included in the superblock associated with the first cursor (e.g., a performance cursor). As described herein, the superblock may be associated with the performance cursor based on one or more performance criteria received from the host device. Furthermore, the superblock associated with the performance cursor may contain one block from each plane of one or more memory dies 505. For example, the superblock may contain blocks 530 listed in Table 1. Some blocks included in the superblock may have undergone maintenance operations and therefore may not be as described in the references. Figure 4 The available blocks are described.

[0112] flat OK 510-a 517-e 510-b 517-d 510-c 517-c 510-d 517-f 510-e 517-b 510-f 517-b 515-a 517-c 515-b 517-g 515-c 517-g 515-d 517-h 515-e 517-a 515-f 517-d

[0113] Table 1

[0114] Therefore, as referenced Figure 5 As described, memory controller 315 may determine to establish a superblock based on a second cursor (e.g., at 350). The superblock associated with the second cursor may contain blocks 535 from a subset of the planes of memory die 505. That is, for illustrative purposes, the superblock may contain a number of blocks 535 less than the total number of planes contained in memory dies 505-a and 505-b. Furthermore, due to an ongoing garbage collection operation (e.g., at 342), at least one block (e.g., the block located at row address 517-f in plane 510-a) may be included in the second superblock. That is, the block located at row address 517-f in plane 510-a may not be used to select for inclusion in the previously established superblock (e.g., at 332).

[0115] Block 535 may be contained within another superblock associated with the second cursor (e.g., a non-performance cursor). As described herein, a superblock not associated with a performance cursor may contain a block from a subset of the planes of one or more memory dies 505. For example, the second superblock may contain block 535 as listed in Table 2. Some blocks contained within a superblock may have undergone maintenance operations and therefore may not be as described in the references. Figure 4 The available blocks are described.

[0116] flat OK 510-a 517-f 510-b 517-e 510-c none 510-d 517-a 510-e 517-d 510-f none 515-a 517-e 515-b 517-b 515-c 517-b 515-d none 515-e none 515-f 517-c

[0117] Table 2

[0118] Therefore, as shown in Table 2, the second superblock may not contain any of the blocks in planes 510-c, 510-f, 515-d, or 515-e. Thus, when a write command is received from the host device, data can be written in parallel to each block in the second superblock. This allows for relatively few write operations followed by periods of idle time for memory device 500 or periods of synchronization with caches (e.g., caches associated with memory device 500). Furthermore, the superblock associated with the second cursor may allow skipping some planes (e.g., planes 510-c, 510-f, 515-d, and 515-e) to enable wear leveling or other maintenance operations.

[0119] The host device 305 can transfer data 358 to the memory device 310. The memory controller 315 can transfer signaling 360 to memory dies 320-a and 320-b. In some instances, signaling 360 can be transmitted sequentially or in parallel by the memory controller 315, and can be in response to receiving data from the host device 305 (e.g., at 358). Signaling 360 can include commands (e.g., read commands, write commands), requests, or other types of communication for writing data to a superblock.

[0120] For example, the signaling may include a write command for writing data to a second superblock associated with memory dies 320-a and 320-b. Therefore, if the superblock is associated with a first cursor, data can be written to each block using multi-plane write operations that access each plane of memory die 320 in parallel, such that portions of the data are stored in each block of the superblock. That is, data can be spread across blocks of the superblock. In other instances, if the superblock is associated with a second cursor, data can be written to each block using multi-plane write operations that access a subset of the planes of memory die 320 in parallel. In either instance (e.g., whether the superblock is associated with the first or second cursor), data can be written uniformly across each block of the superblock (e.g., the same number of pages in each block of the superblock).

[0121] In some instances, data can be written to blocks such that each block is completely filled with data. For example, multiple write commands can be received from the host device, and multiple write operations (e.g., multiple multi-plane write operations) can be performed on each block of the first superblock. After a certain number of write operations (e.g., greater than or equal to one (1)), the superblock may be full. When the superblock is full (e.g., completely filled), the memory controller can open a new cursor corresponding to the new superblock. In some instances, maintenance operations can be performed on one or more blocks of the first superblock after the new cursor (and subsequent superblocks) are opened. By creating and maintaining dynamic superblocks on the memory die of memory device 310, maintenance operations can be performed on some blocks while still meeting the performance requirements established by host device 305.

[0122] Figure 6 A block diagram 600 illustrates a memory controller 620 supporting dynamic superblocks, based on an example disclosed herein. The memory controller 620 may be as described in the references... Figures 1 to 5 Examples of aspects of the described memory controller. Memory controller 620 or its various components may be examples of means for performing various aspects of a dynamic superblock as described herein. For example, memory controller 620 may include a determining component 625, a selecting component 630, a receiving component 635, a transmitting component 640, an establishing component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0123] The determining component 625 may be configured or otherwise support a superblock for determining, at least in part, based on one or more commands received from a host device, a first set of two or more blocks comprising a plurality of planes, wherein the superblock is associated with multi-plane write operations for the memory. In some instances, to support the selection of a corresponding block for the superblock from each of at least two of the plurality of planes, the determining component 625 may be configured or otherwise support a component for determining the number of available blocks within each plane. In some instances, to support the selection of a corresponding block for the superblock from each of at least two of the plurality of planes, the determining component 625 may be configured or otherwise support a component for determining the number of access operations to be performed on the available blocks within each plane.

[0124] Selection component 630 may be configured or otherwise supported to support components for selecting a corresponding block for a superblock from each of at least two of a plurality of planes, at least in part based on a determined superblock. In some instances, to support selecting a corresponding block for a superblock from each of at least two of a plurality of planes, selection component 630 may be configured or otherwise supported to support components for selecting a corresponding block from each plane having a threshold number of available blocks. In some instances, to support selecting a corresponding block for a superblock from each of at least two of a plurality of planes, selection component 630 may be configured or otherwise supported to support components for avoiding selecting blocks from planes that do not contain a threshold number of available blocks.

[0125] In some instances, to support the selection of a corresponding block for a superblock from each of at least two of a plurality of planes, selection component 630 may be configured or otherwise supported to support components for selecting a corresponding block from each plane that failed to meet a threshold number of access operations performed. In some instances, selection component 630 may be configured or otherwise supported to support components for selecting a corresponding block for a superblock from each of at least two of a plurality of planes, at least in part based on an indication of received performance requirements.

[0126] In some instances, selection component 630 may be configured or otherwise support a component for selecting a first block associated with a first block address from a first plane among a plurality of planes used for write operations. In some instances, selection component 630 may be configured or otherwise support a component for selecting a second block associated with a second block address from a second plane among a plurality of planes used for write operations, wherein the first block address is different from the second block address. In some instances, selection component 630 may be configured or otherwise support a component for selecting a first block associated with a first block address from a first plane among a plurality of planes for a superblock, and selecting a second block associated with a second block address from a second plane among a plurality of planes, or both.

[0127] In some instances, selection component 630 may be configured or otherwise support components for a first superblock, the first superblock comprising at least one block from a plane of a first memory die and at least one block from a plane of a second memory die. In some instances, selection component 630 may be configured or otherwise support components for a second superblock, the second superblock comprising at least one block from each plane of the first memory die and at least one block from each plane of the second memory die.

[0128] In some instances, when selecting a first superblock for a first write operation, selection component 630 may be configured or otherwise support a component for selecting a first block from a first plane based at least in part on a threshold number of available blocks in the first plane. In some instances, when selecting a first superblock for a first write operation, selection component 630 may be configured or otherwise support a component for selecting a second block from a second plane based at least in part on a threshold number of available blocks in the second plane. In some instances, when selecting a first superblock for a first write operation, selection component 630 may be configured or otherwise support a component for selecting a third block from a third plane based at least in part on a third plane that does not contain a threshold number of available blocks.

[0129] The receiving component 635 may be configured or otherwise supported to support means for receiving data from a host device for writing to memory. In some instances, the receiving component 635 may be configured or otherwise supported to support means for receiving an indication of performance requirements for data from a host device. In some instances, the receiving component 635 may be configured or otherwise supported to support means for receiving first data associated with a first performance level for writing to memory after the establishment of a first superblock. In some instances, the receiving component 635 may be configured or otherwise supported to support means for receiving second data associated with a second performance level for writing to memory after the establishment of a second superblock.

[0130] The transfer component 640 may be configured or otherwise support means for transferring commands and data to memory, wherein the commands instruct data to be written in parallel to corresponding blocks of a superblock. In some instances, the transfer component 640 may be configured or otherwise support means for transferring second commands and third data to memory before determining the establishment of a superblock containing two or more blocks of memory, wherein determining the establishment of a superblock containing two or more blocks of memory is at least partially based on the completion of writing the third data to memory. In some instances, the transfer component 640 may be configured or otherwise support means for transferring to memory a first command and first data for performing a first write operation on a first superblock, and a second command and second data for performing a second write operation on a second superblock.

[0131] The establishment component 645 may be configured or otherwise support components for establishing a first superblock associated with a first performance level, the first superblock comprising a first block from a first plane of a plurality of planes of memory and a second block from a second plane of a plurality of planes of memory. In some instances, the establishment component 645 may be configured or otherwise support components for establishing a second superblock associated with a second performance level, the second superblock comprising a corresponding block from each of the plurality of planes of memory. In some instances, the establishment component 645 may be configured or otherwise support components for establishing a third superblock associated with a first performance level, the third superblock comprising blocks excluding the first or second plane.

[0132] Figure 7 The flowchart illustrates a method 700 supporting dynamic superblocks based on examples disclosed herein. The operation of method 700 can be implemented by a memory controller or its components as described herein. For example, it can be implemented by a memory controller as described in the references... Figures 1 to 6 The memory controller described performs the operations of method 700. In some instances, the memory controller may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0133] At 705, the method may include determining, at least in part, based on one or more commands received from a host device, a superblock comprising a first set of two or more blocks of memory, the memory comprising multiple planes, wherein the superblock is associated with multi-plane write operations for the memory. The operation at 705 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described aspect is how component 625 performs the operation of 705.

[0134] At 710, the method may include selecting a corresponding block for the superblock from each of at least two of a plurality of planes, at least in part based on determining the establishment of the superblock. The operation at 710 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described aspect is the selection component 630 to perform the operation of 710.

[0135] At 715, the method may include receiving data from a host device for writing to memory. The operation at 715 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 6 The described aspect of receiving component 635 performing the operation of 715.

[0136] At 720, the method may include transferring commands and data to memory, wherein the commands instruct data to be written in parallel to the corresponding blocks of the superblock. The operation at 720 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described transmission component 640 performs the operation of 720.

[0137] In some instances, the device as described herein may perform one or more methods, such as method 700. The device (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) may include features, circuitry, logic, components, or instructions for: determining, at least in part, based on one or more commands received from a host device, a superblock comprising two or more blocks of memory, the memory comprising a plurality of planes, wherein the superblock is associated with multi-plane write operations for the memory; selecting a corresponding block for the superblock from each of at least two of the plurality of planes, at least in part, based on determining the establishment of the superblock; receiving data from the host device for writing to the memory; and transmitting commands and data to the memory, wherein the commands instruct data to be written in parallel to the corresponding blocks of the superblock.

[0138] In some instances of the method 700 and apparatus described herein, selecting a corresponding block for a superblock from each of at least two of a plurality of planes may include operations, features, circuitry, logic, components, or instructions for determining the number of available blocks in each plane and selecting a corresponding block from each plane which may have a threshold number of available blocks.

[0139] In some instances of the method 700 and device described herein, selecting a corresponding block for a superblock from each of at least two of a plurality of planes may include operations, features, circuitry, logic, components, or instructions for avoiding selecting blocks from available blocks that do not contain a threshold number.

[0140] In some instances of the method 700 and apparatus described herein, selecting a corresponding block for a superblock from each of at least two of a plurality of planes may include operations, features, circuitry, logic, components, or instructions for determining the number of access operations to be performed on the available blocks in each plane and selecting a corresponding block from each plane that fails to meet the threshold number of access operations performed.

[0141] Some examples of the method 700 and apparatus described herein may further include an indication for receiving performance requirements for data from a host device, and at least in part based on receiving the performance requirement indication, selecting an operation, feature, circuit, logic, device, or instruction of a corresponding block from each of a plurality of planes for the superblock.

[0142] Some instances of the method 700 and device described herein may further include the following operations, features, circuit systems, logic, components, or instructions: for selecting a first block that can be associated with a first block address from a first plane of a plurality of planes for a write operation and for selecting a second block that can be associated with a second block address from a second plane of a plurality of planes for a write operation, wherein the first block address may be different from the second block address.

[0143] Some instances of the method 700 and apparatus described herein may further include the following operations, features, circuitry, logic, components, or instructions: for determining, at least in part, based on one or more additional commands received from a host device, a second superblock comprising two or more blocks of memory, and for selecting, for the superblock, a first block that can be associated with a first block address from a first plane of a plurality of planes, a second block that can be associated with a second block address from a second plane of a plurality of planes, or both.

[0144] Some examples of the method 700 and apparatus described herein may further include the following operations, features, circuit systems, logic, components, or instructions for transferring second and third data to memory before determining the establishment of a superblock containing two or more blocks of memory, wherein determining the establishment of a superblock containing two or more blocks of memory may be at least partially based on the completion of writing the third data to memory.

[0145] Figure 8 The flowchart illustrates a method 800 supporting dynamic superblocks based on examples disclosed herein. The operation of method 800 can be implemented by a memory controller or its components as described herein. For example, it can be implemented by a memory controller as described in the references... Figures 1 to 6 The memory controller described performs the operations of method 800. In some instances, the memory controller may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0146] At 805, the method may include establishing a first superblock associated with a first performance level, the first superblock comprising a first block from a first plane of a plurality of planes of memory and a second block from a second plane of a plurality of planes of memory. The operation of 805 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described aspect is the creation of component 645 to perform the operation of 805.

[0147] At 810, the method may include establishing a second superblock associated with the second performance level, the second superblock comprising corresponding blocks from each of a plurality of planes of memory. The operation of 810 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described aspect is the creation of component 645 to perform the operations of 810.

[0148] At 815, the method may include transmitting to memory a first command and first data for performing a first write operation on a first superblock, and a second command and second data for performing a second write operation on a second superblock. The operation at 815 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described transmission component 640 performs the operation of 815.

[0149] In some instances, the device as described herein may perform one or more methods, such as method 800. The device (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) may include features, circuitry, logic, components, or instructions for: establishing a first superblock associated with a first performance level, the first superblock comprising a first block from a first plane of a plurality of planes of memory and a second block from a second plane of a plurality of planes of memory; establishing a second superblock associated with a second performance level, the second superblock comprising a corresponding block from each of the plurality of planes of memory; and transmitting to memory a first command and first data for performing a first write operation on the first superblock, and a second command and second data for performing a second write operation on the second superblock.

[0150] Some instances of the method 800 and apparatus described herein may further include the following operations, features, circuit systems, logic, components, or instructions for receiving first data associated with a first performance level for writing to memory after the establishment of a first superblock, and receiving second data associated with a second performance level for writing to memory after the establishment of a second superblock.

[0151] Some instances of the methods 800 and devices described herein may further include the following operations, features, circuit systems, logic, components, or instructions for establishing a third superblock associated with a first performance level, the third superblock containing blocks that can exclude the first plane or the second plane.

[0152] In some instances of the method 800 and device described herein, the second write operation includes a sequential write operation.

[0153] In some instances of the method 800 and apparatus described herein, the method, apparatus, and non-transitory computer-readable medium may include other operations, features, circuitry, logic, components, or instructions for a first superblock and a second superblock, the first superblock comprising at least one block from a plane of a first memory die and at least one block from a plane of a second memory die, and the second superblock comprising at least one block from each plane of the first memory die and at least one block from each plane of the second memory die.

[0154] In some instances of the method 800 and device described herein, selecting a first superblock for a first write operation may include operations, features, circuitry, logic, components, or instructions for: determining the number of available blocks in each plane; selecting a first block from a first plane based at least in part on the first plane containing a threshold number of available blocks; selecting a second block from a second plane based at least in part on the second plane containing a threshold number of available blocks; and avoiding selecting a third block from a third plane based at least in part on the third plane not containing a threshold number of available blocks.

[0155] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0156] Describe an apparatus. The apparatus may include: a memory comprising a plurality of planes, each comprising a plurality of blocks, each of the plurality of blocks comprising a plurality of non-volatile memory cells; and a controller coupled to the memory and operable to: determine, at least in part, based on one or more commands received from a host device, the creation of a superblock comprising two or more blocks of the memory, wherein the superblock is associated with multi-plane write operations for the memory; select a corresponding block for the superblock from each of at least two of the plurality of planes, at least in part based on the determination of the creation of the superblock; receive data from the host device for writing to the memory; and transmit commands and data to the memory, wherein the commands instruct data to be written in parallel to the corresponding blocks of the superblock.

[0157] In some instances, the device may include determining the number of available blocks in each plane and selecting appropriate blocks from each plane that may have a threshold number of available blocks.

[0158] In some instances, the device may include a planar selection block that avoids never including a threshold number of available blocks.

[0159] In some instances, the device may include determining the number of access operations to be performed on the available blocks in each plane, and selecting the appropriate block from each plane that fails to satisfy the threshold number of access operations to be performed.

[0160] In some instances, the device may include receiving an indication of performance requirements for data from a host device, and selecting a corresponding block for the superblock from each of a plurality of planes, at least in part based on the received indication of performance requirements.

[0161] In some instances, the device may include selecting a first block from a first plane of a plurality of planes for write operations that can be associated with a first block address, and selecting a second block from a second plane of a plurality of planes for write operations that can be associated with a second block address, wherein the first block address may be different from the second block address.

[0162] In some instances, the device may include determining, at least in part, to establish a second superblock containing two or more blocks of memory based on one or more additional commands received from a host device, and selecting, for the superblock, a first block that can be associated with a first block address from a first plane of a plurality of planes, a second block that can be associated with a second block address from a second plane of a plurality of planes, or both.

[0163] In some instances, the device may include transferring second and third data to memory before determining the establishment of a superblock containing two or more blocks of memory, wherein determining the establishment of a superblock containing two or more blocks of memory may be at least partially based on the completion of writing the third data to memory.

[0164] In some instances of the device, the memory comprises a plurality of memory dies, and the superblock comprises at least one block of a plane from a first memory die among the plurality of memory dies, and at least one block of a plane from a second memory die among the plurality of memory dies.

[0165] In some instances, the device may include transferring a first portion of the data to be written to a first block of the superblock, and transferring a second portion of the data to be written to a second block of the superblock, wherein the first and second portions contain the same amount of data.

[0166] In some instances, the device may include performing one or more maintenance operations on at least a third block from one of a plurality of planes, wherein the third block may be included in a superblock, and the one or more maintenance operations include: erasing the third block; determining, at least in part, based on one or more additional commands received from a host device, to establish a second superblock comprising two or more blocks of memory after transmitting data and commands for the superblock; and selecting, at least in part, appropriate blocks for the second superblock from at least two of the plurality of planes based on the determination to establish the second superblock, wherein the third block may be included in the second superblock.

[0167] Describing another device. The device may include: a memory comprising a plurality of planes, each plane comprising a plurality of blocks, each containing a plurality of non-volatile memory cells; and a controller coupled to the memory, wherein the controller is operable to: establish a first superblock associated with a first performance level, the first superblock comprising a first block from a first plane of the plurality of planes of the memory and a second block from a second plane of the plurality of planes of the memory; establish a second superblock associated with a second performance level, the second superblock comprising a corresponding block from each of the plurality of planes of the memory; and transmit to the memory a first command and first data for performing a first write operation on the first superblock, and a second command and second data for performing a second write operation on the second superblock.

[0168] In some instances, the device may include receiving first data associated with a first performance level for writing to memory after the establishment of a first superblock, and receiving second data associated with a second performance level for writing to memory after the establishment of a second superblock.

[0169] In some instances, the device may include a third superblock that establishes a first performance level, the third superblock containing blocks that can exclude the first or second plane.

[0170] In some instances of the device, the second write operation includes sequential write operations.

[0171] In some instances of the device, the first superblock comprises at least one block from a plane of the first memory die and at least one block from a plane of the second memory die, and the second superblock comprises at least one block from each plane of the first memory die and at least one block from each plane of the second memory die.

[0172] In some instances, the device may include: determining the number of available blocks in each plane; selecting a first block from a first plane based at least in part on the first plane containing a threshold number of available blocks; selecting a second block from a second plane based at least in part on a second plane containing a threshold number of available blocks; and avoiding selecting a third block from a third plane based at least in part on a third plane not containing a threshold number of available blocks.

[0173] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, where the bus may have various bit widths.

[0174] The terms “electrical communication,” “conductive contact,” “connection,” and “coupling” can refer to the relationship between components that enables the flow of signals between them. Components are considered to be electrically communicating with each other (or electrically contacting each other, or connected to each other, or coupled to each other) if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between electrically connected (or electrically contacting, connected, or coupled) components can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used, for example, to interrupt the flow of signals between the connected components for a period of time.

[0175] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then that component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0176] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, then the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0177] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms are interchangeable if they are used to describe a connection between a conditional action, a conditional process, or parts of a process.

[0178] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0179] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other condition or action.

[0180] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0181] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0182] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or illustration" and is not necessarily "preferred" or "advantageous over other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0183] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0184] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that parts of the functions are implemented in different physical locations.

[0185] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0186] As used herein, the word "or," as used in the claims, as in a list of items (e.g., a list followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0187] Computer-readable media includes both non-transitory computer storage media and communication media that include any media facilitating the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0188] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory comprising multiple planes, each comprising multiple blocks, each of the multiple blocks containing multiple non-volatile memory cells; and A controller, coupled to the memory and operable to: The establishment of a superblock comprising two or more blocks of the memory is determined at least in part based on one or more commands received from the host device, wherein the superblock is associated with a multi-plane write operation for the memory; The appropriate block is selected for the superblock from each of at least two of the plurality of planes that failed to meet the threshold number of access operations performed, based at least in part on the determination of establishing the superblock; Receive data from the host device for writing to the memory; and The command and the data are transmitted to the memory, wherein the command instructs the data to be written in parallel to the corresponding block of the superblock.

2. The device according to claim 1, wherein, In order to select the corresponding block for the superblock from each of at least two of the plurality of planes, the controller may operate to: Determine the number of available blocks in each plane; and Select the appropriate block from each plane that has a threshold number of available blocks.

3. The device according to claim 2, wherein, In order to select the corresponding block for the superblock from each of at least two of the plurality of planes, the controller may operate to: Avoid selecting blocks from planes that do not contain the threshold number of available blocks.

4. The device according to claim 1, wherein the controller is operable to: Determine the number of access operations to be performed on the available blocks in each plane.

5. The device according to claim 1, wherein the controller is operable to: Receive from the host device an indication of the performance requirements for the data; and The appropriate block for the superblock is selected from each of the plurality of planes, at least in part, based on the instruction received regarding the performance requirements.

6. The device according to claim 1, wherein, In order to select the corresponding block for the superblock from each of at least two of the plurality of planes, the controller may operate to: Select a first block associated with a first block address from the first plane of the plurality of planes used for writing the data; and A second block is selected from the second plane of the plurality of planes used for writing the data, and the second block is associated with the second block address, wherein the first block address is different from the second block address.

7. The device of claim 6, wherein the controller is operable to: The creation of a second superblock comprising two or more blocks of the memory is determined, at least in part, based on one or more additional commands received from the host device; and For the superblock, select the first block associated with the first block address from the first plane of the plurality of planes, select the second block associated with the second block address from the second plane of the plurality of planes, or both.

8. The device of claim 1, wherein the controller is operable to: Before determining the creation of the superblock comprising the two or more blocks of the memory, the second command and the third data are transmitted to the memory, wherein determining the creation of the superblock comprising the two or more blocks of the memory is based at least in part on the completion of writing the third data to the memory.

9. The device according to claim 1, wherein: The memory comprises multiple memory dies, and The superblock includes at least one block of a plane from a first memory die among the plurality of memory dies and at least one block of a plane from a second memory die among the plurality of memory dies.

10. The device of claim 1, wherein transmitting the data to the memory comprises: The first portion of the data to be written is transferred to the first block of the superblock; and The second portion of the data to be written is transferred to the second block of the superblock, wherein the first portion and the second portion comprise the same amount of data.

11. The device of claim 1, wherein the controller is operable to: Perform one or more maintenance operations on at least a third block from one of the plurality of planes, wherein the third block is contained in the superblock and the one or more maintenance operations include erasing the third block; The establishment of a second superblock comprising two or more blocks of the memory is determined, at least in part, based on one or more additional commands received from the host device, after the transmission of the data and commands for the superblock. and At least in part, a corresponding block is selected for the second superblock from at least two of the plurality of planes based on the determination to establish the second superblock, wherein the third block is contained within the second superblock.

12. An apparatus comprising: The memory includes multiple planes, each plane including multiple blocks each containing multiple non-volatile memory cells; and A controller, coupled to the memory, wherein the controller is operable to: Receive performance criteria from the host system; Establish a first superblock associated with a first performance level, the first superblock comprising at least in part a first block from a first plane of the plurality of planes of the memory and a second block from a second plane of the plurality of planes of the memory, based on the performance criteria received; A second superblock is established in association with the second performance level, the second superblock comprising at least in part a corresponding block based on each of the plurality of planes from the memory that have received the performance criteria; and The memory is transmitted a first command and first data for performing a first write operation on the first superblock, and a second command and second data for performing a second write operation on the second superblock.

13. The device of claim 12, wherein the controller is operable to: After establishing the first superblock, the first data associated with the first performance level is received for writing to the memory; and After the second superblock is established, the second data associated with the second performance level is received for writing to the memory.

14. The device of claim 12, wherein the controller is operable to: A third superblock is established in association with the first performance level, the third superblock comprising blocks that exclude the first plane or the second plane.

15. The device of claim 14, wherein the second write operation comprises a sequential write operation.

16. The device of claim 12, wherein the memory comprises a plurality of memory dies, wherein: The first superblock comprises at least one block from a plane of a first memory die and at least one block from a plane of a second memory die; and The second superblock comprises at least one block from each plane of the first memory die and at least one block from each plane of the second memory die.

17. The device according to claim 12, wherein, In order to select the first superblock for the first write operation, the controller may operate to: Determine the number of available blocks in each plane; The first block is selected from the first plane based at least in part on the fact that the first plane contains a threshold number of available blocks; The second block is selected from the second plane at least in part based on the fact that the second plane contains the threshold number of available blocks; and The selection of a third block from the third plane is avoided at least in part because the third plane does not contain the threshold number of available blocks.

18. A non-transitory computer-readable medium storing code, comprising instructions that, when executed by a processor of a memory device, cause the memory device to: The creation of a superblock comprising a first set of two or more blocks of memory, including multiple planes, is determined at least in part based on one or more commands received from a host device, wherein the superblock is associated with multi-plane write operations for the memory; The appropriate block is selected for the superblock from each of at least two of the plurality of planes that failed to meet the threshold number of access operations performed, based at least in part on the determination of establishing the superblock; Receive data from the host device for writing to the memory; and The command and the data are transmitted to the memory, wherein the command instructs the data to be written in parallel to the corresponding block of the superblock.

19. The non-transitory computer-readable medium of claim 18, wherein, in order to select the corresponding block for the superblock from each of the at least two of the plurality of planes, the instructions, when executed by the processor of the memory device, further cause the memory device to: Determine the number of available blocks in each plane; and Select the appropriate block from each plane that has a threshold number of available blocks.

20. The non-transitory computer-readable medium of claim 19, wherein, in order to select the corresponding block for the superblock from each of the at least two of the plurality of planes, the instructions, when executed by the processor of the memory device, further cause the memory device to: Avoid selecting blocks from planes that do not contain the threshold number of available blocks.

21. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: Determine the number of access operations to be performed on the available blocks in each plane.

22. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: Receive from the host device an indication of the performance requirements for the data; and The appropriate block for the superblock is selected from each of the plurality of planes, at least in part, based on the instruction received regarding the performance requirements.

23. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: Select a first block associated with a first block address from the first plane of the plurality of planes used for writing the data; and A second block is selected from the second plane of the plurality of planes used for writing the data, and the second block is associated with the second block address, wherein the first block address is different from the second block address.

24. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: The establishment of a second superblock comprising two or more blocks of the memory is determined, at least in part, based on one or more additional commands received from the host device; and For the superblock, select the first block associated with the first block address from the first plane of the plurality of planes, select the second block associated with the second block address from the second plane of the plurality of planes, or both.

25. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: Before determining the creation of the superblock comprising the two or more blocks of the memory, the second command and the third data are transmitted to the memory, wherein determining the creation of the superblock comprising the two or more blocks of the memory is based at least in part on the completion of writing the third data to the memory.

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