Data remapping method based on receiving card, receiving card and electronic equipment

Abstract

The present invention discloses a data remapping method based on a receiving card, a receiving card, and an electronic device. The method, applied to the receiving card, comprises: acquiring data transmitted through a network port and writing the data into a first cache area of an SDRAM; determining the length of data written to a second cache area of the SDRAM each time based on the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data; and sequentially writing data from the first cache area to the second cache area based on the data length to achieve data remapping in the receiving card. The method can segment the data written to the second cache area of the SDRAM based on the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data, thereby improving the problem of large block RAM resource waste in the FPGA of the receiving card and enhancing the SDRAM reading efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of LED display, and in particular to a data remapping method based on a receiving card, a receiving card and an electronic device. Background Art

[0002] Due to the characteristics of the LED driver chip, the screen brightness is too high, typically around 0.2cd / m², which does not meet customer requirements. Furthermore, the current grayscale accuracy of LED displays is insufficient, making it difficult to repair low-grayscale grayscale fluctuations. Therefore, improving the grayscale accuracy of LED displays (i.e., using grayscale expansion) is generally used to enhance the display quality. Using grayscale expansion to increase contrast increases the BlockRam memory in the receiving card, which can lead to insufficient resources for the receiving card's FPGA. In addition, the higher the number of light points in the area used for grayscale expansion (shaking screen function), the more block Ram resources will be occupied. Take the data remapping of the 4*4 area (there are also other expansion areas such as 8*8) as an example. In the SDRAM of the receiving card, the width of the written data in the storage area of the SDRAM receiving data is 32 bits, and the width of the read data in the storage area sending data to the screen is 48 bits. When the total SDRAM data storage is 96 bits, if the width is 32 bits, the number of pixels written is 3, and if the width is 48 bits, the number of pixels read is 2. The 3*4 (4 rows of data in the area) = 12 pixel alignment used for writing (when the total SDRAM data storage is 128 bits, 16 pixel alignment is used), and the 2*4 = 8 pixel alignment used for reading will result in data loss. When 12 alignment is used, the data needs to be padded with 12 (invalid data is padded). When 8 alignment is used, since the padded data does not match, the complete 4*4 = 16 pixels of data will be discarded in each row, which will waste block. RAM storage resources (the above problem exists because the total number of pixels is not a multiple of 96, so there is a pixel misalignment problem). In addition, the data read from the SDRAM is read from each chip's 16 signal pins one by one, and the data is read in jumps (for example, after reading one data from one row, jump to the second row to read another data, etc.), resulting in the SDRAM needing to wrap the data when reading. The cost of SDRAM wrapping is high, which in turn wastes the SDRAM reading efficiency.

[0003] Therefore, people in this field are in urgent need of finding a new technical solution to solve the above problems. Summary of the Invention

[0004] In order to overcome the problems existing in the related art, the present invention discloses a data remapping method based on a receiving card, a receiving card and an electronic device.

[0005] According to a first aspect of the disclosed embodiments of the present invention, a data remapping method based on a receiving card is provided, which is applied to the receiving card. The method includes:

[0006] Acquire data transmitted by the network port and write the data into the first cache area of the SDRAM;

[0007] Determining the length of data written to the second cache area in the SDRAM each time according to the remaining amount of memory in the BlockRAM and the efficiency of the SDRAM in reading data;

[0008] The data is sequentially written from the first buffer area to the second buffer area according to the data length, so as to realize the remapping of the data in the receiving card.

[0009] Optionally, determining the length of data written to the second cache area in the SDRAM each time according to the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data includes:

[0010] Determine the remaining memory in the SDRAM based on the efficiency of reading data from the SDRAM and the memory already occupied in the SDRAM;

[0011] The length of data written into the second cache area in the SDRAM each time is determined according to the remaining memory in the SDRAM and the remaining memory in the BlockRAM.

[0012] Optionally, after writing the data from the first cache area into the second cache area in sequence according to the data length, the method further includes:

[0013] After each data is written into the second buffer area, 1 bit of end information is added after each written data.

[0014] The first cache area includes a first ping cache area and a first pong cache area, the second cache area includes a second ping cache area and a second pong cache area, and acquiring data transmitted by the network port and writing the data into the first cache area of the SDRAM includes:

[0015] Acquire data transmitted by the network port and write the data into a first ping buffer area of a first buffer area of an SDRAM, and then write the data from the first ping buffer area into the first pong buffer area through a pingpong process;

[0016] Writing data from the first cache area to the second cache area in sequence according to the data length includes:

[0017] The data is sequentially written from the first pong buffer area into the second ping buffer area according to the data length, and then the data is written from the second ping buffer area into the second pong buffer area through pingpong processing.

[0018] Optionally, writing the data from the first cache area to the second cache area in sequence according to the data length includes:

[0019] Determining a data remapping table representing a mapping relationship between data written each time and a row number in the second cache area according to the length of data written each time into the second cache area in the SDRAM;

[0020] The data is written into the row number corresponding to the second cache area according to the data remapping table.

[0021] Optionally, the method further includes:

[0022] Get data reading instructions;

[0023] Data of each data length is read sequentially from the second buffer area according to the data length.

[0024] Optionally, the method further includes:

[0025] The data read from the second buffer area each time is sent to each signal pin of the driver chip according to a preset routing table, so as to display the data on the LED display screen.

[0026] According to a second aspect of the disclosed embodiments of the present invention, a receiving card is provided, the receiving card comprising:

[0027] A data acquisition module, which acquires data transmitted by the network port and writes the data into the first cache area of the SDRAM;

[0028] A data length determination module is connected to the data acquisition module and determines the length of data written to the second cache area in the SDRAM each time according to the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data;

[0029] The remapping module is connected to the data length determination module and writes data from the first buffer area to the second buffer area in sequence according to the data length to achieve remapping of the data in the receiving card.

[0030] Optionally, the receiving card further includes: an instruction acquisition module and a data reading module;

[0031] An instruction acquisition module, connected to the remapping module, for acquiring a data reading instruction;

[0032] A data reading module is connected to the instruction acquisition module and reads data of each data length from the second cache area in sequence according to the data length.

[0033] According to a third aspect of the disclosed embodiments of the present invention, there is provided an electronic device, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0034] Memory for storing instructions executable by the processor;

[0035] The processor is configured to implement the steps of the data remapping method based on the receiving card described in the first aspect of the embodiment disclosed in the present invention when executing the instructions stored in the memory.

[0036] In summary, the present invention discloses a data remapping method based on a receiving card, a receiving card, and an electronic device. The method, applied to the receiving card, comprises: acquiring data transmitted via a network port and writing the data into a first cache area of an SDRAM; determining the length of data to be written to a second cache area of the SDRAM at each time based on the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data; and sequentially writing data from the first cache area to the second cache area based on the data length to achieve data remapping in the receiving card. The data written to the second cache area of the SDRAM can be segmented based on the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data, thereby improving the problem of large block RAM resource waste in the FPGA of the receiving card and increasing the SDRAM reading efficiency.

[0037] Other features and advantages disclosed in the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0039] Figure 1 is a flow chart showing a data remapping method based on a receiving card according to an exemplary embodiment;

[0040] Figure 2 is based on Figure 1 A flow chart of a method for determining data length is shown;

[0041] Figure 3 is based on Figure 1 A flow chart of another data remapping method based on a receiving card is shown;

[0042] Figure 4 is based on Figure 3 A flow chart of another data remapping method based on a receiving card is shown;

[0043] Figure 5 is a structural block diagram of a receiving card according to an exemplary embodiment;

[0044] Figure 6 is based on Figure 5 Another structural block diagram of a receiving card is shown;

[0045] Figure 7 The figure is a schematic structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0046] The following is a detailed description of the specific embodiments disclosed in the present invention in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0047] Figure 1 is a flow chart showing a data remapping method based on a receiving card according to an exemplary embodiment, which is applied to a receiving card, such as Figure 1 As shown, the method includes:

[0048] In step 101, data transmitted by a network port is acquired and written into a first cache area of an SDRAM.

[0049] For example, under normal circumstances, SDRAM receives the video data sent from the FPGA network port (located in the receiving card) and writes the data into the cache area of ​​SDRAM, so that when a data read instruction is received later, the data will be sent to the driver chip (column driver chip) in the LED light board for display on the LED display screen.

[0050] In step 102, the length of data written into the second cache area in the SDRAM each time is determined according to the remaining amount of memory in the BlockRAM and the efficiency of the SDRAM in reading data.

[0051] For example, an SDRAM includes a first cache area (i.e., the area with a 32-bit width for writing data) and a second cache area (i.e., the area with a 48-bit width for reading data). Because the number of pixel alignments in the first and second cache areas differs, when pixel padding is performed in the first cache area and then the padded data is written to the second cache area, data loss occurs due to the different data alignments, wasting Block RAM storage resources. In the disclosed embodiments of the present invention, the length of data written from the first cache area to the second cache area is determined based on the remaining memory in the Block RAM and the efficiency of SDRAM data reading.

[0052] Specifically, Figure 2 is based on Figure 1 A flow chart of a method for determining data length is shown in FIG. Figure 2 As shown, step 102 includes:

[0053] In step 1021, the remaining memory in the SDRAM is determined according to the efficiency of reading data from the SDRAM and the memory already occupied in the SDRAM.

[0054] In step 1022, the length of data written into the second cache area in the SDRAM each time is determined according to the remaining memory in the SDRAM and the remaining memory in the BlockRAM.

[0055] For example, under normal circumstances, there is at least one row decoding chip and one column driver chip in an LED light board, and the row and column intersections formed by the row decoding chip and the column driver chip connect the light points. The receiving card in the embodiment disclosed in the present invention is connected to at least one driver chip. Under normal circumstances, the first cache area of the SDRAM includes a first ping cache area and a first pong cache area, and the second cache area of the SDRAM includes a second ping cache area and a second pong cache area. After obtaining the data transmitted by the network port, the data is temporarily stored through the Block RAM, and the data is written to the first ping cache area of the first cache area of the SDRAM. Before the data is written from the first ping cache area to the first pong cache area through the pingpong process, the data also needs to be temporarily stored through the Block RAM. Similarly, before writing the data from the first pong cache area to the second ping cache area in sequence according to the data length, and before writing the data from the second ping cache area to the second pong cache area through the pingpong process, the data needs to be temporarily stored through the Block RAM first. That is, during the process of SDRAM reading and writing data, at least four BlockRAMs participate in the processing, which are used to store data before entering the first ping buffer area, the first pong buffer area, the second ping buffer area and the second pong buffer area respectively.

[0056] Block RAM (Block Random Access Memory) is a fixed resource within the FPGA, offering fast access speeds but small capacity. Synchronous Dynamic Random Access Memory (SDRAM) is a type of dynamic random access memory with a synchronous interface. It waits for a clock signal before responding to control inputs, allowing it to synchronize with the computer's system bus. It boasts large capacity and low price.

[0057] In the disclosed embodiment of the present invention, with reference to the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data, the staff sets the requirements for reading and writing data. For example, if the occupied memory in the BlockRAM is 3 EBRs and the remaining memory is 12 EBRs, and the efficiency of the SDRAM in reading data is 15 EBRs, and the remaining memory in the BlockRAM is 3 EBRs, then the data length written to the first channel ping buffer each time can be set to 3 EBRs. In this way, the occupancy of the EBR in the SDRAM can also be reduced. Among them, EBR (embedded block RAM) is an embedded random access memory, and 1 EBR = 16k = 16x1024bit.

[0058] In step 103, data is sequentially written from the first buffer area to the second buffer area according to the data length, so as to achieve remapping of data in the receiving card.

[0059] Each time data is written into the second cache area, 1 bit of end information is appended after each written data.

[0060] For example, after determining the length of data written to the second cache area each time, the arrangement order of the data in a very long row of data can be changed to achieve the goal of writing out the aggregation (since the data stored in the second cache area needs to be sent to the driver chip connected to the receiving card according to the data reading instruction in accordance with the following steps 301-303, the arrangement order of the data corresponding to the signal pins in the driver chip in the data is rearranged in order to make the data in the same data segment, that is, the aggregation point, be the data on the same signal pin in the driver chip).

[0061] For example, if the data width carried by the receiving card is 1024 pixels per row, and each pixel is 48 bits, the 4 rows of pixel data in the receiving card will need to occupy 4*1024*48 bits of bandwidth, that is, 12 EBRs. If segmentation is implemented, if the data width contained in each data segment after segmentation is 256 pixels per row, the 4 rows of pixel data in the receiving card will need to occupy 4*256*48 bits = 1024*48 bits of bandwidth, requiring only 3 EBRs. Alternatively, if the data width contained in each data segment after segmentation is 512 pixels per row, the 4 rows of pixel data in the receiving card will need to occupy 4*512*48 bits of bandwidth, requiring only 6 EBRs.

[0062] It can be understood that the first cache area includes a first ping cache area and a first pong cache area, and the second cache area includes a second ping cache area and a second pong cache area. The acquisition of data transmitted by the network port and writing the data into the first cache area of the SDRAM includes: acquiring data transmitted by the network port and writing the data into the first ping cache area of the first cache area of the SDRAM, and then writing the data from the data in the first ping cache area into the first pong cache area through pingpong processing; writing the data into the second cache area in sequence from the first cache area according to the data length includes: writing the data into the second ping cache area in sequence from the first pong cache area according to the data length, and then writing the data from the data in the second ping cache area into the second pong cache area through pingpong processing.

[0063] For example, pingpong is a data caching method that can improve data transmission efficiency. When exchanging data between two modules (or two cache areas), the results of the previous level's processing cannot be immediately processed by the next level. Therefore, the previous level must wait for the next level's processing to complete before sending new data, which significantly reduces performance. Therefore, by defining ping and pong cache areas, when data comes in, the process responsible for writing to the buffer (cache area) searches for the first unoccupied and writable buffer (cache area) to write to. After writing, it releases the occupied flag and sets a flag indicating that the buffer is readable. It then searches for another writable buffer to write the new data. Similarly, the process reading data first checks the buffer status. If it finds that the buffer is unoccupied and readable, it retrieves the data from the buffer and marks it as writable.

[0064] In addition, a data remapping table representing the mapping relationship between the data written each time and the row number in the second cache area is determined according to the length of the data written each time in the second cache area in the SDRAM; and the data is written to the row number corresponding to the second cache area according to the data remapping table.

[0065] Normally, when writing data in the first cache area to the second cache area, it is necessary to refer to the data mapping table, which specifies which row of the second cache area the data in the first cache area is written to (i.e., determines the row number corresponding to the data). After determining the length of data written to the second cache area each time through the above steps 101-102, we need to determine which row of the second cache area the data is located in each time the data is written from the first cache area to the second cache area. At this time, we need to refer to the data remapping table. It can be understood that the data remapping table is equivalent to dividing the original data remapping mapping table into several segments (which may be of unequal length because of the relationship between row and table extraction, that is, determining the segmentation according to the number of chips).

[0066] Furthermore, as can be understood from steps 301-303, there is a mapping relationship between the data in the second cache area and the various signal pins on the driver chips. Specifically, each data segment written according to the data length corresponds to a signal pin in the driver chip. For example, a written data segment may include data on the first signal pin of the first driver chip and data on the first signal pin of the second driver chip, data on the second signal pin of the first driver chip and data on the second signal pin of the second driver chip, data on the third signal pin of the first driver chip and data on the third signal pin of the second driver chip, ... data on the sixteenth signal pin of the first driver chip and data on the sixteenth signal pin of the second driver chip. This achieves the goal of writing clusters. For two driver chips, there are 32 pixel data corresponding to signal pins (numbered 1-16 on the first driver chip and 1-16 on the second driver chip), i.e., 32 clusters, with each two cluster points representing data corresponding to the same numbered signal pins on both driver chips, thus reducing block RAM resource waste. Alternatively, in the case of 4 driver chips, there are 64 signal pins, that is, 64 point clusters, and every 4 clustered points represent the pixel data corresponding to the signal pins with the same number; in the case of 8 driver chips, there are 128 point clusters, and every 8 clustered points represent the pixel data corresponding to the signal pins with the same number; in the case of 16 driver chips, there are 256 clusters, and every 16 point clusters represent the pixel data corresponding to the signal pins with the same number in the driver chips; in the case of 32 driver chips, there are 512 point clusters, and every 32 point clusters represent the pixel data corresponding to the signal pins with the same number.

[0067] Preferably, if 8-pixel alignment is adopted (reading 8 pixels), then 128-point aggregation is better (16 signal pins, the total segmented aggregation length is 8*16); if 16-pixel alignment is adopted (reading 16 pixels), then 256-point aggregation is better.

[0068] Therefore, when clustering in the horizontal direction (4*4 mode, i.e., an area consisting of 4×4 light points after grayscale expansion), 3 EBRs basically meet the requirements, and when clustering in the horizontal direction (8*8 mode, i.e., an area consisting of 8*8 light points on the LED display after grayscale expansion), 6 EBRs basically meet the requirements. At the same time, when reading data in the horizontal direction, it reads data in multiples of 8 by sorting each signal pin (sorting each signal channel), such as reading 8 points of data first, then reading 8 points of data, etc. In the vertical direction, clustering is performed in the form of multiples of 8 points of data groups, and clustering is performed based on the width of a module unit.

[0069] The specific aggregation situation is shown in Table 1:

[0070] Table 1

[0071]

[0072] In addition, the embodiment disclosed in the present invention uses the horizontal routing of the LED display screen as an example for explanation. If the routing of the LED display screen is a vertical routing method during actual application, the vertical routing method can be converted into a horizontal routing method, and then the data in the receiving card can be remapped using the method disclosed in the embodiment of the present invention. The specific conversion method is to set parameters in the upper computer software, and convert the horizontal routing table into a vertical routing table by setting the parameters, that is, to rotate the horizontal routing table to obtain a vertical routing table; In addition, if the routing of the LED display screen in the embodiment disclosed in the present invention is a horizontal routing method, the routing can also be performed in the form of one scan as a complete line or in the form of multiple scans as a complete line;

[0073] Figure 3 is based on Figure 1 Another data remapping method based on a receiving card is shown in the flowchart, Figure 3 As shown, the method includes:

[0074] In step 301, a data read instruction is obtained.

[0075] In step 302, data of each data length is read sequentially from the second cache area according to the data length.

[0076] For example, after receiving a data read instruction, the receiving card sequentially reads the data in the second pong buffer area of the SDRAM and sends the data to the corresponding driver chip signal pins in step 303. Finally, the data is displayed on an LED display connected to the receiving card. For example, when the receiving card is connected to two driver chips, the sequentially read data is sent to signal pin 1 of the two driver chips, signal pin 2 of the two driver chips, signal pin 3 of the two driver chips, and so on, to signal pin 16 of the two driver chips.

[0077] Figure 4 is based on Figure 3 A flow chart of another data remapping method based on a receiving card is shown, as shown in FIG. Figure 4 As shown, the method further includes:

[0078] In step 303, the data read from the second buffer area each time is sent to each signal pin of the driver chip according to a preset routing table, so as to display the data on the LED display screen.

[0079] For example, a routing table, i.e., a table of the transmission order of data on the light points of an LED display screen, reflects the transmission order of the video on the light points. Therefore, the data read from the SDRAM in sequence needs to be displayed on the LED display screen according to the routing table.

[0080] Figure 5 is a structural block diagram of a receiving card according to an exemplary embodiment. Figure 5 As shown, the receiving card is connected to at least two driver chips, and the receiving card 500 includes:

[0081] A data acquisition module 510 acquires data transmitted by the network port and writes the data into the first cache area of the SDRAM;

[0082] A data length determination module 520 is connected to the data acquisition module 510 and determines the length of data written to the second cache area in the SDRAM each time according to the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data;

[0083] The remapping module 530 is connected to the data length determining module 520 and writes the data from the first buffer area to the second buffer area in sequence according to the data length, so as to realize the remapping of the data in the receiving card.

[0084] Figure 6 is based on Figure 5 Another receiving card structure diagram is shown, such as Figure 6 As shown, the receiving card 500 further includes: an instruction acquisition module 540 and a data reading module 550;

[0085] An instruction acquisition module 540 is connected to the remapping module 530 and acquires a data read instruction;

[0086] The data reading module 550 is connected to the instruction acquisition module 540 and reads data of each data length from the second cache area in sequence according to the data length.

[0087] Figure 7 FIG. 1 is a schematic structural diagram of an electronic device according to an exemplary embodiment. Figure 7 As shown, it includes a processor 001, a communication interface 002, a memory 003 and a communication bus 004, wherein the processor 001, the communication interface 002, and the memory 003 communicate with each other through the communication bus 004.

[0088] Memory 003, used for storing computer programs;

[0089] The processor 001 is configured to implement the above-mentioned data remapping method based on the receiving card when executing the program stored in the memory 003. The method includes:

[0090] Acquire data transmitted by the network port and write the data into the first cache area of the SDRAM;

[0091] Determine the length of data written into the second cache area in the SDRAM each time according to the remaining amount of memory in the BlockRAM and the efficiency of the SDRAM in reading data;

[0092] The data is sequentially written from the first buffer area to the second buffer area according to the data length, so as to realize the remapping of the data in the receiving card.

[0093] In summary, the present invention discloses a data remapping method based on a receiving card, a receiving card, and an electronic device. The method, applied to the receiving card, comprises: acquiring data transmitted via a network port and writing the data into a first cache area of an SDRAM; determining the length of data to be written to a second cache area of the SDRAM at each time based on the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data; and sequentially writing data from the first cache area to the second cache area based on the data length to achieve data remapping in the receiving card. The data written to the second cache area of the SDRAM can be segmented based on the remaining memory in the BlockRAM and the efficiency of the SDRAM in reading data, thereby improving the problem of large block RAM resource waste in the FPGA of the receiving card and increasing the SDRAM reading efficiency.

[0094] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the scope of protection of the present disclosure.

[0095] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0096] In addition, the various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A data remapping method based on a receiving card, characterized in that: Applied to a receiving card, the method includes: Acquire data transmitted by the network port and write the data into the first cache area of the SDRAM; Determining the length of data written to the second cache area in the SDRAM each time according to the remaining amount of memory in the Block RAM and the efficiency of the SDRAM in reading data; writing data from the first buffer area to the second buffer area in sequence according to the data length, so as to achieve remapping of data in the receiving card; Writing data from the first cache area to the second cache area in sequence according to the data length includes: determining a data remapping table representing a mapping relationship between the data written each time and the row number in the second cache area according to the length of the data written each time to the second cache area in the SDRAM; and writing the data to the row number corresponding to the second cache area according to the data remapping table.

2. The data remapping method based on the receiving card according to claim 1, characterized in that: The step of determining the length of data written into the second cache area in the SDRAM each time according to the remaining amount of memory in the BlockRAM and the efficiency of the SDRAM in reading data includes: Determine the remaining memory in the SDRAM based on the efficiency of reading data from the SDRAM and the memory already occupied in the SDRAM; The length of data written into the second cache area in the SDRAM each time is determined according to the remaining memory in the SDRAM and the remaining memory in the Block RAM.

3. The data remapping method based on the receiving card according to claim 1, characterized in that: After sequentially writing data from the first cache area into the second cache area according to the data length, the method further includes: After each data is written into the second buffer area, 1 bit of end information is added after each written data.

4. The data remapping method based on the receiving card according to claim 1, characterized in that: The first cache area includes a first ping cache area and a first pong cache area, the second cache area includes a second ping cache area and a second pong cache area, and acquiring data transmitted by the network port and writing the data into the first cache area of the SDRAM includes: Acquire data transmitted by the network port and write the data into a first ping buffer area of a first buffer area of an SDRAM, and then write the data from the first ping buffer area into the first pong buffer area through a pingpong process; Writing data from the first cache area to the second cache area in sequence according to the data length includes: The data is sequentially written from the first pong buffer area into the second ping buffer area according to the data length, and then the data is written from the second ping buffer area into the second pong buffer area through pingpong processing.

5. The data remapping method based on the receiving card according to claim 1, characterized in that: The method further comprises: Get data reading instructions; Data of each data length is read sequentially from the second buffer area according to the data length.

6. The data remapping method based on the receiving card according to claim 5, characterized in that: The method further comprises: The data read from the second buffer area each time is sent to each signal pin of the driver chip according to a preset routing table, so as to display the data on the LED display screen.

7. A receiving card, characterized in that: The receiving card includes: A data acquisition module, which acquires data transmitted by the network port and writes the data into the first cache area of the SDRAM; A data length determination module is connected to the data acquisition module and determines the length of data written into the second cache area of the SDRAM each time according to the remaining memory in the Block RAM and the efficiency of the SDRAM in reading data; a remapping module, connected to the data length determination module, and writing data from the first buffer area to the second buffer area in sequence according to the data length, so as to realize remapping of data in the receiving card; The remapping module determines a data remapping table representing the mapping relationship between the data written each time and the row number in the second cache area according to the length of the data written each time to the second cache area in the SDRAM; and writes the data into the row number corresponding to the second cache area according to the data remapping table.

8. The receiving card according to claim 7, wherein: The receiving card also includes: an instruction acquisition module and a data reading module; An instruction acquisition module, connected to the remapping module, for acquiring a data reading instruction; A data reading module is connected to the instruction acquisition module and reads data of each data length from the second cache area in sequence according to the data length.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing instructions executable by the processor; The processor is configured to implement the steps of the receiving card-based data remapping method according to any one of claims 1 to 6 when executing instructions stored in the memory.

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