Electro-optical devices and electronic devices

Abstract

An electro-optical device and an electronic device are provided to meet the requirements for miniaturization and high resolution of the electro-optical device. The electro-optical device (10) includes a DA conversion circuit that converts 10 bits of data into an analog voltage and outputs the converted voltage to a data line (14). The DA conversion circuit includes: a first DA conversion circuit (Upb) that converts the upper 5 bits into a voltage and outputs the converted voltage to the data line; a second DA conversion circuit (Lwb) that converts the lower 5 bits into a voltage and outputs the converted voltage to a relay line (14b); a connecting capacitor, one end of which is electrically connected to the second DA conversion circuit and the other end of which is electrically connected to the data line, the first DA conversion circuit including capacitor elements (C5 to C9) corresponding to the upper 5 bits, arranged in the Y direction along the data line, and the second DA conversion circuit including capacitor elements (C0 to C4) corresponding to the lower 5 bits, arranged in the Y direction along the data line.

Description

Technical Field

[0001] The present invention relates to electro-optical devices and electronic equipment. Background Art

[0002] Electro-optical devices that use, for example, OLEDs as display elements are known. OLED stands for Organic Light Emitting Diode. In such electro-optical devices, pixel circuits, including transistors for passing current through the display element, are arranged corresponding to the pixels of the displayed image. The transistors supply a current corresponding to the grayscale level to the display element. As a result, the display element emits light at a brightness corresponding to the current.

[0003] In the electro-optical device, a voltage corresponding to brightness is applied to the gate node of the transistor via the data line. More specifically, data specifying brightness is converted into an analog voltage by a DA converter circuit, and the converted voltage is applied to the data line.

[0004] As such a DA conversion circuit, for example, a technology has been proposed in which a set of switches and capacitors is provided corresponding to each bit, and charging and discharging of the capacitors is controlled by the switches according to each bit (see, for example, Patent Document 1).

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2000-341125

[0006] In recent years, as electro-optical devices are being required to be smaller and have higher resolutions, there has been a problem in that integrating the above-mentioned DA conversion circuit into the electro-optical device requires considerable effort. Summary of the Invention

[0007] An electro-optical device according to one embodiment of the present disclosure includes: a display element provided corresponding to an intersection of a data line and a scan line; and a DA conversion circuit, the DA conversion circuit including: a first DA conversion circuit for converting two or more upper bits of a plurality of bits into a first grayscale voltage, and applying the first grayscale voltage to the data line, the first grayscale voltage corresponding to the two or more upper bits; a second DA conversion circuit for converting some or all of the bits of the plurality of bits other than the two or more upper bits into a second grayscale voltage reflecting some or all of the bits other than the two or more upper bits; and A connection capacitor has one end electrically connected to the second DA conversion circuit and the other end electrically connected to the data line, the first DA conversion circuit having a high-order capacitance element portion, the high-order capacitance element portion corresponding to the two or more high-order bits, including a first capacitance element and a second capacitance element, the first capacitance element and the second capacitance element being arranged in a direction along the data line, and the second DA conversion circuit having a low-order capacitance element portion corresponding to a part or all of the bits other than the two or more high-order bits, including a third capacitance element and a fourth capacitance element, the third capacitance element and the fourth capacitance element being arranged in a direction along the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a perspective view showing the electro-optical device according to the first embodiment.

[0009] Figure 2 This is a block diagram showing the electrical structure of an electro-optical device.

[0010] Figure 3 This is a circuit diagram showing a pixel circuit in an electro-optical device.

[0011] Figure 4 This is a circuit diagram showing a DA conversion circuit in a data signal output circuit.

[0012] Figure 5 This is a diagram showing an equivalent circuit of a DA conversion circuit.

[0013] Figure 6 This is a timing chart showing the operation of the electro-optical device.

[0014] Figure 7 A diagram for explaining the operation of the electro-optical device.

[0015] Figure 8 It is a diagram for explaining the operation of the electro-optical device.

[0016] Figure 9It is a diagram for explaining the operation of the electro-optical device.

[0017] Figure 10 It is a diagram for explaining the operation of the electro-optical device.

[0018] Figure 11 It is a plan view showing the positions of various elements in the electro-optical device.

[0019] Figure 12 It is a plan view showing the arrangement in the pixel circuit.

[0020] Figure 13 This is a diagram showing the arrangement of three columns of components in a data signal output circuit.

[0021] Figure 14 This diagram shows the arrangement of components of one color in a data signal output circuit.

[0022] Figure 15 It is a diagram for explaining the advantages of the above configuration.

[0023] Figure 16 It is a diagram for explaining the advantages of the above configuration.

[0024] Figure 17 It is a plan view showing an example of a capacitive element in a DA conversion circuit.

[0025] Figure 18 It is a plan view showing an example of a capacitive element in a DA conversion circuit.

[0026] Figure 19 It is a plan view showing an example of a capacitive element in a DA conversion circuit.

[0027] Figure 20 It is a plan view showing an example of a capacitive element in a DA conversion circuit.

[0028] Figure 21 It is a plan view showing an example of a capacitive element in a DA conversion circuit.

[0029] Figure 22 It is along Figures 17 to 21 A partial cross-sectional view obtained by cutting along the Pp line in FIG.

[0030] Figure 23 It is along Figures 17 to 21 A partial cross-sectional view obtained by cutting along the Qq line in FIG.

[0031] Figure 24 This is a diagram showing the arrangement of components of one color in a data signal output circuit of the electro-optical device according to the second embodiment.

[0032] Figure 25This is a diagram showing the arrangement of six columns of components in a data signal output circuit of an electro-optical device according to a third embodiment.

[0033] Figure 26 This is a diagram showing the arrangement of components of one color in a data signal output circuit of an electro-optical device according to a fourth embodiment.

[0034] Figure 27 It is a diagram showing a comparative example for comparison with the arrangement in the fourth embodiment.

[0035] Figure 28 It is a diagram for explaining the advantages of the arrangement in the fourth embodiment.

[0036] Figure 29 This is a diagram showing an equivalent circuit of a DA conversion circuit according to a modified example of the present disclosure.

[0037] Figure 30 This is a perspective view showing a head-mounted display using an electro-optical device.

[0038] Figure 31 A diagram showing the optical structure of a head-mounted display.

[0039] Description of labels

[0040] 10: electro-optical device; 12: scanning line; 14, R14, B14, G14: data line; 14b: relay line; 100: display area; 110: pixel circuit; 121~125: transistors; 130: OLED; 140: capacitor element; 300: head-mounted display; 500: DA conversion circuit; Upb: first DA conversion circuit; Lwb: second DA conversion circuit; C0~C9: capacitor element; Cser: capacitor element (connecting capacitor). DETAILED DESCRIPTION

[0041] Hereinafter, an electro-optical device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0042] In addition, in each figure, the size and scale of each part are appropriately different from the actual one. In addition, the embodiment described below is a preferred specific example, and therefore various technically preferred limitations are added, but as long as there is no record of the meaning of the present invention being particularly limited in the following description, the scope of the present invention is not limited to these embodiments.

[0043] [First embodiment]

[0044] Figure 1This is a perspective view of an electro-optical device 10 according to the first embodiment. The electro-optical device 10 is, for example, a microdisplay panel used to display images in a head-mounted display. The electro-optical device 10 includes a plurality of pixel circuits and a driver circuit for driving the pixel circuits. The pixel circuits and driver circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but other semiconductor substrates may also be used.

[0045] The electro-optical device 10 is housed in a frame-shaped housing 192 that opens into the display area 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC stands for Flexible Printed Circuits. The other end of the FPC board 194 is provided with multiple terminals 196 for connecting to a host device (not shown). When the multiple terminals 196 are connected to the host device, image data, synchronization signals, and the like are supplied from the host device via the FPC board 194 to the electro-optical device 10.

[0046] Figure 2 1 is a block diagram showing the electrical structure of the electro-optical device 10. As shown in the figure, the electro-optical device 10 is roughly divided into a power supply circuit 15, a control circuit 30, a data signal output circuit 50, an initialization circuit 60, a display area 100, and a scan line driving circuit 120.

[0047] In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction in the figure to ensure electrical insulation between the scanning lines 12. Note that m and n are integers greater than 2.

[0048] In the display area 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scan lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix with m rows vertically and n columns horizontally in the figure. In the matrix arrangement, to distinguish the rows (lower row), the diagram may sometimes refer to the 1st, 2nd, 3rd, ..., (m-1), and mth row from the top. Similarly, to distinguish the columns (columns), the diagram may sometimes refer to the 1st, 2nd, 3rd, ..., (n-1), and nth column from the left.

[0049] Furthermore, an integer i of 1 to m is used to generally describe the scanning line 12. Similarly, an integer j of 1 to n is used to generally describe the data line 14.

[0050] The control circuit 30 controls each component based on video data Vid and a synchronization signal Sync supplied from the host device. The video data Vid specifies the grayscale level of a pixel in an image to be displayed using 8 bits for each of the three primary colors.

[0051] The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

[0052] In this embodiment, pixels of an image to be displayed correspond one-to-one to pixel circuits 110 in display area 100. On the other hand, the brightness characteristics represented by grayscale levels do not match the luminance of the pixel circuit 110 corresponding to the pixel (more specifically, the luminance characteristics of the OLED included in pixel circuit 110).

[0053] Therefore, in order to make the OLED emit light at a brightness corresponding to the grayscale specified by the image data Vid, the control circuit 30 up-converts 8 bits of the image data Vid into 10 bits, for example, in this embodiment, and outputs the OLED as image data Vdata specifying the brightness of the OLED.

[0054] In such up-conversion, a lookup table is used that stores in advance the correspondence between 8 bits of input video data Vid and 10 bits of output video data Vdata.

[0055] In addition, the control circuit 30 generates various control signals in order to control each component, and the details will be described later.

[0056] The scan line driver circuit 120 is a circuit for driving the pixel circuits 110 arranged in m rows and n columns for each row under the control of the control circuit 30, and outputs various signals. For example, the scan line driver circuit 120 sequentially supplies scan signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), and / Gwr(m) to the scan lines 12 in the 1st, 2nd, 3rd, ..., (m-1), and mth rows. Typically, the scan signal supplied to the scan line 12 in the i-th row is denoted as / Gwr(i).

[0057] Furthermore, the scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), which will be described in detail later.

[0058] The data signal output circuit 50 is a circuit that outputs a data signal having a voltage corresponding to the luminance to the pixel circuit 110 located in the row selected by the scan line driving circuit 120 .

[0059] Specifically, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes selection circuits 520 corresponding to n columns, the first latch circuit group 54 includes first latch circuits L1 corresponding to n columns, and the second latch circuit group 56 includes second latch circuits L2 corresponding to n columns.

[0060] That is, a set of the selection circuit 520 , the first latch circuit L1 , the second latch circuit L2 , and the DA conversion circuit 500 is provided corresponding to each column.

[0061] Here, the j-th column selection circuit 520 instructs the j-th column's first latch circuit L1 to select the j-th column's image data from the image data Vdata output from the control circuit 30. The j-th column's first latch circuit L1 latches the image data Vdata in accordance with this instruction. The j-th column's second latch circuit L2, under control of the control circuit 30, outputs the image data Vdata latched by the j-th column's first latch circuit L1 to the j-th column's DA converter circuit 500 during a write period, described later.

[0062] The DA converter circuit 500 in the jth column converts the image data Vdata output from the second latch circuit L2 in the jth column into an analog voltage data signal, and outputs the analog voltage data signal to the data line 14 in the jth column.

[0063] The initialization circuit 60 is a collection of transistors 66 that correspond one-to-one to the data lines 14. One end of the transistor 66 corresponding to the j-th column is connected to the supply line of the potential Vini, and the other end of the transistor 66 is connected to the data line 14 of the j-th column. Furthermore, the control signal / Gini from the control circuit 30 is commonly supplied to the gate nodes of the transistors 66 in each column.

[0064] The voltages of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are sequentially expressed as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n). Typically, the voltage of the data line 14 in the jth column is expressed as Vd(j).

[0065] The power supply circuit 15 generates various voltages used in the electro-optical device 10. Examples of the various voltages include power supply voltages in the scanning line driving circuit 120 and the data signal output circuit 50, and potentials Vel, Vini, Vorst, Vrst, VL, and VH.

[0066] Figure 3is a circuit diagram showing the pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to each other. Therefore, the pixel circuit 110 located in the i row and j column will be described as a representative.

[0067] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 125, and a capacitor 140. The transistors 121 to 125 are, for example, MOS transistors. MOS is the abbreviation for Metal-Oxide-Semiconductor field-effect transistor.

[0068] In addition to the scanning signal / Gwr(i), the scanning line driving circuit 120 supplies control signals / Gel(i), / Gcmp(i), and / Gorst(i) to the pixel circuit 110 in the i-th row.

[0069] The control signal / Gel(i) is a signal that is a generalization of the control signals / Gel(1), / Gel(2), ..., / Gel(m-1), and / Gel(m) that are sequentially supplied corresponding to the 1st, 2nd, ..., (m-1), and mth rows. Similarly, the control signal / Gcmp(i) is a signal that is a generalization of the control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), and / Gcmp(m) that are sequentially supplied corresponding to the 1st, 2nd, ..., (m-1), and mth rows. The control signal / Gorst(i) is similarly a signal that is a generalization of the control signals / Gorst(1), / Gorst(2), ..., / Gorst(m-1), and / Gorst(m) that are sequentially supplied corresponding to the 1st, 2nd, ..., (m-1), and mth rows.

[0070] The OLED 130 is a light-emitting element formed by sandwiching a light-emitting functional layer 132 between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is light-transmissive.

[0071] In the OLED 130 , when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby generating white light.

[0072] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective, semi-transmissive layer (not shown), and is emitted at a resonant wavelength set to correspond to one of the colors R (red), G (green), or B (blue). A color filter corresponding to the color is provided on the light emitting side of the optical resonator. Therefore, the light emitted from OLED 130 is colored by the optical resonator and the color filter and is perceived by the observer.

[0073] In addition, the optical resonator is omitted from the illustration. In addition, when the electro-optical device 10 displays only a monochrome image of light and dark, the color filter is omitted.

[0074] In the transistor 121 of the pixel circuit 110 in the i-th row and j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116, which is a power supply wiring supplied with the potential Vel, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. One end of the capacitor 140 is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitor 140 maintains the voltage between the gate node g and the source node s of the transistor 121.

[0075] Alternatively, the other end of the capacitor 140 may be connected to another power supply line other than the power supply line 116 , the voltage of which is maintained substantially constant.

[0076] In this embodiment, a so-called MOS capacitor, formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer and a gate electrode layer of the transistor, is used as capacitor 140. Alternatively, a parasitic capacitor at gate node g of transistor 121 or a so-called metal capacitor formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used as capacitor 140.

[0077] In the transistor 122 of the pixel circuit 110 in the i-th row and the j-th column, the gate node is connected to the scan line 12 in the i-th row, and the source node is connected to the data line 14 in the j-th column. In the transistor 123 of the pixel circuit 110 in the i-th row and the j-th column, the gate node is supplied with the control signal / Gcmp(i), and the drain node is connected to the data line 14 in the j-th column. In the transistor 124 of the pixel circuit 110 in the i-th row and the j-th column, the gate node is supplied with the control signal / Gel(i), and the drain node is connected to the pixel electrode 131 serving as the anode of the OLED 130 and the drain node of the transistor 125.

[0078] In the transistor 125 of the pixel circuit 110 in the i-th row and j-th column, the control signal / Gorst(i) is supplied to the gate node, and the source node is connected to a power supply wiring, ie, a power supply line, supplied with a potential Vorst.

[0079] The potential Vorst is, for example, the potential Gnd, which is a reference for zero voltage, or a lower potential close to the potential Gnd. Specifically, the potential Vorst is a potential such that no current flows through the OLED 130 when applied to the pixel electrode 131 of the OLED 130 .

[0080] Furthermore, a potential Vct is applied to the common electrode 133 functioning as a cathode of the OLED 130 .

[0081] Figure 4 is a circuit diagram showing the DA conversion circuit 500 corresponding to the j-th column.

[0082] The DA converter circuit 500 in the jth column is supplied with bits D0 to D9 by the second latch circuit L2 in the jth column, with control signals Enb0 to Enb9 and a control signal / Rst by the control circuit 30 , and with potentials Vrst, VH, and VL by the power supply circuit 15 .

[0083] Furthermore, the potentials VH and VL are in the relationship of VH>VL.

[0084] Bits D0 to D9 are 10 bits of image data output from the second latch circuit L2 of the jth column. The least significant bit of the 10 bits is set to D0, and the weights of the bits D0 and D1, D2, ... are increased in sequence, with the most significant bit being set to D9.

[0085] Control signals Enb0 to Enb9 are signals for sequentially designating the timing of taking in bits D0 to D9, and control signal / Rst is a signal for resetting the capacitive element.

[0086] As shown in the figure, the DA conversion circuit 500 includes capacitors C0 to C9, Cser, a switch Rsw, and voltage selection circuits 510 to 519. Capacitors C0 to C9 and voltage selection circuits 510 to 519 are paired as follows, corresponding to each bit. Specifically, for bit D0, voltage selection circuit 510 is paired with capacitor C0, for bit D1, voltage selection circuit 511 is paired with capacitor C1, and similarly, for bit D9, voltage selection circuit 519 is paired with capacitor C9. Voltage selection circuits 510 to 519 select a potential of either VH or VL and apply the selected voltage to one end of the corresponding capacitor.

[0087] For example, voltage selection circuit 510 corresponding to bit D0 receives bit D0 at a timing specified by control signal Enb0, selects potential VH or VL according to the logic level of received bit D0, and applies the selected voltage to one end of capacitor element C0. Furthermore, voltage selection circuit 516 corresponding to bit D6 receives bit D6 at a timing specified by control signal Enb6, selects potential VH or VL according to the logic level of received bit D6, and applies the selected voltage to one end of capacitor element C6.

[0088] In the present embodiment, among the 10 bits of the video data Vdata, bits D5 to D9 are examples of high-order bits, and bits D0 to D4 are examples of all bits excluding the high-order bits.

[0089] In this embodiment, capacitor elements C5 to C9 are examples of a high-order capacitor element portion, where, for example, capacitor element C5 is an example of a first capacitor element, and capacitor element C6 is an example of a second capacitor element. Furthermore, in this embodiment, capacitor elements C0 to C5 are examples of a low-order capacitor element portion, where, for example, capacitor element C0 is an example of a third capacitor element, and capacitor element C1 is an example of a fourth capacitor element.

[0090] In this embodiment, the capacitances of capacitor elements C0 to C9 have the following ratios. Specifically, if the capacitance of capacitor element C0 is set to "1," the capacitances of capacitor elements C1, C2, C3, C4, C5, C6, C7, C8, and C9 are "2," "4," "8," "16," "1," "2," "4," "8," and "16," respectively.

[0091] The capacitance element Cser is an example of a connected capacitor, and the capacitance of the capacitance element Cser is, for example, 1. A certain degree of error is permitted in the capacitances of the capacitance elements C0 to C9 and Cser as long as linearity, which will be described later, is maintained.

[0092] In this embodiment, MOS capacitors are used as the capacitor elements 140 , and therefore MOS capacitors are preferably used for the capacitor elements C0 to C9 and Cser as well. However, metal capacitors may also be used.

[0093] When the capacitance ratio is as described above, in this embodiment, capacitor elements C0 to C9 and Cser are formed by connecting capacitor elements with a capacitance of "1" in parallel in a number corresponding to the ratio. For example, if capacitor element C0 or C5 is formed by connecting two basic capacitor elements with a capacitance ratio of "0.5" in parallel, capacitor elements C4 and C9 are formed by connecting 32 basic capacitor elements in parallel.

[0094] In such a structure where the number of electrodes connected in parallel corresponds to the ratio of the capacitance magnitudes, the length of the electrode periphery when viewed from above also corresponds to the ratio of the capacitance magnitudes, and the effect of the capacitance generated by the electrode periphery also corresponds to the ratio. Therefore, in a structure where the number of electrodes connected in parallel corresponds to the ratio of the capacitance magnitudes, the accuracy of the capacitance magnitude ratio can be improved compared to a structure where the electrode area is set as the capacitance magnitude ratio instead of a parallel connection.

[0095] The other ends of capacitor elements C0-C4, which correspond to the lower five bits of capacitor elements C0-C9, are electrically connected to one end of capacitor element Cser. For convenience, the line connecting the other ends of capacitor elements C0-C4 and one end of capacitor element Cser is referred to as relay line 14b. Furthermore, the other ends of capacitor elements C5-C9, which correspond to the upper five bits of capacitor elements C0-C9, are electrically connected to data line 14 and the other end of capacitor element Cser.

[0096] In this description, “electrical connection” refers to direct or indirect connection or connection between two or more elements, and also includes a situation where, for example, two or more elements in a semiconductor substrate are not directly connected but are connected via different wiring layers and contact holes.

[0097] Between the power supply line to which the potential Vrst is applied and the trunk line 14b, the switch Rsw is turned on or off according to the control signal / Rst. Specifically, the switch Rsw is turned on when the control signal / Rst is at an L level and is turned off when the control signal / Rst is at an H level.

[0098] In this specification, the "on" state of a switch or transistor refers to a state in which both ends of the switch, or the source / drain nodes of a transistor, are electrically closed, resulting in a low-impedance state. The "off" state of a switch or transistor refers to a state in which both ends of the switch, or the source / drain nodes, are electrically disconnected, resulting in a high-impedance state.

[0099] Furthermore, the switch Rsw is preferably formed of a NOT circuit Lg0 that outputs a negation signal of the control signal / Rst, and a transmission gate Tg0. The transmission gate Tg0 is an analog switch composed of an n-type transistor that supplies a negation signal based on the NOT circuit Lg0 to a gate node, and a p-type transistor that supplies the control signal / Rst to a gate node.

[0100] The voltage selection circuit 510 paired with the capacitor C0 includes an AND circuit Ds, a level shifter Ls, and a selector Sel.

[0101] The AND circuit Ds outputs a logical AND signal of bit D0 and control signal Enb0 in the image data Vdata output from the second latch circuit L2 in the jth column. The AND circuit Ds is actually composed of a NAND circuit Lg1 that outputs a NAND signal of bit D0 and control signal Enb0, and a NOT circuit Lg2 that outputs a negative signal of the NAND signal.

[0102] The level shifter Ls converts the logic amplitude of the logical AND signal output by the AND circuit Ds, outputs a positive phase signal maintaining the logic level of the logical AND signal from the output terminal Out, and outputs an inverted phase signal obtained by inverting the logic level of the logical AND signal from the output terminal / Out.

[0103] The selector Sel selects the potential VH when the positive phase signal output from the level shifter Ls is at H level and the negative phase signal is at L level, and selects the potential VL when the positive phase signal is at L level and the negative phase signal is at H level, and applies the selected voltage to one end of the capacitor C0.

[0104] The selector Sel is actually composed of a transmission gate Tg1 provided between a power supply line of a potential VH and one end of the capacitance element C0, and a transmission gate Tg2 provided between a power supply line of a potential VL and one end of the capacitance element C0.

[0105] In this structure, if the positive phase signal output from the level shifter Ls is at an H level and the negative phase signal is at an L level, the transmission gate Tg1 becomes conductive and the transmission gate Tg2 becomes cut-off. If the positive phase signal output from the level shifter Ls is at an L level and the negative phase signal is at an H level, the transmission gate Tg1 becomes cut-off and the transmission gate Tg2 becomes conductive.

[0106] Here, the voltage selection circuit 510 paired with the capacitor element C0 is described. However, the other voltage selection circuits 511 to 519 have the same structure as the voltage selection circuit 510 except that the input signal bits D1 to D9 and the control signals Enb1 to Enb9 are different.

[0107] Figure 5 This diagram shows the equivalent circuit of the j-th column DA converter circuit 500. Voltage selection circuit 510 is depicted as a single-pole double-throw switch that selects potential VH or VL based on the logic level of D0 / Enb0, the logical AND signal of bit D0 and control signal Enb0. Voltage selection circuits 511-519 are also depicted as single-pole double-throw switches similar to voltage selection circuit 510.

[0108] exist Figure 4 and Figure 5In the embodiment of the present invention, the DA conversion circuit 500 of the j-th column is described, but the DA conversion circuits 500 corresponding to other columns have the same configuration.

[0109] in addition, Figure 4 and Figure 5 It only shows the electrical structure and does not show the position and arrangement of actual elements.

[0110] The operation of the DA converter circuit 500 is divided into a reset period and an output period. The reset period is an initialization period and a compensation period (b) described later, and the output period is a writing period (c) of the electro-optical device 10.

[0111] In DA converter circuit 500, during the reset period, charge corresponding to the capacitance of capacitor elements C0-C9 is accumulated. During the output period, the voltage at one end of capacitor elements C0-C9 changes (increases) or remains constant according to bits D0-D9. At the other end of capacitor elements C0-C9 where the voltage at one end changes, the voltage increases according to the capacitance due to the discharge of the accumulated charge.

[0112] At the other end of capacitor elements C5 to C9 among capacitor elements C0 to C9, the voltage of data line 14 increases according to the capacitance size, but the other end of capacitor elements C0 to C4 is separated from data line 14 by capacitor element Cser, so the voltage change at the other end of capacitor elements C0 to C4 is compressed according to the capacitance ratio, causing the voltage of data line 14 to change.

[0113] Thus, the DA conversion circuit 500 changes the voltage of the data line 14 in a linear relationship with respect to bits D0 to D9. The details are described in detail in the aforementioned Patent Document 1.

[0114] A voltage (first grayscale voltage) corresponding to the weight of the upper bits D5 to D9 is output to the data line 14 via the capacitors C5 to C9 and the voltage selection circuits 515 to 519. Therefore, for convenience, the circuit including the capacitors C5 to C9 and the voltage selection circuits 515 to 519 is referred to as a first DA conversion circuit Upb.

[0115] Similarly, a voltage corresponding to the weight of the lower bits D0 to D4 is output to the data line 14 via the capacitors C0 to C4, Cser, and the voltage selection circuits 510 to 514. However, assuming a configuration without the capacitor Cser, a voltage reflecting bits D0 to D4, i.e., a voltage before compression (the second grayscale voltage), is output to the relay line 14b. For convenience, the configuration including the capacitors C0 to C4 and the voltage selection circuits 510 to 514, excluding the capacitor Cser, is referred to as the second DA conversion circuit Lwb.

[0116] Figure 6 This is a timing chart for explaining the operation of the electro-optical device 10 .

[0117] In the electro-optical device 10, the m rows of scanning lines 12 are scanned one row at a time in the order of the 1st, 2nd, 3rd, ..., mth row during a frame (V). Specifically, as shown in the figure, the scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), and / Gwr(m) are sequentially and exclusively driven to the L level by the scanning line driver circuit 120 during each horizontal scanning period (H).

[0118] Furthermore, in this embodiment, the periods during which adjacent scanning signals / Gwr(1) to / Gwr(m) are at an L level are separated in time. Specifically, after scanning signal / Gwr(i-1) changes from an L level to an H level, the next scanning signal / Gwr(i) changes to an L level for a period of time. This period corresponds to a horizontal retrace period.

[0119] In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by the video data Vid. If the length of the period of one frame (V) is the same as the vertical synchronization period, and for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, then the period is 16.7 milliseconds, which is equivalent to one cycle of the vertical synchronization signal. Furthermore, the horizontal scanning period (H) is the interval during which the scanning signals / Gwr(1) to / Gwr(m) are sequentially at the L level. However, for convenience in the figures, the start timing of the horizontal scanning period (H) is set to be approximately in the center of the horizontal retrace period.

[0120] In this embodiment, one horizontal scanning period (H) is mainly divided into three periods: an initialization period (a), a compensation period (b), and a writing period (c). In addition to the above three periods, the pixel circuit 110 also operates during a light-emission period (d).

[0121] During the initialization period (a) of each horizontal scanning period (H), the control signal / Gini is at an L level, the control signal / Rst is at an L level, and the control signal Enb is at an L level. Furthermore, the control signal Enb is a collective term for control signals Enb0 through Enb9. As described later, the control signals Enb0 through Enb9 are sequentially phase-shifted during the write period (c). However, since they maintain the same waveform outside of the write period (c), they are collectively referred to as the control signal Enb.

[0122] During the compensation period (b), the control signal / Gini is at the H level, and the control signals / Rst and Enb are maintained at the L level.

[0123] In the writing period (c), the control signal / Gini is maintained at the H level, and the control signals / Rst and Enb are set to the H level.

[0124] The operation in the horizontal scanning period (H) will be described using the i-th row as an example. Also, the pixel circuit 110 will be described using the i-th row and j-th column as an example.

[0125] During the horizontal scanning period (H) of the i-th row, before the scanning signal / Gwr(i) goes to the L level, the initialization period (a) for the i-th row begins. The initialization period (a) is used to reset the voltage or charge remaining in each component during the horizontal scanning period (H) of the (i-1)-th row.

[0126] Figure 7 This is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the data line 14 in the j-th column during the initialization period (a) in the i-th row.

[0127] During the initialization period (a), the control signal / Gini goes low, turning on transistor 66. Data line 14 is initialized to potential Vini. Furthermore, during the initialization period (a), the control signal / Rst goes low, turning on switch Rsw. Consequently, potential Vrst is applied to relay line 14b. During the initialization period (a), control signal Enb is low. Specifically, control signals Enb0 through Enb9 are all low. Therefore, regardless of the logic levels of bits D0 through D9 output from second latch circuit L2, the logical AND signals of the AND circuits Ds in voltage selection circuits 510 through 519 are low. Consequently, voltage selection circuits 510 through 519 select potential VL.

[0128] Therefore, during the initialization period (a), a potential VL is applied to one end of the capacitor elements C0 to C9, a potential Vrst is applied to one end of the capacitor element Cser and the other ends of the capacitor elements C0 to C4, and a potential Vini is applied to the other end of the capacitor element Cser and the other ends of the capacitor elements C5 to C9 via the data line 14. Thus, during the initialization period (a), the charge stored in the capacitor elements C0 to C9 and Cser is initialized simultaneously with the initialization of the data line 14.

[0129] Furthermore, during the initialization period (a) for the i-th row, the control signal / Gel(i) is set to an H level, and the control signal / Gorst(i) is set to an L level. Consequently, in the pixel circuit 110 for the i-th row, the transistor 124 is turned off, and the transistor 125 is turned on. As a result, a potential Vorst is applied to the anode of the OLED 130, i.e., the pixel electrode 131. Consequently, the OLED 130 is turned off, and the pixel electrode 131 is reset to the potential Vorst.

[0130] In addition, since capacitance is parasitic in the OLED 130 , the pixel electrode 131 is reset in order to eliminate the influence of the voltage applied during the immediately preceding light emission period.

[0131] After the initialization period (a) ends, the compensation period (b) begins. The compensation period (b) is a period for causing the gate node g of each transistor 121 in the n pixel circuits 110 located in the i-th row to converge to a voltage corresponding to the threshold of the transistor 121 .

[0132] Figure 8 This is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the data line 14 in the j-th column during the compensation period (b) of the i-th row.

[0133] During the compensation period (b), the control signal / Gini is at an H level, turning off transistor 66. Furthermore, during the compensation period (b), the control signal / Rst is at an L level, maintaining the on state of switch Rsw. The control signal Enb is at an L level, maintaining the selection of potential VL by voltage selection circuits 510 to 519.

[0134] Furthermore, during the compensation period (b) for the i-th row, the scanning signal / Gwr(i) is at an L level. While at this L level, the control signal / Gcmp(i) is also at an L level. Consequently, in the pixel circuit 110 for the i-th row, the transistor 122 is turned on, and the transistor 123 is turned on. Consequently, the transistor 121 is in a diode-connected state, and the voltage between the gate node and the source node of the transistor 121 converges to the threshold voltage of the transistor 121.

[0135] During the compensation period (b) of the i-th row, the transistors 122 and 123 in the pixel circuit 110 are in the on state. Therefore, the other end of the capacitor Cser and the other ends of the capacitors C5 to C9 also converge to a voltage corresponding to the threshold voltage of the transistor 121 via the data line 14 .

[0136] In addition, during the compensation period (b), the application of the potential VL is maintained at one end of the capacitor elements C0 to C9 through the voltage selection circuits 510 to 519, and the application of the potential Vrst is maintained at one end of the capacitor element Cser and the other end of the capacitor elements C0 to C4 by the on state of the switch Rsw.

[0137] Furthermore, in the compensation period (b) of the i-th row, in the pixel circuit 110 of the i-th row, the off state of the transistor 124 and the on state of the transistor 125 continue from the initialization period (a).

[0138] After the compensation period (b) ends, the writing period (c) begins. The writing period (c) is a period for applying a voltage corresponding to the brightness to the gate node g of each transistor 121 in the pixel circuit 110 located in the i-th row and n-th column.

[0139] Figure 9 This is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the data line 14 in the j-th column during the writing period (c) of the i-th row.

[0140] During the write period (c), the control signal / Rst becomes H level, so the switch Rsw becomes OFF. Figure 6 As shown, after control signal Enb0 becomes H level, control signals Enb1 to Enb9 are sequentially delayed by time Δt and become H level. Also, when control signal Enb0 changes from H level to L level, control signals Enb1 to Enb9 are sequentially delayed by time Δt and become L level.

[0141] The period during which bit D0 of the video data output from the second latch circuit L2 in the jth column is input to the level shifter Ls of the voltage selection circuit 510 is limited by the AND circuit Ds to the period during which the control signal Enb0 is at an H level. Similarly, the period during which bits D1 through D9 are sequentially input to the level shifters Ls of the voltage selection circuits 511 through 519 is sequentially limited by the AND circuit Ds to the period during which the control signals Enb1 through Enb9 are at an H level. Therefore, bits D0 through D9 are not simultaneously input to the voltage selection circuits 510 through 519, but are sequentially input with a delay of time Δt.

[0142] Among the voltage selection circuits 510 to 519 , the voltage selection circuit for a bit of “1” input to the level shifter Ls selects the potential VH, and the voltage selection circuit for a bit of “0” selects the potential VL.

[0143] During the writing period (c), one end of the capacitive element corresponding to the bit “0” input to the level shifter Ls among the capacitive elements C0 to C9 does not undergo voltage change since the compensation period (b), and therefore does not contribute to the voltage rise of the data line 14 .

[0144] Among the capacitor elements C5 to C9 corresponding to the upper five bits, one end of the capacitor element corresponding to the bit "1" input to the level shifter Ls changes from potential VL to potential VH during the write period (c). Therefore, the capacitor element corresponding to the bit "1" among the capacitor elements C5 to C9 causes the data line 14 to rise from a voltage corresponding to the threshold voltage during the compensation period (b) by an amount corresponding to the weight of the capacitance size.

[0145] Among the capacitors C0-C4 corresponding to the lower-order five bits, one end of the capacitor corresponding to the "1" bit input to the level shifter Ls changes from potential VL to potential VH during the write period (c). However, unlike the other ends of capacitors C5-C9, the other ends of capacitors C0-C4 are separated from data line 14 by capacitor Cser. Therefore, the change from potential VL to potential VH at the one end of the capacitor corresponding to the "1" bit among capacitors C0-C4 is suppressed by the capacitance ratio, causing the voltage on data line 14 to rise.

[0146] Thus, during the write period (c), the DA conversion circuit 500 of the jth column causes the data line 14 of the jth column to rise from a voltage equivalent to the threshold voltage to a voltage corresponding to bits D0 to D9 of the image data Vdata of the i row and j column, that is, a voltage amount that specifies the brightness of the OLED of the i row and j column.

[0147] In this embodiment, the period during which control signals Enb0-Enb9 are at an H level during the write period (c) is sequentially delayed by a time Δt. This is because if control signals Enb0-Enb9 were all at an H level, a simultaneous switch from potential VL to VH would occur. This increased peak fluctuation associated with the voltage switch would propagate to various components, particularly to data line 14, reducing DA conversion accuracy. Therefore, in this embodiment, the phases of control signals Enb0-Enb9 are sequentially shifted to prevent simultaneous switching from potential VL to VH.

[0148] According to the present embodiment, the influence of voltage fluctuation caused by the peak value accompanying voltage switching is reduced, thereby suppressing a decrease in DA conversion accuracy.

[0149] In addition, the order in which the control signals Enb0 to Enb9 become H level does not necessarily need to be the same order as the control signals Enb0 to Enb9.

[0150] During the writing period (c), in the pixel circuit 110 of the i row and j column, the transistor 122 is turned on and the transistor 123 is turned off, so the voltage Vd(j) output from the DA conversion circuit 500 of the j column is applied to the gate node g of the transistor 121 via the data line 14.

[0151] In the figure, the difference between the voltage of the gate node g and the potential Vel of the source node in the transistor 121 is represented as Vgs, and is held in the capacitor 140 .

[0152] Furthermore, during the writing period (c) of the i-th row, in the pixel circuit 110 of the i-th row, the off state of the transistor 124 and the on state of the transistor 125 continue.

[0153] in addition, Figure 9 This shows a case where bits D0 to D9 of the video data output from the second latch circuit L2 are all “1”.

[0154] After the writing period (c) ends, the light emitting period (d) begins. The light emitting period (d) is a period for causing a current corresponding to the voltage Vgs maintained during the writing period (c) to flow through the OLED 130 to cause the OLED 130 to emit light.

[0155] Figure 10 1 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column during the light emission period (d) of the i-th row.

[0156] Before the light-emitting period (d) of the i-th row, the control signal / Gcmp(i) reaches an H level, turning off transistor 123. Furthermore, when the light-emitting period (d) of the i-th row begins, the control signal / Gel(i) inverts to an L level, turning on transistor 124. Consequently, a current Ids corresponding to the voltage Vgs held by capacitor 140 flows through transistor 121 in OLED 130. Consequently, OLED 130 emits light at a brightness corresponding to the current Ids.

[0157] also, Figure 10 This example shows a continuous light-emission period (d) after the i-th row scan line 12 is selected. However, the period during which the control signal / Gel(i) is at the L level may be intermittent, and may be adjusted according to brightness control. Furthermore, the level of the control signal / Gel(i) during the light-emission period (d) may be higher than the L level during the compensation period (b). In other words, the level of the control signal / Gel(i) during the light-emission period (d) may be a level intermediate between the H level and the L level.

[0158] In addition, during the light-emitting period (d) of the i-th row, the DA conversion circuit 500 corresponding to the j-th column sometimes performs the horizontal scanning period (H) operation on rows other than the i-th row. Figure 10 The DA conversion circuit 500 is omitted.

[0159] exist Figures 7 to 9 During the horizontal scan period (H) of the i-th row, the DA conversion circuit 500 corresponding to the j-th column and the pixel circuit 110 of the i-th row and j-th column are focused on, but the same operation is performed on the DA conversion circuits 500 and pixel circuits 110 corresponding to other columns other than the j-th column.

[0160] In addition, Figures 7 to 9 In the description, the action during the horizontal scanning period (H) of the i-th row is focused on, but the same action is performed sequentially during the horizontal scanning periods (H) of the 1st, 2nd, 3rd, ..., mth rows.

[0161] In pixel circuit 110, voltage Vgs during the writing period (c) and the light-emission period (d) varies from a voltage equivalent to the threshold voltage during the compensation period (b) according to the grayscale level of the pixel circuit 110. Since the same operation is performed in other pixel circuits 110, in this embodiment, a current corresponding to the grayscale level flows through OLED 130 while the threshold value of transistor 121 is compensated for in all pixel circuits 110 in m rows and n columns. Therefore, in this embodiment, luminance variations are reduced, resulting in high-quality display.

[0162] Figure 11 This is a plan view showing the arrangement of the various components of the electro-optical device 10 according to the first embodiment. Since the electro-optical device 10 is cut from a wafer-shaped semiconductor substrate, it has a rectangular shape. Therefore, in the rectangular electro-optical device 10, the upper edge is labeled Ue, the lower edge is labeled De, the left edge is labeled Le, and the right edge is labeled Re.

[0163] In the rectangular electro-optical device 10 , the upper side Ue and the lower side De are along the X direction, which is the extending direction of the scanning lines 12 , and the left side Le and the right side Re are along the Y direction, which is the extending direction of the data lines 14 .

[0164] In the drawings, the Z direction is a direction perpendicular to the X and Y directions and is a direction in which light is emitted from the OLED 130. A plan view in this description indicates a state in which the electro-optical device 10 is viewed in a direction opposite to the Z direction.

[0165] A scan line driving circuit 120 is provided in the area between the display area 100 and the left side Le, and a scan line driving circuit 120 is provided in the area between the display area 100 and the right side Re. The two scan line driving circuits 120 have the same structure and drive the scan lines 12 and the like on the left and right sides.

[0166] In a configuration where the scanning line driving circuit 120 is disposed only on one of the left and right sides, signal delay occurs on the other side. In contrast, in a configuration where the scanning line driving circuit 120 is disposed on both the left and right sides, signal delay can be prevented.

[0167] In the electro-optical device 10 , a plurality of terminals 20 are provided along the lower side De. In the region between the display region 100 and the plurality of terminals 20 , circuits Rb, Bb, Gb, and a control circuit 30 are provided in order from the display region 100 .

[0168] Circuit Rb is a circuit formed by integrating the circuits corresponding to the data line 14 of R in the data signal output circuit 50, which includes the selection circuit group 52, the first latch circuit group 54, the second latch circuit group 56, and the DA conversion circuit 500. Circuit Bb is a circuit formed by integrating the output circuits corresponding to the data line 14 of B in the data signal output circuit 50. Circuit Gb is a circuit formed by integrating the output circuits corresponding to the data line 14 of G in the data signal output circuit 50.

[0169] A power supply circuit 15 is provided in the area between the circuits Rb, Bb, Gb and the left side Le, and a power supply circuit 15 is also provided in the area between the circuits Rb, Bb, Gb and the right side Re. The two power supply circuits 15 have the same structure and supply various voltages to the scan line driving circuit 120, the circuits Rb, Bb, Gb and the control circuit 30.

[0170] Figure 12 This is a top view showing the arrangement of pixel circuits 110 in the display area 100. As shown in the figure, R pixel circuits 110, B pixel circuits 110, and G pixel circuits 110 are arranged along the X direction, and pixel circuits 110 of the same color are arranged along the Y direction. Therefore, if the data lines 14 in any column are considered, they correspond to pixel circuits 110 of the same color.

[0171] Furthermore, a single color is represented by additive color mixing of adjacent RBG pixel circuits 110 in the X direction. Therefore, strictly speaking, the pixel circuits 110 should be referred to as sub-pixel circuits. However, in this embodiment, since they can also display a monochrome image with only light and dark, as described above, they are not specifically distinguished and are described as pixel circuits.

[0172] In the figure, width W is the arrangement interval of the data lines 14 when viewed in the X direction and is an example of the first width. Width 3W is three times the width W, that is, the interval when three data lines 14 required to display one color are taken as one unit.

[0173] In the figure, to distinguish the data lines 14 by color, the data lines corresponding to the R pixel circuits 110 are labeled R14, the data lines corresponding to the B pixel circuits 110 are labeled B14, and the data lines corresponding to the G pixel circuits 110 are labeled G14. When no color distinction is made, the data lines are labeled 14 as described above.

[0174] Figure 13 This figure focuses on the j-th column in the data signal output circuit 50 and shows the arrangement of the elements in the circuits Rb, Bb, and Gb corresponding to the j-th column. Figure 14 This diagram shows one of the circuits Rb, Bb, and Gb being extracted.

[0175] like Figure 13 As shown, circuits Rb, Bb, and Gb are arranged in a row along the Y direction within a range wider than width W and narrower than width 3W. In circuit Rb, the elements are arranged in the following order along the Y direction (i.e., when viewed from above in the figure). Specifically, in circuit Rb, capacitor element C9, circuit D9_L1L2, capacitor element C8, circuit D8_L1L2, capacitor element C7, circuit D7_L1L2, capacitor element C6, circuit D6_L1L2, capacitor element C5, circuit D5_L1L2, capacitor element Cser, capacitor element C4, circuit D4_L1L2, capacitor element C3, circuit D3_L1L2, capacitor element C2, circuit D2_L1L2, capacitor element C1, circuit D1_L1L2, capacitor element C0, circuit D0_L1L2, and selection circuit 520 are arranged in order.

[0176] Furthermore, circuit Dk_L1L2 is the circuit corresponding to bit Dk in the first latch circuit L1 and the second latch circuit L2 provided for the j-th column. k is an integer generally used to describe a bit and, in this embodiment, is any one of 0 to 9. For example, circuit D6_L1L2 is the circuit corresponding to bit D6 in the first latch circuit L1 and the second latch circuit L2 provided for the j-th column.

[0177] Regarding circuits Gb and Rb, the elements are arranged in the same order as in circuit Rb.

[0178] Therefore, in circuits Rb, Bb, and Gb, capacitor elements C0 to C4 corresponding to the lower bits in the jth column are located near the control circuit 30 at the bottom in the figure, capacitor elements C5 to C9 are located near the display area 100 at the top in the figure, and capacitor element Cser is located between capacitor elements C0 to C4 and capacitor elements C5 to C9.

[0179] In addition, among the circuits Rb, Bb, and Gb, the selection circuit 520 is located at the lowest position in the figure, that is, close to the control circuit 30.

[0180] In addition, for simplicity, Figure 13 The voltage selection circuits 510 to 519 and the switch Rsw in the DA conversion circuit 500 are omitted.

[0181] like Figure 14 As shown, in the circuits Rb, Bb, and Gb, bits D0 to D9 of the image data Vdata selected by the selection circuit 520 are sequentially supplied to the circuits D0_L1L2 to D9_L1L2 in the direction opposite to the Y direction.

[0182] The other ends of the capacitive elements C0 to C4 are connected to one end of the capacitive element Cser via a relay line 14 b provided in the Y direction. The other end of the capacitive element Cser is connected to the data line 14 provided in the Y direction together with the other ends of the capacitive elements C5 to C9 .

[0183] Next, in this embodiment, each element in the circuits Rb, Bb, and Gb is set to Figure 14 The advantages of the configuration shown are explained.

[0184] Regarding the capacitance element Cser, for example, it can be considered as follows Figure 15 As shown in the left column of the figure, the configuration is provided at a position close to the selection circuit 520, and as shown in the right column of the figure, the configuration is provided at a position close to the display area 100.

[0185] However, in Figure 15 In the structure shown in the left column of FIG, the data line 14 substantially passes through the circuit Rb, Bb, or Gb, and therefore the data line 14 becomes longer outside the display area 100.

[0186] On the other hand, in the structure shown in the right column of the figure, since the trunk line 14b passes through the circuit Rb, Bb or Gb, the trunk line 14b is larger than the Figure 14 In the embodiment shown, the trunk line 14b, Figure 15 The trunk line 14b shown in the left column is long.

[0187] In other words, in Figure 15In the structure shown in the left column of the figure and the right column of the figure, there is a portion where the data line 14 and the relay line 14b belonging to the same column are arranged along the Y direction, but Figure 14 In the illustrated embodiment, there is no portion where the data lines 14 and the relay lines 14 b belonging to the same column are arranged.

[0188] Therefore, in this embodiment, Figure 15 Compared to the structures shown in the left column of the figure and the right column of the figure, the data lines 14 outside the display area 100 can be shortened, and the relay lines 14b can be shortened. If the wiring is long, parasitic capacitance is likely to occur, which can easily lead to a decrease in analog conversion accuracy. In this embodiment, since the data lines 14 and relay lines 14b can be shortened, the decrease in analog conversion accuracy can be suppressed.

[0189] Furthermore, regarding the capacitor elements C0 to C9 and the circuits D0_L1L2 to D9_L1L2, it is also possible to arrange the capacitor elements C0 to C9 in the X direction instead of in the Y direction. For example, Figure 16 Specifically, as shown in the figure, a configuration is also conceivable in which the circuits Rb, Bb, and Gb are arranged along the X direction, the capacitor element Cser is located close to the display area 100, and the selection circuit 520 is located close to the control circuit 30.

[0190] However, in Figure 16 In the structure shown, when the width W has to be narrowed due to the requirements of miniaturization and high resolution, it is difficult to fit all the capacitor elements C0 to C9 in circuit Rb, Bb or Gb or circuit D0_L1L2 to circuit D9_L1L2 within a range narrower than the arrangement interval of the data line 14, that is, the width W.

[0191] In addition, Figure 16 In FIG. 1 , circuits D0_L1L2 to D9_L1L2 are described only as D0 to D9 due to space constraints.

[0192] On the other hand, in this embodiment, the lengths of the capacitor elements C0 to C9 and the circuits D0_L1L2 to D9_L1L2 along the X direction only need to be within a range narrower than the width 3W. Figure 16 Compared with the arrangement shown, it is possible to easily cope with the demand for narrowing the width W.

[0193] right Figure 13 The structure shown (ie, the structure in which the circuits Rb, Bb, and Gb are arranged along the Y direction within a range narrower than the width 3W) will be described in more detail.

[0194] Although Figure 13Although omitted in the figure, capacitor elements C5-C9 of circuit Rb closest to display area 100 not only pass data line R14 corresponding to circuit Rb itself, but also data line B14 corresponding to circuit Bb below and data line G14 corresponding to circuit Gb, resulting in dense wiring. Therefore, the structure of capacitor elements C5-C9 in circuit Rb will be described using one of the basic capacitor elements in capacitor element C5 as an example.

[0195] Figures 17 to 21 1 is a top view showing a structure of one basic capacitance element and its periphery connected in parallel in capacitance element C5. Figure 22 So the Pp line will Figures 17 to 21 A partial cross-sectional view of the basic capacitor element in FIG. Figure 23 So Qq line will Figures 17 to 21 A partial cross-sectional view of the basic capacitor element in FIG.

[0196] The electro-optical device 10 in this embodiment is formed on a semiconductor substrate as described above. In this semiconductor substrate, the layers used as conductive layers or wiring layers are, in order from the base material, a semiconductor layer 210, a gate electrode layer 220, a first wiring layer 230, a second wiring layer 240, a third wiring layer 250, and a fourth wiring layer 260, a total of six layers. Therefore, if a top view of the capacitor element C5 and its surroundings is to be represented in a single figure, it will be complicated. Therefore, Figures 17 to 21 , two adjacent layers of the six layers are shown in a plan view.

[0197] More specifically, Figure 17 A wiring pattern composed of a semiconductor layer 210 and a gate electrode layer 220 is shown. Figure 18 A wiring pattern composed of the gate electrode layer 220 and the first wiring layer 230 is shown. Figure 19 A wiring pattern composed of a first wiring layer 230 and a second wiring layer 240 is shown. Figure 20 A wiring pattern composed of the second wiring layer 240 and the third wiring layer 250 is shown. Figure 21 A wiring pattern composed of a third wiring layer 250 and a fourth wiring layer 260 is shown.

[0198] like Figure 17 、 Figure 22 as well as Figure 23 As shown, this basic capacitor element has a structure in which a gate insulating layer 270 is sandwiched between an electrode 211 formed of a semiconductor layer 210 and an electrode 221 formed by patterning a gate electrode layer 220 .

[0199] The electrode 211 is formed by, for example, implanting impurity ions into the p-well region Well. The region St is a trench for separating adjacent element regions.

[0200] like Figure 17 、 Figure 18 as well as Figure 23 As shown, the electrode 211 is connected to the wiring 231 via a contact hole Ct1 formed by opening the gate insulating layer 270 and the first interlayer insulating layer 271. Figure 17 、 Figure 18 as well as Figure 22 As shown, electrode 221 is connected to wiring 232 via contact hole Ct2 opened in first interlayer insulating layer 271. First interlayer insulating layer 271 is an insulating layer provided between gate electrode layer 220 and first wiring layer 230. Wiring 231 and wiring 232 are relay wiring formed by patterning first wiring layer 230.

[0201] like Figure 18 、 Figure 19 as well as Figure 23 As shown, the wiring 231 is connected to the wiring 241 via a contact hole Ct3 formed by opening the second interlayer insulating layer 272. Figure 18 、 Figure 19 as well as Figure 22 As shown, the wiring 232 is connected to the wiring 242 via a contact hole Ct4 formed by opening the second interlayer insulating layer 272. The second interlayer insulating layer 272 is an insulating layer provided between the first wiring layer 230 and the second wiring layer 240.

[0202] Wiring 241 is formed by patterning the second wiring layer 240 and is connected to the voltage selection circuit 515. That is, the electrode 211, which is one end of the basic capacitor, is connected to the voltage selection circuit 515 via wirings 231 and 241 in sequence. Wiring 242 is a relay wiring formed by patterning the second wiring layer 240.

[0203] like Figure 19 、 Figure 20 as well as Figure 22 As shown, wiring 242 is connected to wiring 252 via contact hole Ct6 formed in third interlayer insulating layer 273. Third interlayer insulating layer 273 is an insulating layer provided between second wiring layer 240 and third wiring layer 250. Wiring 252 is a relay wiring formed by patterning third wiring layer 250.

[0204] In addition to the wiring 252, a wiring 253 is formed by patterning the third wiring layer 250. A voltage used as a power supply is supplied to the wiring 253.

[0205] like Figure 20 、 Figure 21 as well as Figure 22 As shown, the wiring 252 is connected to the data line R14 via a contact hole Ct8 formed by opening the fourth interlayer insulating layer 274. The fourth interlayer insulating layer 274 is an insulating layer provided between the third wiring layer 250 and the fourth wiring layer 260. The data line R14 is formed by patterning the fourth wiring layer 260.

[0206] In addition to the data line R14 , data lines B14 , G14 and wirings 261 , 262 , and 263 are formed by patterning the fourth wiring layer 260 .

[0207] Data line B14 Figures 17 to 21 The data line G14 is connected to the other ends of the capacitors C5 to C9 and the other end of the capacitor Cser in the circuit Bb below. The data line G14 is connected to the other ends of the capacitors C5 to C9 and the other end of the capacitor Cser in the circuit Gb below the circuit Bb.

[0208] Furthermore, a power supply voltage, that is, a voltage that is substantially constant over time, is supplied to the wirings 261 , 262 , and 263 .

[0209] Therefore, data line R14 is shielded by the adjacent wirings 261 and 262 in the figure. That is, from the perspective of data line R14, wirings 261 and 262 serve as an example of shielded wiring. Similarly, data line B14 is shielded by the adjacent wirings 262 and 263, and data line G14 is shielded by the adjacent wirings 263 and 261. That is, from the perspective of data line B14, wirings 262 and 263 serve as an example of shielded wiring, and from the perspective of data line G14, wirings 263 and 261 serve as an example of shielded wiring.

[0210] Here, the basic capacitance elements connected in parallel among the capacitance element C5 of the circuit Rb are described, but the structures of the basic capacitance elements constituting the capacitance elements C6 to C9 are also similar. Figures 17 to 23 The structures shown are the same. In addition, the number of basic capacitor elements connected in parallel in capacitor elements C6 to C9 is different from that in capacitor element C5.

[0211] In addition, regarding the capacitor elements C0 to C4 of the circuit Rb, the connection destination of the other end is replaced with the relay line 14b related to R. The basic structure is the same as Figures 17 to 23 The structures shown are the same.

[0212] Circuits Bb and Gb also have capacitor elements C0 to C9. However, since data line R14 does not exist in the area where circuit Bb is located, there is no need to consider wiring for shielding data line R14. Furthermore, since data lines R14 and B14 do not exist in the area where circuit Gb is located, there is no need to consider wiring for shielding data lines R14 and B14.

[0213] In this embodiment, outside the display area 100, the data lines R14, B14, and G14 are shielded not only by the adjacent wirings 261, 262, and 263 but also by the underlying wiring 253. This suppresses potential fluctuations of the data lines R14, B14, and G14 caused by the propagation of noise. Therefore, in this embodiment, potential fluctuations of the data lines R14, B14, and G14 are suppressed, enabling high-quality display.

[0214] [Second embodiment]

[0215] Next, an electro-optical device 10 according to a second embodiment will be described. In the following embodiments, the same components as those in the previously described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0216] Figure 24 This diagram shows the electro-optical device 10 of the second embodiment, focusing on the data line 14 of the j-th column in the data signal output circuit 50 , and extracting any one of the circuits Rb, Bb, and Gb corresponding to the j-th column.

[0217] exist Figure 24 In the second embodiment shown, Figure 14 The difference from the first embodiment shown is the arrangement of capacitors C5 to C9 and circuits D5_L1L2 to D9_L1L2 corresponding to the higher-order bits. Specifically, in the second embodiment, the arrangement of capacitors C9 to C5 and circuits D9_L1L2 to D5_L1L2 is symmetrical with the arrangement of capacitors C4 to C0 and circuits D4_L1L2 to D0_L1L2, with capacitor Cser as a reference.

[0218] Capacitance elements C4 and C9 have substantially the same capacitance, and have the largest capacitance compared to other capacitance elements C0 to C3 and C5 to C8.

[0219] Therefore, according to Figure 24 In the arrangement shown, capacitor elements C4 and C9, which have relatively large capacitances, are positioned close together. The capacitor elements in the electro-optical device 10 are formed using a semiconductor process, but in the second embodiment, the proximity of the relatively large capacitor elements minimizes variations in capacitance. Consequently, in the second embodiment, the accuracy of analog conversion is improved, and grayscale linearity is enhanced, enabling high-quality display.

[0220] Furthermore, in the second embodiment, for capacitor elements other than capacitor elements Cser, C4, and C9, the distance from capacitor element Cser gradually increases as the capacitance decreases. Capacitor elements that are not positioned close together are more likely to experience capacitance deviations than those positioned close together, but their capacitance is smaller, so the impact is smaller.

[0221] [Third embodiment]

[0222] Figure 25 This diagram shows the circuit configuration corresponding to six columns in the data signal output circuit 50 of the electro-optical device 10 according to the third embodiment. The six columns correspond to two columns of color pixels, specifically, columns corresponding to R, B, G, R, B, and G. In the diagram, width 6W is twice the length of width 3W. For convenience, the circuits corresponding to the columns of data lines R14, B14, and G14 on the left side of the diagram are designated Rb1, Bb1, and Gb1, respectively, while the circuits corresponding to the columns of data lines R14, B14, and G14 on the right side are designated Rb2, Bb2, and Gb2, respectively.

[0223] like Figure 25 As shown, in the third embodiment, the circuits Rb1 , Rb2 , Bb1 , Bb2 , Gb1 , and Gb2 are sequentially arranged in a row along the Y direction within a range wider than the width W and narrower than the width 6W.

[0224] Therefore, in the third embodiment, the circuits Rb1, Rb2, Bb1, Bb2, Gb1, and Gb2 only need to be within a range narrower than the width 6W. Figure 14 The first embodiment shown, Figure 24 Compared with the second embodiment shown, it is possible to more easily cope with the narrowing of the width W.

[0225] [Fourth embodiment]

[0226] Figure 26 This diagram shows the electro-optical device 10 according to the fourth embodiment, focusing on the data line 14 of the j-th column in the data signal output circuit 50 , and extracting any one of the circuits Rb, Bb, and Gb corresponding to the j-th column.

[0227] In a fourth embodiment, Figure 14 The first embodiment shown is different in that first DA conversion circuits Upb corresponding to upper bits and second DA conversion circuits Lwb corresponding to lower bits are arranged in two rows.

[0228] Specifically, in the first DA converter circuit Upb, capacitor element C9, circuit D9_L1L2, capacitor element C8, circuit D8_L1L2, capacitor element C7, circuit D7_L1L2, capacitor element C6, circuit D6_L1L2, capacitor element C5, and circuit D5_L1L2 are arranged in a row in the Y direction. Furthermore, in the second DA converter circuit Lwb, capacitor element C4, circuit D4_L1L2, capacitor element C3, circuit D3_L1L2, capacitor element C2, circuit D2_L1L2, capacitor element C1, circuit D1_L1L2, capacitor element C0, and circuit D0_L1L2 are arranged in the Y direction adjacent to the row of the first DA converter circuit Upb.

[0229] In the fourth embodiment, the selection circuit 520 is located at the bottom in the figure, ie, close to the control circuit 30 , and the capacitive element Cser is located at the top in the figure, ie, close to the display area 100 .

[0230] Figure 27 is a diagram showing a comparative example of the fourth embodiment. In this comparative example, the arrangement order of the elements in the second DA conversion circuit Lwb is the same as Figure 26 Specifically, in this comparative example, in the second DA converter circuit Lwb, capacitor element C0, circuit D0_L1L2, capacitor element C1, circuit D1_L1L2, capacitor element C2, circuit D2_L1L2, capacitor element C3, circuit D3_L1L2, capacitor element C4, and circuit D4_L1L2 are arranged in a row in the Y direction.

[0231] exist Figure 26 The fourth embodiment shown and Figure 27 In the comparative example shown, there seems to be no difference at first glance, but a difference occurs when the basic capacitance elements C0 to C9 are connected in parallel in a number corresponding to the weight.

[0232] As described above, the capacitance of capacitors C0 to C4 (C5 to C9) is 1:2:4:8:16. Therefore, in the fourth embodiment, the number and arrangement of parallel-connected basic capacitors corresponding to a capacitance of "1" are considered for capacitors C0 to C4 (C5 to C9).

[0233] Figure 28 It is a diagram for explaining the superiority of the fourth embodiment over the comparative example.

[0234] The left column in the figure shows the component configuration of the fourth embodiment, and the right column shows the component configuration of the comparative example. In the figure, the shaded areas represent the components associated with the first DA converter circuit Upb, while the unshaded areas represent the components associated with the second DA converter circuit Lwb. In the first DA converter circuit Upw and the second DA converter circuit Lwb, the circuits D0_L1L2 to D9_L1L2 are identical in size.

[0235] In addition, Figure 28 In FIG. 1 , circuits D0_L1L2 to D9_L1L2 are described only as D0 to D9 due to space constraints.

[0236] like Figure 28 As shown, among the capacitor elements C0 to C9, when the basic capacitor elements connected in parallel are arranged in two columns, in the fourth embodiment, the number of rows required for the capacitor elements C5 to C9 (C0 to C4) is "1," "1," "2," "4," and "8," for a total of 16 rows. On the other hand, in the comparative example, the number of rows required for the capacitor elements C5 to C9 (C4 to C0) is "5," "3," "2," "3," and "5," for a total of 18 rows.

[0237] Therefore, in the fourth embodiment, the length in the Y direction can be reduced by two rows of basic capacitive elements compared to the comparative example, and thus space can be saved accordingly.

[0238] [Application Examples, Modification Examples]

[0239] Furthermore, in the various embodiments described above (hereinafter referred to as “embodiments etc.”), the OLED 130 is described as an example of a display element, but other display elements may be used. For example, an LED may be used as a display element.

[0240] In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 500 , but the number of bits is not limited thereto.

[0241] In the embodiment, the data is divided into two parts, namely, the lower bits D0 to D4 and the upper bits D5 to D9. However, the data can be divided into three or more parts. For example, the data can be divided into three parts, namely, the lower bits D0 to D2, the middle bits D3 to D6, and the upper bits D7 to D9. In the case of such a three-part division, the DA conversion circuit 500 becomes Figure 29 The structure shown.

[0242] Specifically, the DA conversion circuit 500 is configured such that the other ends of the capacitor elements C0 to C2 are connected to one end of the capacitor element Cser1, the other end of the capacitor element Cser1 is connected to the other ends of the capacitor elements C3 to C6 and one end of the capacitor element Cser2, and the other end of the capacitor element Cser2 is connected to the other ends of the capacitor elements C7 to C9 and the data line 14. Furthermore, in this configuration, when the connection line between the other ends of the capacitor elements C0 to C2 and the capacitor element Cser1 is set as the relay line 14b, and the connection line between the other end of the capacitor element Cser1 and the other ends of the capacitor elements C3 to C6 is set as the relay line 14c, during the initialization period (a), the potential Vrst can be applied to the relay lines 14b and 14c via the switches Rsw1 and Rsw2.

[0243] In this configuration, voltages corresponding to the weights of upper bits D7 to D9 are output to data line 14 via capacitors C7 to C9 and voltage selection circuits 517 to 519. Therefore, the circuit including capacitors C7 to C9 and voltage selection circuits 517 to 519 serves as the upper first DA converter circuit Upb.

[0244] Voltages corresponding to the weights of the middle bits D3 to D6 are output to the data line 14 via capacitors C3 to C6, Cser2, and voltage selection circuits 513 to 516. Therefore, the configuration including capacitors C3 to C6, voltage selection circuits 513 to 516, and excluding capacitor Cser2 constitutes the middle bit DA converter circuit Mdb.

[0245] Furthermore, voltages corresponding to the weights of the lower bits D0 to D2 are output to the data line 14 via the capacitors C0 to C2, Cser1, and Cser2, and the voltage selection circuits 510 to 512. Therefore, the configuration including the capacitors C0 to C2 and the voltage selection circuits 510 to 512, excluding the capacitors Cser1 and Cser2, constitutes the lower-bit second DA conversion circuit Lwb.

[0246] In addition, Figure 29 In the illustrated structure, among the 10 bits of video data Vdata, bits D7 to D9 are examples of two or more upper bits, and bits D0 to D2 are examples of a portion of the bits excluding the two or more upper bits.

[0247] In this structure, capacitor elements C7 to C9 are examples of a high-order capacitor element portion, where, for example, capacitor element C7 is an example of a first capacitor element, and capacitor element C8 is an example of a second capacitor element. Furthermore, in this structure, capacitor elements C0 to C2 are examples of a low-order capacitor element portion, where, for example, capacitor element C0 is an example of a third capacitor element, and capacitor element C1 is an example of a fourth capacitor element.

[0248] In the embodiment and the like, a configuration is employed in which the threshold voltage of the transistor 121 in the pixel circuit 110 is compensated. However, a configuration in which the threshold voltage is not compensated may be employed. Specifically, a configuration in which the transistor 123 is omitted may be employed.

[0249] The channel type of transistors 66 and 121 to 125 is not limited to the embodiment, etc. Moreover, these transistors 66 and 121 to 125 may be replaced with transmission gates as appropriate. Conversely, the transmission gates Tg0 to Tg2 may be replaced with single-channel transistors.

[0250] [Electronic equipment]

[0251] Next, an electronic device to which the electro-optical device 10 of the embodiment is applied will be described. The electro-optical device 10 is suitable for high-definition display applications with small pixel sizes. Therefore, a head-mounted display will be described as an example of an electronic device.

[0252] Figure 30 is a diagram showing the appearance of a head-mounted display. Figure 31 is a diagram showing its optical structure.

[0253] First, if Figure 30 As shown in FIG, the head mounted display 300 has temples 310, a nose bridge 320, and lenses 301L and 301R similar to ordinary glasses in appearance. Figure 31 As shown, the head mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the nose bridge 320 and on the back side (lower side in the figure) of the lenses 301L and 301R.

[0254] The image display surface of the electro-optical device 10L is Figure 31 302R. As a result, the display image of the electro-optical device 10L is emitted in the direction of 9 o'clock in the figure through the optical lens 302L. The semi-transparent half-reflecting mirror 303L reflects the display image of the electro-optical device 10L in the direction of 6 o'clock, while on the other hand, allowing light incident from the direction of 12 o'clock to pass through. The image display surface of the electro-optical device 10R is configured so as to be on the right side opposite to the electro-optical device 10L. As a result, the display image of the electro-optical device 10R is emitted in the direction of 3 o'clock in the figure through the optical lens 302R. The semi-transparent half-reflecting mirror 303R reflects the display image of the electro-optical device 10R in the direction of 6 o'clock, while on the other hand, allowing light incident from the direction of 12 o'clock to pass through.

[0255] In this configuration, the wearer of the head mounted display 300 can observe the display images of the electro-optical devices 10L and 10R in a see-through state that overlaps with the external scene.

[0256] In the head mounted display 300 , if the electro-optical device 10L displays the left-eye image and the electro-optical device 10R displays the right-eye image in binocular images with parallax, the wearer can perceive the displayed images as having depth and three-dimensionality.

[0257] Furthermore, the electronic device including the electro-optical device 10 can be applied to not only the head-mounted display 300 but also an electronic viewfinder in a video camera, a lens-interchangeable digital camera, and the like.

[0258] [Note]

[0259] An electro-optical device according to one embodiment (embodiment 1) comprises: a display element provided corresponding to an intersection of a data line and a scan line; and a DA conversion circuit, the DA conversion circuit comprising: a first DA conversion circuit for converting two or more upper bits of a plurality of bits into a first grayscale voltage, and applying the first grayscale voltage to the data line, the first grayscale voltage corresponding to the two or more upper bits; a second DA conversion circuit for converting some or all of the bits of the plurality of bits other than the two or more upper bits into a second grayscale voltage reflecting some or all of the bits other than the two or more upper bits; and a connection capacitor, one end of which is electrically connected to the second DA conversion circuit and the other end of which is electrically connected to the data line, the first DA conversion circuit having a high-order capacitance element portion, the high-order capacitance element portion corresponding to the two or more high-order bits, including a first capacitance element and a second capacitance element, the first capacitance element and the second capacitance element being arranged in a direction along the data line, the second DA conversion circuit having a low-order capacitance element portion, the low-order capacitance element portion corresponding to a part or all of the bits other than the two or more high-order bits, including a third capacitance element and a fourth capacitance element, the third capacitance element and the fourth capacitance element being arranged in a direction along the data line.

[0260] According to Method 1, the voltage converted by the second DA conversion circuit is compressed via the connection capacitor and output to the data line. In Method 1, the first and second capacitor elements included in the upper capacitor element portion are arranged along the data line, and the third and fourth capacitor elements included in the lower capacitor element portion are also arranged along the data line. This allows for smaller dimensions, for example, compared to a configuration in which these capacitor elements are arranged perpendicular to the data line.

[0261] In the electro-optical device as a specific embodiment (method 2) of method 1, the high-order capacitance element portion, the connecting capacitor and the low-order capacitance element portion are arranged in a direction along the data line, and the connecting capacitor is arranged between the high-order capacitance element portion and the low-order capacitance element portion.

[0262] According to this method 2, the wiring length of the data line can be shortened compared to a structure in which the high-order capacitance element part, the low-order capacitance element part, and the connection capacitor are arranged in this order, or in which the connection capacitor, the high-order capacitance element part, and the low-order capacitance element part are arranged in this order.

[0263] In the electro-optical device of a specific embodiment (Aspect 3) of Aspect 1 or Aspect 2, the connection capacitor is provided between the data line and a relay line to which the second grayscale voltage converted by the second DA conversion circuit is applied.

[0264] In the electro-optical device of a specific embodiment (Aspect 4) of Aspect 3, the relay line is provided along the data line, and the data line and the relay line are not arranged in parallel. According to this Aspect 4, both the wiring length of the data line and the wiring length of the relay line can be shortened.

[0265] Furthermore, "not arranged in parallel" means that there is no portion where the data line and the trunk line are arranged in parallel, and specifically, there is no portion where the data line and the trunk line overlap when viewed in a direction perpendicular to the data line.

[0266] In an electro-optical device according to a specific embodiment (Aspect 5) of any one of Aspects 1 to 4, a width of the first DA conversion circuit, the connection capacitor, and the second DA conversion circuit along the scanning line is greater than a first width between the data line and a data line adjacent to the data line along the scanning line, and less than six times the first width. According to Aspect 5, even if the data line arrangement interval is narrowed, it can be easily accommodated.

[0267] In an electro-optical device that is a specific embodiment (embodiment 6) of any one of embodiments 1 to 5, the wiring for supplying a signal to one end of the high-level capacitor element portion and the data line for outputting a signal from the other end of the high-level capacitor element portion are arranged in different wiring layers.

[0268] According to this embodiment 6, since the wiring for the signal supplied to one end of the high-voltage capacitor element portion and the wiring for the signal output from the other end of the high-voltage capacitor element portion are arranged in different wiring layers, noise caused by voltage changes is less likely to propagate.

[0269] In the electro-optical device according to a specific embodiment (embodiment 7) of embodiment 6, the data line is provided between two shield lines of a fixed potential.

[0270] According to aspect 7, noise is less likely to propagate to the data lines, and thus degradation of display quality due to voltage fluctuations on the data lines can be suppressed.

[0271] An electronic device according to any specific embodiment (Aspect 8) of Embodiments 1 to 7 includes the electro-optical device according to any of the above embodiments. According to this aspect 8, miniaturization and downsizing of the electro-optical device are facilitated.

Claims

1. An electro-optical device, wherein: The electro-optical device comprises: a data line extending along a first direction; a scan line intersecting the data line; A display element is provided in a display area corresponding to an intersection of the data line and the scan line; as well as A DA conversion circuit converts a plurality of bits into a voltage corresponding to the grayscale of the display element outside the display area. The DA conversion circuit includes: a first DA conversion circuit for converting two or more upper bits of the plurality of bits into a first grayscale voltage and applying the first grayscale voltage to the data line, wherein the first grayscale voltage corresponds to the two or more upper bits; a second DA conversion circuit, disposed on an opposite side of the display area from the first DA conversion circuit in a plan view, and configured to convert a portion or all of the bits other than the two or more upper bits among the plurality of bits into a second grayscale voltage reflecting a portion or all of the bits other than the two or more upper bits; a connecting capacitor disposed between the first DA conversion circuit and the second DA conversion circuit in a plan view; as well as a relay line electrically connected to one end of the connection capacitor and extending along the first direction, The data line is electrically connected to the other end of the connection capacitor, The first DA conversion circuit includes a high-order capacitance element portion, the high-order capacitance element portion corresponding to each of the two or more high-order bits, and including a first capacitance element and a second capacitance element. The first capacitor element and the second capacitor element are arranged along the first direction and are electrically connected to the data line. The second DA conversion circuit includes a low-order capacitance element portion corresponding to a portion or all of the bits other than the two or more high-order bits, and including a third capacitance element and a fourth capacitance element. The third capacitor element and the fourth capacitor element are arranged along the first direction and are electrically connected to the relay line. One electrode of each of the first capacitive element, the second capacitive element, the third capacitive element, and the fourth capacitive element overlaps with another electrode in a plan view. The data line overlaps with the first capacitor element and the second capacitor element in a plan view. The relay line overlaps the third capacitive element and the fourth capacitive element in a plan view.

2. The electro-optical device according to claim 1, wherein The high-level capacitance element portion, the connection capacitor, and the low-level capacitance element portion are arranged in a direction along the data line. The connection capacitor is provided between the high-level capacitance element portion and the low-level capacitance element portion.

3. The electro-optical device according to claim 1, wherein The connection capacitor is provided between the relay line to which the second grayscale voltage converted by the second DA conversion circuit is applied and the data line.

4. The electro-optical device according to claim 3, wherein The relay line is arranged in a direction along the data line, The data lines and the relay lines are arranged non-parallel.

5. The electro-optical device according to claim 1, wherein The width of the first DA conversion circuit, the connection capacitor, and the second DA conversion circuit in the direction along the scan line is larger than a first width between the data line and a data line adjacent to the data line in the direction along the scan line, and smaller than 6 times the first width. The electro-optical device according to claim 1 , wherein: A wiring for supplying a signal to one end of the high-level capacitance element portion and the data line for outputting a signal from the other end of the high-level capacitance element portion are provided in different wiring layers.

7. The electro-optical device according to claim 6, wherein The data line is arranged between two shielding lines with fixed potential.

8. An electronic device, wherein: This electronic equipment comprises the electro-optical device according to claim 1 .

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