Changing the time average of feedback of a memory system

Abstract

This application is directed to changing the time averaging of feedback for a memory system. An apparatus can include a voltage supply, a memory array, and a regulator coupled with the voltage supply and memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus can also include a voltage sensor configured to measure a second voltage of the memory array, and a digital feedback circuit coupled with the memory array and regulator and configured to generate feedback comprising information averaged over a duration of time based at least in part on the second voltage measured by the voltage sensor, and transmit an analog signal to the regulator based at least in part on the feedback.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 243,444, filed April 28, 2021, entitled “VARYING A TIME AVERAGE FOR FEEDBACK OF A MEMORY SYSTEM,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves altering the time averaging of feedback in memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a voltage supply, a memory array, and a regulator, the regulator being coupled to the voltage supply and the memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus may further include: a voltage sensor configured to measure a second voltage of the memory array; and a digital feedback circuit coupled to the memory array and the regulator and configured to generate feedback, at least in part, based on the second voltage measured by the voltage sensor, including information averaged over a duration, and to transmit an analog signal to the regulator at least in part based on the feedback.

[0007] A method is described. The method may include: transmitting a first voltage from a voltage source to a regulator; transmitting a second voltage from the regulator to a memory array, at least in part based on the transmission of the first voltage; receiving a first signal at a digital feedback circuit indicating a voltage of the memory array, at least in part based on the transmission of the second voltage to the memory array; generating feedback by the digital feedback circuit, at least in part based on the receipt of the first signal, containing averaged information over a duration; and transmitting an analog signal from the digital feedback circuit to the regulator, at least in part based on the generation of the feedback.

[0008] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller may be configured such that the device: transmits a first voltage from a voltage source to a regulator; transmits a second voltage from the regulator to the memory array, at least in part based on the transmission of the first voltage; receives a first signal at a digital feedback circuit indicating the voltage of the memory array, at least in part based on the transmission of the second voltage to the memory array; generates feedback by the digital feedback circuit, at least in part based on the receipt of the first signal, including information averaged over a duration; and transmits an analog signal from the digital feedback circuit to the regulator, at least in part based on the generation of the feedback. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports changing the time averaging of feedback in a memory system, based on the examples disclosed herein.

[0010] Figure 2 This document describes examples of memory dies that support changing the time-averaged feedback of a memory system, based on the examples disclosed herein.

[0011] Figure 3 This document describes examples of circuits that support changing the time averaging of feedback in a memory system, based on the examples disclosed herein.

[0012] Figure 4 This document illustrates an example of a flowchart that supports changing the time averaging of feedback in a memory system, based on the examples disclosed herein.

[0013] Figure 5 A block diagram is shown of a memory device that supports time averaging of feedback in a memory system, based on examples disclosed herein.

[0014] Figure 6 The flowchart illustrates one or more methods for supporting the time averaging of feedback in a memory system, based on the examples disclosed herein. Detailed Implementation

[0015] Memory devices may comprise memory dies or memory arrays for storing data. In some instances, a voltage source (e.g., in a power distribution network (PDN)) may supply voltage to the memory array during operations performed by the memory device. Due to the intrinsic resistance in the memory die, the actual voltage supplied to the memory array may be less than the voltage generated by the voltage source. In such instances, the voltage source may be coupled to a regulator to regulate the voltage supply to the memory array. In some cases, the intrinsic capacitance and current requirements of the memory array may cause the voltage supplied to the memory array by the regulator to oscillate—for example, if the current changes rapidly, the stability of the voltage supplied to the memory array by the regulator may be affected. In some instances, a resistor-capacitor (RC) circuit may be coupled to the voltage supplied to the memory array and provide feedback to the regulator—e.g., an analog feedback circuit. In such instances, the feedback filter (e.g., providing feedback to the regulator) may be fixed—for example, the resistance and capacitance of the RC circuit may be fixed and may not be changeable. Therefore, the RC circuit may not be able to handle different bandwidth and performance levels of the memory array. Additional RC circuitry (e.g., to match various bandwidths and performance levels) can consume excessive space in the memory device. Furthermore, RC circuitry can take a relatively long time to reflect changes in the supplied voltage.

[0016] This document describes systems, techniques, and apparatus for memory devices to supply voltage to a memory array using a regulator and a digital feedback circuit that generates feedback containing information averaged over a certain duration. For example, the digital feedback circuit may be coupled to a regulator and a memory array and receive a signal indicating the voltage supplied to the memory array. The digital feedback circuit may include an oscillator, a counter, and a digital-to-analog circuit (DAC). The oscillator may generate a second analog signal operating at a first frequency in response to the magnitude of the signal indicating the voltage supplied to the memory array. In some instances, the counter may count the number of oscillations of the second analog signal over a selected duration. That is, the memory device may select the duration based on the performance or bandwidth constraints of the memory device—for example, a shorter duration may increase responsiveness and a longer duration may result in a more stable output. The DAC may convert the digital signal output from the counter into a third analog signal and transmit the third analog signal back to the regulator to provide feedback to improve the regulation of the voltage supplied to the memory array. By utilizing the digital feedback circuit, the memory device can supply a better-regulated voltage to the memory array and handle various bandwidth and performance levels of the memory cells. Additionally, the digital feedback circuit can save area on the memory device compared to other examples.

[0017] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figure 3 and 4 The features of this disclosure are described in the context circuitry and flowcharts. Further details are provided by reference to [reference needed]. Figure 5 and 6 The device diagrams and flowcharts described herein, which involve changing the time averaging of feedback in a memory system, are used to illustrate and refer to these and other features of this disclosure.

[0018] Figure 1 This document describes an example of a system 100 that supports changing the time averaging of feedback in a memory system, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0019] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0020] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0021] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more host devices of different types. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulated signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0022] Memory device 110 is operable to store data for components of host device 105. In some instances, memory device 110 may act as a secondary or subordinate device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0023] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0024] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0025] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0026] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0027] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0028] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0029] External memory controller 120 can be used to enable the communication of one or more of the following between system 100 or a component of host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0030] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0031] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0032] In some instances, memory device 110 may supply voltage to memory die 160-a. For example, memory device 110 may include a power delivery network (PDN) that supplies voltage to memory die 160. In some instances, memory device 110 may supply voltage to memory die 160 via a regulator. To increase the stability and accuracy of the voltage supplied to memory die 160, memory device 110 may also include digital feedback circuitry coupled to memory die 160 and the regulator. In such instances, the digital feedback circuitry may be configured to generate a feedback signal that includes information over a variable duration—for example, memory device 110 may be configured to select a duration from a plurality of durations. For example, memory device 110 may select a longer duration to supply a more stable voltage to memory die 160 or select a shorter duration to adjust the voltage supplied to memory die 160 more frequently. By utilizing digital feedback circuitry over a variable duration, memory device 110 may adjust the voltage supply to memory die 160 based on the bandwidth and performance level of the memory cells in memory die 160.

[0033] Figure 2 This document describes an example of a memory die 200 that supports changing the time-averaged feedback of a memory system, based on the examples disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which can be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multilevel memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference]. Figure 1 The memory array 170 is described.

[0034] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic storage components, such as capacitor 230, and switching components 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be a cell board reference voltage, such as Vpl, or ground, such as Vss.

[0035] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern, such as a grid pattern. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0036] Memory cell 205 can be accessed, for example, by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection point by biasing word line 210 and digital line 215 (e.g., by applying a voltage to word line 210 or digital line 215). The intersection point of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of memory cell 205.

[0037] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital line 215 based on the received column addresses.

[0038] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating activation switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and can be coupled to digital line 215 when switch assembly 235 is activated.

[0039] Sensing component 245 is operable to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or additionally convert signals generated by accessing memory cell 205. Sensing component 245 may compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., to input / output 255) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0040] The local memory controller 260 can control access to memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). In some instances, one or more of the row decoder 220, column decoder 225, and sensing component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the execution of said one or more operations. The local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target number line 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may be varied and may differ for the various operations discussed in operating the memory die 200.

[0041] The local memory controller 260 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0042] In some instances, memory devices (e.g., as referenced) Figure 1The described memory device 110 can supply voltage to memory die 200 during operation. For example, the memory device can utilize a PDN to generate the voltage for memory die 200. Additionally, the memory device can include regulators and digital feedback circuitry to increase the accuracy and stability of the voltage supplied to memory die 200—for example, the regulators and digital feedback circuitry can adjust the voltage from the PDN to account for the intrinsic capacitance and current requirements of memory die 200. In some instances, the digital feedback circuitry can generate a time-averaged feedback signal over a duration selected by the memory device. That is, the memory device can select a duration from multiple durations to monitor the feedback signal. In such instances, the memory device can adjust the duration based on the performance level or bandwidth constraints of the memory cells 205 of memory die 200. For example, the memory device can select a longer duration to supply a more stable voltage to memory die 200 or select a shorter duration to adjust the voltage supplied to memory die 200 more frequently.

[0043] Figure 3 This document describes an example of a circuit 300 that supports changing the time averaging of feedback in a memory system, based on the examples disclosed herein. Circuit 300 can be used to supply voltage from voltage source 305 to a memory device (e.g., as shown in the reference). Figure 1 The memory array 335 in the described memory device 110. In some instances, circuitry 300 may be included in the memory die (e.g., as referenced). Figure 1 The memory die 160 described is located on the memory die. In other instances, analog feedback circuitry 350 or digital feedback circuitry 360, or both, may be located outside the memory die. Circuitry 300 may include voltage source 305, regulator 315, memory array 335, analog feedback circuitry 350, digital feedback circuitry 360, and voltage sensor 385. Analog feedback circuitry 350 may further include resistor-capacitor (RC) circuitry 355. Digital feedback circuitry 360 may further include oscillator 365, counter 375, and digital-to-analog converter (DAC) 380. In some instances, circuitry 300 may be controlled by a controller (e.g., as described in Reference 300). Figure 1 The described device is controlled by memory controller 155 or local memory controller 165. In other instances, components of circuit 300 may be operated by fuses or timers.

[0044] Voltage source 305 may be configured to generate or supply voltage to memory array 335. For example, voltage source 305 may generate voltage to activate or supply voltage to memory array 335 during operation (e.g., read, write, refresh, or other operations associated with memory array 335). In some instances, voltage source 305 may be a pad. In other instances, voltage source may also be referred to as PDN. In some cases, intrinsic resistance 310 may cause a drop in the voltage generated or supplied by voltage source 305—for example, the voltage source may generate a reduced voltage (VDD) due to intrinsic resistance 310. That is, intrinsic resistance 310 may not be a physical component in circuit 300, but may represent the intrinsic resistance of the supply voltage or the supply line of memory array 335.

[0045] Regulator 315 may be configured to receive a voltage from voltage source 305 and supply a second voltage to memory array 335—for example, outputting a second voltage 330 to memory array 335. In some instances, regulator 315 may be configured to regulate the output second voltage 330 to be the same as the desired voltage of memory array 335—for example, regulating the second voltage 330 to be as close as possible to VDD. In some instances, regulator 315 may receive a reference voltage 320 (e.g., VDD) and a feedback signal 325 to determine the difference between the desired voltage (e.g., VDD) of memory array 335 and the actual voltage of memory array 335. In such instances, the actual voltage of memory array 335 may be affected by the intrinsic resistance 390, capacitance 340, and current demand 345 of memory array 335. That is, regulator 315 can be configured to regulate the voltage supplied to the memory array (e.g., second voltage 330) and reduce the inherent drop in second voltage 330 based on the intrinsic resistance 390, capacitance 340, and current demand 345 of the memory array 335. In such examples, the intrinsic resistance 390, capacitance 340, and current demand 345 may not be physical components in circuit 300, but may be symbolic representations of the intrinsic properties of the memory device. In some examples, regulator 315 may receive feedback signal 325 from analog feedback circuit 350. In other examples, regulator 315 may receive feedback signal 325 from digital feedback circuit 360. That is, circuit 300 may further include switching or other similar components to select analog feedback circuit 350 or digital feedback circuit 360.

[0046] Memory array 335 can be configured to store data for use with a host device (e.g., as referenced). Figure 1The data described in the host device 105). In some instances, the memory array 335 may be configured to receive a second voltage 330 of the output, for example, during operation associated with the memory array 335. Based on the intrinsic resistance 390, capacitance 340, and current requirement 345 of the memory array 335, the actual voltage at the memory array 335 may differ from the desired voltage (e.g., VDD) of the memory array 335.

[0047] Voltage sensor 385 can be configured to measure the actual voltage of memory array 335, for example, based on intrinsic resistance 390, capacitance 340, and current demand 345 of memory array 335. In some instances, voltage sensor 385 can be further configured to generate a signal indicating the actual voltage of the memory array to feedback circuitry. For example, voltage sensor 385-a can provide a signal indicating the voltage at memory array 335 to digital feedback circuitry 360, and voltage sensor 385-b can provide a signal indicating the voltage at memory array 335 to analog feedback circuitry 350.

[0048] In some instances, circuit 300 may include one or more analog feedback circuits 350 or one or more digital feedback circuits 360, but not both simultaneously. In such instances, circuit 300 may be configured with either analog feedback circuit 350 or digital feedback circuit. In some instances, circuit 300 may include both analog feedback circuit 350 and digital feedback circuit 360. In such instances, it is selectable whether circuit 300 will use analog feedback circuit 350 or digital feedback circuit 360. In some cases, the selection between analog feedback circuit 350 and digital feedback circuit 360 can be dynamically selected by the control logic of circuit 300. In some cases, the selection between analog feedback circuit 350 and digital feedback circuit 360 can be determined during the manufacturing or testing process and can be hard-decoded into the circuit (e.g., using fuses or antifuse).

[0049] Analog feedback circuit 350 can be configured to generate and transmit feedback signal 325 to regulator 315. In some instances, analog feedback circuit 350 may include one or more RC circuits 355. In some instances, RC circuit 355 can be configured to generate analog feedback signal based on a signal received from voltage sensor 385-b indicating the voltage of the memory array and the resistance and capacitance values ​​of RC circuit 355. That is, different resistance and capacitance values ​​for the resistor and capacitor, respectively, can change the feedback signal 325 generated for regulator 315. In some instances, the number of different RC circuit combinations (e.g., combinations of different resistance and capacitance values) may be limited by the size of memory die 200—for example, the analog feedback circuit 350 may not be able to achieve certain results using feedback signal 325 for different bandwidth constraints and performance levels of memory array 335.

[0050] Digital feedback circuitry 360 may be configured to generate feedback signal 325 and transmit the feedback signal to regulator 315. In some instances, oscillator 365 may receive a signal (e.g., a first analog signal) indicating the voltage of memory array 335 from voltage sensor 385-a. In such instances, the plurality of inverters 370 may be configured to receive the first analog signal and generate a second analog signal operating at a first frequency in response to the magnitude of the signal indicating the voltage of memory array 335. That is, the second analog signal has an oscillation quantity proportional (or inversely proportional) to the magnitude of the signal indicating the voltage of memory array 335 (e.g., the first analog signal). In some instances, oscillator 365 may be further configured to transmit the second analog signal to counter 375.

[0051] Counter 375 can be configured to measure or determine the number of oscillations of a second analog signal received from oscillator 365 during a selected duration. For example, the counter can initiate a count and increment the count value by an amount (1) each time an oscillation is measured. In some instances, counter 375 can generate a digital signal based on determining the number of oscillations and transmit the digital signal to DAC 380. In some instances, counter 375 can be configured to determine the number of oscillations in a variable duration. That is, counter 375 can be configured to determine the number of oscillations in a particular duration among a plurality of durations. In such instances, the memory device can select a duration from the plurality of durations before counter 375 receives the second analog signal or before a signal indicating the voltage of memory array 335 at digital feedback circuit 360. In some cases, the memory device can be based on memory cells in memory array 335 (e.g., as referenced). Figure 2 The duration is selected based on the performance level or bandwidth constraints of the described memory cell 205. For example, the memory device may select a shorter duration to adjust the voltage supplied to the memory array 335 more frequently—for example, to adjust the second voltage 330 output by the regulator more frequently. This allows the memory device to reduce voltage drops supplied to the memory array 335. In other instances, the memory device may select a longer duration to increase the stability of the voltage supplied to the memory array 335. Additionally, the counter 375 may be configured to reset the count value after the digital signal is transmitted to the DAC 380 or before receiving different analog signals from the oscillator 365.

[0052] DAC 380 can be configured to convert a digital signal received from counter 375 into a third analog signal. DAC 380 can also transmit the third analog signal to regulator 315 (or control logic associated with regulator 315). In some instances, the third analog signal (e.g., feedback signal 325) may contain averaged feedback information over a selected duration. For example, the third analog signal may indicate the average voltage of the memory array over the selected duration. In some cases, feedback signal 325 may enable regulator 315 to adjust the output second voltage 330 to better align with the desired voltage of memory array 335. By utilizing digital feedback circuitry 360, the memory device can determine the averaged feedback information over a variable duration and adjust the voltage supplied to memory array 335 based on the bandwidth and performance level of memory cell 205.

[0053] Figure 4 This document illustrates an example of a flowchart 400 that supports changing the time averaging of feedback in a memory system, based on the examples disclosed herein. For instance, flowchart 400 may be derived from a memory device (e.g., as shown in the reference). Figure 1 The described memory device 110) and circuitry (e.g., as referenced) Figure 1 The circuit 400 described is executed. In some instances, the flowchart 400 may be executed by a controller (e.g., as referenced). Figure 1 The described device (memory controller 155 or local memory controller 165) executes the process. In other instances, flowchart 400 may be executed by circuit 300 or by fuses or timers in memory device 110. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise stated. Therefore, the illustrated examples are for illustrative purposes only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various examples. Therefore, not all processes are required in each example. Other process diagrams are possible. Flowchart 400 illustrates the memory device utilizing digital feedback circuitry (e.g., as referenced) for a variable duration. Figure 3 The described digital feedback circuit 360) sends a signal to the regulator (e.g., as in reference). Figure 3 An example of a regulator 315 described is provided with a negative feedback signal to a memory array (e.g., as referenced). Figure 3 The described memory array 335) is supplied with voltage.

[0054] In 405, the voltage source (e.g., as referenced) Figure 3 The voltage source 305 described herein can generate a voltage. For example, the voltage source can generate a voltage VDD. In some instances, the voltage source can also transmit the voltage to a regulator (e.g., as referenced). Figure 3 The regulator 315 described.

[0055] At 410, the regulator can supply a second voltage to the memory array (e.g., as referenced). Figure 3 The described memory array 335) regulates the voltage. In some instances, the regulator may generate a second voltage based on the voltage received from a voltage source. Additionally, the regulator may receive a reference voltage (e.g., the desired voltage for the memory array) and a negative feedback signal (e.g., such as a reference voltage). Figure 3 The feedback signal 325 is described. In these cases, the regulator can generate a second voltage based on the received reference voltage and the negative feedback signal.

[0056] In 415, voltage sensors (e.g., as reference) Figure 3 The described voltage sensor 385 measures a third voltage at the memory array. In some instances, the intrinsic resistance (e.g., intrinsic resistance 390), intrinsic capacitance (e.g., capacitance 340), or current drop (e.g., current demand 345) of the memory array, or any combination thereof, can cause the third voltage at the memory array to differ from the second voltage generated by the regulator. In such instances, the memory device can select a digital feedback circuit to generate a negative feedback signal to more accurately regulate the voltage supplied by the regulator. In some instances, the memory device can also deactivate the analog feedback circuit 350 when the digital feedback circuit is selected. Thus, the voltage sensor can generate an analog signal (e.g., a first analog signal) and transmit it to the digital feedback circuit to indicate the third voltage at the memory array.

[0057] At 420, an oscillator (e.g., oscillator 365) may generate a second analog signal based on a first analog signal received from a voltage sensor. In such examples, the oscillator may utilize multiple inverters (e.g., inverter 370) to generate the second analog signal. In some cases, the second analog signal generated by the oscillator may operate at a first frequency in response to the magnitude of the first analog signal. That is, the second analog signal has an oscillation quantity proportional to the magnitude of the first signal. In some instances, the oscillator may transmit the second analog signal to a counter (e.g., as referenced). Figure 3 The described counter 375).

[0058] At 425, the duration for the counter can be selected. For example, a controller (e.g., device memory controller 155 or local memory controller 165) can select the duration for the counter. In some instances, the duration of the counter can be variable. In such instances, the controller can select the duration for the counter from multiple durations. In some cases, the controller can select the duration based on the bandwidth constraints or performance level of the memory array. For example, the controller can select a duration of 100 nanoseconds. In some instances, the duration of the counter can be selected before generating a voltage source, before regulating the voltage, before measuring a third voltage of the memory array, or before the oscillator receives the first analog signal. In other instances, the controller can maintain the counter for a last duration—for example, the controller can maintain it for 100 nanoseconds based on a previous duration of 100 nanoseconds.

[0059] At 430, a counter can determine the number of oscillations of the second analog signal during the duration. For example, the counter can initiate a count based on the receipt of the second analog signal. In some instances, the counter can increment the count value by an amount (1) each time an oscillation of the second analog signal is measured—for example, incrementing the count value from zero (0) to one (1) based on the first oscillation of the second analog signal measured. In such instances, the counter can continuously increment the count value until the selected duration expires. After the duration expires, the counter can generate a digital signal indicating the number of oscillations of the second analog signal during the duration. Additionally, the counter can transmit the digital signal to a DAC (e.g., as referenced). Figure 3 (The DAC 380 is described). In some cases, the counter can also be reset based on the transmitted digital signal—for example, the counter can be reset to zero (0) based on the transmitted digital signal. In other instances, the counter can be reset when selecting the duration used for the counter or before the counter receives an analog signal from the oscillator.

[0060] In the 435, the DAC can convert a digital signal received from a counter into a third analog signal. In some instances, the DAC can also transmit the third analog signal to the regulator. That is, the third analog signal can be a negative feedback signal.

[0061] At 440, the regulator can adjust the generated voltage based on the received negative feedback signal. That is, the negative feedback signal can indicate the average voltage at the memory array over a duration. The regulator can adjust the voltage to bring the third voltage at the memory array closer to the desired voltage of the memory array—for example, closer to VDD. In some instances, after adjusting the voltage at the regulator, the circuitry can repeat the process described in 415 to 440. That is, a voltage sensor can measure the new voltage at the memory array based on the voltage adjustment of the regulator. The voltage sensor can transmit the new analog signal to an oscillator, and the oscillator can generate another analog signal operating at a second frequency in response to the magnitude of the new analog signal. The controller can then maintain the duration for the counter or select a second duration for the counter from the plurality of durations. The counter can then generate a second digital signal, which can be converted by a DAC and transmitted back to the regulator. By utilizing digital feedback circuitry, the memory device can better regulate the voltage supply based on a negative feedback signal averaged over a variable time. For example, because the negative feedback signal is over a variable time, the memory device can regulate the voltage based on different bandwidths or performance levels of the memory cells.

[0062] Figure 5 A block diagram 500 illustrates a memory device 520 that supports time averaging of feedback in a memory system according to an example disclosed herein. The memory device 520 may be as described in the reference... Figures 1 to 4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of means for performing various aspects of changing the time averaging of feedback in a memory system as described herein. For example, memory device 520 may include a transmission component 525, a receiving component 530, a generator component 535, a counter component 540, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0063] The transmission component 525 may be configured or otherwise support means for transmitting a first voltage from a voltage source to a regulator. In some instances, the transmission component 525 may be configured or otherwise support means for transmitting a second voltage from the regulator to a memory array, at least in part based on the transmission of the first voltage. In some instances, the transmission component 525 may be configured or otherwise support means for transmitting an analog signal from a digital feedback circuit to a regulator, at least in part based on generating feedback. In some cases, the transmission component 525 may be configured or otherwise support means for transmitting a first signal indicating the voltage of the memory array to an oscillator of the digital feedback circuit.

[0064] In some instances, the transmission component 525 may be configured or otherwise support a component for transmitting a second analog signal to a counter of a digital feedback circuit, at least in part, based on the generation of the second analog signal.

[0065] The receiving component 530 may be configured or otherwise supported to include means for receiving, at least in part, a first signal indicating the voltage of the memory array at a digital feedback circuit based on the transmission of a second voltage to the memory array. In some instances, the receiving component 530 may be configured or otherwise supported to include means for receiving, at a digital feedback circuit, a second signal indicating a third voltage of the memory array after the duration stated thereafter.

[0066] Generator component 535 may be configured or otherwise supported for generating feedback, at least in part, based on the receipt of a first signal, containing information averaged over a duration by a digital feedback circuit. In some cases, generator component 535 may be configured or otherwise supported for generating a second analog signal operating at a first frequency, at least in part, based on the transmission of a first signal to an oscillator, and the oscillator responding to the magnitude of the first signal. In some instances, generator component 535 may be configured or otherwise supported for generating a digital signal, at least in part, based on a determined number of oscillations.

[0067] In some instances, generator component 535 may be configured or otherwise supported for means of converting a digital signal into an analog signal at a digital-to-analog converter, at least in part based on the generation of a digital signal. In some cases, generator component 535 may be configured or otherwise supported for means of generating a third analog signal at an oscillator, at least in part based on the receipt of a second signal, and for transmitting the third analog signal to a counter. In some instances, generator component 535 may be configured or otherwise supported for means of generating a second digital signal, at least in part based on determining a second number of oscillations.

[0068] In some instances, the counter component 540 may be configured or otherwise supported to support means for selecting a duration for the counter from a plurality of durations. In some cases, the counter component 540 may be configured or otherwise supported to support means for determining at the counter the number of oscillations of a second analog signal during said duration, wherein the number of oscillations during said duration is associated with said feedback. In some instances, the counter component 540 may be configured or otherwise supported to support means for resetting the counter to a default value at least in part based on converting a digital signal to an analog signal. In some instances, the counter component 540 may be configured or otherwise supported to support means for selecting a duration for the counter. In some cases, the counter component 540 may be configured or otherwise supported to support means for determining at the counter a second number of oscillations of a third analog signal during said duration.

[0069] In some instances, the counter component 540 may be configured or otherwise supported to support means for selecting a second duration for the counter among the plurality of durations. In some instances, the counter component 540 may be configured or otherwise supported to support means for determining at the counter a second number of oscillations of a third analog signal during the said duration, and for generating a second digital signal at least in part based on the determination of the second number of oscillations.

[0070] Figure 6 A flowchart illustrating a method 600 for changing the time averaging of feedback in a memory system, based on examples disclosed herein, is shown. The operation of method 600 can be implemented by a memory device or a component thereof as described herein. For example, it can be implemented by, as referenced... Figures 1 to 5 The described memory device performs the operations of method 600. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0071] In 605, the method may include transmitting a first voltage from a voltage source to a regulator. Operation of 605 can be performed according to examples disclosed herein. In some instances, aspects of the operation of 605 may be determined by reference to [reference needed]. Figure 5 The described transmission component 525 is executed.

[0072] In 610, the method may include transmitting a second voltage from the regulator to the memory array, at least in part based on the transmission of the first voltage. Operation of 610 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 610 may be derived from references... Figure 5 The described transmission component 525 is executed.

[0073] In 615, the method may include receiving a first signal indicating the voltage of the memory array at a digital feedback circuit, at least in part based on transmitting a second voltage to the memory array. Operation of 615 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 615 may be as described in references... Figure 5 The described receiving component 530 is executed.

[0074] In 620, the method may include feedback generated by a digital feedback circuit, at least in part based on the receipt of a first signal, comprising information averaged over a duration. Operation of 620 can be performed according to examples as disclosed herein. In some examples, aspects of the operation of 620 may be as described in references... Figure 5 The described generator component 535 is executed.

[0075] In 625, the method may include transmitting an analog signal from a digital feedback circuit to a regulator, at least in part based on generating feedback. Operation of 625 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 625 can be found in references... Figure 5 The described transmission component 525 is executed.

[0076] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for transmitting a first voltage from a voltage source to a regulator, transmitting a second voltage from the regulator to a memory array at least in part based on the transmission of the first voltage, receiving a first signal at a digital feedback circuit indicating the voltage of the memory array at least in part based on the transmission of the second voltage to the memory array, generating feedback by the digital feedback circuit at least in part based on the receipt of the first signal, including information averaged over a duration, and transmitting an analog signal from the digital feedback circuit to the regulator at least in part based on the generation of the feedback.

[0077] Some aspects of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting a first signal indicating the voltage of a memory array to an oscillator of a digital feedback circuit, generating a second analog signal operating at a first frequency by the oscillator in response to the magnitude of the first signal, at least in part based on transmitting the first signal to the oscillator, and transmitting the second analog signal to a counter of the digital feedback circuit, at least in part based on generating the second analog signal.

[0078] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for selecting a duration for a counter from a plurality of durations, determining at the counter the number of oscillations of a second analog signal during said duration, wherein the number of oscillations during said duration may be associated with said feedback, and generating a digital signal at least in part based on determining the number of oscillations.

[0079] In some instances of the method 600 and apparatus described herein, the digital signal is converted into an analog signal at a digital-to-analog converter, at least in part, based on the generation of a digital signal.

[0080] Some aspects of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for resetting a counter to a default value based at least in part on converting a digital signal to an analog signal.

[0081] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving a second signal at a digital feedback circuit indicating a third voltage of a memory array after the said duration, and generating a third analog signal at an oscillator based at least in part on the receipt of the second signal, and transmitting the third analog signal to a counter.

[0082] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for selecting a duration for a counter, determining at the counter a second number of oscillations of a third analog signal during said duration, and generating a second digital signal at least in part based on the determination of the second number of oscillations.

[0083] Some aspects of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for selecting a second duration for a counter among the plurality of durations, determining at the counter a second number of oscillations of a third analog signal during the duration, and generating a second digital signal at least in part based on the determination of the second number of oscillations.

[0084] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0085] Describe an apparatus. The apparatus may include a voltage supply, a memory array, a regulator coupled to the voltage supply and the memory array and configured to supply a first voltage received from the voltage supply to the memory array, a voltage sensor configured to measure a second voltage of the memory array, and a digital feedback circuit coupled to the memory array and the regulator and configured to generate feedback, at least in part, based on the second voltage measured by the voltage sensor, including information averaged over a duration, and to transmit an analog signal to the regulator at least in part based on the feedback.

[0086] In some cases of the device, the digital feedback circuit further includes an oscillator comprising one or more inverters and configured to receive a signal indicating a second voltage of the memory array based at least in part on a second voltage measured by a voltage sensor.

[0087] In some cases of the device, the oscillator may be further configured to generate a second analog signal operating at a first frequency in response to the magnitude of the signal.

[0088] In some cases of the device, the digital feedback circuit may further include a counter coupled to an oscillator, the counter being configured to receive a second analog signal from the oscillator, and to determine a count of the number of oscillations of the second analog signal during the duration based on the received second analog signal, wherein the feedback is generated at least in part based on the count, and at least in part based on the determination of the number of oscillations during the duration to generate a digital signal.

[0089] In some instances of the device, the digital feedback circuit further includes a digital-to-analog circuit configured to receive digital signals and generate analog signals, wherein the digital feedback circuit transmits analog signals to the regulator based at least in part on the analog signals generated by the digital-to-analog circuit.

[0090] In some cases of the device, the digital feedback circuitry may be further configured to apply the duration from a series of multiple durations associated with the counter.

[0091] In some cases of the device, the counter can be configured to be reset to a default value, at least in part, based on transmitting digital signals to the digital / analog circuitry.

[0092] In some instances of the device, the analog signal indicates the average voltage of the memory array over the duration.

[0093] In some cases, the device may include a resistor-capacitor circuit coupled to a regulator and configured to generate an analog feedback signal based at least in part on a second voltage of the memory array and to transmit the analog feedback signal to the regulator.

[0094] In some instances of the device, the device may be configured to select between using a digital feedback circuit or a resistor-capacitor circuit.

[0095] Another device is described. The device may include a memory array and a controller, the controller being coupled to the memory array and configured such that the device transmits a first voltage from a voltage source to a regulator, transmits a second voltage from the regulator to the memory array at least in part based on the transmission of the first voltage, receives a first signal at a digital feedback circuit indicating the voltage of the memory array at least in part based on the transmission of the second voltage to the memory array, the digital feedback circuit generates feedback containing averaged information over a duration at least in part based on the receipt of the first signal, and transmits an analog signal from the digital feedback circuit to the regulator at least in part based on the generation of the feedback.

[0096] In some instances, the controller may be further configured such that the device transmits a first signal indicating the voltage of the memory array to the oscillator of the digital feedback circuit, at least in part based on transmitting the first signal to the oscillator to generate a second analog signal operating at a first frequency in response to the magnitude of the first signal, and at least in part based on generating the second analog signal to the counter of the digital feedback circuit.

[0097] In some cases, the controller may be further configured such that the device selects a duration for a counter from a plurality of durations, determines at the counter the number of oscillations of a second analog signal during the duration, wherein the number of oscillations during the duration may be associated with the feedback, and a digital signal is generated at least in part based on the determination of the number of oscillations.

[0098] In some cases of the device, the controller may be further configured such that the device converts the digital signal into an analog signal at a digital-to-analog converter, at least in part, based on the generation of the digital signal.

[0099] In some cases, the controller can be further configured such that the device resets the counter to its default value, at least in part, based on converting the digital signal to an analog signal.

[0100] In some instances, the controller may be further configured such that the device receives a second signal at a digital feedback circuit indicating a third voltage of the memory array after the said duration, generates a third analog signal at an oscillator based at least in part on the receipt of the second signal, and transmits the third analog signal to a counter.

[0101] In some cases, the controller may be further configured such that the device selects the duration for the counter and determines at the counter the second number of oscillations of the third analog signal during the duration, and generates a second digital signal based at least in part on the determination of the second number of oscillations.

[0102] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, which may have various bit widths.

[0103] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0104] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0105] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0106] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0107] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0108] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0109] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0110] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For instance, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0111] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0112] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0113] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0114] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Voltage supply; Memory array; A regulator coupled to the voltage supply and the memory array and configured to supply a first voltage received from the voltage supply to the memory array; A voltage sensor configured to measure a second voltage of the memory array; A resistor-capacitor circuit coupled to the regulator and configured to generate an analog feedback signal based at least in part on the second voltage of the memory array and transmit the analog feedback signal to the regulator; as well as A digital feedback circuit, coupled to the memory array and the regulator, is configured to generate feedback at least in part based on the second voltage measured by the voltage sensor, the feedback including averaged information over a duration, and to transmit an analog signal to the regulator at least in part based on the feedback.

2. The device according to claim 1, wherein the digital feedback circuit further comprises: An oscillator comprising one or more inverters and configured to receive a signal indicating the second voltage of the memory array, at least in part based on the second voltage measured by the voltage sensor.

3. The device of claim 2, wherein the oscillator is further configured to: A second analog signal operating at a first frequency is generated in response to the magnitude of the signal.

4. The device of claim 3, wherein the digital feedback circuit further comprises a counter coupled to the oscillator, the counter being configured to: Receive the second analog signal from the oscillator; A count of the number of oscillations of the second analog signal during the said duration is determined based on the received second analog signal, wherein the feedback is generated at least in part based on the count; and The digital signal is generated at least in part based on determining the number of oscillations during the duration.

5. The device according to claim 4, wherein the digital feedback circuit further comprises: A digital-to-analog circuit configured to receive the digital signal and generate the analog signal, wherein the digital feedback circuit transmits the analog signal to the regulator based at least in part on the analog signal generated by the digital-to-analog circuit.

6. The device of claim 4, wherein the digital feedback circuit is further configured to apply the duration from a plurality of durations associated with the counter.

7. The device of claim 4, wherein the counter is configured to be reset to a default value at least in part based on transmitting the digital signal to the digital / analog circuitry.

8. The device of claim 1, wherein the analog signal indicates the average voltage of the memory array during the duration.

9. The device of claim 1, wherein the device is configured to select between using the digital feedback circuit or the resistor-capacitor circuit.

10. A method comprising: The first voltage from the voltage source is transmitted to the regulator; The second voltage from the regulator is transmitted to the memory array, at least in part, based on the transmission of the first voltage; A first signal indicating the voltage of the memory array is transmitted to the oscillator of the digital feedback circuit; The first signal indicating the voltage of the memory array is received at the digital feedback circuit, at least in part, based on transmitting the second voltage to the memory array; At least in part, it is based on transmitting the first signal to the oscillator so that the oscillator generates a second analog signal operating at a first frequency in response to the magnitude of the first signal; The second analog signal is transmitted to the counter of the digital feedback circuit at least in part based on the generation of the second analog signal; Select the duration for the counter from a plurality of durations; The number of oscillations of the second analog signal during the duration is determined at the counter, wherein the number of oscillations during the duration is associated with feedback; The digital signal is generated at least in part based on determining the number of oscillations; The feedback is generated by the digital feedback circuit based at least in part on the receipt of the first signal, and the feedback includes information averaged over the duration. as well as At least in part, the feedback is generated by transmitting analog signals from the digital feedback circuit to the regulator.

11. The method of claim 10, further comprising: At least in part, the digital signal is converted into an analog signal at a digital-to-analog converter (DAC) based on the generation of the digital signal.

12. The method of claim 11, further comprising: The counter is reset to its default value, at least in part, by converting the digital signal into the analog signal.

13. The method of claim 11, further comprising: A second signal indicating a third voltage of the memory array after the duration is received at the digital feedback circuit; as well as A third analog signal is generated at the oscillator, at least in part based on the receipt of the second signal; and the third analog signal is transmitted to the counter.

14. The method of claim 13, further comprising: Select the duration for the counter; The second number of oscillations of the third analog signal during the duration is determined at the counter; as well as The second digital signal is generated at least in part based on determining the second oscillation quantity.

15. The method of claim 13, further comprising: Select a second duration from the plurality of durations for the counter; as well as The second number of oscillations of the third analog signal during the duration is determined at the counter; And at least in part based on determining the second oscillation quantity, a second digital signal is generated.

16. An apparatus comprising: Memory array; as well as A controller, coupled to and configured to cause the device to: The first voltage from the voltage source is transmitted to the regulator; The second voltage from the regulator is transmitted to the memory array, at least in part, based on the transmission of the first voltage; A first signal indicating the voltage of the memory array is transmitted to the oscillator of the digital feedback circuit; The first signal indicating the voltage of the memory array is received at the digital feedback circuit, at least in part, based on transmitting the second voltage to the memory array; At least in part, it is based on transmitting the first signal to the oscillator so that the oscillator generates a second analog signal operating at a first frequency in response to the magnitude of the first signal; The second analog signal is transmitted to the counter of the digital feedback circuit at least in part based on the generation of the second analog signal; Select the duration for the counter from a plurality of durations; The number of oscillations of the second analog signal during the duration is determined at the counter, wherein the number of oscillations during the duration is associated with feedback; The digital signal is generated at least in part based on determining the number of oscillations; The digital feedback circuit generates feedback at least in part based on the receipt of the first signal, the feedback including information averaged over the duration; as well as At least in part, the feedback is generated by transmitting analog signals from the digital feedback circuit to the regulator.

17. The device of claim 16, wherein the controller is further configured to: At least in part, the digital signal is converted into an analog signal at a digital-to-analog converter (DAC) based on the generation of the digital signal.

18. The device of claim 17, wherein the controller is further configured to: The counter is reset to its default value, at least in part, by converting the digital signal into the analog signal.

19. The device of claim 17, wherein the controller is further configured to: A second signal indicating a third voltage of the memory array after the duration is received at the digital feedback circuit; and A third analog signal is generated at the oscillator, at least in part based on the receipt of the second signal; and the third analog signal is transmitted to the counter.

20. The device of claim 19, wherein the controller is further configured to: Select the duration for the counter; as well as The second number of oscillations of the third analog signal during the duration is determined at the counter; And at least in part based on determining the second oscillation quantity, a second digital signal is generated.

Images