A method for preparing a semiconductor device by wet cleaning

Abstract

A process for the production of a pattern collapse free wet clean for semiconductor devices is provided. By using a post reactive ion etch (RIE) with a fluorine containing gas such as C2F6, followed by a clean in a single wafer clean (SWC) with dilute hydrofluoric acid (HF) or ammonia and HF solution, a substrate with multiple high aspect ratio shallow trench isolation (STI) features free of pattern collapse can be obtained.

Description

[0001] Cross-referencing

[0002] This application claims priority and benefits from U.S. formal application No. 17 / 243,159, filed on April 28, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a method for preparing a semiconductor device, and particularly to a wet cleaning method for preparing a semiconductor device. Background Technology

[0004] Recent trends in developing semiconductor devices with smaller dimensions and higher integration density have led to reduced spacing between transistors. Shallow trench isolation (STI) is currently the most widely used method for isolating transistors. STI has replaced the existing local oxidation of silicon (LOCOS) method to meet the requirements of semiconductor generations smaller than 0.18 micrometers. Generally, at some stage of the fabrication process, a "deep trench" can extend 4 to 8 micrometers below the substrate surface. Deep trenches are typically high aspect ratio trenches. "Aspect ratio" refers to the ratio of the trench depth to the width of the opening at the top of the trench. For example, in advanced semiconductor manufacturing, the aspect ratio of high aspect ratio trenches can be between 20:1 and 60:1, or even higher.

[0005] As semiconductor device dimensions shrink, with critical dimensions (CD) less than 50 nanometers, fabricating arrays with high aspect ratio trenches using wet stripping processes can lead to trench boundary distortion, such as bending, or pattern collapse. Pattern collapse was first observed in a backend of line (BEOL) application using ultra-low dielectric (ULK) films. The frequency of pattern collapse defects occurring during wet stripping is increasing with the continuous reduction in size and spacing. Furthermore, due to the high aspect ratio of the patterns, collapse problems frequently occur in the photoresist layer. Pattern collapse can lead to leakage and short circuits in semiconductor devices, resulting in low yields.

[0006] The investigation following etching confirmed that in prior art manufacturing, bending typically occurs during the wet stripping process, not before. This observation confirms that bending is caused by capillary forces on the trench sidewalls generated by the wet stripping process. However, eliminating wet stripping from the process is not a feasible or attractive solution to the bending / collapse problem, as wet stripping also provides a significant function, for example, for removing polymer residues.

[0007] Therefore, in the semiconductor manufacturing industry, there is a need for a method for processing substrates (e.g., wafers) of semiconductor devices to reduce or eliminate the collapse of high aspect ratio features on the substrate, especially features with an aspect ratio of about 10 or greater.

[0008] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0009] One embodiment of this disclosure provides a wet cleaning method for fabricating a semiconductor device, comprising: providing a substrate, including a pad oxide layer disposed on the substrate and an oxide layer disposed on the pad oxide layer; performing a dry etching process to etch the substrate to form a plurality of high aspect ratio shallow trench isolation (STI) features on the substrate, while removing the oxide layer from the substrate; performing a cleaning process to clean the substrate in a single wafer cleaner (SWC) using a diluted hydrofluoric acid (HF) or a solution of ammonia and HF to remove the pad oxide layer and polymer residues left by the dry etching process; and performing a vapor etching process to etch the substrate using an HF vapor to form a substrate having a plurality of pattern-free, high aspect ratio STI features.

[0010] In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate.

[0011] In some embodiments, the pad oxide layer is a SiO2 buffer layer.

[0012] In some embodiments, the pad oxide layer is grown on the substrate by a thermal oxidation process performed at a temperature ranging from approximately 800 degrees Celsius (°C) to 1200 degrees Celsius.

[0013] In some embodiments, the oxide layer is a tetraethyl orthosilicate (TEOS) layer.

[0014] In some embodiments, the dry etching process is performed using a post-reactive ion etching (RIE) process with a fluorine-containing gas.

[0015] In some embodiments, the fluorine-containing gas is selected from the group consisting of CF4, CH2F2, CHF3 and C2F6.

[0016] In some embodiments, the fluorine-containing gas is C2F6.

[0017] In some embodiments, the dry etching process forms a plurality of high aspect ratio STI features on the substrate, wherein at least a portion of the plurality of high aspect ratio STI features has an aspect ratio of 20:1 or greater.

[0018] In some embodiments, the dry etching process forms the plurality of high aspect ratio STI features on the substrate, wherein the aspect ratio of at least a portion of the plurality of high aspect ratio STI features is in the range of 20:1 to 60:1.

[0019] In some embodiments, the dry etching process forms the plurality of high aspect ratio STI features on the substrate, wherein the aspect ratio of at least a portion of the plurality of high aspect ratio STI features is in the range of 30:1 to 60:1.

[0020] In some embodiments, the concentration of the diluted HF in the cleaning process is 0.5% or higher.

[0021] In some embodiments, the concentration of the diluted HF in the cleaning process is in the range of 1% to 5%.

[0022] In some embodiments, the vapor etching process is performed using HF vapor in the presence of an alcohol.

[0023] Due to the design of the wet cleaning preparation method disclosed herein, which includes post-RIE using a fluorine-containing gas such as C2F6, followed by cleaning in SWC with diluted HF or in a solution of ammonia and HF, a substrate with high aspect ratio STI characteristics exhibiting multiple pattern collapses can be obtained. The yield of semiconductor devices is improved due to the significant reduction or elimination of collapse phenomena in semiconductor devices.

[0024] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the same purpose as this disclosure can be achieved quite readily by utilizing the concepts and specific embodiments disclosed below to modify or design other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0025] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0026] Figure 1 This is a flowchart illustrating a wet cleaning method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 2A This is an example of an embodiment of the present disclosure. Figure 1 A top view of the semiconductor structure in step S101 is shown.

[0028] Figure 2B These are examples illustrating some embodiments of this disclosure. Figure 2A A cross-sectional view taken along line AA.

[0029] Figure 3A This is an example of an embodiment of the present disclosure. Figure 1 A top view of the semiconductor structure in step S102 is shown.

[0030] Figure 3B These are examples illustrating some embodiments of this disclosure. Figure 3A A cross-sectional view taken from the middle BB line.

[0031] Figure 4A This is an example of an embodiment of the present disclosure. Figure 1 A top view of the semiconductor structure in step S103 is shown.

[0032] Figure 4B These are examples illustrating some embodiments of this disclosure. Figure 4A A cross-sectional view taken from the middle CC line.

[0033] Figure 4C This is an example of an embodiment of the present disclosure. Figure 1 A top-view micrograph of the semiconductor structure in step S103.

[0034] Figure 4D These are examples illustrating some embodiments of this disclosure. Figure 4CCross-sectional micrograph taken from the middle DD line.

[0035] Figure 5A This is an example of an embodiment of the present disclosure. Figure 1 A top view of the semiconductor structure in step S104 is shown.

[0036] Figure 5B These are examples illustrating some embodiments of this disclosure. Figure 5A A cross-sectional view taken along the EE line.

[0037] Figure 5C This is an example of an embodiment of the present disclosure. Figure 1 A top-view micrograph of the semiconductor structure in step S104.

[0038] Figure 5D These are examples illustrating some embodiments of this disclosure. Figure 5C Cross-sectional micrograph taken along the middle FF line.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10: Wet cleaning preparation method

[0041] 200: Semiconductor Structure

[0042] 201: Base

[0043] 202: Pad oxide layer

[0044] 203: Oxide layer

[0045] S101: Steps

[0046] S102: Steps

[0047] S103: Steps

[0048] S104: Steps Detailed Implementation

[0049] For the sake of brevity, this disclosure may or may not describe in detail conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs). Furthermore, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein. In particular, the various steps involved in manufacturing semiconductor devices and semiconductor-based integrated circuits are well-known; therefore, for the sake of brevity, many conventional steps will be mentioned only briefly in this disclosure or omitted entirely, without providing well-known process details.

[0050] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0051] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” indicate that the embodiments described in this disclosure may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0052] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description below of a first feature being formed "on" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0053] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatial relative terms are intended to encompass not only the orientation shown in the figure but also different orientations of the element during use or operation. The element may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be translated accordingly.

[0054] Figure 1 This is a flowchart illustrating a wet cleaning preparation method 10 according to an embodiment of this disclosure. Figure 2A and Figure 2B , Figure 3A and Figure 3B , Figures 4A to 4D and Figures 5A to 5D This is a top view or cross-sectional view of a semiconductor structure 200 after performing the steps of the preparation method, illustrating some embodiments of this disclosure.

[0055] Figure 2A This is a schematic top view illustrating an embodiment of the present disclosure. Figure 1 The semiconductor structure shown in step S101. Figure 2B These are examples illustrating some embodiments of this disclosure. Figure 2A A cross-sectional view taken along line AA. (Refer to...) Figure 1 , Figure 2A and Figure 2B In step S101, a pad oxide layer 202 is grown on the surface of the substrate 201, and an oxide layer 203 is grown on top of the pad oxide layer 202.

[0056] In this disclosure, semiconductor elements generally refer to elements that can function by utilizing semiconductor properties, such as electro-optic elements, light-emitting display elements, semiconductor circuits, and electronic components, all of which are included within the scope of semiconductor elements. Furthermore, pattern collapse can refer to unintentional contact between adjacent features after wet processing and drying. In particular, contact can occur during the drying process and remain after drying. Below the contact location, the underlying features of the pattern are not destroyed; instead, these features are deformed, that is, they have bent towards each other to form a contact.

[0057] In this disclosure, the term "substrate" refers to the base material or structure on which materials are formed. It should be understood that a substrate can include a single material, multiple layers of different materials, single or multiple layers with different material regions or structures, or other similar combinations of materials. The material of the substrate can include semiconductors, insulators, conductors, or combinations thereof. For example, it can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate on which single or multiple layers, structures, or regions are formed. Substrate 201 can be an existing silicon substrate or other bulk substrate comprising layers of semiconducting material. In some embodiments, substrate 201 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon-on-sapphire (SOS) substrate, a silicon-on-quartz substrate, a silicon-on-insulator (SOI) substrate, a III-V compound semiconductor, combinations thereof, or the like. Preferably, substrate 201 is an SOI substrate. Generally, composite layer structures, such as SOI, are initiated by direct contact between two wafers, thus achieving bonding through van der Waals forces, followed by thermal treatment to strengthen the bond. The choice of insulator largely depends on the intended application; sapphire is used for high-performance radio frequency (RF) and radiation-sensitive applications, while silicon dioxide is used to mitigate short-channel effects in other microelectronic components. In some embodiments, the substrate is a composite layer structure, generally comprising a processing wafer or layer, a device insulating layer, and a layer of insulating film (i.e., dielectric) (typically an oxide layer) between the processing wafer and the device insulating layer. Generally, the thickness of a device layer ranges from 0.01 micrometers (mm) to 20 micrometers, such as 0.05 to 20 micrometers. The thickness of a thick-film device layer can range from about 1.5 micrometers to about 20 micrometers. The thickness of a thin-film device layer can range from about 0.01 micrometers to about 0.20 micrometers.

[0058] The material of the pad oxide layer 202 may include silicon oxide (SiO), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), or combinations thereof. In a preferred embodiment, the pad oxide layer 202 is a SiO2 buffer layer. For example, the pad oxide layer 202 (e.g., a SiO2 buffer layer) may be grown on the substrate 201 by a thermal oxidation process. Typically, this thermal oxidation process is performed at a temperature of approximately 800 degrees Celsius to 1200 degrees Celsius. In this thermal oxidation process, for example, a silicon wafer substrate is consumed and replaced by silicon oxide. For example, the pad oxide layer 202 may include layers of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed as a single-layer structure or a multilayer structure. In some embodiments, the thickness of the pad oxide layer 202 is approximately 150 angstroms. Up to approximately 2000 angstroms.

[0059] For example, the oxide layer 203 can be fabricated using a thin-film related process. In one embodiment, a process gas for fabricating the oxide layer 203 may include tetrachlorosilicic acid (TEOS) and nitrous oxide (N2O). In another embodiment, the process gas for fabricating the oxide layer 203 may include TEOS and oxygen (O2). In either case, the process gas may include one or more carrier gases (e.g., inert gases such as helium (He) or argon (Ar)) to facilitate the delivery and distribution of the process gas in a process chamber. In one example, the process gas includes TEOS, N2O, and Ar. In another example, the process gas includes TEOS, He, and O2. In some embodiments, the oxide layer 203 is fabricated using a plasma-enhanced oxide (PEOX), an undoped silicate glass (USG), or the like. In some embodiments, the oxide layer 203 is a TEOS layer. In some embodiments, the thickness of the oxide layer 203 is approximately 150 angstroms. Up to approximately 2000 angstroms.

[0060] Figure 3A This is a schematic top view illustrating an embodiment of the present disclosure. Figure 1 The semiconductor structure shown in step S102. Figure 3B These are examples illustrating some embodiments of this disclosure. Figure 3A A cross-sectional view taken along the middle BB line. (Refer to...) Figure 1 and Figure 3A and Figure 3BIn step S102, a dry etching process is performed to etch the pad oxide layer 202 and the substrate 201. The upper portions of the pad oxide layer 202 and the substrate 201 can be partially removed by this dry etching process, thus forming multiple high aspect ratio shallow trench isolation (STI) features on the substrate 201. The dimensions of the multiple high aspect ratio STI features can be in the range of 32 nanometers or smaller. Although the illustrated STIs are depicted as equal, the spacing between the multiple high aspect ratio STI features can vary between different adjacent features. It should be understood that the spacing between the multiple high aspect ratio STI features can be a factor in pattern collapse.

[0061] In some embodiments, the dry etching process may use an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasma, or combinations thereof. Preferably, the dry etching process uses a fluorine-containing gas. More preferably, the dry etching process uses a fluorocarbon gas with the chemical formula CnFxHy, where n is an integer of 1 or 2, x is an integer from 1 to 6, and y is an integer from 0 to 3. In some embodiments, (x+y) equals 6. In some embodiments, the fluorocarbon gas may be CF4, C2F6, CHF3, or combinations thereof. Most preferably, the dry etching process uses a C2F6 gas.

[0062] In a preferred embodiment, the dry etching process is performed via reactive ion etching (RIE). RIE offers numerous important micromachining capabilities, including patterning of trench / via features on low-k or ultra-low-k interlayer dielectric layers, ashing / removal of photoresist, etching / removal of bottom anti-reflective coating (BARC), minimization / removal of plasma-etched polymers, etching / removal of organic contaminants, and recovery from damage to low-k materials. After performing step S102, oxide layer 203 is removed from substrate 201, forming multiple high aspect ratio STI features on substrate 201. The multiple high aspect ratio STI features are separated from each other in a cross-sectional view.

[0063] In some embodiments, the dry etching process forms a plurality of high aspect ratio STI features on substrate 201, wherein at least a portion of the plurality of high aspect ratio STI features has an aspect ratio of 20:1 or greater, preferably in the range of 20:1 to 60:1, and more preferably in the range of 30:1 to 60:1. A feature size of the STI feature, such as a feature width, may be less than 40 nanometers. In other embodiments, the feature size may be less than 30 nanometers. In another embodiment, the feature size may be less than 25 nanometers.

[0064] As the design rules for semiconductor devices shrink to the submicron scale, the tolerable size of contaminants generated during manufacturing processes also decreases. Submicron-sized contaminants (or particles) are difficult to remove due to strong adhesion forces between the particles and the substrate, such as van der Waals forces, capillary forces, chemical bonds, and / or electrostatic forces. A pre-cleaning process using a reducing agent can be chosen to remove submicron-sized contaminants from the substrate surface. This reducing agent can be titanium tetrachloride, tantalum tetrachloride, or a combination thereof. This pre-cleaning process can be repeated multiple times if necessary.

[0065] Figure 4A This is a schematic top view illustrating an embodiment of the present disclosure. Figure 1 The semiconductor structure shown in step S103. Figure 4B These are examples illustrating some embodiments of this disclosure. Figure 4A A cross-sectional view taken along the CC line. (Refer to...) Figure 1 , Figure 4A and Figure 4BIn step S103, substrate 201 undergoes a cleaning process in a Single Wafer Cleaner (SWC) using a diluted HF (hydrofluoric acid) or a solution of ammonia and HF. After step S103 is performed, polymer residues left by the dry etching process are removed from substrate 201, and pad oxide layer 202 is also removed from substrate 201. Single wafer cleaners (SWCs) are widely used in microelectronics processes due to their high performance in cleaning large-diameter (especially 300 mm) wafers. Specifically, SWCs enable the limitation of certain defects at wafer edges, which is typically associated with batch cleaners, which operate by a series of immersions in a chemical bath. In some embodiments, the cleaning process uses diluted HF at a concentration of 0.5% or higher. Preferably, the cleaning process uses diluted HF at a concentration between 1% and 5%. More preferably, the cleaning process uses diluted HF at a concentration in the range of 2% to 5%. Any conventional SWC can be used in this cleaning process. Various documents related to the manufacture of SWC have been reported, such as US 5,148,823, US 6,730,176 B2, etc.

[0066] Figure 5A This is a schematic top view illustrating an embodiment of the present disclosure. Figure 1 The semiconductor structure shown in step S104. Figure 5B These are examples illustrating some embodiments of this disclosure. Figure 5A A cross-sectional view taken along the EE line. (Refer to...) Figure 1 , Figure 5A and Figure 5B In step S104, the substrate 201 is placed in a vapor-etching process using HF vapor. In some embodiments, the vapor-etching process is performed with HF vapor in the presence of alcohols. The alcohols ionize the HF vapor and act as catalysts. This vapor-etching process using HF vapor can be performed using any commercially available HF vapor-etching system, such as those manufactured by SPTS Technologies. Monarch 25 Monarch 3 or Uetch.

[0067] Alternatively, after the vapor etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, can be deposited in multiple high aspect ratio STI features by a metallization process, such as a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, or a similar process.

[0068] Due to the design of the wet cleaning preparation method of this disclosure, namely, using a fluorine-containing gas such as C2F6 for a post-RIE process, followed by cleaning in a SWC with diluted HF or a solution of ammonia and HF, this disclosure enables the realization of substrates with multiple pattern collapse-free, high aspect ratio STI features. The yield of semiconductor devices is improved due to the significant reduction or elimination of pattern collapse in the semiconductor devices.

[0069] One embodiment of this disclosure provides a wet cleaning method for fabricating a semiconductor device, comprising: providing a substrate, including a pad oxide layer disposed on the substrate and an oxide layer disposed on the pad oxide layer; performing a dry etching process to etch the substrate to form a plurality of high aspect ratio shallow trench isolation (STI) features on the substrate, while removing the oxide layer from the substrate; performing a cleaning process to clean the substrate in a single wafer cleaner (SWC) using a diluted hydrofluoric acid (HF) or a solution of ammonia and HF to remove the pad oxide layer and polymer residues left by the dry etching process; and performing a vapor etching process to etch the substrate using an HF vapor to form a substrate having a plurality of pattern-free, high aspect ratio STI features.

[0070] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0071] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for wet cleaning and preparing a semiconductor device, comprising: A substrate is provided, including a pad oxide layer disposed on the substrate, and an oxide layer disposed on the pad oxide layer; A dry etching process is performed to etch the substrate to form multiple shallow trench isolation features with a high aspect ratio on the substrate, while removing the oxide layer from the substrate. A cleaning process is performed using a diluted hydrofluoric acid or a solution of ammonia and hydrofluoric acid to clean the substrate in a single-wafer cleaning machine to remove the pad oxide layer and polymer residues left by the dry etching process. as well as A vapor etching process is performed, using hydrofluoric acid vapor to etch the substrate to form a substrate with a high aspect ratio shallow trench isolation feature with multiple patternless collapses.

2. The wet cleaning preparation method according to claim 1, wherein the substrate is a silicon-on-insulator substrate.

3. The wet cleaning preparation method according to claim 1, wherein the oxide layer of the pad is a SiO2 buffer layer.

4. The wet cleaning preparation method according to claim 1, wherein the pad oxide layer is grown on the substrate by a thermal oxidation process, the thermal oxidation process being carried out at a temperature in the range of approximately 800 degrees Celsius (°C) to 1200 degrees Celsius.

5. The wet cleaning preparation method according to claim 1, wherein the oxide layer is a tetrachlorosilicic acid layer.

6. The wet cleaning preparation method according to claim 1, wherein the dry etching process is performed by post-reactive ion etching using a fluorine-containing gas.

7. The wet cleaning preparation method according to claim 6, wherein the fluorine-containing gas is selected from the group consisting of CF4, CH2F2, CHF3 and C2F6.

8. The wet cleaning preparation method according to claim 7, wherein the fluorine-containing gas is C2F6.

9. The wet cleaning preparation method according to claim 1, wherein the dry etching process forms a plurality of high aspect ratio shallow trench isolation features on the substrate, wherein at least a portion of the plurality of high aspect ratio shallow trench isolation features has an aspect ratio of 20:1 or greater.

10. The wet cleaning preparation method of claim 9, wherein the dry etching process forms the plurality of high aspect ratio shallow trench isolation features on the substrate, wherein the aspect ratio of at least a portion of the plurality of high aspect ratio shallow trench isolation features is in the range of 20:1 to 60:

1.

11. The wet cleaning preparation method of claim 9, wherein the dry etching process forms the plurality of high aspect ratio shallow trench isolation features on the substrate, wherein the aspect ratio of at least a portion of the plurality of high aspect ratio shallow trench isolation features is in the range of 30:1 to 60:

1.

12. The wet cleaning preparation method according to claim 1, wherein the concentration of the diluted hydrofluoric acid in the cleaning process is 0.5% or higher.

13. The wet cleaning preparation method according to claim 12, wherein the concentration of the diluted hydrofluoric acid in the cleaning process is in the range of 1% to 5%.

14. The wet cleaning preparation method according to claim 1, wherein the vapor etching process is carried out using hydrofluoric acid vapor in the presence of an alcohol.

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