Key control device and key control method

Abstract

Disclosed are a key control device and a key control method. The key control device comprises: an encoder circuit, wherein the encoder circuit comprises a first output terminal and a second output terminal, wherein the encoder circuit is configured to, under the triggering of a rotation operation, enable the first output terminal and the second output terminal to respectively output a first voltage signal and a second voltage signal; a first interface expansion circuit, configured to receive the first voltage signal and the second voltage signal, and generate an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit; and a main control circuit, configured to determine the rotation direction of the rotation operation according to the interrupt signal and the voltage state transition data.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a key control device and a key control method. Background Art

[0002] In the display system, the keypad is connected to the system board. When the keys on the keypad are pressed, the system board generates corresponding control instructions to control the display to perform corresponding actions. Summary of the invention

[0003] The present disclosure provides a key control device and a key control method.

[0004] The present disclosure provides a key control device, comprising:

[0005] An encoder circuit, the encoder circuit comprising a first output terminal and a second output terminal, the encoder circuit being configured to, under the triggering of a rotation operation, cause the first output terminal and the second output terminal to output a first voltage signal and a second voltage signal respectively;

[0006] A first interface expansion circuit is configured to receive the first voltage signal and the second voltage signal, and generate an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit;

[0007] The main control circuit is configured to determine the rotation direction of the rotation operation according to the interrupt signal and the voltage state transition data.

[0008] In some embodiments, the first interface expansion circuit includes a first state register, which is configured to generate and store voltage state transition data of the first output terminal and the second output terminal of the encoder circuit according to the first voltage signal and / or the second voltage signal.

[0009] In some embodiments, the main control circuit responds to the interrupt signal output by the first interface expansion circuit, reads the voltage state jump data stored in the first state register, and determines the rotation direction of the rotation operation at least based on the voltage state jump data stored in the first state register.

[0010] In some embodiments, the first status register includes: a first sub-register and a second sub-register;

[0011] The first sub-register is configured to generate and store voltage state transition data of the first output terminal according to a first voltage signal outputted from the first output terminal of the encoder circuit; and when a voltage state transition occurs at the first output terminal, the first interface expansion circuit outputs an interrupt signal of a first type;

[0012] The second sub-register is configured to generate and store voltage state transition data of the second output end according to a second voltage signal outputted from the second output end of the encoder circuit; and when a voltage state transition occurs at the second output end, the first interface expansion circuit outputs a second type of interrupt signal.

[0013] In some embodiments, the first interface expansion circuit includes: a first interrupt terminal and a second interrupt terminal, the first type of interrupt signal is: an interrupt signal output by the first interrupt terminal; the second type of interrupt signal is: an interrupt signal output by the second interrupt terminal.

[0014] In some embodiments, the first interface expansion circuit further comprises: a level register configured to obtain the voltage state of the first output terminal and the second output terminal of each of the encoder circuits in real time;

[0015] Determining the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register specifically includes:

[0016] According to the voltage state obtained by the level register, determine whether the voltage states of the first output terminal and the second output terminal of the encoder circuit triggered by the rotation operation are the same; if different, determine whether the type of the interrupt signal is the first type or the second type; if the type of the interrupt signal is the first type, determine that the rotation direction is clockwise, and if the type of the interrupt signal is the second type, determine that the rotation direction is counterclockwise.

[0017] In some embodiments, the main control circuit is specifically configured as:

[0018] When the main control circuit receives the interrupt signal output by the first interface expansion circuit for the i-th time, it waits for the interrupt signal output by the first interface expansion circuit for the i+1th time; and determines the rotation direction according to the voltage state jump data of the first output terminal and the second output terminal when the first interface expansion circuit outputs the interrupt signal for the i-th time and the i+1-th time;

[0019] Here, i is an odd number.

[0020] In some embodiments, there are multiple encoder circuits; the main control circuit is further configured to determine the number of the encoder circuit triggered by the rotation operation according to the interrupt signal and the voltage state transition data.

[0021] In some embodiments, the key control device further includes:

[0022] A plurality of key circuits, each of which is configured to output a signal of a third voltage when triggered; otherwise, output a signal of a fourth voltage;

[0023] The second interface expansion circuit includes a second status register, wherein the second status register is configured to generate and store trigger status data of each of the key circuits according to an output signal of the key circuit; when any of the key circuits is triggered, an interrupt terminal of the second interface expansion circuit outputs an interrupt signal;

[0024] Wherein, the main control circuit is further configured to, when the second interface expansion circuit outputs an interrupt signal, determine the number of the triggered key circuit according to the trigger state data of each key circuit stored in the second state register.

[0025] The embodiment of the present disclosure also provides a key control method applied to a key control device, wherein the key control device comprises: a first interface expansion circuit, a main control circuit and an encoder circuit, the encoder circuit comprises a first output terminal and a second output terminal, and the encoder circuit is configured to, under the triggering of a rotation operation, cause the first output terminal and the second output terminal to output a first voltage signal and a second voltage signal respectively;

[0026] The method comprises:

[0027] The first interface expansion circuit receives the first voltage signal and the second voltage signal, and generates an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit;

[0028] The main control circuit determines the rotation direction of the rotation operation according to the interrupt signal and the voltage state transition data.

[0029] In some embodiments, the first interface expansion circuit includes a first state register; the first interface expansion circuit generates voltage state transition data, including:

[0030] The first state register generates and stores voltage state transition data of the first output terminal and the second output terminal of the encoder circuit according to the first voltage signal and / or the second voltage signal.

[0031] In some embodiments, the main control circuit determines the rotation direction of the rotation operation in response to the interrupt signal and the voltage state transition data, specifically including:

[0032] The main control circuit responds to the interrupt signal output by the first interface expansion circuit, reads the voltage state transition data stored in the first state register, and determines the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register.

[0033] In some embodiments, the first state register generates and stores voltage state transition data of the first output terminal and the second output terminal of the encoder circuit according to the first voltage signal and / or the second voltage signal, specifically including:

[0034] The first sub-register generates and stores voltage state transition data of each first output terminal according to a first voltage signal output by the first output terminal of each encoder circuit;

[0035] The second sub-register generates and stores voltage state transition data of each second output terminal according to the second voltage signal output by the second output terminal of each encoder circuit;

[0036] When a voltage state jump occurs at any one of the first output terminals, the first interface expansion circuit outputs a first type of interrupt signal; when a voltage state jump occurs at any one of the second output terminals, the first interface expansion circuit outputs a second type of interrupt signal.

[0037] In some embodiments, the first interface expansion circuit includes: a first interrupt terminal and a second interrupt terminal, the first type of interrupt signal is: an interrupt signal output by the first interrupt terminal; the second type of interrupt signal is: an interrupt signal output by the second interrupt terminal.

[0038] In some embodiments, the first interface expansion circuit further includes: a level register, and the method further includes: the level register acquiring the voltage state of the first output terminal and the second output terminal of the encoder circuit in real time;

[0039] Determining the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register specifically includes:

[0040] According to the voltage state obtained by the level register, determine whether the voltage states of the first output terminal and the second output terminal of the encoder circuit triggered by the rotation operation are the same; if different, determine whether the type of the interrupt signal is the first type or the second type; if the type of the interrupt signal is the first type, determine that the rotation direction is clockwise, and if the type of the interrupt signal is the second type, determine that the rotation direction is counterclockwise.

[0041] In some embodiments, the main control circuit reads the voltage state transition data stored in the first state register in response to the interrupt signal output by the first interface expansion circuit, and determines the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register, specifically including:

[0042] When the main control circuit receives the interrupt signal output by the first interface expansion circuit for the i-th time, it waits for the first interface expansion circuit to output the interrupt signal for the i+1th time; and determines the rotation direction according to the voltage state jump data of each of the first output terminal and the second output terminal when the first interface expansion circuit outputs the interrupt signal for the i-th time and the i+1-th time;

[0043] Here, i is an odd number.

[0044] In some embodiments, the number of the encoder circuits is multiple;

[0045] The method further includes: the main control circuit determining the serial number of the encoder circuit triggered by the rotation operation according to the interrupt signal and the voltage state transition data.

[0046] In some embodiments, the key control device further includes: a second interface expansion circuit and a plurality of key circuits, the second interface expansion circuit includes a second state register; the key circuit is configured to output a signal of a third voltage when triggered; otherwise, output a signal of a fourth voltage;

[0047] The method further comprises:

[0048] The second status register generates and stores the trigger status data of each of the key circuits according to the output signal of the key circuit, and when any of the key circuits is triggered, the interrupt terminal of the second interface expansion circuit outputs an interrupt signal;

[0049] When the main control circuit receives the interrupt signal output by the second interface expansion circuit, the serial number of the triggered key circuit is determined according to the trigger status data of each key circuit stored in the second status register. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0051] Figure 1 The figure is a schematic diagram of the connection between a system board and a key control device in a display device provided in an embodiment.

[0052] Figure 2This is a circuit diagram of a key control device provided in some embodiments of the present disclosure.

[0053] Figure 3 A schematic diagram of an encoder circuit provided in some embodiments of the present disclosure.

[0054] Figure 4 This is a schematic diagram of the connection between the first interface expansion circuit and the encoder circuit provided in some embodiments of the present disclosure.

[0055] Figure 5 This is a schematic diagram of the connection between the first interface expansion circuit and the encoder circuit provided in some other embodiments of the present disclosure.

[0056] Figure 6 Schematic diagram of a circuit of a key control device provided in some other embodiments of the present disclosure.

[0057] Figure 7 It is a schematic diagram of a key circuit provided in an embodiment of the present disclosure.

[0058] Figure 8 This is a schematic diagram of the connection between the second interface expansion circuit and the key circuit provided in some embodiments of the present disclosure.

[0059] Fig. 9 This is a schematic diagram of an electronic device provided in some embodiments of the present disclosure.

[0060] Fig.10 This is a flowchart of a key control method provided in some embodiments of the present disclosure.

[0061] Fig.11 This is a flowchart of a key control method provided in some other embodiments of the present disclosure.

[0062] Fig.12 This is a flowchart of a key control method provided in some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0063] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0064] Figure 1 FIG. 1 is a schematic diagram showing the connection between a system board and a key control device in a display device provided in an embodiment. Figure 1As shown, in the display device, the system board 11 is connected to the key control device 12, and the I / O interface (input / output interface) 12a of the key control device 12 is connected to the I / O interface 11a of the system board 11 through a connector. When a key on the key control device 12 is triggered to generate an action, the microcontroller (Micro-Controller Unit, MCU) of the key control device 12 determines the type of input instruction (for example, which key is triggered); the system board 11 performs a corresponding action, for example, sends a corresponding control instruction to the display according to the judgment result of the microcontroller.

[0065] In some display devices (such as monitors), the key control device 12 not only needs to be provided with touch or push buttons as command input devices, but also needs to be provided with multiple rotary encoders as command input devices. In this application scenario, when a rotary encoder rotates, the microcontroller not only needs to determine which rotary encoder rotates, but also needs to determine the direction of the rotation. However, it is difficult for the microcontroller to provide sufficient I / O interfaces, which makes it difficult for the microcontroller to determine the type of input command.

[0066] Figure 2 is a circuit diagram of a key control device provided in some embodiments of the present disclosure, such as Figure 2 As shown, the key control device comprises: a first interface expansion circuit 31, a main control circuit 40, and an encoder circuit 21. The number of the encoder circuit 21 can be one or more.

[0067] Figure 3 Schematic diagram of an encoder circuit provided in some embodiments of the present disclosure, such as Figure 3As shown, the encoder circuit 21 has a first output terminal OUT1 and a second output terminal OUT2. The encoder circuit 21 is configured to: under the triggering of the rotation operation, the first output terminal OUT1 outputs a first voltage signal, and the second output terminal OUT2 outputs a second voltage signal. It should be noted that the first voltage signal and the second voltage signal are signals output by the first output terminal OUT1 and the second output terminal OUT2, respectively; the first voltage signal and the second voltage signal both have two voltage states, which refers to the high and low states of the voltage of the first voltage signal or the second voltage signal. The voltage state of the first output terminal OUT1 hereinafter is the voltage state of the first voltage signal, and the voltage state of the second output terminal OUT2 is the voltage state of the second voltage signal. For example, under the triggering of the rotation operation, the first voltage signal and the second voltage signal both jump between the first voltage state and the second voltage state, that is, the first output terminal OUT1 and the second output terminal OUT2 both jump between the first voltage state and the second voltage state; and when the rotation direction is clockwise, the first voltage signal jumps before the second voltage signal; when the rotation direction is counterclockwise, the second voltage signal jumps before the first voltage signal. The first voltage state is a low level state, and the second voltage state is a high level state; or, the first voltage state is a high level state, and the second voltage state is a low level state. Taking the state where the first voltage state is a low level and the second voltage state is a high level as an example, when the first voltage signal is in the first voltage state, the voltage value of the first voltage signal is recorded as v11; when the first voltage signal is in the second voltage state, the voltage value of the first voltage signal is recorded as v12; when the second voltage signal is in the first voltage state, the voltage value of the second voltage signal is recorded as v21; when the second voltage signal is in the second voltage state, the voltage value of the second voltage signal is recorded as v22, then, v11<v12, v21<v22, and v11 and v21 may be equal or unequal; v12 and v22 may be equal or unequal.

[0068] The encoder circuit 21 includes: a first pull-up resistor R101, a second pull-up resistor R102, a first switch K1, a second switch K2, a first filter resistor R103, a first filter capacitor C101, a second filter resistor R104 and a second filter capacitor C102. Among them, the first end of the first pull-up resistor R101 is connected to the first power supply terminal V1, and the first power supply terminal V1 can be a high-level voltage terminal; the second end of the first pull-up resistor R101 is connected to the first switch K1. The two ends of the first switch K1 are respectively connected to the second end of the first pull-up resistor R101 and the second power supply terminal V2, and the second power supply terminal V2 can be a low-level signal terminal, for example, a ground terminal. The first filter resistor R103 and the first filter capacitor C101 form a first filter circuit, and the two ends of the first filter resistor R103 are respectively connected to the second end of the first pull-up resistor R101 and the first output terminal OUT1 of the encoder circuit 21. The two ends of the first filter capacitor C101 are respectively connected to the first output terminal OUT1 of the encoder circuit 21 and the second power supply terminal V2. The first end of the second pull-up resistor R102 is connected to the first power supply terminal V1, and the second end of the second pull-up resistor R102 is connected to the second switch K2. The two ends of the second switch K2 are respectively connected to the second end of the second pull-up resistor R102 and the second power supply terminal V2. The second filter resistor R104 and the second filter resistor R104 form a second filter circuit, and the two ends of the second filter resistor R104 are respectively connected to the second end of the second pull-up resistor R102 and the second output terminal OUT2 of the encoder circuit 21; the second filter capacitor C102, whose two ends are respectively connected to the second output terminal OUT2 of the encoder circuit 21 and the second power supply terminal V2.

[0069] Among them, the on-off states of the first switch K1 and the second switch K2 are switched under the trigger of the rotation operation, and when the rotation direction is clockwise, the on-off state of the first switch K1 is switched before the second switch K2; when the rotation direction is counterclockwise, the on-off state of the second switch K2 is switched before the first switch K1.

[0070] Optionally, the first pull-up resistor R101 and the second pull-up resistor R102 have the same resistance value, the first filter resistor R103 and the second filter resistor R104 have the same resistance value, the first filter capacitor C101 and the second filter capacitor C102 have the same capacitance value, and when the first switch K1 and the second switch K2 are both turned on, the output signals of the first output terminal OUT1 and the second output terminal OUT2 are both in a first voltage state, and the voltages of the output signals of the first output terminal OUT1 and the second output terminal OUT2 are the same; when the first switch K1 and the second switch K2 are both turned off, the output signals of the first output terminal OUT1 and the second output terminal OUT2 are both in a second voltage state, and the voltages of the output signals of the first output terminal OUT1 and the second output terminal OUT2 are the same.

[0071] For example, in the initial state, both the first switch K1 and the second switch K2 are in the off state. When the rotation operation occurs for the first time and the rotation direction is clockwise, the first switch K1 is switched to the on state first, and the second switch K2 is switched to the on state later; when the rotation operation occurs for the first time and the rotation direction is counterclockwise, the second switch K2 is switched to the on state first, and the first switch K1 is switched to the on state later; when the rotation operation occurs for the second time and the rotation direction is clockwise, the first switch K1 is switched to the off state first, and the second switch K2 is switched to the off state later; when the rotation operation occurs for the second time and the rotation direction is counterclockwise, the second switch K2 is switched to the off state first, and the first switch K1 is switched to the off state later.

[0072] It should be noted that the “off state” of the switch means that the two ends of the switch are disconnected; and the “on state” of the switch means that the two ends of the switch are connected.

[0073] It should also be noted that the first switch K1 and the second switch K2 can be arranged inside the rotary encoder, and when the rotary encoder rotates a preset angle, the first switch K1 and the second switch K2 both switch on and off once, and when the rotary encoder rotates at a larger angle (for example, a full circle), the first switch K1 and the second switch K2 both switch on and off for multiple times in succession. The "rotation operation" in the embodiment of the present disclosure refers to one rotation operation, that is, the first switch K1 and the second switch K2 both switch on and off once.

[0074] In some embodiments, the first output terminal OUT1 and the second output terminal OUT2 of all encoder circuits 21 are connected to the input interface of the first interface expansion circuit 31, wherein each first output terminal OUT1 is connected to an input interface, each second output terminal OUT2 is connected to an input interface, different first output terminals OUT1 are connected to different input interfaces, and different second output terminals OUT2 are connected to different input interfaces. The input interface is, for example, a GPIO (General-purpose input / output) interface.

[0075] The first interface expansion circuit 31 is configured to receive the first voltage signal and the second voltage signal output by the encoder circuit 21 , and generate an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit 21 .

[0076] Figure 4 is a schematic diagram of connection between a first interface expansion circuit and an encoder circuit provided in some embodiments of the present disclosure, Figure 4 The number of encoder circuits 21 is only for illustrative purposes. Figure 4As shown, the first interface expansion circuit 31 includes a first state register 311, which is configured to generate and store voltage state jump data of the first output terminal OUT1 and the second output terminal OUT2 of the encoder circuit 21 according to the first voltage signal and / or the second voltage signal output by the encoder circuit 21; and when a voltage state jump occurs at any first output terminal OUT1 or any second output terminal OUT2, the first state register 311 provides an interrupt signal to the interrupt terminal INT of the first interface expansion circuit 31, so that the interrupt terminal INT of the first interface expansion circuit 31 outputs the interrupt signal. The first state register 311 has an interrupt issuing terminal, and the interrupt issuing terminal of the first state register 311 is connected to the interrupt terminal INT.

[0077] The so-called "voltage state jump data" is: data used to indicate whether the voltage state jumps, for example, a digital signal "1" indicates that the voltage state has changed, and a digital signal "0" indicates that the voltage state has not changed. In one example, the input interfaces of the first interface expansion circuit 31 are respectively recorded as: interface I_0, interface I_1, interface I_2, interface I_3, interface I_4, interface I_5, interface I_6, and interface I_7, wherein the first output end OUT1 of the first encoder circuit 21 is connected to interface I_0, and the second output end OUT2 is connected to interface I_1; the first output end OUT1 of the second encoder circuit 21 is connected to interface I_2, and the second output end OUT2 is connected to interface I_3; the first output end OUT1 of the third encoder circuit 21 is connected to interface I_4, and the second output end OUT2 is connected to interface I_5; the first output end OUT1 of the fourth encoder circuit 21 is connected to interface I_6, and the second output end OUT2 is connected to interface I_7. When no voltage state jump occurs at each of the first output terminal OUT1 and the second output terminal OUT2, the data stored in the first state register 311 is "00000000"; when the voltage state jump occurs at the first output terminal OUT1 of the first encoder, the data stored in the first state register 311 is updated to "00000001"; when the voltage state jump occurs at the second output terminal OUT2 of the first encoder, the data stored in the first state register 311 is updated to "00000010".

[0078] The main control circuit 40 is configured to determine the direction of the rotation operation according to the interrupt signal and the voltage state transition data.

[0079] In some embodiments, the main control circuit responds to the interrupt signal output by the first interface expansion circuit 31 , reads the voltage state transition data stored in the first state register 311 , and determines the rotation direction of the rotation operation at least based on the voltage state transition data stored in the first state register 311 .

[0080] For example, the main control circuit 40 includes a microcontroller, specifically MCP23017. The main control circuit 40 also includes a first interrupt receiving interface 40a and a first signal reading interface 40b. The first interrupt receiving interface 40a is connected to the interrupt terminal INT of the first interface expansion circuit 31, and is used to receive the interrupt signal output by the first interface expansion circuit 31; the first signal reading interface 40b is connected to the data port 31a of the first interface expansion circuit 31, so as to read the voltage state jump data of the first output terminal OUT1 and the second output terminal OUT2 stored in the first state register 311 through the data port 31a. For example, the first signal reading interface adopts I 2 C interface, the first interrupt receiving interface 40a can adopt a GPIO interface.

[0081] It should be noted that, after the main control circuit 40 reads the voltage state jump data stored in the first state register 311, the first state register 311 resets the voltage state jump data stored therein, so that each voltage state jump data is reset to an initial value, and the initial value indicates that the voltage state has not jumped. For example, when the voltage state jump does not occur at each of the first output terminal OUT1 and the second output terminal OUT2, the data stored in the first state register 311 is "00000000"; when the voltage state jump occurs at the first output terminal OUT1 of the first encoder circuit 21, the data stored in the first state register 311 is updated to "00000001"; when the voltage state jump occurs at the second output terminal OUT2 of the first encoder circuit 21, the data stored in the first state register 311 is updated to "00000010". At this time, after the main control circuit 40 reads the data of the first state register 311 once, the data stored in the first state register 311 is reset to "00000000".

[0082] The main control circuit 40 may also include: a transmission interface 40c, the main control circuit 40 outputs an action control instruction to the system board of the display device according to the result determined by it (for example, the number and rotation direction of the rotary encoder triggered by the rotation operation), and the system board performs a corresponding action according to the action control instruction output by the main control circuit 40. For example, the display is controlled to display a corresponding picture. Among them, the transmission interface 40c can be a UART interface, and the UART interface is connected to the RS232 interface 60 of the key board through the UART to RS232 chip 50, and the RS232 interface 60 of the key board is connected to the RS232 interface of the system board.

[0083] In the disclosed embodiment, when the encoder circuit 21 is triggered by the rotation operation, the voltage state jump occurs at both the first output terminal OUT1 and the second output terminal OUT2 of the encoder circuit 21, and when the rotation direction is different, the voltage state jump timing of the first output terminal OUT1 and the second output terminal OUT2 is also different, and the first state register 311 can store the voltage state jump state of the first output terminal OUT1 and the second output terminal OUT2, and when the voltage state jump occurs at any first output terminal OUT1 and any second output terminal OUT2, the first interface expansion circuit 31 outputs an interrupt signal. When the main control circuit 40 receives the interrupt signal, it determines the rotation direction of the rotation operation according to the interrupt signal and the voltage state jump data, and then determines the input instruction received by the key control device.

[0084] In the embodiment of the present disclosure, when there are multiple encoder circuits 21, the main control circuit 40 is further configured to determine the number of the encoder circuit 21 triggered by the rotation operation according to the interrupt signal and the voltage state transition data. For example, when the first interface expansion circuit 31 outputs an interrupt signal, the number of the encoder circuit 21 triggered by the rotation operation is determined at least according to the voltage state transition data of each first output terminal OUT1 and each second output terminal OUT2 stored in the first state register 311.

[0085] The embodiments below are described with the number of encoder circuits 21 being multiple.

[0086] In some embodiments, the main control circuit 40 determines the number of the rotary encoder triggered by the rotation operation and the rotation direction of the rotation operation by the following method 1.

[0087] Mode 1: When the main control circuit 40 receives the interrupt signal outputted by the first interface expansion circuit 31 for the i-th time, it waits for the interrupt signal outputted by the first interface expansion circuit 31 for the i+1th time; and according to the voltage state jump data of each first output terminal OUT1 and second output terminal OUT2 when the first interface expansion circuit 31 outputs the interrupt signal for the i-th time and the i+1th time, the number of the encoder circuit 21 triggered by the rotation operation is determined; and according to the voltage jump data of the first output terminal OUT1 and second output terminal OUT2 when the first interface expansion circuit 31 outputs the interrupt signal for the i-th time and the i+1th time, the rotation direction is determined. For example, according to the voltage jump data of the first output terminal OUT1 and second output terminal OUT2 when the first interface expansion circuit 31 outputs the interrupt signal for the i-th time and the i+1th time, the timing of the voltage state jump of the first output terminal OUT1 and second output terminal OUT2 is determined, and then the rotation direction is determined according to the timing of the voltage state jump of the first output terminal OUT1 and second output terminal OUT2. Wherein, i is an odd number.

[0088] For example, when the main control circuit 40 receives the interrupt signal outputted by the first interface expansion circuit 31 for the i-th time, it determines that the voltage state jump occurs at the first output terminal OUT1 of the first encoder circuit 21 by reading the voltage state jump data stored in the first state register 311; thereafter, the main control circuit 40 waits for the first interface expansion circuit 31 to output the interrupt signal again, and when the main control circuit 40 receives the interrupt signal outputted by the first interface expansion circuit 31 for the i+1th time, it determines that the voltage state jump occurs at the second output terminal OUT2 of the first encoder circuit 21 by reading the voltage state jump data stored in the first state register 311. In this case, the main control circuit 40 determines that the first encoder circuit 21 is controlled by the rotation operation, and the rotation direction is clockwise.

[0089] For another example, when the main control circuit 40 receives the interrupt signal outputted by the first interface expansion circuit 31 for the i-th time, it determines that the voltage state jump occurs at the second output terminal OUT2 of the first encoder circuit 21 by reading the voltage state jump data stored in the first state register 311; thereafter, the main control circuit 40 waits for the first interface expansion circuit 31 to output the interrupt signal again, and when the main control circuit 40 receives the interrupt signal outputted by the first interface expansion circuit 31 for the i+1th time, it determines that the voltage state jump occurs at the first output terminal OUT1 of the first encoder circuit 21 by reading the voltage state jump data stored in the first state register 311. In this case, the main control circuit 40 determines that the first encoder circuit 21 is controlled by the rotation operation, and the rotation direction is counterclockwise.

[0090] Figure 5 is a schematic diagram of connection between a first interface expansion circuit and an encoder circuit provided in some other embodiments of the present disclosure, Figure 5 The number of encoder circuits 21 is only for illustrative purposes. Figure 5As shown, the first state register includes: a first sub-register 3111 and a second sub-register 3112, wherein the first sub-register 3111 is configured to generate and store the voltage state jump data of the first output terminal OUT1 according to the first voltage signal of the first output terminal OUT1 of the encoder circuit 21; and when the voltage state jumps at the first output terminal OUT1, the first interface expansion circuit 31 outputs a first type of interrupt signal. The second sub-register 3112 is configured to generate and store the voltage state jump state of the second output terminal OUT2 according to the second voltage signal outputted from the second output terminal OUT2 of the encoder circuit 21; and when the second output terminal OUT2 jumps, the first interface expansion circuit 31 outputs a second type of interrupt signal. It should be noted that the first sub-register 3111 can generate and store the voltage state jump data of each first output terminal OUT1 according to the output signal of the first output terminal OUT1 of each encoder circuit 21; and when any first output terminal OUT1 jumps, the first type of interrupt signal is provided to the interrupt terminal of the first interface expansion circuit 31 for the first interface expansion circuit 31 to output. The second sub-register 3112 can generate and store the voltage state jump state of each second output terminal OUT2 according to the output signal of the second output terminal OUT2 of each encoder circuit 21; and when any second output terminal OUT2 jumps, a second type of interrupt signal is provided to the interrupt terminal of the first interface expansion circuit 31 for the first interface expansion circuit 31 to output.

[0091] It should be noted that the first sub-register 3111 and the second sub-register 3112 may be two independent registers or may be integrated into one.

[0092] The first interface expansion circuit 31 further includes: a level register 312. In some embodiments, the level register 312 is configured to obtain the voltage state of the first output terminal OUT1 and the second output terminal OUT2 of each encoder circuit 21. The level register 312 can obtain the voltage state of each first output terminal OUT1 and the second output terminal OUT2 in real time.

[0093] In this case, for a certain rotary encoder, when the rotary encoder completes a clockwise rotation operation, the voltage state jump occurs at the first output terminal OUT1 first, and the voltage state jump occurs at the second output terminal OUT2 later; accordingly, the first interface expansion circuit 31 first outputs the first type of interrupt signal, and then outputs the second type of interrupt signal. Wherein, when the voltage state jump of the first output terminal OUT1 is completed, and the voltage state jump of the second output terminal OUT2 has not occurred (that is, the first type of interrupt signal has been output, and the second type of interrupt signal has not been output), the voltage states of the first output terminal OUT1 and the second output terminal OUT2 are different; when the voltage state jump of the second output terminal OUT2 is completed (that is, after the second type of interrupt signal is output), the voltage states of the first output terminal OUT1 and the second output terminal OUT2 are the same. When the rotary encoder completes a counterclockwise rotation operation, the voltage state jump occurs at the second output terminal OUT2 first, and the voltage state jump occurs at the first output terminal OUT1 later; accordingly, the first interface expansion circuit 31 first outputs the second type of interrupt signal, and then outputs the first type of interrupt signal. Among them, when the second output terminal OUT2 completes the voltage state jump, and the first output terminal OUT1 does not complete the voltage state jump (that is, the first interface expansion circuit 31 outputs the second type of interrupt signal, and has not yet output the first type of interrupt signal), the voltage states of the first output terminal OUT1 and the second output terminal OUT2 are different; when the first output terminal OUT1 completes the voltage state jump (that is, after outputting the first type of interrupt signal), the voltage states of the first output terminal OUT1 and the second output terminal OUT2 are the same. Therefore, after receiving the interrupt signal output by the first interface expansion circuit 31, the main control circuit 40 can first determine the number of the encoder circuit 21 that can be triggered by the rotation operation, and then determine the number of the encoder circuit 21 triggered by the rotation operation and the rotation direction of the rotation operation by judging whether the voltage states of the first output terminal OUT1 and the second output terminal OUT2 are the same, and according to the type of the interrupt signal.

[0094] Specifically, the number of the encoder circuit 21 triggered by the rotation operation and the rotation direction of the rotation operation may be determined according to the following second method.

[0095] Method 2: Determine the number of the encoder circuit 21 triggered by the rotation operation according to the voltage state jump data stored in the first state register 311; and determine whether the voltage states of the first output terminal OUT1 and the second output terminal OUT2 of the encoder circuit 21 triggered by the rotation operation obtained by the level register 312 are the same. If different, determine whether the type of the interrupt signal is the first type or the second type; if the type of the interrupt signal is the first type, determine that the rotation direction is clockwise, and if the type of the interrupt signal is the second type, determine that the rotation direction is counterclockwise.

[0096] In some embodiments, the first interface expansion circuit 31 includes: a first interrupt terminal INT1 and a second interrupt terminal INT2. The first type of interrupt signal is: an interrupt signal output by the first interrupt terminal; the second type of interrupt signal is: an interrupt signal output by the second interrupt terminal. It should be noted that the first interface expansion circuit 31 may include only one interrupt terminal. In this case, the first type and the second type of interrupt signals may be distinguished by other features. For example, the first type of interrupt signal and the second type of interrupt signal may be signals of different voltages, respectively.

[0097] For example, when the first rotary encoder rotates clockwise once, the first output terminal OUT1 of the encoder circuit 21 first undergoes a voltage state jump, and the second output terminal OUT2 undergoes a voltage state jump later. The level register 312 obtains the voltage states of the first output terminal OUT1 and the second output terminal OUT2 in real time. When the voltage state jump occurs at the first output terminal OUT1 and the voltage state jump does not occur at the second output terminal OUT2, the first sub-register 3111 stores the voltage state jump data of the first output terminal OUT1, and the first sub-register 3111 provides an interrupt signal to the first interrupt terminal INT1, so that the first interrupt terminal INT1 outputs the interrupt signal. When the main control circuit 40 receives the interrupt signal, it determines that the first encoder circuit 21 is triggered by the rotation operation according to the voltage state jump data stored in the first sub-register 3111. In addition, the main control circuit 40 also reads the voltage states of the first output terminal OUT1 and the second output terminal OUT2 obtained by the level register 312. By comparison, it can be determined that the voltage states of the first output terminal OUT1 and the second output terminal OUT2 of the first encoder circuit 21 are different (the reason is that the voltage state jump occurs at the first output terminal OUT1 of the first encoder circuit 21, while the voltage state jump does not occur at the second output terminal OUT2. Therefore, the voltage states of the first output terminal OUT1 and the second output terminal OUT2 of the first encoder circuit 21 obtained by the level register 312 are different). At this time, the main control circuit 40 determines that the interrupt signal comes from the first interrupt terminal INT1, which means that the voltage state jump occurs first at the first output terminal OUT1 of the first encoder circuit 21. In this way, it can be determined that the rotary encoder corresponding to the first encoder circuit 21 rotates clockwise. When the voltage state of the second output terminal OUT2 changes, the second sub-register 3112 outputs an interrupt signal; at this time, the voltage states of the first output terminal OUT1 and the second output terminal OUT2 acquired by the level register 312 are the same. After receiving the interrupt signal, the main control circuit 40 determines that the voltage states of the first output terminal OUT1 and the second output terminal OUT2 of the first encoder circuit 21 are the same according to the voltage state acquired by the level register 312, and at this time, the action control instruction is no longer output to the system board.

[0098] For example, the input interfaces of the first interface expansion circuit 31 are respectively recorded as: interface I_0, interface I_1, interface I_2, interface I_3, wherein the first output terminal OUT1 of the first encoder circuit 21 is connected to interface I_0, and the second output terminal OUT2 is connected to interface I_1; the first output terminal OUT1 of the second encoder circuit 21 is connected to interface I_2, and the second output terminal OUT2 is connected to interface I_3. Each of the first output terminal OUT1 and the second output terminal OUT2 can be switched between a first voltage state and a second voltage state, wherein when the first output terminal OUT1 is in the first voltage state, the specific value of the first voltage signal output by the first output terminal OUT1 is 0V; when the first output terminal OUT1 is in the second voltage state, the second voltage signal output by the first output terminal OUT1 is 3V; when the second output terminal OUT2 is in the first voltage state, the specific value of the second voltage signal output by the second output terminal OUT2 is 0V; when the second output terminal OUT2 is in the second voltage state, the second voltage signal output by the second output terminal OUT1 is 3V. At the initial time t0, the first voltage signal outputted by the first output terminal OUT1 of the first encoder circuit 21 is 0V, and the second voltage signal outputted by the second output terminal OUT2 is 3V. The voltage state jump data stored in the first sub-register 3111 is "00", and the voltage state jump data stored in the second sub-register 3112 is "00". After the time t0, the rotary encoder corresponding to the first encoder circuit 21 rotates in the clockwise direction. Specifically, at the time t1 after the time t0, the first voltage signal outputted by the first encoder circuit 21 jumps from 0V to 3V, and at the time t2 after the time t1, the second voltage signal outputted by the first encoder circuit 21 jumps from 0V to 3V.

[0099] In this case, when the first voltage signal output by the first encoder circuit 21 jumps to 3V and the time t2 has not yet arrived, the voltage state jump data stored in the first sub-register 3111 is updated to "01", and the first interrupt terminal INT1 outputs an interrupt signal; the level register 312 obtains that the first output terminal OUT1 of the first encoder circuit 21 is in the second voltage state and the second output terminal OUT2 is in the first voltage state. After receiving the interrupt signal at time t1, the main control circuit 40 reads the voltage state jump data stored in the first sub-register 3111, thereby determining that the first encoder circuit 21 is triggered by the rotation operation; in addition, the main control circuit 40 reads the voltage state of the first output terminal OUT1 and the second output terminal OUT2 obtained by the first level register 312, and determines that the voltage states of the first output terminal OUT1 and the second output terminal OUT2 of the first encoder circuit 21 are different. In addition, the main control circuit 40 also determines that the interrupt signal comes from the first interrupt terminal INT1, thereby determining that the rotary encoder corresponding to the first encoder circuit 21 has rotated clockwise. At time t2, when the second voltage signal output by the first encoder circuit 21 jumps to 3V, the voltage state jump data stored in the first sub-register 3111 is updated to "10", and the second interrupt terminal INT2 outputs an interrupt signal; the level register 312 obtains that the first output terminal OUT1 and the second output terminal OUT2 of the first encoder circuit 21 are both in the second voltage state. After receiving the interrupt signal at time t2, the main control circuit 40 reads the voltage state jump data stored in the first sub-register 3111, thereby determining that the first encoder circuit 21 is triggered by the rotation operation; in addition, the main control circuit 40 reads the voltage states of the first output terminal OUT1 and the second output terminal OUT2 obtained by the first level register 312, and determines that the voltage states of the first output terminal OUT1 and the second output terminal OUT2 of the first encoder circuit 21 are the same, and at this time, the action control instruction is no longer output to the system board.

[0100] It can be seen from the above examples that when the rotary encoder undergoes a rotation operation, when one of the first output terminal OUT1 and the second output terminal OUT2 undergoes a voltage state jump first, and the other has not undergone a voltage state jump, the main control circuit 40 can determine the rotation direction, thereby improving the judgment speed, and can also improve the accuracy of the judgment. Taking the first rotary encoder as an example, assuming that the first output terminal OUT1 undergoes a first voltage state jump, the voltage state jump data generated and stored by the first sub-register 3111 is not read by the main control circuit 40; when the second output terminal OUT2 undergoes a voltage state jump, and the first output terminal OUT1 undergoes a second voltage state jump, the voltage state jump data generated and stored by the first sub-register 3111 is read by the main control circuit 40; when the second output terminal OUT2 undergoes a second voltage state jump, the voltage state jump data generated and stored by the second sub-register 3112 is not read by the main control circuit 40. Then, in this case, when the voltage state of the second output terminal OUT2 changes for the first time, the voltage states of the first output terminal OUT1 and the second output terminal OUT2 are the same (because the voltage state of both the first output terminal OUT1 and the second output terminal OUT2 changes once), and when the voltage state of the first output terminal OUT1 changes for the second time, the main control circuit 40 determines that the first rotary encoder has completed a clockwise rotation. It can be seen that when the rotary encoder rotates rapidly and the data reading speed of the main control circuit 40 is low, the main control circuit 40 can ensure the accuracy of the judgment when using the second method to determine the number and rotation direction of the rotary encoder triggered by the rotation operation.

[0101] Figure 6 is a circuit diagram of a key control device provided in some other embodiments of the present disclosure, and Figure 2 compared to, Figure 6 The key control device includes, in addition to a first interface expansion circuit 31, a main control circuit 40 and multiple encoder circuits 21, a second interface expansion circuit 32 and multiple key circuits 22. The key circuit 22 is configured to output a third voltage signal when triggered (the trigger is, for example, a touch or press operation); if no trigger is received, a fourth voltage signal is output, and the third voltage is different from the fourth voltage.

[0102] Figure 7 Schematic diagram of a key circuit provided in an embodiment of the present disclosure, such as Figure 7As shown, the key circuit 22 includes: a pull-up resistor R201 and a key switch SW1. The two ends of the pull-up resistor R201 are respectively connected to the first power supply terminal V1 and the output terminal OUTK of the key circuit 22; the two ends of the key switch SW1 are respectively connected to the second power supply terminal V2 and the output terminal OUTK of the key circuit 22. The key switch SW1 is turned on when triggered by a touch operation, and is turned off when no touch or pressing operation occurs. The third voltage is the voltage of the output terminal OUTK of the key circuit 22 when the key switch SW1 is turned on; the fourth voltage is the voltage of the output terminal OUTK of the key circuit 22 when the key switch SW1 is turned off.

[0103] Figure 8 is a schematic diagram of connection between a second interface expansion circuit and a key circuit provided in some embodiments of the present disclosure, Figure 8 The number of key circuits 22 is only for illustrative purposes. Figure 8 As shown, the second interface expansion circuit 32 includes a second state register 321. In some embodiments, the output terminal OUTK of each key circuit 22 is connected to an input interface of the second interface expansion circuit 32, and the input interface is, for example, a GPIO interface.

[0104] The second status register 321 is connected to each input interface of the second interface expansion circuit 32, and the second status register 321 is configured to generate and store the trigger status data of each key circuit 22 according to the output signal of the key circuit 22; when any key circuit 22 is triggered, the second status register 321 provides an interrupt signal to the interrupt terminal INT' of the second interface expansion circuit 32, and the interrupt terminal INT' of the second interface expansion circuit 32 outputs the interrupt signal. The trigger status data of the key circuit 22 is used to indicate whether the key circuit 22 is triggered. For example, a digital signal "1" indicates that the key circuit 22 is triggered, and a digital signal "0" indicates that the key circuit 22 is not triggered.

[0105] The main control circuit 40 is further configured to determine the number of the triggered key circuit 22 according to the trigger state data of each key circuit 22 stored in the second state register 321 when the interrupt terminal INT′ of the second interface expansion circuit 32 outputs an interrupt signal.

[0106] For example, the main control circuit 40 includes: a first interrupt receiving interface 40a, a first signal reading interface 40b, a second interrupt receiving interface 40d and a second signal reading interface 40e. The first interrupt receiving interface 40a is connected to the interrupt terminal INT of the first interface expansion circuit 31, and is used to receive the interrupt signal output by the first interface expansion circuit 31; the first signal reading interface 40b is used to read the voltage state transition data of the first output terminal OUT1 and the second output terminal OUT2 stored in the first state register 311. The second interrupt receiving interface 40d is connected to the interrupt terminal INT' of the second interface expansion circuit 32, and is used to receive the interrupt signal output by the second interface expansion circuit 32. The second signal reading interface 40e is connected to the data port 32a of the second interface expansion circuit 32, so as to read the data stored in the second state register 321 through the data port 32a. When the main control circuit 40 receives an interrupt signal, it determines whether the interrupt signal comes from the first interface expansion circuit 31 or the second interface expansion circuit 32. When it is determined that the interrupt signal comes from the first interface expansion circuit 31, it determines which encoder circuit 21 is triggered by the rotation operation and determines the rotation direction according to the method one or method two described above; when it is determined that the interrupt signal comes from the second interface expansion circuit 32, it determines which key circuit 22 is triggered by the touch or press operation according to the trigger status data of each key circuit 22 stored in the second status register 321.

[0107] like Figure 6 As shown, the key control device also includes a first indication structure 71 and a second indication structure 72, wherein the first indication structure 71 is connected to the main control circuit 40, and the first indication structure 71 is configured to output a corresponding indication signal according to the number of the encoder circuit 21 triggered by the rotation operation determined by the main control circuit 40. For example, the first indication structure 71 includes a plurality of first indication elements, and the first indication elements correspond to the encoder circuits 21 one by one. When the main control circuit 40 determines that a certain encoder circuit 21 is triggered by the rotation operation, the indication element corresponding to the encoder circuit 21 is controlled to output an indication signal.

[0108] The second indication structure 72 is connected to the main control circuit 40, and the second indication structure 72 is configured to output a corresponding indication signal according to the number of the triggered key circuit 22. The number of the triggered key circuit 22 is determined by the main control circuit 40. For example, the second indication structure 72 includes a plurality of second indication elements, and the second indication elements correspond to the encoder circuits 21 one by one. When the main control circuit 40 determines that a certain key circuit 22 is triggered, the indication element corresponding to the key circuit 22 is controlled to output an indication signal.

[0109] The indication signal is at least one of a light signal, a sound signal, and a vibration signal. In one example, both the first indication element and the second indication element are light emitting diodes.

[0110] Fig. 9 The schematic diagram of an electronic device provided in some embodiments of the present disclosure is particularly suitable for a monitor device. The electronic device includes a system board 11 and the key control device in the above embodiment. The system board 11 communicates with the main control circuit 40, and the main control circuit 40 outputs an action control instruction to the system board 11 according to the result determined by the main control circuit 40 (for example, the number and rotation direction of the rotary encoder triggered by the rotation operation, or the number of the key circuit triggered). The system board 11 performs a corresponding action according to the action control instruction output by the main control circuit 40.

[0111] Fig.10 This is a flowchart of a key control method provided in some embodiments of the present disclosure, and the key control method is applied to the key control device provided in the above embodiments. Figures 2 to 8 As shown, the key control device includes: a first interface expansion circuit 31, a main control circuit 40 and an encoder circuit 21. The encoder circuit 21 is configured to cause its first output terminal INT1 and the second output terminal INT2 to output a first voltage signal and a second voltage signal respectively under the triggering of the rotation operation; wherein the first voltage signal and the second voltage signal both have two voltage states, and the voltage state refers to the state of the voltage of the first voltage signal or the second voltage signal. For example, under the triggering of the rotation operation, the first voltage signal and the second voltage signal both jump between the first voltage state and the second voltage state, that is, the first output terminal OUT1 and the second output terminal OUT2 both jump between the first voltage state and the second voltage state; and when the rotation direction is clockwise, the first voltage signal jumps to a voltage state before the second voltage signal; when the rotation direction is counterclockwise, the second voltage signal jumps to a voltage state before the first voltage signal.

[0112] The key control method comprises:

[0113] S11, the first interface expansion circuit 31 receives the first voltage signal and the second voltage signal, and generates an interrupt signal and voltage state jump data in response to the first voltage signal or the second voltage signal output by the encoder circuit 21; the voltage state jump data is used to indicate whether the voltage state jumps.

[0114] In some embodiments, the first interface expansion circuit 31 includes a first state register 311, and the first interface expansion circuit 31 generates voltage state jump data, specifically including: the first state register 311 generates and stores voltage state jump data of the first output end and the second output end of the encoder circuit according to the first voltage signal and / or the second voltage signal.

[0115] The first interface expansion circuit 31 generates an interrupt signal, which may specifically include: when the first voltage signal of the first output terminal OUT1 or the second voltage signal of the second output terminal OUT2 undergoes a voltage state jump, the interrupt terminal of the first interface expansion circuit 31 outputs the interrupt signal.

[0116] S12. The main control circuit 40 determines the rotation direction of the rotation operation according to the interrupt signal and the voltage state transition data.

[0117] In some embodiments, step S12 includes: the main control circuit 40 responds to the interrupt signal output by the first interface expansion circuit 31, reads the voltage state jump data stored in the first state register 311, and determines the rotation direction of the rotation operation at least based on the voltage state jump data stored in the first state register 311.

[0118] In some embodiments, there are multiple encoder circuits 21, and the key control method further includes: the main control circuit 40 determines the number of the encoder circuit triggered by the rotation operation according to the interrupt signal and the voltage state jump data.

[0119] Fig.11 is a flowchart of a key control method provided in some other embodiments of the present disclosure, wherein: Fig.11 The method shown in Figure 6 The structure shown, such as Figure 6 As shown, the keypad further includes: a second interface expansion circuit 32, a plurality of key circuits 22, a first indication structure 71 and a second indication structure 72, wherein the second interface expansion circuit 32 is as shown in FIG. Figure 8 As shown, it includes a second state register 321. The key circuit 22 is configured to output a signal of a third voltage when triggered; otherwise, it outputs a signal of a fourth voltage.

[0120] like Fig.11 As shown, the key control method includes:

[0121] S21a, the first state register 311 generates and stores voltage state jump data of the first output terminal and the second output terminal of the encoder circuit 21 according to the first voltage signal and / or the second voltage signal output by each encoder circuit 21; the voltage state jump data is used to indicate whether the voltage state jumps. And when the voltage state of any first voltage signal or any second voltage signal jumps, the first interface expansion circuit 31 outputs an interrupt signal.

[0122] S21b, the second status register 321 generates and stores the trigger status data of each key circuit 22 according to the output signal of the key circuit 22, and when any key circuit 22 is triggered, the interrupt terminal of the second interface expansion circuit 32 outputs an interrupt signal.

[0123] S22. When the main control circuit 40 receives an interrupt signal, it determines whether the received interrupt signal comes from the first interface expansion circuit 31 or the second interface expansion circuit 32. When the interrupt signal comes from the first interface expansion circuit 31, step S23 is executed; when the interrupt signal comes from the second interface expansion circuit 32, step S24 is executed.

[0124] S23 , the main control circuit 40 reads the voltage state transition data stored in the first state register 311 , and determines the number and rotation direction of the encoder circuit 21 triggered by the rotation operation at least according to the voltage state transition data stored in the first state register 311 .

[0125] In some optional implementations, step S23 includes: if the interrupt signal currently received by the main control circuit 40 is the interrupt signal output by the first interface expansion circuit 31 for the i-th time, and i is an odd number, the main control circuit 40 waits for the first interface expansion circuit 31 to output the interrupt signal for the i+1th time; and determines the rotation direction according to the voltage state jump data of each first output terminal and the second output terminal when the first interface expansion circuit 31 outputs the interrupt signal for the i-th time and the i+1th time. For example, according to the voltage jump data of the first output terminal OUT1 and the second output terminal OUT2 when the first interface expansion circuit 31 outputs the interrupt signal for the i-th time and the i+1th time, determine the timing of the voltage state jump of the first output terminal OUT1 and the second output terminal OUT2, and then determine the rotation direction according to the timing of the voltage state jump of the first output terminal OUT1 and the second output terminal OUT2.

[0126] The specific process of the main control circuit 40 determining the rotation direction according to the timing of the voltage state jump occurring at the first output terminal and the second output terminal is described above and will not be repeated here.

[0127] When the main control circuit 40 determines that one of the encoder circuits 21 is triggered by the rotation operation, it can also control the first indication structure to output a corresponding indication signal according to the number of the triggered encoder circuit 21 .

[0128] S24 , the main control circuit 40 determines the number of the triggered key circuit 22 according to the trigger state data of each key circuit 22 stored in the second state register 321 .

[0129] When the main control circuit 40 determines that one of the key circuits 22 is triggered, the second indication structure can be controlled to output a corresponding indication signal according to the number of the triggered key circuit 22 .

[0130] Fig.12 This is a flow chart of a key control method provided in some other embodiments of the present disclosure. Fig.12 The method shown in Figure 6 The structure shown in FIG. 1 and the first interface expansion circuit 31 adopts Figure 5 According to the structure shown in , the first state register 311 includes: a first sub-register 3111 and a second sub-register 3112 ; in addition, the first interface expansion circuit 31 also includes: a level register 312 .

[0131] like Fig.12 As shown, the key control method includes:

[0132] S31, the first state register 311 generates and stores the voltage state jump data of the first output terminal and the second output terminal of the encoder circuit 21 according to the first voltage signal and / or the second voltage signal output by each encoder circuit 21; and when a voltage state jump occurs at any first output terminal or any second output terminal, the first interface expansion circuit 31 outputs an interrupt signal.

[0133] Specifically, step S31 includes: the first sub-register 311 generates and stores the voltage state transition data of each first output terminal according to the first voltage signal outputted by the first output terminal of each encoder circuit 21; and when the voltage state transition occurs at any first output terminal, the first interface expansion circuit 31 outputs the first type of interrupt signal. And, the second sub-register 3112 generates and stores the voltage state transition data of each second output terminal according to the second voltage signal outputted by the second output terminal of each encoder circuit 21; and when the transition occurs at any second output terminal, the first interface expansion circuit 31 outputs the second type of interrupt signal.

[0134] In some embodiments, the interrupt terminal of the first interface expansion circuit 31 includes: a first interrupt terminal INT1 and a second interrupt terminal INT2, the first type of interrupt signal is: the interrupt signal output by the first interrupt terminal INT1; the second type of interrupt signal is: the interrupt signal output by the second interrupt terminal INT2

[0135] S32, the second status register 321 generates and stores the trigger status data of each key circuit 22 according to the output signal of the key circuit 22, and when any key circuit 22 is triggered, the interrupt terminal of the second interface expansion circuit 32 outputs an interrupt signal.

[0136] S33. When the main control circuit 40 receives an interrupt signal, it determines whether the received interrupt signal comes from the first interface expansion circuit 31 or the second interface expansion circuit 32. When the interrupt signal comes from the first interface expansion circuit 31, step S34 is executed; when the interrupt signal comes from the second interface expansion circuit 32, step S35 is executed.

[0137] S34 . The main control circuit 40 determines the number and rotation direction of the encoder circuit 21 triggered by the rotation operation at least according to the voltage state transition data stored in the first state register 311 .

[0138] Specifically, step S34 includes: judging whether the voltage states of the first output terminal and the second output terminal of the encoder circuit 21 triggered by the rotation operation are the same according to the voltage state obtained by the level register 312; if they are different, judging whether the type of the interrupt signal is the first type or the second type; if the type of the interrupt signal is the first type, determining that the rotation direction is clockwise, and if the type of the interrupt signal is the second type, determining that the rotation direction is counterclockwise.

[0139] When the main control circuit 40 determines that one of the encoder circuits 21 is triggered by the rotation operation, it can also control the first indication structure to output a corresponding indication signal according to the number of the triggered encoder circuit 21 .

[0140] S35 . The main control circuit 40 determines the serial number of the triggered key circuit 22 according to the trigger status data of each key circuit 22 stored in the second status register 321 .

[0141] When the main control circuit 40 determines that one of the key circuits 22 is triggered, the second indication structure can be controlled to output a corresponding indication signal according to the number of the triggered key circuit 22 .

[0142] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A key control device, comprising: An encoder circuit, the encoder circuit comprising a first output terminal and a second output terminal, the encoder circuit being configured to, under the triggering of a rotation operation, cause the first output terminal and the second output terminal to output a first voltage signal and a second voltage signal respectively; A first interface expansion circuit is configured to receive the first voltage signal and the second voltage signal, and generate an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit; A main control circuit is configured to determine a rotation direction of the rotation operation according to the interrupt signal and the voltage state transition data; A plurality of key circuits, each of which is configured to output a signal of a third voltage when triggered; otherwise, output a signal of a fourth voltage; The second interface expansion circuit includes a second status register, wherein the second status register is configured to generate and store trigger status data of each of the key circuits according to an output signal of the key circuit; when any of the key circuits is triggered, an interrupt terminal of the second interface expansion circuit outputs an interrupt signal; Wherein, the main control circuit is further configured to, when the second interface expansion circuit outputs an interrupt signal, determine the number of the triggered key circuit according to the trigger state data of each key circuit stored in the second state register.

2. The key control device according to claim 1, wherein: The first interface expansion circuit includes a first state register, which is configured to generate and store voltage state transition data of the first output terminal and the second output terminal of the encoder circuit according to the first voltage signal and / or the second voltage signal.

3. The key control device according to claim 2, wherein: The main control circuit responds to the interrupt signal output by the first interface expansion circuit, reads the voltage state transition data stored in the first state register, and determines the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register.

4. The key control device according to claim 3, wherein: The first status register includes: a first sub-register and a second sub-register; The first sub-register is configured to generate and store voltage state transition data of the first output terminal according to a first voltage signal outputted from the first output terminal of the encoder circuit; and when a voltage state transition occurs at the first output terminal, the first interface expansion circuit outputs an interrupt signal of a first type; The second sub-register is configured to generate and store voltage state transition data of the second output end according to a second voltage signal outputted from the second output end of the encoder circuit; and when a voltage state transition occurs at the second output end, the first interface expansion circuit outputs a second type of interrupt signal.

5. The key control device according to claim 4, wherein: The first interface expansion circuit includes: a first interrupt terminal and a second interrupt terminal. The first type of interrupt signal is: an interrupt signal output by the first interrupt terminal; the second type of interrupt signal is: an interrupt signal output by the second interrupt terminal.

6. The key control device according to claim 4, wherein: The first interface expansion circuit further includes: a level register configured to obtain the voltage state of the first output terminal and the second output terminal of each encoder circuit in real time; Determining the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register specifically includes: According to the voltage state obtained by the level register, determine whether the voltage states of the first output terminal and the second output terminal of the encoder circuit triggered by the rotation operation are the same; if different, determine whether the type of the interrupt signal is the first type or the second type; if the type of the interrupt signal is the first type, determine that the rotation direction is clockwise, and if the type of the interrupt signal is the second type, determine that the rotation direction is counterclockwise.

7. The key control device according to claim 3, wherein: The main control circuit is specifically configured as follows: When the main control circuit receives the interrupt signal output by the first interface expansion circuit for the i-th time, it waits for the interrupt signal output by the first interface expansion circuit for the (i+1)th time; and determining the rotation direction according to voltage state transition data of the first output terminal and the second output terminal when the first interface expansion circuit outputs the interrupt signal for the i-th time and the (i+1)-th time; Here, i is an odd number.

8. The key control device according to any one of claims 1 to 3, wherein: There are multiple encoder circuits; the main control circuit is further configured to determine the number of the encoder circuit triggered by the rotation operation according to the interrupt signal and the voltage state transition data.

9. A key control method applied to a key control device, wherein: The key control device comprises: a first interface expansion circuit, a main control circuit and an encoder circuit, wherein the encoder circuit comprises a first output terminal and a second output terminal, and the encoder circuit is configured to, under the triggering of a rotation operation, cause the first output terminal and the second output terminal to output a first voltage signal and a second voltage signal respectively; The method comprises: The first interface expansion circuit receives the first voltage signal and the second voltage signal, and generates an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit; The main control circuit determines the rotation direction of the rotation operation according to the interrupt signal and the voltage state jump data; The key control device further comprises: a second interface expansion circuit and a plurality of key circuits, wherein the second interface expansion circuit comprises a second state register; the key circuit is configured to output a signal of a third voltage when triggered; otherwise, output a signal of a fourth voltage; The method further comprises: The second status register generates and stores the trigger status data of each of the key circuits according to the output signal of the key circuit, and when any of the key circuits is triggered, the interrupt terminal of the second interface expansion circuit outputs an interrupt signal; When the main control circuit receives the interrupt signal output by the second interface expansion circuit, the serial number of the triggered key circuit is determined according to the trigger status data of each key circuit stored in the second status register.

10. The method according to claim 9, wherein: The first interface expansion circuit includes a first state register; the first interface expansion circuit generates voltage state transition data, including: The first state register generates and stores voltage state transition data of the first output terminal and the second output terminal of the encoder circuit according to the first voltage signal and / or the second voltage signal.

11. The method according to claim 10, wherein: The main control circuit determines the rotation direction of the rotation operation in response to the interrupt signal and the voltage state transition data, specifically including: The main control circuit responds to the interrupt signal output by the first interface expansion circuit, reads the voltage state transition data stored in the first state register, and determines the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register.

12. The method according to claim 11, wherein: The first status register includes: a first sub-register and a second sub-register; The first state register generates and stores voltage state transition data of the first output terminal and the second output terminal of the encoder circuit according to the first voltage signal and / or the second voltage signal, specifically including: The first sub-register generates and stores voltage state transition data of each first output terminal according to a first voltage signal output by the first output terminal of each encoder circuit; The second sub-register generates and stores voltage state transition data of each second output terminal according to the second voltage signal output by the second output terminal of each encoder circuit; When a voltage state jump occurs at any one of the first output terminals, the first interface expansion circuit outputs a first type of interrupt signal; when a voltage state jump occurs at any one of the second output terminals, the first interface expansion circuit outputs a second type of interrupt signal.

13. The method according to claim 12, wherein: The first interface expansion circuit includes: a first interrupt terminal and a second interrupt terminal. The first type of interrupt signal is: an interrupt signal output by the first interrupt terminal; the second type of interrupt signal is: an interrupt signal output by the second interrupt terminal.

14. The method according to claim 12, wherein: The first interface expansion circuit further includes: a level register, and the method further includes: the level register acquiring the voltage states of the first output terminal and the second output terminal of the encoder circuit in real time; Determining the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register specifically includes: According to the voltage state obtained by the level register, determine whether the voltage states of the first output terminal and the second output terminal of the encoder circuit triggered by the rotation operation are the same; if different, determine whether the type of the interrupt signal is the first type or the second type; if the type of the interrupt signal is the first type, determine that the rotation direction is clockwise, and if the type of the interrupt signal is the second type, determine that the rotation direction is counterclockwise.

15. The method according to claim 11, wherein: The main control circuit responds to the interrupt signal output by the first interface expansion circuit, reads the voltage state transition data stored in the first state register, and determines the rotation direction of the rotation operation at least according to the voltage state transition data stored in the first state register, specifically including: When the main control circuit receives the interrupt signal output by the first interface expansion circuit for the i-th time, it waits for the first interface expansion circuit to output the interrupt signal for the i+1th time; and determines the rotation direction according to the voltage state jump data of each of the first output terminal and the second output terminal when the first interface expansion circuit outputs the interrupt signal for the i-th time and the i+1-th time; Here, i is an odd number.

16. The method according to any one of claims 9 to 11, wherein: The number of the encoder circuits is multiple; The method further includes: the main control circuit determining the serial number of the encoder circuit triggered by the rotation operation according to the interrupt signal and the voltage state transition data.

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