A defect detection method, apparatus, and device, and storage medium

Abstract

Embodiments of the present disclosure provide a defect detection method, device and equipment and a storage medium. The detection method comprises: providing a semiconductor device to be detected, the semiconductor device to be detected comprising a plurality of units to be detected; setting the semiconductor device to be detected in a field of view of a laser lens, performing first electrical detection on the units to be detected to obtain first detection values of the units to be detected at room temperature and second detection values of the units to be detected under scanning of the laser lens; and determining whether the units to be detected have defects according to the first detection values and the second detection values.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a defect detection method, apparatus, device, and storage medium. Background Technology

[0002] In integrated circuit manufacturing, the processing of semiconductor devices involves a series of steps, including cleaning, film deposition, etching, and heat treatment. Each step can introduce various defects. Defects in semiconductor devices can lead to device failure.

[0003] Therefore, there is an urgent need for a method to detect defects in semiconductor devices. Summary of the Invention

[0004] In view of the above, this disclosure provides a defect detection method, apparatus, device, and storage medium to solve at least one technical problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a defect detection method, the detection method comprising:

[0007] A semiconductor device under test (DUT) is provided, the semiconductor DUT comprising a plurality of test cells;

[0008] The semiconductor device under test is placed within the field of view of the laser lens, and a first electrical test is performed on the device under test to obtain a first detection value of the device under test at room temperature and a second detection value of the device under test under the scanning of the laser lens.

[0009] Based on the first detection value and the second detection value, it is determined whether the unit under test has a defect.

[0010] In some embodiments, a first electrical detection is performed on the unit under test to obtain a second detection value of the unit under test under the laser lens scanning, including:

[0011] If the first detection value of the unit under test is greater than the first preset detection value, then the unit under test is determined to be a suspected unit;

[0012] The suspected unit is scanned by a laser beam using the laser lens to obtain a second detection value for the suspected unit.

[0013] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0014] If the second detection value is substantially the same as the first preset detection value, then it is determined that the unit under test has a defect.

[0015] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0016] If the second detection value is less than the first detection value, then the unit under test is determined to have a defect.

[0017] In some embodiments, each unit under test includes multiple MOSFETs, and if a defect is determined to exist in the unit under test, the detection method further includes:

[0018] A first electrical test is performed on each MOS transistor of the unit under test to obtain a third test value of the MOS transistor at room temperature and a fourth test value of the MOS transistor under the scanning of the laser lens;

[0019] Based on the third and fourth detection values, it is determined whether the MOS transistor has a defect.

[0020] In some embodiments, a first electrical detection is performed on the MOS transistor to obtain a fourth detection value of the MOS transistor under the scanning of the laser lens, including:

[0021] If the third detection value of the MOS transistor is greater than the second preset detection value, then the MOS transistor is determined to be a suspected MOS transistor;

[0022] The suspected MOS transistor is scanned by a laser beam using the laser lens to obtain a fourth detection value for the suspected MOS transistor.

[0023] In some embodiments, determining whether the MOSFET has a defect based on the third detection value and the fourth detection value includes:

[0024] If the fourth detection value is basically the same as the second preset detection value, then it is determined that the MOS transistor has a defect.

[0025] In some embodiments, determining whether the MOSFET has a defect based on the third detection value and the fourth detection value includes:

[0026] If the fourth detection value is less than the third detection value, then the MOS transistor is determined to have a defect.

[0027] In some embodiments, before performing the first electrical detection on the unit under test, the detection method further includes:

[0028] A second electrical test is performed on the semiconductor device under test to obtain a fifth detection value of the semiconductor device under test at a first temperature and a sixth detection value at a second temperature; wherein the first temperature is lower than the second temperature;

[0029] The test cell in the semiconductor device under test is determined based on the fifth detection value, the sixth detection value, and the design layout of the semiconductor device under test.

[0030] In some embodiments, prior to providing the semiconductor device under test, the detection method further includes:

[0031] Provides multiple semiconductor devices;

[0032] A low voltage and a higher turn-on voltage are sequentially applied to the semiconductor device;

[0033] If the semiconductor device operates differently under the low voltage and the turn-on voltage, then the semiconductor device is determined to be a semiconductor device under test.

[0034] Secondly, embodiments of this disclosure provide a defect detection device, the detection device comprising:

[0035] A laser detection module is used to provide a laser lens for scanning the unit under test; wherein, a plurality of the units under test constitute a semiconductor device under test; the semiconductor device under test is disposed within the field of view of the laser lens;

[0036] An electrical detection module is used to perform a first electrical detection on the unit under test at room temperature to obtain a first detection value; and to perform a first electrical detection on the unit under test under the scanning of the laser lens to obtain a second detection value;

[0037] The defect detection module is used to determine whether the unit under test has a defect based on the first detection value and the second detection value.

[0038] In some embodiments, the defect detection module is specifically used to determine the unit under test as a suspected unit if the first detection value of the unit under test is greater than a first preset detection value;

[0039] The laser detection module is specifically used to perform laser beam scanning on the suspected unit;

[0040] The electrical detection module is specifically used to perform a first electrical detection on the suspected unit under laser beam scanning to obtain a second detection value.

[0041] In some embodiments, the defect detection module is specifically used to determine that the unit under test has a defect if the second detection value is substantially the same as the first preset detection value.

[0042] In some embodiments, the defect detection module is specifically used to determine that the unit under test has a defect if the second detection value is less than the first detection value.

[0043] In some embodiments, each unit under test includes multiple MOSFETs, and when it is determined that the unit under test has a defect...

[0044] The electrical detection module is specifically used to perform a first electrical detection on each MOS transistor of the unit under test at room temperature to obtain a third detection value; and is specifically used to perform a first electrical detection on each MOS transistor of the unit under test under the scanning of the laser lens to obtain a fourth detection value.

[0045] The defect detection module is specifically used to determine whether the MOS transistor has a defect based on the third detection value and the fourth detection value.

[0046] In some embodiments, the defect detection module is specifically used to determine that the MOS transistor is a suspected MOS transistor if the third detection value of the MOS transistor is greater than the second preset detection value;

[0047] The laser detection module is specifically used to perform laser beam scanning on the suspected MOS transistor;

[0048] The electrical detection module is specifically used to perform a first electrical detection on the suspected MOS transistor under laser beam scanning to obtain a fourth detection value.

[0049] In some embodiments, the defect detection module is specifically used to determine that the MOS transistor has a defect if the fourth detection value is substantially the same as the second preset detection value.

[0050] In some embodiments, the defect detection module is specifically used to determine that the MOS transistor has a defect if the fourth detection value is less than the third detection value.

[0051] Thirdly, embodiments of this disclosure provide a defect detection device, the detection device comprising:

[0052] Network interfaces are used to enable communication and connection between components;

[0053] Memory, used to store executable instructions;

[0054] The processor is used to execute executable instructions stored in the memory to implement the defect detection method described in the above technical solution.

[0055] Fourthly, embodiments of this disclosure provide a storage medium storing a computer program that, when executed by at least one processor, implements the defect detection method described in the above technical solution.

[0056] This disclosure provides a defect detection method, apparatus, device, and storage medium. The detection method includes: providing a semiconductor device under test (DUT), the DUT including a plurality of test units; placing the semiconductor DUT within the field of view of a laser lens; performing a first electrical test on the test units to obtain a first detection value of the test unit at room temperature and a second detection value of the test unit under laser lens scanning; and determining whether the test unit has a defect based on the first detection value and the second detection value. As can be seen from the above, the defect detection method provided by this disclosure performs a first electrical test on the test units placed within the field of view of a laser lens, utilizing the heating characteristics of the laser lens to create a dynamic high and low temperature environment with a temperature difference from room temperature. Thus, based on the first detection value of the test unit at room temperature and the second detection value of the test unit under laser lens scanning, it is possible to quickly determine whether there is a difference between the detection values ​​of the test unit at room temperature and under laser lens scanning, and thereby determine whether the test unit has a defect, effectively saving detection time and improving detection efficiency. Attached Figure Description

[0057] Figure 1 A diagram showing the relationship between drain-source voltage and gate voltage for a failed device and a reference device provided in an embodiment of this disclosure;

[0058] Figure 2 A schematic flowchart of the defect detection method provided in the embodiments of this disclosure;

[0059] Figure 3 A graph showing the relationship between current and applied voltage in the pre-charge power-off mode of a semiconductor device under test and a reference device provided in embodiments of this disclosure;

[0060] Figure 4 A graph showing the relationship between current and detection time in the pre-charge power-off mode of a defective semiconductor device and a reference device provided in embodiments of this disclosure. Detailed Implementation

[0061] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0063] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0064] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0065] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0068] Currently, indium gallium arsenide (InGaAs) emission microscopy (EMMI), optical beam induced resistance change (OBIRCH), and thermal emission microscopy are commonly used for failure analysis and defect localization of semiconductor devices.

[0069] The working principle of EMMI (Electronically Modulated Microscope) is to apply a bias voltage to a semiconductor device to capture photons emitted during electron-hole recombination, thereby detecting defects in the semiconductor device. Indium gallium arsenide (IGaAs) lenses can detect wavelengths ranging from 900 nm to 1600 nm. IGaAs microscopy can locate defects by detecting leakage currents caused by various defects. For example, IGaAs microscopy can detect gate oxide defects, latch-up, and junction leakage in metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0070] The working principle of OBIRCH is as follows: A laser beam scans the surface of a semiconductor device under a constant voltage. Part of the laser beam's energy is absorbed by the semiconductor device and converted into heat, causing a temperature change in the scanned area. If defects or voids exist in the metal interconnect layer of the semiconductor device, the heat conduction in these areas differs from that in other intact areas, resulting in different temperature changes and thus altering the resistance of the metal interconnect layer. Furthermore, since a constant voltage is applied to the metal interconnect layer, this change in resistance can be converted into a change in current. Therefore, by detecting the change in resistance induced by the laser and detecting the change in current at the induced point, the location of defects can be determined. OBIRCH is commonly used to detect voids in the interconnect layer of semiconductor devices, voids under vias, and short circuits in the metal interconnect layer.

[0071] The working principle of thermal microscopy is to locate defects by receiving abnormal thermal radiation generated by defects in semiconductor devices using a mid-infrared sensor. For example, thermal microscopy can be used to detect microampere (μA) level leakage currents, short circuits at the bottom of metal layers, and so on.

[0072] As semiconductor device manufacturing processes continue to shrink, the requirements for leakage current in MOSFETs become increasingly stringent. Therefore, controlling leakage current is particularly important after MOSFETs are miniaturized. Currently, testing equipment for failure analysis and defect localization mainly targets MOSFETs with high leakage current to identify hot spots. However, some defective MOSFETs often do not exhibit leakage current; the only issue is a mismatch in the MOSFET's threshold voltage Vt.

[0073] refer to Figure 1 , Figure 1 A graph showing the relationship between drain-source voltage and gate voltage for a failed device and a reference device provided in an embodiment of this disclosure. Figure 1 The failed devices are shown separately (e.g.) Figure 1 (shown by solid lines) and reference device (e.g.) Figure 1 The relationship curves between drain-source voltage Vds and gate voltage VG (shown by the dashed line in the middle) are shown; the Vds-VG curves of the failed device and the reference device almost completely overlap, except for... Figure 1 The solid circle indicates that the curves of the failed device and the reference device are separated. Here, the failed device includes a MOSFET with a Vt mismatch defect. That is to say, the leakage current of the MOSFET with this Vt mismatch defect is not obvious, and there is only a slight difference in the threshold voltage. It is difficult to determine which circuit's MOSFET has the defect using the aforementioned EMMI, OBIRCH, and thermal microscopy.

[0074] Therefore, for MOSFETs with Vt mismatch defects, the only method available is the traditional Focused Ion Beam (FIB) method. This involves connecting the suspected Vt mismatch circuit externally and confirming the defect using an oscilloscope. However, this method requires collecting a large amount of experimental data beforehand to accurately determine the presence of a defect in a specific circuit. Therefore, this method for detecting Vt mismatch defects in MOSFETs is cumbersome and time-consuming.

[0075] In view of this, embodiments of the present disclosure provide a defect detection method, apparatus, device, and storage medium.

[0076] refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating the defect detection method provided in an embodiment of this disclosure. Figure 2 As shown, the detection method includes:

[0077] Step S201: Provide a semiconductor device under test, wherein the semiconductor device under test includes a plurality of test units;

[0078] Step S202: Place the semiconductor device under test (DUT) within the field of view of the laser lens, and perform a first electrical test on the DUT to obtain a first detection value of the DUT at room temperature and a second detection value of the DUT under the scanning of the laser lens.

[0079] Step S203: Determine whether the unit under test has a defect based on the first detection value and the second detection value.

[0080] In this embodiment, a first electrical test is performed on the unit under test (UDT) located within the field of view of the laser lens. The heating characteristics of the laser lens are used to create a dynamic high and low temperature environment with a temperature difference from room temperature. Based on the first detection value of the UDT at room temperature and the second detection value of the UDT under laser lens scanning, it can be quickly determined whether there is a difference between the detection values ​​of the UDT at room temperature and under laser lens scanning, and thus determine whether the UDT has a defect. This can effectively save detection time and improve detection efficiency.

[0081] In some embodiments, prior to providing the semiconductor device under test, the detection method further includes:

[0082] Provides multiple semiconductor devices;

[0083] A low voltage and a higher turn-on voltage are sequentially applied to the semiconductor device;

[0084] If the semiconductor device operates differently under the low voltage and the turn-on voltage, then the semiconductor device is determined to be a semiconductor device under test.

[0085] Here, before providing the semiconductor device under test in step S201, it is necessary to screen the semiconductor devices and identify those with abnormal operating conditions as semiconductor devices under test. Here, abnormal operating conditions can be caused by abnormal precharge power-down current (IDD2P) of the semiconductor device.

[0086] In this embodiment of the disclosure, semiconductor devices can be screened using a Write Direct Read (WDR) test. In a specific example, a turn-on voltage can be applied to the semiconductor device. Here, the turn-on voltage can be the supply voltage VDD2, for example, VDD2 = 1.1V. The supply voltage VDD2 can be used to power the peripheral circuits of the semiconductor device. Applying the turn-on voltage or a higher voltage to the semiconductor device will cause it to conduct normally (power on), i.e., it is operating normally. Applying a lower voltage than the turn-on voltage will also cause the semiconductor device to conduct normally when the difference between the turn-on voltage and the lower voltage is less than a preset voltage, i.e., it is operating normally. For example, if the turn-on voltage VDD2 = 1.1V, then applying a voltage of 1.1V or higher will cause the semiconductor device to conduct normally; and applying a lower voltage of 1.05V (i.e., the difference between the turn-on voltage 1.1V and the lower voltage 1.05V is 0.05V) will also cause the semiconductor device to conduct normally.

[0087] In a specific example, a low voltage, such as 1.05V, can be applied to a semiconductor device. If the semiconductor device conducts normally, meaning its operation is normal, it can be preliminarily determined that the power supply circuit of the semiconductor device is not defective. Then, if a conduction voltage, such as 1.1V, is applied, the semiconductor device will still conduct normally, meaning its operation remains normal. Further applying a low voltage, such as 1.05V, will also result in the semiconductor device conducting normally, meaning its operation remains normal. In other words, applying a low voltage, a conduction voltage, and then another low voltage sequentially results in the same operating state for the semiconductor device. Therefore, based on the fact that the semiconductor device operates normally under both low voltage and higher conduction voltages, it can be determined that the power supply circuit of the semiconductor device is not defective.

[0088] In another specific example, a low voltage, such as 1.05V, can be applied to a semiconductor device. If the semiconductor device cannot conduct normally, i.e., its operating state is abnormal, then a conduction voltage, such as 1.1V, can be applied. At this point, the semiconductor device can conduct normally, i.e., its operating state is normal. Further applying a low voltage, such as 1.05V, will also allow the semiconductor device to conduct normally, i.e., its operating state remains normal. In other words, by sequentially applying a low voltage, a conduction voltage, and a low voltage, the semiconductor device's operating state changes from abnormal to normal. Furthermore, even after applying a low voltage, the semiconductor device's operating state remains normal. Therefore, by observing the different operating states of the semiconductor device under sequentially applied low voltage and conduction voltages higher than the low voltage, a defect in the semiconductor device's power supply circuit can be determined, thus identifying the semiconductor device as a semiconductor device under test.

[0089] Here, for the aforementioned semiconductor device under test (DUT), if applying a low voltage and then a turn-on voltage sequentially causes the DUT's operating state to change from abnormal to normal, and it still passes the WDR test under normal operating conditions, then the possibility of a problem with the write / read operation (W / R) can be ruled out. Therefore, it can be determined that the abnormal operating state of the DUT under low voltage is caused by the power supply circuit. In other words, a problem with the power supply circuit causes the write / read operation problem. Thus, it can be determined that the power supply circuit of the DUT is defective. In a specific example, the power supply circuit of the DUT is a VDD2 detection circuit.

[0090] refer to Figure 3 , Figure 3 A graph showing the relationship between current and applied voltage in the pre-charge power-off mode of the semiconductor device under test and reference device provided in embodiments of this disclosure. Figure 3As shown, Mark26 represents the reference device, which is a semiconductor device without defects. First, a voltage VDD2 of 1.05V is applied to the reference device. At this time, the IDD2P current of the reference device is 3.25mA, indicating that the reference device can conduct normally, i.e., its operating state is normal. Next, a voltage VDD2 of 1.1V is applied to the reference device. At this time, the IDD2P current of the reference device is 2.12mA, indicating that the reference device can still conduct normally, i.e., its operating state is normal. Finally, a voltage VDD2 of 1.05V is applied to the reference device. At this time, the IDD2P current of the reference device is 2.12mA, indicating that the reference device can still conduct normally, i.e., its operating state is normal. In other words, for the reference device, applying a low voltage, a turn-on voltage, and a low voltage sequentially will allow the reference device to conduct normally. That is, once a voltage is applied that enables the reference device to conduct normally, subsequent increases or decreases in voltage will not affect the normal conduction of the reference device.

[0091] Still Figure 3 As shown, Mark31 represents a semiconductor device under test (DUT), which is a defective semiconductor device. Applying a voltage VDD2 of 1.05V to the DUT results in an IDD2P current of 59mA, indicating that the DUT cannot conduct normally, i.e., its operating state is abnormal. Next, applying a voltage VDD2 of 1.1V results in an IDD2P current of 2mA, indicating that the DUT conducts normally, i.e., its operating state is normal. Finally, applying a voltage VDD2 of 1.05V again results in an IDD2P current of 2mA, indicating that the DUT still conducts normally, i.e., its operating state is normal. In other words, for the DUT, sequentially applying a low voltage, a conduction voltage, and a low voltage causes its operating state to change from abnormal to normal; even after continuing to apply a low voltage, the DUT's operating state remains normal. Performing a write-dial (WDR) test on the semiconductor device under test (DUT) allows us to rule out write / read (W / R) operation issues if the DUT passes the WDR test. Therefore, the inability of the DUT to power on at low voltages is determined to be due to a defect in the power supply circuit. Furthermore, once a turn-on voltage is applied to power on the DUT, subsequent increases or decreases in voltage do not affect its power-on state.

[0092] The inventors of this disclosure discovered that MOSFETs with the aforementioned Vt mismatch defect exhibit minimal leakage current, with only a slight difference in threshold voltage. Traditional detection methods are insufficient to accurately identify and locate MOSFETs with Vt mismatch defects in the circuit. Therefore, the inventors utilize the heating characteristics of a laser lens to create a dynamic high-low temperature environment with a temperature difference from room temperature. They compare the detection values ​​of the unit under test (DUT) at room temperature and under laser lens scanning to determine whether the DUT has a Vt mismatch defect.

[0093] It should be noted that a semiconductor device includes multiple units under test (DUTs), and each DUT includes multiple MOSFETs. Similarly, a semiconductor device under test (DUT) also includes multiple DUTs, and each DUT includes multiple MOSFETs. After determining the semiconductor DUT, the characteristics of the MOSFET can be changed by adjusting the substrate voltage of the MOSFET to determine the type of MOSFET, that is, to determine whether the MOSFET is an NMOS or a PMOS.

[0094] In some embodiments, each of the devices under test (DUTs) includes multiple MOSFETs, and before performing electrical testing on the DUTs of the semiconductor device under test, the testing method further includes:

[0095] A constant gate voltage is applied to the gate of the MOS transistor of the unit under test, and different source voltages are applied to the source of the MOS transistor of the unit under test.

[0096] If the difference between the gate voltage and the source voltage is greater than a preset voltage, the MOS transistor is turned on, and the MOS transistor is determined to be an NMOS transistor.

[0097] If the MOS transistor turns on when the difference between the gate voltage and the source voltage is less than a preset voltage, then the MOS transistor is determined to be a PMOS transistor.

[0098] Here, the characteristics of different types of MOSFETs are used to determine whether an NMOS transistor can conduct when the difference between the gate voltage and the source voltage is greater than the threshold voltage; and a PMOS transistor can conduct when the difference between the gate voltage and the source voltage is less than the threshold voltage.

[0099] The semiconductor device under test will be subjected to a second electrical test at the first and second temperatures respectively. Based on whether there is a difference in the test values ​​of the semiconductor device under test at the first and second temperatures, it can be quickly determined whether there is a Vt mismatch defect in the semiconductor device under test.

[0100] In some embodiments, before performing the first electrical detection on the unit under test, the detection method further includes:

[0101] A second electrical test is performed on the semiconductor device under test to obtain a fifth detection value of the semiconductor device under test at a first temperature and a sixth detection value at a second temperature; wherein the first temperature is lower than the second temperature;

[0102] The test cell in the semiconductor device under test is determined based on the fifth detection value, the sixth detection value, and the design layout of the semiconductor device under test.

[0103] Here, a second electrical test is performed on the semiconductor device under test at different temperatures, and the test cell in the semiconductor device under test is determined based on the electrical test results of the semiconductor device under test at different temperatures.

[0104] In a specific example, a second electrical test is performed on the semiconductor device under test (DUT), and the fifth and sixth test values ​​may include the IDD2P current. Here, the presence of a Vt mismatch defect in the semiconductor DUT can be determined by comparing the IDD2P current at different temperatures.

[0105] In a specific example, the first temperature can be room temperature, and the second temperature can be any temperature higher than room temperature.

[0106] refer to Figure 4 , Figure 4 A graph showing the relationship between current and detection time in the pre-charge power-off mode of a defective semiconductor device and a reference device provided in embodiments of this disclosure. (See figure.) Figure 4 As shown, defective semiconductor devices (such as...) were detected respectively. Figure 4 (shown by solid lines) and reference device (e.g.) Figure 4 The figure shows the IDD2P current at different temperatures (indicated by the dashed line). For the reference device, the fifth and sixth detection values ​​are essentially the same at both the first and second temperatures. For the defective semiconductor device, the fifth detection value at the first temperature is greater than the sixth detection value at the second temperature. In other words, the reference device's IDD2P current is essentially the same at room temperature (i.e., the first temperature) and at high temperature (i.e., the second temperature). Compared to the reference device, the defective semiconductor device exhibits an abnormally large IDD2P current at room temperature (i.e., the first temperature), while its IDD2P current returns to normal at high temperature (i.e., the second temperature). Therefore, the defective semiconductor device exhibits different IDD2P currents at high and room temperatures. More specifically, the defective semiconductor device shows an abnormally large IDD2P current at room temperature, while its IDD2P current returns to normal at high temperatures.

[0107] By performing second electrical tests on defective semiconductor devices at room temperature and high temperature, the inventors of this disclosure discovered that MOSFETs with the aforementioned Vt mismatch defect are temperature-sensitive. Specifically, during the second electrical test at room temperature, the IDD2P current exhibits an abnormal increase, while during the second electrical test at high temperature, the IDD2P current returns to normal. In other words, by comparing the IDD2P current of the semiconductor device under test at room temperature and high temperature, it is possible to quickly determine whether the semiconductor device under test has a Vt mismatch defect.

[0108] The inventors of this disclosure have also discovered that MOSFETs with Vt mismatch defects can be detected through electrical testing at high and room temperatures. However, how to detect MOSFETs with Vt mismatch defects in a semiconductor device composed of thousands of MOSFETs has become an urgent problem to be solved.

[0109] It should be noted that, due to the temperature sensitivity of semiconductor devices under test (DUTs) with Vt mismatch defects, second electrical testing at room temperature and high temperature will reveal that the IDD2P current of potentially defective DUT cells will be abnormally high at room temperature; however, the IDD2P current of these cells will return to normal at high temperature. Therefore, based on the results of the second electrical testing, potentially defective DUT cells can be identified, and suspected circuit blocks—i.e., potentially defective DUT cells—can be preliminarily identified in the design layout.

[0110] In this embodiment, a new defect detection method is provided by utilizing the temperature sensitivity of MOSFETs with Vt mismatch defects. MOSFETs with Vt mismatch defects can be detected using existing testing equipment, thus expanding the limitations of traditional testing equipment.

[0111] Here, in step S202, the unit under test is subjected to a first electrical test at room temperature and under laser lens scanning, that is, the unit under test is subjected to a first electrical test at room temperature and high temperature; in step S203, based on the results of the first electrical test of the unit under test at room temperature and high temperature, it is determined whether the unit under test has a defect.

[0112] In a specific example, a first electrical test is performed on the unit under test (DUT), and the first and second test values ​​may include the IDD2P current. Here, the presence of a Vt mismatch defect in the DUT can be determined by comparing the IDD2P current of the DUT at room temperature and high temperature.

[0113] In this embodiment of the present disclosure, by utilizing the heating characteristics of the laser lens and the temperature sensitivity of the defective unit under test, the presence of a defect in the unit under test can be quickly determined based on the first electrical test results of the unit under test at room temperature and high temperature, which can effectively save test time and improve test efficiency.

[0114] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0115] If the first detection value of the unit under test is substantially the same as the first preset detection value, then it is determined that the unit under test has no defects.

[0116] Here, the first and second detection values ​​of the test unit without defects are basically the same at room temperature and high temperature, respectively. That is, the first and second detection values ​​of the test unit without defects at room temperature and high temperature are determined as the first preset detection values.

[0117] Here, the unit under test is subjected to a first electrical test at room temperature to obtain a first detection value. The first detection value is compared with a first preset detection value. If the first detection value and the first preset detection value are substantially the same, it can be determined that the unit under test has no defects. Here, "substantially the same" means that the first detection value and the first preset detection value are the same, or the difference between the first detection value and the first preset detection value meets the error range.

[0118] In this embodiment of the disclosure, by performing a first electrical test on the unit under test at room temperature and comparing the obtained first detection value with a first preset detection value, it can be determined that the unit under test is free of defects. In other words, performing a first electrical test on the unit under test at room temperature is sufficient to determine that the unit under test is free of defects, which can effectively save testing time and improve testing efficiency.

[0119] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0120] If the first detection value of the unit under test is substantially the same as the first preset detection value, and the second detection value of the unit under test is substantially the same as the first preset detection value, then it is determined that the unit under test has no defects.

[0121] Here, the unit under test is subjected to a first electrical test at room temperature to obtain a first detection value. The first detection value is compared with a first preset detection value. If the first detection value is substantially the same as the first preset detection value, it can be determined that the unit under test has no defects. Further, the unit under test is subjected to a first electrical test at high temperature to obtain a second detection value. The second detection value is compared with the first preset detection value. If the second detection value is substantially the same as the first preset detection value, it can be further determined that the unit under test has no defects. Here, "substantially the same" means that the second detection value is the same as the first preset detection value or the difference between the second detection value and the first preset detection value meets the error range.

[0122] In this embodiment of the disclosure, by performing a first electrical test on the unit under test at room temperature and high temperature, and comparing the first detection value and the second detection value with the first preset detection value, it can be determined that the unit under test has no defects.

[0123] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0124] If the first detection value and the second detection value of the unit under test are substantially the same, then it is determined that the unit under test has no defects.

[0125] Here, a first electrical test is performed on the unit under test at room temperature to obtain a first detection value, and a second electrical test is performed on the unit under test at high temperature to obtain a second detection value. The first and second detection values ​​are compared. If the first and second detection values ​​are substantially the same, it can be determined that the unit under test has no defects. Here, "substantially the same" means that the first and second detection values ​​are the same or the difference between the first and second detection values ​​meets the error range.

[0126] In this embodiment of the disclosure, by performing a first electrical test on the unit under test at room temperature and high temperature, and comparing the first detection value and the second detection value, it can be determined that the unit under test has no defects. There is no need to obtain an additional first preset detection value, which can effectively save detection time and improve detection efficiency.

[0127] In some embodiments, a first electrical detection is performed on the unit under test to obtain a second detection value of the unit under test under the laser lens scanning, including:

[0128] If the first detection value of the unit under test is greater than the first preset detection value, then the unit under test is determined to be a suspected unit;

[0129] The suspected unit is scanned by a laser beam using the laser lens to obtain a second detection value for the suspected unit.

[0130] Here, a first electrical test is performed on the unit under test at room temperature to obtain a first detection value. This first detection value is compared with a first preset detection value. If the first detection value is greater than the first preset detection value, it indicates that the first detection value of the unit under test at room temperature is abnormally increased, thus confirming that the unit under test may have a defect. This potentially defective unit under test is identified as a suspected unit. Subsequently, the heating characteristics of the laser lens can be used to scan the suspected unit with a laser beam to obtain a second detection value of the suspected unit at a high temperature.

[0131] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0132] If the second detection value is substantially the same as the first preset detection value, then it is determined that the unit under test has a defect.

[0133] Here, the suspected unit is subjected to a first electrical test at high temperature to obtain a second test value. The second test value is compared with the first preset test value. If the second test value is basically the same as the first preset test value, it means that the second test value of the suspected unit at high temperature has turned into normal. Since the test unit with Vt mismatch defect is temperature sensitive, the heating characteristics of the laser lens and the temperature sensitivity of the test unit with Vt mismatch defect can be used to determine that the test unit has a defect.

[0134] In some embodiments, determining whether the unit under test has a defect based on the first detection value and the second detection value includes:

[0135] If the second detection value is less than the first detection value, then the unit under test is determined to have a defect.

[0136] Here, a first electrical test is performed on the unit under test at room temperature to obtain a first test value, and a second electrical test is performed on the unit under test at high temperature to obtain a second test value. The first test value and the second test value are compared. If the first test value is greater than the second test value, it can be determined that there is a defect in the unit under test.

[0137] In this embodiment of the disclosure, by performing a first electrical test on the unit under test at room temperature and high temperature, and comparing the first detection value and the second detection value, it can be determined that the unit under test has a defect. There is no need to obtain an additional first preset detection value, which can effectively save detection time and improve detection efficiency.

[0138] Furthermore, in some embodiments, if the first detection value of the unit under test is different from the first preset detection value, and the second detection value of the unit under test is also different from the first preset detection value, then the unit under test may have other defects that prevent it from working properly.

[0139] In this embodiment of the disclosure, the unit under test includes multiple MOS transistors. The heating characteristics of the laser lens will be used to magnify and scan the unit under test where the second detection value is greater than the first preset detection value under the laser lens, so as to quickly and accurately locate the MOS transistor with defects in the unit under test.

[0140] In some embodiments, each unit under test includes multiple MOSFETs, and if a defect is determined to exist in the unit under test, the detection method further includes:

[0141] A first electrical test is performed on each MOS transistor of the unit under test to obtain a third test value of the MOS transistor at room temperature and a fourth test value of the MOS transistor under the scanning of the laser lens;

[0142] Based on the third and fourth detection values, it is determined whether the MOS transistor has a defect.

[0143] Here, the unit under test is subjected to a first electrical test at different temperatures. Based on the results of the electrical test at different temperatures, it is determined whether the unit under test has any defects.

[0144] In a specific example, a first electrical detection is performed on the unit under test, and the third and fourth detection values ​​may include the IDD2P current.

[0145] In this embodiment, by utilizing the heating characteristics of the laser lens and the temperature sensitivity of the defective MOS transistor, the presence of a defect in the MOS transistor can be quickly determined based on the first electrical test results of the MOS transistor at room temperature and high temperature, which can effectively save detection time and improve detection efficiency.

[0146] In some embodiments, a first electrical detection is performed on the MOS transistor to obtain a fourth detection value of the MOS transistor under the scanning of the laser lens, including:

[0147] If the third detection value of the MOS transistor is greater than the second preset detection value, then the MOS transistor is determined to be a suspected MOS transistor;

[0148] The suspected MOS transistor is scanned by a laser beam using the laser lens to obtain a fourth detection value for the suspected MOS transistor.

[0149] Here, the third and fourth detection values ​​of the MOSFET without defects are basically the same at room temperature and high temperature, respectively. That is, the third and fourth detection values ​​of the MOSFET without defects at room temperature and high temperature are determined as the second preset detection values.

[0150] Here, a first electrical test is performed on the MOSFET at room temperature to obtain a third detection value. This third detection value is then compared with a second preset detection value. If the third detection value is greater than the second preset detection value, it indicates an abnormal increase in the third detection value of the MOSFET at room temperature, suggesting a possible defect in the MOSFET. This potentially defective MOSFET is then identified as a suspected MOSFET. Subsequently, the heating characteristics of a laser lens can be used to perform laser beam scanning on the suspected MOSFET to obtain a fourth detection value at high temperature.

[0151] In this embodiment of the disclosure, the first preset detection value may be the same as or different from the second preset detection value.

[0152] In some embodiments, determining whether the MOSFET has a defect based on the third detection value and the fourth detection value includes:

[0153] If the fourth detection value is basically the same as the second preset detection value, then it is determined that the MOS transistor has a defect.

[0154] Here, the suspected MOSFET is subjected to a first electrical test at high temperature to obtain a fourth test value. The fourth test value is compared with the second preset test value. If the fourth test value is basically the same as the second preset test value, it means that the fourth test value of the suspected MOSFET at high temperature has returned to normal. Since the MOSFET with Vt mismatch defect is temperature sensitive, the heating characteristics of the laser lens and the temperature sensitivity of the MOSFET with Vt mismatch defect can be used to determine that the MOSFET has a defect.

[0155] In some embodiments, determining whether the MOSFET has a defect based on the third detection value and the fourth detection value includes:

[0156] If the fourth detection value is less than the third detection value, then the MOS transistor is determined to have a defect.

[0157] Here, a first electrical test is performed on the MOSFET at room temperature to obtain a third test value, and a first electrical test is performed on the MOSFET at high temperature to obtain a fourth test value. The third test value and the fourth test value are compared. If the third test value is greater than the fourth test value, it can be determined that the MOSFET has a defect.

[0158] In this embodiment of the disclosure, by performing a first electrical test on the MOSFET at room temperature and high temperature, and comparing the obtained third and fourth test values, it can be determined that the MOSFET has a defect. The location of the defective MOSFET in the circuit can be dynamically located without the need to obtain an additional second preset test value, which can effectively save detection time and improve detection efficiency.

[0159] It should be noted that when using a laser lens with a testing equipment to prepare for testing, the semiconductor device under test (DUT) is placed within the field of view of the laser lens. The laser lens is used to scan the entire suspected circuit block; that is, the laser lens is used to scan the DUT that may have defects. The failure and pass status is reflected by observing the first electrical test results. When a certain area is scanned without using the laser lens, if the first detection value in the first electrical test results shows an abnormal increase (i.e., failure), the laser lens is used to scan that area. If the second detection value in the first electrical test results changes to normal (i.e., pass), the scan area can be gradually enlarged to gradually start scanning a specific MOSFET. If the fourth detection value in the first electrical test results returns to normal (i.e., pass), the location of the MOSFET with the Vt mismatch defect can be gradually identified. Using a laser lens can provide a dynamic high-temperature environment for the unit under test (DUT). That is, it can provide a high-temperature environment for the entire DUT or for a specific MOSFET within the DUT. Combined with the temperature sensitivity of MOSFETs with Vt mismatch defects, it is possible to quickly and accurately locate a specific MOSFET with Vt mismatch defects in a DUT containing hundreds or thousands of MOSFETs.

[0160] In some embodiments, after determining whether the unit under test has a defect based on the first detection value and the second detection value, the detection method further includes:

[0161] Circuit simulation is performed on the MOS transistor in the unit under test to obtain the threshold voltage of the MOS transistor in the unit under test;

[0162] Based on the threshold voltage of the MOS transistor in the unit under test, determine whether the MOS transistor has a defect.

[0163] Here, after locating the defective MOS transistor in a specific circuit using the above defect detection method, circuit simulation can be used to verify the accuracy of the detection results.

[0164] In some embodiments, the detection method further includes:

[0165] The defect detection result of the unit under test obtained based on the first detection value and the second detection value is compared with the defect detection result of the unit under test obtained based on the threshold voltage of the MOS transistor in the unit under test.

[0166] If the defect detection results are consistent, then output the defect detection results;

[0167] If the defect detection results are inconsistent, a re-inspection will be conducted.

[0168] Here, the results of the two defect detection methods for the MOSFET with defects are compared. If the defect detection results are consistent, it is more certain that the MOSFET has defects.

[0169] This disclosure also provides a defect detection device, the detection device comprising:

[0170] A laser detection module is used to provide a laser lens for scanning the unit under test; wherein, a plurality of the units under test constitute a semiconductor device under test; the semiconductor device under test is disposed within the field of view of the laser lens;

[0171] An electrical detection module is used to perform a first electrical detection on the unit under test at room temperature to obtain a first detection value; and to perform a first electrical detection on the unit under test under the scanning of the laser lens to obtain a second detection value;

[0172] The defect detection module is used to determine whether the unit under test has a defect based on the first detection value and the second detection value.

[0173] In this embodiment of the present disclosure, the electrical detection module is used to perform a first electrical test on the unit under test located in the field of view of the laser lens. The laser lens provided by the laser detection module scans the unit under test to form a dynamic high-temperature environment with a temperature difference from room temperature. The defect detection module analyzes the first detection value of the unit under test at room temperature and the second detection value at high temperature to determine whether there is a defect in the unit under test. This can effectively save detection time and improve detection efficiency.

[0174] In some embodiments, the defect detection module is specifically used to determine the unit under test as a suspected unit if the first detection value of the unit under test is greater than a first preset detection value;

[0175] The laser detection module is specifically used to perform laser beam scanning on the suspected unit;

[0176] The electrical detection module is specifically used to perform a first electrical detection on the suspected unit under laser beam scanning to obtain a second detection value.

[0177] In some embodiments, the defect detection module is specifically used to determine that the unit under test has a defect if the second detection value is substantially the same as the first preset detection value.

[0178] In some embodiments, the defect detection module is specifically used to determine that the unit under test has a defect if the second detection value is less than the first detection value.

[0179] In some embodiments, each unit under test includes multiple MOSFETs, and in the event of a defect in the unit under test...

[0180] The electrical detection module is specifically used to perform a first electrical detection on each MOS transistor of the unit under test at room temperature to obtain a third detection value; and is specifically used to perform a first electrical detection on each MOS transistor of the unit under test under the scanning of the laser lens to obtain a fourth detection value.

[0181] The defect detection module is specifically used to determine whether the MOS transistor has a defect based on the third detection value and the fourth detection value.

[0182] In some embodiments, the defect detection module is specifically used to determine that the MOS transistor is a suspected MOS transistor if the third detection value of the MOS transistor is greater than the second preset detection value;

[0183] The laser detection module is specifically used to perform laser beam scanning on the suspected MOS transistor;

[0184] The electrical detection module is specifically used to perform a first electrical detection on the suspected MOS transistor under laser beam scanning to obtain a fourth detection value.

[0185] In some embodiments, the defect detection module is specifically used to determine that the MOS transistor has a defect if the fourth detection value is substantially the same as the second preset detection value.

[0186] In some embodiments, the defect detection module is specifically used to determine that the MOS transistor has a defect if the fourth detection value is less than the third detection value.

[0187] In this embodiment of the disclosure, after determining that there is a defect in the unit under test, a laser detection module can be used to provide a high-temperature environment for the entire unit under test, or for a few MOS transistors in the unit under test, or even for a single MOS transistor in the unit under test. Combined with the temperature sensitivity of the MOS transistor with Vt mismatch defect, a MOS transistor with Vt mismatch defect can be quickly located in a unit under test that includes hundreds or thousands of MOS transistors.

[0188] In the embodiments of this disclosure, the components can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.

[0189] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0190] For software implementation, the techniques described herein can be achieved through modules (e.g., procedures, functions, etc.) that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented within the processor or externally.

[0191] This disclosure also provides a defect detection device, the detection device comprising:

[0192] Network interfaces are used to enable communication and connection between components;

[0193] Memory, used to store executable instructions;

[0194] The processor is used to execute executable instructions stored in the memory to implement the defect detection method described in the above technical solution.

[0195] This disclosure also provides a storage medium storing a computer program that, when executed by at least one processor, implements the defect detection method described in the above technical solution.

[0196] In this embodiment of the disclosure, the computer program may include computer program code, which may be in the form of source code, an executable file, or some intermediate form. In this embodiment of the disclosure, the storage medium may include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), and a random access memory (RAM), etc.

[0197] This disclosure provides a defect detection method, apparatus, device, and storage medium. The detection method includes: providing a semiconductor device under test (DUT), the DUT including a plurality of test units; placing the semiconductor DUT within the field of view of a laser lens; performing a first electrical test on the test units to obtain a first detection value of the test unit at room temperature and a second detection value of the test unit under laser lens scanning; and determining whether the test unit has a defect based on the first detection value and the second detection value. As can be seen from the above, the defect detection method provided by this disclosure performs a first electrical test on the test units placed within the field of view of a laser lens, utilizing the heating characteristics of the laser lens to create a dynamic high and low temperature environment with a temperature difference from room temperature. Thus, based on the first detection value of the test unit at room temperature and the second detection value of the test unit under laser lens scanning, it is possible to quickly determine whether there is a difference between the detection values ​​of the test unit at room temperature and under laser lens scanning, and thereby determine whether the test unit has a defect, effectively saving detection time and improving detection efficiency.

[0198] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0199] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A defect detection method, characterized in that, The detection method includes: A semiconductor device under test (DUT) is provided, the semiconductor DUT comprising a plurality of test cells; The semiconductor device under test is placed within the field of view of the laser lens, and a first electrical test is performed on the device under test to obtain a first detection value of the device under test at room temperature and a second detection value of the device under test under the scanning of the laser lens. Based on the first detection value and the second detection value, determine whether the unit under test has a defect; Wherein, the first detection value and the second detection value are the current of the pre-charge power-off mode; The first electrical detection of the unit under test (DUT) to obtain a second detection value of the DUT under the laser lens scanning includes: If the first detection value of the unit under test is greater than the first preset detection value, then the unit under test is determined to be a suspected unit; The suspected unit is scanned by a laser beam using the laser lens to obtain a second detection value for the suspected unit.

2. The defect detection method according to claim 1, characterized in that, The step of determining whether the unit under test has a defect based on the first detection value and the second detection value includes: If the second detection value is the same as the first preset detection value, then it is determined that the unit under test has a defect.

3. The defect detection method according to claim 1, characterized in that, The step of determining whether the unit under test has a defect based on the first detection value and the second detection value includes: If the second detection value is less than the first detection value, then the unit under test is determined to have a defect.

4. The defect detection method according to claim 1, characterized in that, Each of the units under test includes multiple MOSFETs. If a defect is determined in the unit under test, the detection method further includes: A first electrical test is performed on each MOS transistor of the unit under test to obtain a third test value of the MOS transistor at room temperature and a fourth test value of the MOS transistor under the scanning of the laser lens; Based on the third and fourth detection values, determine whether the MOS transistor has a defect; The third and fourth detection values ​​are the current in the pre-charge power-off mode.

5. The defect detection method according to claim 4, characterized in that, A first electrical test is performed on the MOS transistor to obtain a fourth detection value of the MOS transistor under the scanning of the laser lens, including: If the third detection value of the MOS transistor is greater than the second preset detection value, then the MOS transistor is determined to be a suspected MOS transistor; The suspected MOS transistor is scanned by a laser beam using the laser lens to obtain a fourth detection value for the suspected MOS transistor.

6. The defect detection method according to claim 5, characterized in that, The step of determining whether the MOSFET has a defect based on the third detection value and the fourth detection value includes: If the fourth detection value is the same as the second preset detection value, then it is determined that the MOS transistor has a defect.

7. The defect detection method according to claim 4, characterized in that, The step of determining whether the MOSFET has a defect based on the third detection value and the fourth detection value includes: If the fourth detection value is less than the third detection value, then the MOS transistor is determined to have a defect.

8. The defect detection method according to claim 1, characterized in that, Before performing the first electrical test on the unit under test, the detection method further includes: A second electrical test is performed on the semiconductor device under test to obtain a fifth detection value of the semiconductor device under test at a first temperature and a sixth detection value at a second temperature; wherein the first temperature is lower than the second temperature; Based on the fifth detection value, the sixth detection value, and the design layout of the semiconductor device under test, the cell under test in the semiconductor device under test is determined; The fifth and sixth detection values ​​are the currents in the pre-charge power-off mode.

9. The defect detection method according to claim 1, characterized in that, Before providing the semiconductor device under test, the detection method further includes: Provides multiple semiconductor devices; A low voltage and a higher turn-on voltage are sequentially applied to the semiconductor device; If the semiconductor device operates differently under the low voltage and the turn-on voltage, then the semiconductor device is determined to be a semiconductor device under test.

10. A defect detection device, characterized in that, The detection device includes: A laser detection module is used to provide a laser lens for scanning the unit under test; wherein, a plurality of the units under test constitute a semiconductor device under test; the semiconductor device under test is disposed within the field of view of the laser lens; An electrical detection module is used to perform a first electrical detection on the unit under test at room temperature to obtain a first detection value; and to perform a first electrical detection on the unit under test under the scanning of the laser lens to obtain a second detection value; The defect detection module is used to determine whether the unit under test has a defect based on the first detection value and the second detection value. Wherein, the first detection value and the second detection value are the current of the pre-charge power-off mode; Specifically, the defect detection module is used to determine the unit under test as a suspected unit if the first detection value of the unit under test is greater than the first preset detection value. The laser detection module is specifically used to perform laser beam scanning on the suspected unit; The electrical detection module is specifically used to perform a first electrical detection on the suspected unit under laser beam scanning to obtain a second detection value.

11. The defect detection device according to claim 10, characterized in that, The defect detection module is specifically used to determine that the unit under test has a defect if the second detection value is the same as the first preset detection value.

12. The defect detection device according to claim 10, characterized in that, The defect detection module is specifically used to determine that the unit under test has a defect if the second detection value is less than the first detection value.

13. The defect detection device according to claim 10, characterized in that, Each of the units under test includes multiple MOSFETs. If a defect is determined in the unit under test... The electrical detection module is specifically used to perform a first electrical detection on each MOS transistor of the unit under test at room temperature to obtain a third detection value; and is specifically used to perform a first electrical detection on each MOS transistor of the unit under test under the scanning of the laser lens to obtain a fourth detection value; The defect detection module is specifically used to determine whether the MOS transistor has a defect based on the third detection value and the fourth detection value; The third and fourth detection values ​​are the current in the pre-charge power-off mode.

14. The defect detection device according to claim 13, characterized in that, The defect detection module is specifically used to determine that the MOS transistor is a suspected MOS transistor if the third detection value of the MOS transistor is greater than the second preset detection value; The laser detection module is specifically used to perform laser beam scanning on the suspected MOS transistor; The electrical detection module is specifically used to perform a first electrical detection on the suspected MOS transistor under laser beam scanning to obtain a fourth detection value.

15. The defect detection device according to claim 14, characterized in that, The defect detection module is specifically used to determine that the MOS transistor has a defect if the fourth detection value is the same as the second preset detection value.

16. The defect detection device according to claim 13, characterized in that, The defect detection module is specifically used to determine that the MOS transistor has a defect if the fourth detection value is less than the third detection value.

17. A defect detection device, characterized in that, The detection equipment includes: Network interfaces are used to enable communication and connection between components; Memory, used to store executable instructions; A processor is configured to execute executable instructions stored in the memory to implement the defect detection method according to any one of claims 1 to 9.

18. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by at least one processor, implements the defect detection method according to any one of claims 1 to 9.

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