Methods and equipment for measuring the resistance of contact nodes on bit lines

Abstract

This disclosure provides a method and apparatus for measuring the bit line contact node resistance. The method includes: measuring a first resistance of a DRAM bit line; measuring a second resistance of a first path when a first transistor connected to the bit line is in a conducting state, the first path including: a node contact of the first transistor, a word line channel, a bit line contact node, and a read / write bit line; measuring a third resistance of a second path when two adjacent transistors connected to the bit line are in a conducting state, the second path including: a word line channel and a node contact of the two adjacent transistors; and determining the bit line contact node resistance based on the first, second, and third resistances. This disclosure determines the bit line contact node resistance by performing multiple measurements to determine the first to third resistances respectively. The bit line contact node resistance is equivalent to being obtained from solving multiple equations, eliminating bit line resistance and channel resistance, thus improving the accuracy of the bit line contact node resistance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for measuring the resistance of bit line contact nodes. Background Technology

[0002] DRAM (Dynamic Random Access Memory) is a type of internal memory that includes at least one memory array, each array comprising M rows and N columns of memory cells. Each memory cell includes a storage capacitor and a transistor. The transistor controls reading and writing to the storage capacitor, which stores charge to represent one bit of data. Memory cells are connected to bit lines via BLC (bit line contact) nodes to enable reading and writing. Excessive resistance at the bit line contact node can negatively impact read / write efficiency; therefore, the bit line contact node resistance can be measured to determine its effect on read / write efficiency.

[0003] In the prior art, the bit line contact node resistance can be measured in two ways. In the first way, a set of voltages and currents are measured at the BLC, and the resistance is calculated based on the voltages and currents to serve as the measured bit line contact node resistance.

[0004] However, the above two methods have poor accuracy in measuring the resistance of the bit line contact node. Summary of the Invention

[0005] This disclosure provides a method and apparatus for measuring the resistance of bit line contact nodes, thereby improving the measurement accuracy of bit line contact node resistance.

[0006] In a first aspect, embodiments of this disclosure provide a method for measuring the resistance of a bit line contact node, the method comprising:

[0007] Measure the first resistance of the DRAM upper bit line;

[0008] When the first transistor connected to the bit line is in the on state, the second resistance of the first path is measured. The first path includes, in sequence: the node contact of the first transistor, the word channel of the first transistor, the bit line contact node of the first transistor, and the read / write bit line of the first transistor.

[0009] With the two adjacent transistors connected by the bit line in the on state, the third resistance of the second path is measured. The second path includes: the word line channel of the two adjacent transistors and the node contact of the two adjacent transistors.

[0010] The bit line contact node resistance is determined based on the first resistor, the second resistor, and the third resistor.

[0011] In some embodiments, measuring the second resistance of the first path when the first transistor connected to the bit line is in the on state includes:

[0012] A first voltage is applied to the word line of the first transistor to control the first transistor to be in the on state; the first transistor is an NMOS, and the first voltage is greater than or equal to the on voltage of the NMOS;

[0013] The second resistance is measured for the first path.

[0014] In some embodiments, the first transistor and the second transistor are located in the same active region, and before measuring the second resistance of the first path, the method further includes:

[0015] A second voltage is applied to the word line of the second transistor to control the second transistor to be in the off state; the second transistor is an NMOS, and the second voltage is less than or equal to the off voltage of the NMOS.

[0016] In some embodiments, the method further includes:

[0017] A third voltage is applied to the substrate of the active region, the third voltage being less than the first voltage.

[0018] In some embodiments, measuring the second resistance of the first path includes:

[0019] With a constant fourth current supplied to the first path, the voltage difference across the first path is measured and taken as the fourth voltage.

[0020] The second resistor is determined based on the fourth voltage and the fourth current.

[0021] In some embodiments, the third resistance of the second path measurement includes:

[0022] The first voltage is applied to the word line of two adjacent transistors in the same active region to control both adjacent transistors to be in the on state;

[0023] The third resistance is measured for the second path.

[0024] In some embodiments, before measuring the third resistance on the second path, the method further includes:

[0025] The third voltage is applied to the substrate of the active region, the third voltage being less than the first voltage of the two adjacent transistors.

[0026] In some embodiments, the two ends of the second path are the node contacts of the two adjacent transistors, and measuring the third resistance of the second path includes:

[0027] When a constant fifth current is supplied to the second path, the voltage difference across the second path is measured as the fifth voltage, and the fifth current is the same as the fourth current.

[0028] The third resistor is determined based on the fifth voltage and the fifth current.

[0029] In some implementations, measuring the first resistance of the DRAM upper bit line includes:

[0030] Determine the two test contact points of the bit line;

[0031] The first resistance is measured with the transistor located between the two test contacts and connected to the bit line in the off state.

[0032] In some embodiments, measuring the first resistance includes:

[0033] With a constant sixth current supplied to the bit line, the voltage difference between the two test contact points is measured as the sixth voltage, which is the same as the fourth current.

[0034] The first resistor is determined based on the sixth voltage and the sixth current.

[0035] In some implementations, the two test contact points are located at both ends of the bit line.

[0036] In some embodiments, determining the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor includes:

[0037] Measure the distance between the two test contact points;

[0038] Measure the length of the read / write bit line;

[0039] The fourth resistance of the read / write bit line is determined based on the ratio of the distance to the length and the first resistance.

[0040] The bit line contact node resistance is determined based on the fourth resistor, the second resistor, and the third resistor.

[0041] In some implementations, the bit line contact node resistance is calculated using the following formula:

[0042]

[0043] Wherein, Rblc is the bit line contact node resistance, R2 is the second resistance, R3 is the third resistance, and R4 is the fourth resistance.

[0044] Secondly, embodiments of this disclosure provide a measuring device for the resistance of bit line contact nodes, comprising:

[0045] The first resistance measurement module is used to measure the first resistance of the DRAM upper bit line;

[0046] The second resistance measurement module is used to measure the second resistance of the first path when the first transistor connected to the bit line is in the on state. The first path includes, in sequence: the node contact of the first transistor, the word channel of the first transistor, the bit line contact node of the first transistor, and the bit line for reading and writing the first transistor.

[0047] The third resistance measurement module is used to measure the third resistance of the second path when the two adjacent transistors connected by the bit line are in the on state. The second path includes: the word line channel of the two adjacent transistors and the node contact of the two adjacent transistors.

[0048] The bit line contact node resistance determination module is used to determine the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor.

[0049] In some embodiments, the second resistance measurement module is further used for:

[0050] A first voltage is applied to the word line of the first transistor to control the first transistor to be in the on state; the first transistor is an NMOS, and the first voltage is greater than or equal to the on voltage of the NMOS;

[0051] The second resistance is measured for the first path.

[0052] In some embodiments, the first transistor and the second transistor are located in the same active region, and the device further includes:

[0053] The second voltage application module is configured to apply a second voltage to the word line of the second transistor before measuring the second resistance of the first path, so as to control the second transistor to be in a cutoff state; the second transistor is an NMOS, and the second voltage is less than or equal to the cutoff voltage of the NMOS.

[0054] In some embodiments, the apparatus further includes:

[0055] A first substrate pressurization module is used to apply a third voltage to the substrate of the active region, the third voltage being less than the first voltage.

[0056] In some embodiments, the second resistance measurement module is further used for:

[0057] With a constant fourth current supplied to the first path, the voltage difference across the first path is measured and taken as the fourth voltage.

[0058] The second resistor is determined based on the fourth voltage and the fourth current.

[0059] In some embodiments, the third resistance measurement module is further used for:

[0060] The first voltage is applied to the word line of two adjacent transistors in the same active region to control both adjacent transistors to be in the on state;

[0061] The third resistance is measured for the second path.

[0062] In some embodiments, the apparatus further includes:

[0063] A second substrate pressure module is configured to apply a third voltage to the substrate of the active region before measuring the third resistance of the second path, the third voltage being less than the first voltage of the two adjacent transistors.

[0064] In some embodiments, the two ends of the second path are the node contacts of the two adjacent transistors, and the third resistance measurement module is further used for:

[0065] When a constant fifth current is supplied to the second path, the voltage difference across the second path is measured as the fifth voltage, and the fifth current is the same as the fourth current.

[0066] The third resistor is determined based on the fifth voltage and the fifth current.

[0067] In some implementations, the first resistance measurement module is further used for:

[0068] When measuring the first resistance of the DRAM bit line, determine the two test contact points of the bit line;

[0069] The first resistance is measured with the transistor located between the two test contacts and connected to the bit line in the off state.

[0070] In some implementations, the first resistance measurement module is also used for:

[0071] With a constant sixth current supplied to the bit line, the voltage difference between the two test contact points is measured as the sixth voltage, which is the same as the fourth current.

[0072] The first resistor is determined based on the sixth voltage and the sixth current.

[0073] In some implementations, the two test contact points are located at both ends of the bit line.

[0074] In some embodiments, the bit line contact node resistance determination module is further used for:

[0075] When determining the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor, the distance between the two test contact points is measured;

[0076] Measure the length of the read / write bit line;

[0077] The fourth resistance of the read / write bit line is determined based on the ratio of the distance to the length and the first resistance.

[0078] The bit line contact node resistance is determined based on the fourth resistor, the second resistor, and the third resistor.

[0079] In some implementations, the bit line contact node resistance is calculated using the following formula:

[0080]

[0081] Wherein, Rblc is the bit line contact node resistance, R2 is the second resistance, R3 is the third resistance, and R4 is the fourth resistance.

[0082] Thirdly, embodiments of this disclosure also provide an electronic device, including: at least one processor and a memory;

[0083] The memory stores computer-executed instructions;

[0084] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to implement the method described in the first aspect.

[0085] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method described in the first aspect.

[0086] Fifthly, embodiments of this disclosure also provide a computer program product for performing the method described in the first aspect.

[0087] The bit line contact node resistance measurement method and device provided in this disclosure can determine the first resistance, the second resistance and the third resistance by taking multiple measurements, so as to solve for the bit line contact node resistance. The bit line contact node resistance is equivalent to being obtained from solving multiple equations, eliminating bit line resistance and channel resistance, and improving the accuracy of bit line contact node resistance. Attached Figure Description

[0088] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0089] Figure 1 This is a top view of a DRAM structure provided in an embodiment of this disclosure;

[0090] Figure 2 This is a side view of a DRAM structure provided in an embodiment of this disclosure;

[0091] Figure 3 This is a flowchart illustrating the steps of a method for measuring the resistance of a bit line contact node according to an embodiment of this disclosure;

[0092] Figure 4 This is a schematic diagram of a first pathway on an active region provided in an embodiment of this disclosure;

[0093] Figure 5 This is a schematic diagram of a second path on a DRAM provided in an embodiment of this disclosure;

[0094] Figure 6 This is a schematic diagram of the structure of a bit line contact node resistance measuring device provided in an embodiment of this disclosure;

[0095] Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of this disclosure.

[0096] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0097] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure as detailed in the appended claims.

[0098] This disclosure embodiment can be used to test the bit line contact node resistance on DRAM, where the bit line contact node resistance is the resistance of the bit line contact node. Figure 1 This is a top view of a DRAM structure provided in an embodiment of this disclosure. Figure 1 The distribution of bit line contact nodes in the DRAM can be seen. (Refer to...) Figure 1 As shown, the DRAM has multiple body contacts 100, which can be distributed around the perimeter. Multiple elliptical active areas (AA) 101 are disposed between the body contacts 100. Each active area 101 can be provided with at least two node contacts (NC) 104 and bit line contact nodes 105 located between the node contacts 104. Figure 1 The position of the main body 100 can be adjusted so that the position of the main body 100 from the node contact 104 is the same or basically the same.

[0099] The DRAM also includes multiple horizontal word lines (WL) 102 and multiple vertical bit lines (BL) 103. Each word line 102 can connect to multiple active regions 101, and the word line 102 is used to control the access of the bit line 103 to the active region 101. Each bit line 103 is connected to the bit line contact nodes 105 of multiple active regions 101, so that the bit line 103 can access the active region 101.

[0100] based on Figure 1 The top view shown, Figure 2 This is a side view of a DRAM structure provided in an embodiment of this disclosure. Figure 2 A side view of the two active regions 101 is shown, with shallow trench isolation (STI) 107 separating them. (See reference...) Figure 2 As shown, the main body 100, bit line contact node 105, and transistor substrate 106 form a path 108. The main body 100 can be set to 0 voltage, and a set of voltage and current measurements can be taken at the bit line contact node 105. Therefore, the resistance can be calculated from this voltage and current as the bit line contact node resistance. Figure 2 As can be seen, since the path 108 includes bit line contact node 105, body 100, substrate 106 and PN junction (between P-type substrate 106 and N), the calculated resistance includes not only the actual bit line contact node resistance, but also the body resistance, substrate resistance and PN junction resistance.

[0101] In summary, the bit line contact node resistances obtained by the two measurement methods described above are both too high and have low accuracy. The transistors mentioned above can be any type of transistor, such as NMOS (negative channel metal-oxide-semiconductor field-effect transistor).

[0102] To address the aforementioned issues, embodiments of this disclosure can determine the bit line contact node resistance by performing multiple measurements to separately determine the resistance of the bit line 103 (referred to as the first resistance), the resistance of the first path (referred to as the second resistance), and the resistance of the second path (referred to as the third resistance). The first path is formed by the node contact 104, the word channel of the first transistor, the bit line contact node 105, and the bit line 103. The second path is formed by the word channel and the node contact 104. Therefore, the bit line contact node resistance determined by embodiments of this disclosure is equivalent to that obtained from solving multiple equations, excluding the bit line resistance and channel resistance, and only including the actual bit line contact node resistance, thus improving the accuracy of the bit line contact node resistance. Figure 2 The contact resistance of N can be considered as part of the contact node resistance of the bit line.

[0103] Figure 3 This is a flowchart illustrating the steps of a method for measuring the resistance of a bit line contact node according to an embodiment of this disclosure. Please refer to... Figure 3 As shown, the method for measuring the resistance of the bit line contact node includes S201 to S204.

[0104] S201: Measure the first resistance of the DRAM upper line.

[0105] Here, the bit line can be any bit line on the DRAM, and the first resistance of the bit line can be the resistance between its two ends. There are two ways to measure the first resistance.

[0106] In the first measurement method, an equivalent bit line is fabricated that is identical to the DRAM upper bit line, but this equivalent bit line is not connected to any other structures such as bit line contact nodes. Therefore, the resistivity of this equivalent bit line is exactly the same as that of the DRAM upper bit line, and its resistance can represent the first resistance of the bit line. In this scenario, the resistance of this equivalent bit line can be measured as the first resistance without the influence of other structures.

[0107] Specifically, current can be supplied to the equivalent potential line to measure the voltage difference across the two ends, so the resistance is the ratio of the voltage difference across the two ends to the current.

[0108] In the second measurement method, the first resistance of the bit line on the DRAM can be tested to obtain the first resistance, which is the ratio between the voltage difference and the current across the bit line on the DRAM.

[0109] However, in the second measurement method described above, the connection between the bit line and the transistor on the DRAM may cause measurement inaccuracies. To improve accuracy, embodiments of this disclosure can control the transistor to be in a cutoff state to prevent current from passing through the transistor. In this way, the current only passes through the bit line, ensuring that both the current and voltage difference are relative to the bit line, thereby improving the accuracy of the first resistor.

[0110] Specifically, first, two test contact points of the bit line can be identified; then, with the transistor connected to the bit line and located between the two test contact points in the off state, the first resistance is measured. The state of the transistor can be controlled by WL. The transistor is an NMOS, and the word line can control the NMOS to be in the conducting state via a high-level signal. Correspondingly, WL can also control the NMOS to be in the off state via a low-level signal. Furthermore, no arbitrary voltage can be applied to the NMOS to make it float, in which case no current will pass through the NMOS, thus preventing current leakage into the NMOS when measuring the first resistance.

[0111] The test contact points can be located at any two positions on the bit line. When the two test contact points are at both ends of the bit line, the first resistance being tested is the resistance of the entire bit line. When the two test contact points are at the two middle positions of the bit line, the first resistance being tested is the resistance of a portion of the bit line. The resistance of the entire bit line and the resistance of a portion of the bit line can be converted based on length; the resistance of a portion of the bit line can be the resistance of the entire bit line multiplied by the ratio of the length of the portion of the bit line to the length of the entire bit line.

[0112] It should be noted that, compared to having the two test contact points located in the middle of the bit line, having the two test contact points located at both ends of the bit line allows for testing the average resistance of the entire bit line as much as possible. This avoids the poor accuracy of the first resistance due to the uniform resistance distribution of the bit line, and helps to further improve the accuracy of the BLC resistor.

[0113] Understandably, because of the first resistance between the two test contacts we are testing, we only need to ensure that the transistor between the test contacts is in the off state, and we do not need to pay attention to the state between the other transistors.

[0114] Similar to the aforementioned method for testing the resistance of the equivalent bit line, in this embodiment of the disclosure, when testing the first resistance of the DRAM upper bit line, the voltage difference between the two test contact points can be measured as the sixth voltage while providing a constant sixth current to the bit line. Therefore, the first resistance can be determined based on the sixth voltage and the sixth current; that is, the ratio of the sixth voltage to the sixth current is determined as the first resistance.

[0115] In the traditional process of applying the sixth voltage to test the sixth current, due to the different structures of different paths, it is impossible to guarantee that the bit line works under the same voltage division condition in different paths, resulting in poor accuracy of the calculated BLC resistor.

[0116] In this embodiment, a sixth voltage is measured when a sixth current is applied. When the sixth current on the bit line is the same as the fourth current in the first path, it can be ensured that the bit line here and the bit line in the first path operate under the same voltage division condition, which helps to improve the accuracy of the BLC resistor.

[0117] S202: When the first transistor connected to the bit line is in the on state, measure the second resistance of the first path, which includes, in sequence: the node contact of the first transistor, the word channel of the first transistor, the bit line contact node of the first transistor, and the read / write bit line of the first transistor.

[0118] The first transistor is any one of the plurality of transistors connected to bit line 103. Figure 4 This is a schematic diagram of a first pathway on an active region provided in an embodiment of this disclosure. (Refer to...) Figure 4 As shown, the first path 109 includes: the node contact 104 of the first transistor 110, the word channel of the first transistor 110, the bit line contact node 105 of the first transistor 110, and the read / write bit line of the first transistor 110 (that is, a part of the bit line 103).

[0119] Specifically, a first voltage can be applied to the word line 102 of the first transistor 110 to control the first transistor 110 to be in a conducting state, so that the word line 102 of the first transistor 110 generates channel current, that is, current can flow through it. Figure 4 The first path 109 is shown. The first transistor is an NMOS, and the first voltage is greater than or equal to the NMOS's turn-on voltage. Then, the second resistance can be measured on the first path 109. When the word line 102 is a thick oxide layer, the NMOS's turn-on voltage can be 3V, and the thick oxide layer can be, for example, an oxide layer larger than 5nm.

[0120] from Figure 4As can be seen, the read / write bit line of the first transistor 110 includes a first end 1031 and a second end 1032. The first end 1031 is connected to the bit line contact node 105 of the first transistor 110. The two ends of the first path 109 are the node contact 104 of the first transistor 110 and the second end 1032 of the read / write bit line, respectively. Therefore, the second resistance can be determined based on the voltage difference across the first path 109 and the current in the first path. The fourth current can be from... Figure 4 The direction indicated by the middle arrow or the opposite direction.

[0121] In some implementations, while providing a constant fourth current to the first path, the voltage difference across the first path can be measured as the fourth voltage, and a second resistance can be determined based on the fourth voltage and the fourth current, wherein the second resistance is the ratio between the fourth voltage and the fourth current, and the fourth current is the same as the sixth current.

[0122] In the traditional process of applying a fourth voltage to test a fourth current, due to the different structures of different paths, it is impossible to guarantee that the components in the first path and the same components and bit lines in the second path are working under the same voltage division conditions, resulting in poor accuracy of the calculated BLC resistor.

[0123] In this embodiment, a fourth voltage is measured when a fourth current is applied. When the fourth current in the first path and the sixth current in the bit line are the same, it ensures that each component in the first path operates under the same voltage division condition as the same component in the other paths, which helps improve the accuracy of the BLC resistor. For example, the bit line in the first path operates under the same voltage division condition when measuring the first resistance, the NC in the first path and the NC in the second path operate under the same voltage division condition, and the word line channel in the first path and the word line channel in the second path operate under the same voltage division condition. The fourth current can be the operating current range of the transistor after it is turned on, for example, -10uA (microamps) to 10uA, thus obtaining multiple sets of fourth voltages and fourth currents through multiple measurements. One set can be selected to calculate the second resistance, or the resistance can be calculated separately for each set of fourth voltages and fourth currents, with the average resistance used as the second resistance. When the fourth voltage is greater than the first voltage, the fourth current can smoothly flow from the second terminal of the first path 109, along the drain and source of the first transistor, to the first terminal of the first path 109, further improving the success rate and accuracy of the second resistance measurement. It should be noted that the active region containing the first transistor may contain only the first transistor, or it may also contain a second transistor. When the same active region includes both the first and second transistors, the second transistor is any transistor other than the first transistor in that active region. In this case, the second transistor in the active region may affect the measurement of the first path. For example, if the second transistor is turned on, some current may leak into the second transistor, making the measured fourth current inaccurate, which in turn leads to poor accuracy of the second resistor and the BLC resistor.

[0124] To improve the accuracy of the BLC resistor measurement, a second voltage can be applied to the word line of the second transistor before measuring the second resistance in the first path to control the second transistor to be in the off state. The second transistor is an NMOS transistor, and the second voltage is less than or equal to the NMOS cutoff voltage. Alternatively, no voltage can be applied to the second transistor to make it float; in this case, no current will pass through the second transistor, preventing current leakage into the second transistor when measuring the second resistance.

[0125] In this design, the cutoff voltage of the NMOS can be 0V, and the smaller the second voltage applied to the word line of the second transistor, the more completely the NMOS is cut off, preventing leakage current. Therefore, to ensure the NMOS is as completely cut off as possible, the second voltage can be less than 0V, for example, -0.2V.

[0126] As can be seen, the embodiments of this disclosure can use the second voltage to keep the second transistor in a completely off state as much as possible, so as to avoid leakage current in the second transistor as much as possible, which helps to improve the accuracy of the fourth current, and thus improve the accuracy of the second resistor and the BLC resistor.

[0127] In some embodiments, a third voltage, lower than the first voltage, can be applied to the substrate of the active region. For example, the third voltage can be -0.7V. This avoids leakage current in the substrate, helps to further improve the accuracy of the fourth current, and thus improves the accuracy of the second resistor and the BLC resistor.

[0128] S203: When two adjacent transistors connected by a bit line are in the on state, measure the third resistance of the second path, which includes: the word line channel of the two adjacent transistors and the node contact of the two adjacent transistors.

[0129] Figure 5 This is a schematic diagram of a second path on a DRAM provided in an embodiment of this disclosure. (Refer to...) Figure 5 As shown, the second path 111 is formed by the word line channels of two adjacent transistors 112 and 113, the node contact 104, and the PN structure.

[0130] In some embodiments, when there is shallow trench isolation 107 between different active regions, the two transistors in different active regions cannot be connected. Therefore, in this embodiment of the present disclosure, a first voltage can be applied to the word line of two adjacent transistors in the same active region, thereby controlling both adjacent transistors to be in the on state to measure the third resistance of the second path 111. This first voltage is the same as the first voltage of the first transistor mentioned above, and will not be described again here.

[0131] from Figure 5 It can be seen that the two ends of the second path 111 are the node contacts 104 of two adjacent transistors 112 and 113, respectively. Therefore, the third resistance can be determined based on the voltage difference between the two ends of the second path 111 and the current in the second path 111. Optionally, with a constant fifth current supplied to the second path 111, the voltage difference across the second path 111 can be measured as the fifth voltage; then, the third resistance can be determined based on the fifth voltage and the fifth current, where the third resistance can be the ratio of the fifth voltage to the fifth current. The fifth current can be from, for example... Figure 5 The direction indicated by the middle arrow or the opposite direction.

[0132] Similarly, in the traditional process of applying the fifth voltage to test the fifth current, due to the different structures of different paths, it is impossible to guarantee that the components in the second path and the same component in the first path are working under the same voltage division conditions, resulting in poor accuracy of the calculated BLC resistor.

[0133] In this embodiment, a fifth voltage is measured when a fifth current is applied. When the fifth current in the second path is the same as the fourth current in the first path, the components in the second path and the same components in the first path operate under the same voltage division condition, which helps improve the accuracy of the BLC resistor. For example, the NC operates under the same voltage division condition in both the first and second paths, and the word line channel operates under the same voltage division condition in both the first and second paths.

[0134] The fifth current can be the operating current range of the transistor after it is turned on, for example, from -10uA (microamps) to 10uA. This allows for multiple sets of fifth voltages and fifth currents to be measured. One set can be selected to calculate the third resistance, or the resistance can be calculated separately for each of these multiple sets of fifth voltages and fifth currents, with the average resistance used as the third resistance.

[0135] In some embodiments, a third voltage, less than the first voltage between two adjacent transistors, can be applied to the substrate of the active region before measuring the third resistance of the second path. This avoids leakage current in the substrate, helps improve the accuracy of the fifth voltage and fifth current, and consequently improves the accuracy of the third resistance and the BLC resistance. The third voltage here is the same as the previously mentioned third voltage and will not be repeated here.

[0136] S204: Determine the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor.

[0137] As can be seen from the foregoing description, the first resistor is the resistance of the bit line, the second resistor is the resistance of the first path, and the third resistor is the resistance of the second path. Figure 4 As shown in the first path 109, it includes: the node contact 104 of the first transistor 110, the word channel of the first transistor 110, the bit line contact node 105 of the first transistor 110, and read / write bit lines with terminals 1031 and 1032 respectively. Therefore, the relationship between the second resistor R2 and the node contact resistor Rnc, the word channel resistor Rch, the bit line contact node resistor Rblc, and the fourth resistor R4 of the read / write bit line is as follows:

[0138] R2=Rnc+Rch+Rblc+R4 (1)

[0139] from Figure 5 As shown in the second path 111, it includes the node contacts 104 of the two transistors 112 and 113 and the word channel of the two transistors 112 and 113. Therefore, the relationship between the third resistor R3, the node contact resistance Rnc, and the word channel resistance Rch is as follows:

[0140] R3=2×Rnc+2×Rch (2)

[0141] The read / write bit line resistor R4 can be determined based on the first resistor of the aforementioned bit line.

[0142] When the length of the equivalent resistance used for testing the first resistor is the same as the length of the read / write bit line, or when the distance between the two test contact points of the bit line during measurement is the same as the length of the read / write bit line, the measured first resistor R1 is also the read / write bit line resistor R4.

[0143] Therefore, the bit line contact node resistance Rblc can be obtained by solving the relationship between the aforementioned formulas (1) and (2), as follows:

[0144]

[0145] As can be seen, in this embodiment of the present disclosure, when measuring the first resistance, the BLC of the first transistor and the second end of the read / write bit line can be used as two test contact points to test the first resistance, which is also the fourth resistance of the read / write bit line. Therefore, it is not necessary to determine the fourth resistance based on the length ratio and the first resistance, which helps to further reduce the computational complexity of the bit line contact node resistance.

[0146] When the distance between the two test contact points of the bit line differs from the length of the read / write bit line, it is necessary to measure the distance L1 between the two test contact points and the length L2 of the read / write bit line to determine the fourth resistance R4 of the read / write bit line. Considering the resistivity formula: Resistance R = Resistivity ρ × Length L / Cross-sectional area S, in a scenario where the bit lines are uniformly distributed (i.e., both the resistivity ρ and the cross-sectional area S are fixed), the resistance of the bit line is directly proportional to its length L. Therefore, the relationship between the fourth resistance R4 and the first resistance R1 is as follows:

[0147] R4=R1×L2 / L1 (4)

[0148] Similarly, when the length of the equivalent resistance used to measure the first resistance is different from the length of the read / write bit line, it is also necessary to measure the length of the equivalent resistance as L1, so that the fourth resistance R4 of the read / write bit line can be calculated by the above formula (3).

[0149] After determining the fourth resistor, the bit line contact node resistance can be determined based on the fourth resistor, the second resistor, and the third resistor. That is, the bit line contact node resistance Rblc can be solved according to formulas (1), (2), and (4).

[0150] As can be seen, in this embodiment of the present disclosure, R4 can also be determined by L1, L2 and R1, so that the fourth resistor can be calculated even when L1 and L2 are different.

[0151] In some implementations, the bit line contact node resistance can be calculated using the following formula:

[0152]

[0153] Where Rblc is the bit line contact node resistance, R2 is the second resistance of the first path, R3 is the third resistance of the second path, and R4 is the fourth resistance of the read / write bit line.

[0154] It can be seen that when L1 equals L2, the above formula (5) is also formula (3).

[0155] As can be seen from formula (5), the bit line contact node resistance Rblc can be obtained by simple calculation between R1, R2 and R3 and L1 and L2 in this embodiment of the present disclosure, with low computational complexity.

[0156] In some implementations, the DRAM can be processed before performing the measurements in S201 to S204 above to expose the polysilicon gate (PG) layer of the DRAM. This allows for more accurate determination of the positions of the NC, BLC, and the main body, leading to better identification of the second and third paths, avoiding abnormal path selection, and further improving the accuracy of the bit line contact node resistance.

[0157] In some implementations, it is also necessary to verify the functionality of the NC pin before testing. A brightening of the NC pin indicates it is functioning correctly. This ensures proper electrical conductivity on the NC, facilitating successful testing.

[0158] Corresponding to the above method embodiments, Figure 6 This is a schematic diagram of the structure of a bit line contact node resistance measuring device provided in an embodiment of this disclosure. Please refer to... Figure 6 The aforementioned measuring device 300 for the resistance of the bit line contact node includes:

[0159] The first resistance measurement module 301 is used to measure the first resistance of the DRAM upper line.

[0160] The second resistance measurement module 302 is used to measure the second resistance of the first path when the first transistor connected to the bit line is in the on state. The first path includes, in sequence: the node contact of the first transistor, the word channel of the first transistor, the BLC of the first transistor, and the bit line for reading and writing the first transistor.

[0161] The third resistance measurement module 303 is used to measure the third resistance of the second path when the two adjacent transistors connected by the bit line are in the on state. The second path includes: the word line channel of the two adjacent transistors and the node contact of the two adjacent transistors.

[0162] Bit line contact node resistance determination module 304 is used to determine the bit line contact node resistance based on the first resistor, the second resistor and the third resistor.

[0163] In some embodiments, the second resistance measurement module is further used for:

[0164] A first voltage is applied to the word line of the first transistor to control the first transistor to be in the on state; the first transistor is an NMOS, and the first voltage is greater than or equal to the on-state voltage of the NMOS.

[0165] The second resistance is measured for the first path.

[0166] In some embodiments, the first transistor and the second transistor are located in the same active region, and the device further includes:

[0167] The second voltage application module is configured to apply a second voltage to the word line of the second transistor before measuring the second resistance of the first path, so as to control the second transistor to be in a cutoff state; the second transistor is an NMOS, and the second voltage is less than or equal to the cutoff voltage of the NMOS.

[0168] In some embodiments, the apparatus further includes:

[0169] A first substrate pressurization module is used to apply a third voltage to the substrate of the active region, the third voltage being less than the first voltage.

[0170] In some embodiments, the second resistance measurement module is further used for:

[0171] With a constant fourth current supplied to the first path, the voltage difference across the first path is measured and taken as the fourth voltage.

[0172] The second resistor is determined based on the fourth voltage and the fourth current.

[0173] In some embodiments, the third resistance measurement module is further used for:

[0174] The first voltage is applied to the word lines of two adjacent transistors in the same active region to control both adjacent transistors to be in the on state.

[0175] The third resistance is measured for the second path.

[0176] In some embodiments, the apparatus further includes:

[0177] A second substrate pressure module is configured to apply a third voltage to the substrate of the active region before measuring the third resistance of the second path, the third voltage being less than the first voltage of the two adjacent transistors.

[0178] In some embodiments, the two ends of the second path are the node contacts of the two adjacent transistors, and the third resistance measurement module is further used for:

[0179] With a constant fifth current supplied to the second path, the voltage difference across the second path is measured as the fifth voltage, which is the same as the fourth current.

[0180] The third resistor is determined based on the fifth voltage and the fifth current.

[0181] In some implementations, the first resistance measurement module is further used for:

[0182] When measuring the first resistance of the DRAM bit line, two test contact points of the bit line are determined.

[0183] The first resistance is measured with the transistor located between the two test contacts and connected to the bit line in the off state.

[0184] In some implementations, the first resistance measurement module is also used for:

[0185] With a constant sixth current supplied to the bit line, the voltage difference between the two test contacts is measured as the sixth voltage, which is the same as the fourth current.

[0186] The first resistor is determined based on the sixth voltage and the sixth current.

[0187] In some implementations, the two test contact points are located at both ends of the bit line.

[0188] In some embodiments, the bit line contact node resistance determination module is further used for:

[0189] When determining the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor, the distance between the two test contact points is measured.

[0190] Measure the length of the read / write bit line.

[0191] The fourth resistance of the read / write bit line is determined based on the ratio of the distance to the length and the first resistance.

[0192] The bit line contact node resistance is determined based on the fourth resistor, the second resistor, and the third resistor.

[0193] In some implementations, the bit line contact node resistance is calculated using the following formula:

[0194]

[0195] Wherein, Rblc is the bit line contact node resistance, R2 is the second resistance, R3 is the third resistance, and R4 is the fourth resistance.

[0196] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.

[0197] Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device 600 includes a memory 602 and at least one processor 601.

[0198] Among them, memory 602 stores computer-executed instructions.

[0199] At least one processor 601 executes computer execution instructions stored in memory 602, causing electronic device 601 to implement the aforementioned method for measuring bit line contact node resistance.

[0200] In addition, the electronic device may also include a receiver 603 and a transmitter 604, wherein the receiver 603 is used to receive information from other devices or equipment and forward it to the processor 601, and the transmitter 604 is used to send information to other devices or equipment.

[0201] This disclosure also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, enable the computing device to implement a method for measuring the resistance of bit line contact nodes.

[0202] This disclosure also provides a computer program product for executing the above-described method for measuring the resistance of bit line contact nodes.

[0203] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0204] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0205] The above are merely preferred embodiments of the present disclosure and do not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.

Claims

1. A method for measuring the resistance of a bit line contact node, characterized in that, The method includes: Measure the first resistance of the DRAM upper bit line; When the first transistor connected to the bit line is in the on state, the second resistance of the first path is measured. The first path includes, in sequence: the node contact of the first transistor, the word channel of the first transistor, the bit line contact node of the first transistor, and the read / write bit line of the first transistor. With the two adjacent transistors connected by the bit line in the on state, the third resistance of the second path is measured. The second path includes: the word line channel of the two adjacent transistors and the node contact of the two adjacent transistors. The bit line contact node resistance is determined based on the first resistor, the second resistor, and the third resistor.

2. The method according to claim 1, characterized in that, Measuring the second resistance of the first path when the first transistor connected to the bit line is in the on state includes: A first voltage is applied to the word line of the first transistor to control the first transistor to be in the on state; the first transistor is an NMOS, and the first voltage is greater than or equal to the on voltage of the NMOS; The second resistance is measured for the first path.

3. The method according to claim 2, characterized in that, The first transistor and the second transistor are located in the same active region. Before measuring the second resistance of the first path, the method further includes: A second voltage is applied to the word line of the second transistor to control the second transistor to be in the off state; the second transistor is an NMOS, and the second voltage is less than or equal to the off voltage of the NMOS.

4. The method according to claim 3, characterized in that, The method further includes: A third voltage is applied to the substrate of the active region, the third voltage being less than the first voltage.

5. The method according to claim 4, characterized in that, Measuring the second resistance in the first path includes: With a constant fourth current supplied to the first path, the voltage difference across the first path is measured and taken as the fourth voltage. The second resistor is determined based on the fourth voltage and the fourth current.

6. The method according to claim 5, characterized in that, The third resistance of the second measurement path includes: The first voltage is applied to the word line of two adjacent transistors in the same active region to control both adjacent transistors to be in the on state; The third resistance is measured for the second path.

7. The method according to claim 6, characterized in that, Before measuring the third resistance in the second path, the method further includes: The third voltage is applied to the substrate of the active region, the third voltage being less than the first voltage of the two adjacent transistors.

8. The method according to claim 7, characterized in that, The two ends of the second path are the node contacts of the two adjacent transistors, and the measurement of the third resistance of the second path includes: When a constant fifth current is supplied to the second path, the voltage difference across the second path is measured as the fifth voltage, and the fifth current is the same as the fourth current. The third resistor is determined based on the fifth voltage and the fifth current.

9. The method according to claim 5, characterized in that, The measurement of the first resistance of the DRAM upper bit line includes: Determine the two test contact points of the bit line; The first resistance is measured with the transistor located between the two test contacts and connected to the bit line in the off state.

10. The method according to claim 9, characterized in that, The measurement of the first resistance includes: With a constant sixth current supplied to the bit line, the voltage difference between the two test contact points is measured as the sixth voltage, which is the same as the fourth current. The first resistor is determined based on the sixth voltage and the sixth current.

11. The method according to claim 9, characterized in that, The two test contact points are located at both ends of the bit line.

12. The method according to claim 9, characterized in that, Determining the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor includes: Measure the distance between the two test contact points; Measure the length of the read / write bit line; The fourth resistance of the read / write bit line is determined based on the ratio of the distance to the length and the first resistance. The bit line contact node resistance is determined based on the fourth resistor, the second resistor, and the third resistor.

13. The method according to claim 12, characterized in that, The resistance of the bit line contact node is calculated using the following formula: Wherein, Rblc is the bit line contact node resistance, R2 is the second resistance, R3 is the third resistance, and R4 is the fourth resistance.

14. A measuring device for the resistance of a bit line contact node, characterized in that, include: The first resistance measurement module is used to measure the first resistance of the DRAM upper bit line; The second resistance measurement module is used to measure the second resistance of the first path when the first transistor connected to the bit line is in the on state. The first path includes, in sequence: the node contact of the first transistor, the word channel of the first transistor, the bit line contact node of the first transistor, and the bit line for reading and writing the first transistor. The third resistance measurement module is used to measure the third resistance of the second path when the two adjacent transistors connected by the bit line are in the on state. The second path includes: the word line channel of the two adjacent transistors and the node contact of the two adjacent transistors. The bit line contact node resistance determination module is used to determine the bit line contact node resistance based on the first resistor, the second resistor, and the third resistor.

15. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1 to 13.

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