Latch array with mask write functionality

Abstract

A latch array having mask write functionality includes a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; and a slave latch in the column of the array, wherein the slave latch of the array includes a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 574,431, filed January 12, 2022, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] All aspects of this disclosure relate to memory circuitry in general, and more particularly to latch arrays with mask write functionality. Background Technology

[0004] Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) are commonly used in circuits such as integrated circuits (ICs) that include System-on-Chip (SoC) type ICs. SRAM and DRAM memory circuits typically operate at relatively high memory voltage domains to ensure data transfer margins are met. Latch arrays, which also store data, are becoming increasingly popular because they typically operate at relatively low logic voltage domains, making them more power-efficient compared to SRAM and DRAM. Therefore, there has been a drive to swap or replace SRAM and DRAM with latch arrays in the design of circuits such as ICs and SoCs. Summary of the Invention

[0005] The following is a simplified overview of one or more specific implementations to provide a basic understanding of such implementations. This overview is not an exhaustive summary of all envisioned implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] One aspect of this disclosure relates to a latch array. The latch array includes: a first set of master latches, the first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches, the second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; and a slave latch array arranged in columns and rows, wherein a slave latch in a column of the array includes a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

[0007] Another aspect of this disclosure relates to a method. The method includes: providing a deasserted write bit signal to a target slave latch in a set of slave latches; providing a first set of data signals to the set of slave latches respectively; providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches respectively based on one or more of the first set of data signals; and while the slave clock is causing the data to be written to one or more of the set of slave latches respectively based on one or more of the first set of data signals, operating the target slave latch in response to the deasserted write bit signal to retain previously stored data.

[0008] Another aspect of this disclosure relates to an apparatus. The apparatus includes: means for providing a de-asserted write bit signal to a target slave latch in a set of slave latches; means for providing a first set of data signals to the set of slave latches respectively; means for providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches respectively based on one or more of the first set of data signals; and means for operating the target slave latch to retain previously stored data in response to the de-asserted write bit signal while the first slave clock is causing data to be written to one or more of the set of slave latches respectively based on one or more of the first set of data signals.

[0009] Another aspect of this disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a latch array coupled to the one or more signal processing cores, wherein the latch array includes: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data respectively, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; and a slave latch array arranged in columns and rows, wherein a slave latch in a column of the array includes a second set of data inputs coupled to the set of bit lines and a second set of write bit inputs respectively coupled to the set of write bit lines.

[0010] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying illustrations elaborate certain exemplary aspects of these one or more embodiments. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the embodiments in this specification are intended to include all such aspects and their equivalents. Attached Figure Description

[0011] Figure 1A A block diagram / schematic representation of an example memory circuit according to one aspect of this disclosure is shown.

[0012] Figure 1B Example of another aspect of this disclosure Figure 1A A bitmap of example data stored in a memory circuit.

[0013] Figure 1C An example of writing data to according to another aspect of this disclosure is illustrated. Figure 1A A flowchart of an example method in a memory circuit.

[0014] Figure 2A A block diagram / schematic representation of an example memory circuit with mask write functionality according to another aspect of this disclosure is shown.

[0015] Figure 2B An example of writing data to according to another aspect of this disclosure is illustrated. Figure 2A A flowchart of an example method in a memory circuit.

[0016] Figure 3 A block diagram / schematic representation of an example latch array according to another aspect of this disclosure is shown.

[0017] Figure 4A A block diagram / schematic representation of an example latch array having mask write functionality according to another aspect of this disclosure is shown.

[0018] Figure 4B Example of another aspect of this disclosure Figure 4A Timing diagram of example data write and write mask operations performed by the latch array.

[0019] Figure 5 A schematic diagram of a latch is illustrated as an example of another aspect of this disclosure.

[0020] Figure 6 A schematic diagram of another example of a latch according to another aspect of this disclosure is illustrated.

[0021] Figure 7A schematic diagram of a latch is illustrated, representing yet another example of a different aspect of this disclosure.

[0022] Figure 8 A flowchart illustrating an example method for writing data to a latch array and masking the writing of data to a latch array according to another aspect of this disclosure is provided.

[0023] Figure 9 A block diagram illustrating an example wireless communication device according to another aspect of this disclosure is shown. Detailed Implementation

[0024] The detailed description following, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. Specific details are included to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0025] Figure 1A A block diagram / schematic representation of an example memory circuit 100 according to one aspect of this disclosure is shown. The memory circuit 100 may be a static random access memory (SRAM) or a dynamic random access memory (DRAM) type memory circuit.

[0026] Specifically, the memory circuit 100 includes a two-dimensional array of memory cells C00 to C75. In this example, the array size is eight (8) rows and six (6) columns (e.g., an 8×6 memory array). However, it should be understood that the size of the memory array (including the number of rows and columns) may vary depending on the application. Memory cells C00-C05 to C70-C75 are shared by rows zero (0) to seven (7), respectively. Memory cells C00-C70 to C05-C75 are shared by columns zero (0) to five (5), respectively. As discussed, each of the memory cells C00 to C75 may be implemented as an SRAM or DRAM cell.

[0027] The memory circuitry 100 also includes a word line (WL) decoder 110, a write driver 120, a sense amplifier 130, and a memory buffer 140. The WL decoder 110 includes a first input configured to receive a write enable (we) signal, a second input configured to receive a read enable (re) signal, and a third input configured to receive an address (ADDR). The WL decoder 110 includes a set of outputs, each coupled to a set of word lines (e.g., metallized traces) WL0 to WL7. These word lines WL0 to WL7 are sequentially coupled to multi-row cells C00-C05 to C70-C75.

[0028] The write driver 120 includes an input configured to receive a write enable (we) signal and a set of data inputs configured to receive a set of data D0 through D5, respectively. The write driver 120 also includes inputs coupled to a set of complementary bit lines (BLs) (e.g., metallized traces). to A set of complementary (e.g., differential) outputs. This set of complementary bit lines... to These are sequentially coupled to multiple column cells C00-C70 to C05-C75. It should be understood that DRAM memory circuits typically do not include complementary bit lines, but only single-ended bit lines.

[0029] The sense amplifier 130 (which may also be referred to as a memory read circuit) includes an input configured to receive a read enable (re) signal. The sense amplifier 130 also includes inputs coupled to the set of complementary bit lines. to The set of complementary (e.g., differential) inputs. Additionally, the sense amplifier 130 includes a set of data inputs D0 to D5 and a set of data outputs D0 to D5, respectively coupled to the memory buffer 140. The memory buffer 140 also includes inputs configured to receive a read enable (re) signal, and a set of data outputs D0-D5. See below for further details. Figures 1B to 1C The operation of memory circuit 100 was discussed.

[0030] Figure 1B A bitmap illustrating example data stored in a memory circuit 100 according to another aspect of this disclosure is shown. The horizontal axis of the bitmap identifies columns 0-5 of the memory cells. The vertical axis of the bitmap identifies rows 0-7 of the memory cells. An array of boxes below and to the right of the columns and rows shows the data in memory cells C00-C75. For example, the first row of cells C00-C05 stores the data 1, 0, 1, 0, 1, and 0, respectively; the second row of cells C10-C15 stores the data 0, 1, 0, 1, 0, and 1, respectively; and so on in a similar manner. In this example, write operations of the memory circuit 100 will be concentrated on cells C50-C55 in the sixth row coupled to word line WL5. The data stored in these cells C50-C55 are 0, 1, 0, 1, 0, and 1, respectively.

[0031] Figure 1CA flowchart illustrating an example method 150 for writing data into memory circuitry 100 according to another aspect of this disclosure is provided. According to method 150, data or words stored in the fifth row units C50-C55 are first transferred to memory buffer 140 (box 160). In this regard, the address provided to WL decoder 110 points to the sixth row units C10-C15, and in response to a read enable (re) signal being asserted, WL decoder 110 generates an asserted select signal on word line WL5 (and deasserted select signals on word lines WL0-WL4 and WL6-7). The asserted select signal on word line WL5 selects memory units C50-C55 for data reading purposes. Furthermore, in response to a read enable (re) signal being asserted, sense amplifier 130 differentially senses the complementary bit lines respectively. to The voltage level at the location. By performing differential sensing and comparison of complementary bit line voltages, the sensing amplifier 130 generates data D0-D5. In addition, in response to the asserted read enable (re) signal, the memory buffer 140 reads or receives data D0-D5 from the sensing amplifier 130.

[0032] Furthermore, according to data writing method 150, one or more of the data bits D0-D5 in memory buffer 140 are modified (box 170). For example... Figure 1B As illustrated, the bits indicated by the darker shaded boxes are the bits to be modified, and the bits in the lighter shaded boxes are the bits that will not be modified. Therefore, the data writing method 150 includes modifying the words stored in the memory buffer 140 to change the data 1, 1, and 0 stored in memory cells C51, C53, and C54, respectively. Although not explicitly illustrated, this set of data outputs of the memory buffer 140 is coupled to the same set of data inputs D0-D5 of the write driver 120.

[0033] Then, according to data writing method 150, the modified words in memory buffer 140 are rewritten into memory cells C50-C55 respectively (box 180). In this regard, the address provided to WL decoder 110 again points to the fifth row of memory cells C50-C55 (e.g., the target memory cells for the write operation). Then, a write enable (we) signal is asserted. In response to the asserted write enable (we) signal, WL decoder 110 generates an asserted select signal on word line WL5 coupled to the target memory cells C50-C55 (and generates a deasserted select signal on word lines WL0-WL4 and WL6-7 coupled to the non-target memory cells C00-C45 and C60-C75). The asserted select signal on word line WL5 selects the target memory cells C50-C55 for data writing purposes.

[0034] Furthermore, in response to the write enable (we) signal, the write driver 120 writes data D0-D5 received from the memory buffer 140 onto the complementary bit lines respectively. to Complementary bit line signals are generated. This operation causes the data D0-D5 associated with the modified word (e.g., 000011) to be written into target memory cells C50-C55, respectively.

[0035] There are some drawbacks associated with memory circuitry 100. As discussed, write operations of memory circuitry 100 typically involve three (3) main operations: transferring a word (one or more bits to be rewritten to the word) from a row of memory cells to memory buffer 140 according to box 160; modifying one or more bits of the word stored in memory buffer 140 according to box 170; and then rewriting the modified word back to the row of memory cells according to box 180. Therefore, data write method 150 involves significant latency due to the three (3) required operations. This is even the case where some bits of the word do not need to be modified (such as bits stored in memory cells C50, C52, and C54 (lighter shaded boxes)).

[0036] Figure 2A A block diagram / schematic representation of an example memory circuit 200 with mask write functionality according to another aspect of this disclosure is illustrated. As mentioned, in contrast to the three (3) operations previously discussed with respect to memory circuit 200, memory circuit 200 employs mask write functionality to allow data writing in a single operation. As discussed in more detail below, mask write functionality essentially isolates one or more non-target memory cells of a word from data operations of one or more target memory cells of the same word.

[0037] More specifically, memory circuit 200 is similar to memory circuit 100; because memory circuit 200 includes a two-dimensional array of memory cells C00-C75, a WL decoder 210, and a write driver 220, and may also include a sense amplifier and a memory buffer, although for simplicity... Figure 2A Not shown. Similarly, the array of memory cells C00-C75 is arranged in eight (8) rows of C00-C05 to C70-C75 and six (6) columns of C00-C70 to C05-C75 (e.g., an 8×6 memory array). Each of the memory cells C00-C75 may be an SRAM or DRAM memory cell.

[0038] Similarly, the WL decoder 210 includes a first input for receiving a write enable (we) signal, a second input for receiving an address (ADDR) of the row memory cell to which data will be written, and a set of outputs coupled to word lines WL0 through WL7, respectively. As previously discussed, these word lines WL0 through WL7 are coupled to multi-row cells C00-C05 through C70-C75, respectively. In a similar manner, the write driver 220 includes an input configured to receive a write enable (we) signal, a set of data inputs configured to receive a set of data D0 through D5, and a set of complementary bit lines coupled to each other. to A set of complementary outputs. As mentioned earlier, this set of complementary bit lines... to They are sequentially coupled to multiple column cells C00-C70 to C05-C75. As discussed earlier, DRAM memory circuitry typically does not include complementary bit lines; and therefore, each of the DRAM memory cells is coupled to a single-ended bit line.

[0039] The memory circuit 200 differs from the memory circuit 100 in that the memory circuit 200 and the write driver 220 also include mask write functionality. In this respect, the write driver 220 also includes another set of inputs configured to receive a set of write bit signals WB0 to WB5 that specify the bits of the identified word to be written (or, inferred, which bits of the selected word, if any, will be masked during the data write operation).

[0040] For example, if memory circuit 200 is an SRAM memory circuit, then when writing data "1" to an SRAM cell, write driver 220 will complement the bit line. Set to 1 / 0; when writing data "0" to an SRAM cell, the write driver 220 will use complementary bit lines. Set to 0 / 1; and when the corresponding write bit (WB) signal is de-asserted, the write driver 220 will complement the bit line. The write driver 220 sets the bit line BL to "1" when writing data "1" to the DRAM cell; when writing data "0" to the DRAM cell, the write driver 220 sets the bit line BL to "0"; and when the corresponding write bit (WB) signal is de-asserted, the write driver 220 causes the bit line BL to float, so that the corresponding DRAM cell retains the previously stored data.

[0041] Figure 2BA flowchart illustrating an example method 250 for writing data into memory circuitry 200 according to another aspect of this disclosure is shown. According to method 250, in response to identifying the bits (such as those stored in the memory) of the write operation mask, Figure 1B The write driver 220 generates 1 / 1 or floats the bit lines coupled to the bit lines of memory cells C50, C52, and C55 to which it will write mask data, in response to an asserted write enable signal (we). The write driver 220 also generates appropriate signals on the bit lines coupled to the bit lines of memory cells C51, C53, and C54 to which data will be written.

[0042] Simultaneously, the address is provided to the WL decoder 210, which, as discussed, points to the target memory cells C50-C55. In response to the asserted write enable (WE) signal, the WL decoder 210 generates an asserted select signal on word line WL5 coupled to the target memory cells C50-C55 (and generates an asserted de-select signal on word lines WL0-WL4 and WL6-WL7 coupled to the non-target memory cells C00-C45 and C60-C75). Word lines WL0-WL7 and bit lines... to The signals on the device select target memory cells C51, C53, and C54 for data writing purposes.

[0043] Furthermore, according to method 250, in response to the write enable (we) signal, the write driver 220 performs a write operation on the complementary bit lines based on the new data D1, D3, and D4 and the write bits WB0, WB2, and WB5. to Complementary bit line signals are generated. Bits D0, D2, and D5 are "ignorable" because the corresponding memory cells C50, C52, and C55 are masked by the deasserted write bit signals WB0, WB2, and WB5, respectively. Complementary bit lines and The complementary bit line signals modify the bits stored in the target memory cells C51, C53, and C54 (box 270). All these operations, as outlined in boxes 260 and 270 of data write method 250, can be performed substantially simultaneously; resulting in the modification of the bits stored in memory cells C51, C53, and C54 in a single write operation. Therefore, the data write latency relating to the mask write functionality of memory circuit 200 can be substantially smaller compared to the data write latency associated with memory circuit 100.

[0044] Figure 3A block diagram / schematic representation of an example latch array 300 according to another aspect of this disclosure is illustrated. A latch array is another type of memory circuit that uses latches to store data, as opposed to SRAM and DRAM memory cells. Latch arrays used in integrated circuits (ICs) (such as systems-on-chips (SoCs)) have become increasingly popular due to their relatively low power consumption compared to SRAM or DRAM memory circuits. This is typically because the voltage domain (MX) associated with SRAM and DRAM memory circuits is much higher than the voltage domain (CX) used in logic circuits. Since latch arrays are constructed using logic circuits, they can use a lower logic voltage domain (CX) to consume less power compared to SRAM or DRAM memory circuits on the MX voltage domain.

[0045] Specifically, latch array 300 includes a set of clock gate circuits (CGCs) 310-0 to 310-3, a set of master latches 320-0 to 320-3, a two-dimensional array of slave latches 330-00 to 330-33, and a set of multiplexers 340-0 to 340-3. In this example, the slave latch array is arranged in four (4) rows of slave latches 330-00-330-03 to 330-30-330-33, and four (4) columns of slave latches 330-00-330-30 to 330-03-330-33 (e.g., a 4×4 latch array). Similarly, it should be understood that the size and dimensions of latch array 300 may vary depending on the specific application in which it is used.

[0046] The clock gating circuits (CGCs) 310-0 to 310-3 include a set of clock inputs configured to receive the master clock (clk). The clock gating circuits (CGCs) 310-0 to 310-3 also include a set of enable inputs configured to receive a write address (WADDR), which may include a write enable (we) signal. In this example, the write address has a two-bit length to uniquely address each of the clock gating circuits (CGCs) 310-0 to 310-3. The clock gating circuits 310-0 to 310-3 additionally include a set of slave clock outputs (SCLK) coupled to a set of word lines WL0 to WL3. The word lines WL0 to WL3 are coupled to a set of clock inputs for each row of slave latches 330-00-330-03 to 330-30-330-33.

[0047] The master latches 320-0 to 320-3 include a set of clock inputs configured to receive the master clock clk. Additionally, the master latches 320-0 to 320-3 include a set of data inputs (d) configured to receive a set of data D0 to D3 respectively. Furthermore, the master latches 320-0 to 320-3 include a set of data outputs (q) coupled to a set of bit lines BL0 to BL3 respectively. The bit lines BL0 to BL3 are coupled to a set of data inputs (d) in each column from latches 330-00-330-30 to 330-03-330-33.

[0048] Each of the multiplexers 340-0 to 340-3 includes a set of data inputs that are respectively coupled to a set of data outputs (q) of each of the latches 330-00-330-30 to 330-03-330-33. For clarity, multiplexer 340-0 includes a set of data inputs coupled to a set of data outputs (q) from latches 330-00 to 330-30, respectively, in column "0"; multiplexer 340-1 includes a set of data inputs coupled to a set of data outputs (q) from latches 330-01 to 330-31, respectively, in column "1"; multiplexer 340-2 includes a set of data inputs coupled to a set of data outputs (q) from latches 330-02 to 330-32, respectively, in column "2"; and multiplexer 340-3 includes a set of data inputs coupled to a set of data outputs (q) from latches 330-03 to 330-33, respectively, in column "3". The set of multiplexers 340-0 to 340-3 also includes a set of selection inputs configured to receive a read address (RADDR). In addition, the multiplexers 340-0 to 340-3 include a set of data outputs configured to generate outputs or read data Q0 to Q3 respectively.

[0049] The write operation of latch array 300 can be performed as follows: the write address of the row of latches to which data will be written is provided to the group of clock gate circuits (CGCs) 310-0 to 310-3. In this particular example, the write address points to the third row of latches 330-20 to 330-23. Furthermore, new data D0 to D3 to be written to the third row of latches 330-20 to 330-23 are respectively provided to the group of data inputs of the master latches 320-0 to 320-3.

[0050] In response to a high phase of the master clock clk, the master latches 320-0 to 320-3 become opaque, and new data D0 to D3 are provided to the bit lines BL0 to BL3 respectively. Additionally, in response to a write enable (we) being asserted and the write address pointing to the third row of slave latches 330-20 to 330-23, the clock gating circuit (CGC) 310-2 generates a slave clock sclk, which is provided to the slave latches 330-20 to 330-23 via word line WL2. Since the other clock gating circuits (CGC) 310-0, 310-1, and 310-3 are not addressed in this data write example, they do not generate slave clock sclk on word lines WL0, WL1, and WL3 respectively.

[0051] The slave clock sclk is essentially 180 degrees out of phase with the master clock clk. Therefore, in response to a low phase of the slave clock sclk, latches 330-20 to 330-23 become transparent to accept new data D0 to D3 on bit lines BL0 to BL3, respectively. A subsequent high phase of the slave clock sclk then causes latches 330-20 to 330-23 to become opaque to hold or store data D0 to D3, respectively. Furthermore, a subsequent low phase of the master clock clk causes master latches 320-0 to 320-3 to become transparent to accept subsequent new data D0 to D3, respectively.

[0052] The read operation of latch array 300 is performed directly; because the read address causes the multiplexers 340-0 to 340-3 to output the data stored in the row of latches identified by the read address. For example, if the data stored in the third row of latches 330-20 to 330-23 is to be read, the read address causes the multiplexers 340-0 to 340-3 to select the second input from the left, respectively. These inputs of the multiplexers 340-0 to 340-3 are coupled to the data output (q) of the third row of latches 330-20 to 330-23. Therefore, the data stored in the third row of latches 330-20 to 330-23 is generated as output data Q0 to Q3 at the output of the multiplexers 340-0 to 340-3.

[0053] Although, as discussed, latch array 300 is generally more power efficient than SRAM or DRAM memory circuitry, latch array 300 does not have mask write functionality. That is, according to the data write operation discussed earlier, all slave latches belonging to a row or word line are rewritten with new data D0 through D3, even if some data does not need to be rewritten. For example, suppose the data stored in slave latches 330-21 and 330-22 is to be rewritten with new data D1 and D2, and the data stored in slave latches 330-20 and 330-23 needs to remain the same, the write operation of latch array 330 still requires providing the same data D0 and D3 to slave latches 330-20 and 330-23 respectively. In some cases, applications using latch array 300 may not know the values ​​of data that will not be rewritten. Therefore, in such cases, mask write functionality would be desirable for the latch array.

[0054] Figure 4A A block diagram / schematic representation of an example latch array 400 with mask write functionality according to another aspect of this disclosure is illustrated. In summary, latch array 400 is reconfigured to provide mask write functionality, as discussed in more detail below. Similar to latch array 300, latch array 400 is a 4×4 latch array; however, it should be understood that latch array 400 can be implemented with different sizes, and the number of rows may differ from the number of columns.

[0055] The latch array 400 is similar to the latch array 300 in that it includes a set of clock gate circuits (CGCs) 410-0 to 410-3 (each including a set of clock inputs configured to receive the master clock clk, a set of inputs configured to receive the write address / write enable (WE) signal, and a set of slave clock outputs (SCLK) coupled to the set of word lines WL0 to WL3); and a first set of master-slave latches 420-0 to 420-3 (each including a set of clock inputs configured to receive the master clock clk, and a set of data inputs configured to receive the data D0 to D3 to be written into the latch array 400). (d), and the set of data outputs (q) coupled to the set of bit lines BL0 to BL3; a two-dimensional array from latches 430-00 to 430-33, wherein each row from latches 430-00-430-03 to 430-30-430-33 includes the set of clock inputs coupled to the set of word lines WL0 to WL3 and a set of data outputs (q) coupled to the set of data inputs coupled to the set of multiplexers 440-0 to 440-3, and wherein each column from latches 430-00-430-30 to 430-03-430-33 includes the set of data inputs (d) respectively coupled to the set of bit lines BL0 to BL3.

[0056] For mask write functionality, latch array 400 also includes a second set of master latches 450-0 to 450-3. The second set of master latches 450-0 to 450-3 includes a set of clock inputs configured to receive the master clock clk. The second set of master latches 450-0 to 450-3 includes a set of write bit inputs (d) configured to receive a set of write bit signals wb0 to wb3. The second set of master latches 450-0 to 450-3 includes a set of write bit outputs (q) coupled to a set of write bit lines WB0 to WB3. Each column from latches 430-00-430-30 to 430-03-430-33 includes a set of write bit inputs (wbt) coupled to the set of write bit lines WB0 to WB3. It should be understood that in some specific implementations, the first and second sets of master latches 420-0 to 420-3 and 450-0 to 450-3 may be the same or different. See below for reference. Figure 4B Discuss the mask write operation of latch array 400.

[0057] Figure 4B A timing diagram illustrating an example mask write operation performed by a latch array 400 relative to a target from a latch according to another aspect of this disclosure is shown. The horizontal axis of the timing diagram represents time. The time axis is divided into two write cycles, #1 and #2. The vertical axis, from top to bottom, represents the logic voltage levels of various signals, such as the master clock (clk), write enable signal (we), data signal (d), write bit signal (wbt), and complementary write bit signal. Complementary from clock Internal non-complementary slave clock sclk i And the output data signal (q).

[0058] According to the first write cycle #1, the write bit signal (wbt) is asserted at a high logic voltage (1). This means that data will be written to the target slave latch (or, conversely, the target slave latch is not masked). As illustrated, before the rising edge of the master clock (clk) at time t1, the write enable signal (we) is asserted, the data signal (d) is present at the input of the corresponding master latch of the first group, and the write bit signal (wbt) is present at the input of the corresponding master latch of the second group. In response to the rising edge of the master clock (clk) at time t1, the corresponding master latch of the first group passes the data signal (d) to the corresponding bit line, and the corresponding master latch of the second group writes the complementary bit signal. (Because the second master latch can invert the write bit signal (wbt)) it is passed to the corresponding write bit line, and the corresponding clock gate circuit (CGC) generates a complementary slave clock on the corresponding word line. The falling edge.

[0059] As discussed in this article with reference to various examples, latch implementations in response to complementary clock signals are discussed in more detail. At the falling edge, the target latch generates an internal non-complementary slave clock (sclk) at time t2. i The rising edge of the master clock at time t3 causes the target to become transparent from the latch and accept or receive the data signal (d) from the corresponding bit line. Then, in response to the next falling edge of the master clock at time t3, the corresponding clock gate circuit (CGC) generates the complementary slave clock on the corresponding word line. The rising edge. Responding to the complementary clock. On the rising edge, the target latch generates an internal non-complementary slave clock (sclk) at time t4. i The falling edge of the latch causes the target to become opaque from the latch and retains or stores the received data.

[0060] According to the second write cycle #2, the write bit signal (wbt) is deasserted at a low logic voltage (0). This means the target is masked from the latch and the "don't care" data signal (d) on the corresponding bit line will not be accepted. As illustrated, before the rising edge of the master clock at time t5 during the second write cycle #2, the write enable signal (we) is asserted, the "don't care" data signal (d) is present at the input of the corresponding master latch of the first group, and the write bit signal (wbt) is present at the input of the corresponding master latch of the second group. In response to the rising edge of the master clock (clk) at time t5, the corresponding master latch of the first group passes the "don't care" data signal (d) to the corresponding bit line, and the corresponding master latch of the second group passes the complementary write bit signal. The clock signal is passed to the corresponding write bit line, and the corresponding clock gate circuit (CGC) generates a complementary slave clock on the corresponding word line. The falling edge. However, in this case, in response to the complementary slave clock. On the falling edge, the target latch does not generate an internal non-complementary slave clock (sclk). i This causes the latch to remain opaque and retains previously stored data.

[0061] Figure 5 A schematic diagram illustrating an example slave latch 500 according to another aspect of this disclosure is shown. Slave latch 500 may be an example implementation of any of the slave latches 430-00 to 430-33 of latch array 400. In summary, slave latch 500 gates the slave clock in response to the write bit signal wbt being deasserted (meaning a write mask is being applied to slave latch 500). Otherwise, from the clock The data is passed to the data gating and latching circuits. Specifically, latch 500 includes a data gating circuit 510, a data latching circuit 520, and a clock gating circuit 530.

[0062] If the write bit signal wbt is asserted (e.g., logic 1 (1)) (or complementary write bit signal) If the logic is zero (0), then the clock gate circuit 530 is configured to respond to the complementary slave clock received via the corresponding word line. And generate the internal non-complementary slave clock sclk i and internal complement from clock If the write bit signal wbt is de-asserted (e.g., logic zero (0)) (or complementary write bit signal) If logic is 1 (1), then the clock gate circuit 530 is further configured to gate the complementary slave clock received via the corresponding word line. .

[0063] More specifically, the clock gate circuit 530 includes a NOR gate 532, which includes a component coupled to a corresponding write bit line to receive a complementary write bit signal. The first input is coupled to the corresponding word line to receive the complementary slave clock signal. The second input, and configured to generate the internal non-complementary clock signal sclk. i The clock gate circuit 530 also includes an inverter 534, which includes an input coupled to the output of the NOR gate 532, and is configured to generate an internal complementary slave clock. The output.

[0064] When latch 500 is transparent, data gating circuit 510 is configured to pass the data signal (d) received via the corresponding bit line to the output of data gating circuit 510 (and the input of data latch circuit 520). When latch 500 is opaque, data gating circuit 510 is configured to gate the data signal (d).

[0065] More specifically, the data gating circuit 510 includes a first field-effect transistor (FET) M1, a second FET M2, a third FET M3, and a fourth FET M4 series coupled between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). The first FET M1 and the second FET M2 can be implemented as p-channel metal-oxide-semiconductor field-effect transistors (PMOS FETs). The third FET M3 and the fourth FET M4 can be implemented as n-channel metal-oxide-semiconductor field-effect transistors (NMOS FETs). The gates of the first FET M1 and the fourth FET M4 are coupled together and coupled to corresponding bit lines to receive the data signal (d). The gates of the second FET M2 and the third FET M3 are coupled to the outputs of an inverter 534 and a NOR gate 532 to receive internal complementary slave clocks, respectively. and internal non-complementary slave clock sclk i The output of the data gating circuit 510 is located at the node between FET M2 and FET M3 (e.g., their drains).

[0066] When latch 500 is transparent, data latch circuit 520 opens to receive data signal (d) from the output of data gating circuit 510. When latch 500 is opaque, data latch circuit 520 closes to hold the received data (d).

[0067] More specifically, the data latch circuit 520 includes a fifth FET M5, a sixth FET M6, a seventh FET M7, and an eighth FET M8 series coupled between the upper voltage rail Vdd and the lower voltage rail Vss. The fifth FET M5 and the sixth FET M6 can be implemented as PMOS FETs. The seventh FET M7 and the eighth FET M8 can be implemented as NMOS FETs. The input of the data latch circuit 520 is located at a node between FET M6 and FET M7 (e.g., their drains), which is the same node as the output of the data gate circuit 510. The gates of FET M5 and FET M8 are coupled together and coupled to the data output (q) from the latch 500, which is coupled to the input of a corresponding multiplexer (e.g., one of multiplexers 440-0 to 440-3). The gates of FET M6 and FET M7 are coupled to the outputs of NOR gate 532 and inverter 534 to receive the internal non-complementary slave clock sclk, respectively. i and internal complement from clock The data latch circuit 520 also includes an inverter 522, which includes an input and an output coupled to the input and data output (q) of the data latch circuit 520, respectively.

[0068] During operation, when data is to be written to latch 500 (the latch is transparent), the complementary write bit signal is... Both the complementary and non-complementary clock signals are logic low. In response, the clock gating circuit 530 generates an internal non-complementary clock signal sclk. i As a logic high, it generates an internal complementary clock signal. As a logic low, FETs M2 and M3 of the data gating circuit 510 are turned on to allow the data signal (d) to be passed to the input of the data latch circuit 520. Similarly, FETs M6 and M7 of the data latch circuit 520 are turned off; thereby keeping the data latch circuit 520 open to receive the data signal (d) from the data gating circuit 510.

[0069] Under two conditions, the data will be held by the slave latch 500 (the slave latch is opaque): (1) Complementary slave clock. It is logic high; and / or (2) complementary write bit signal It is logic high. Under these two conditions, the clock gating circuit 530 generates the internal complementary clock signal sclk. i As a logic low, it generates an internal complementary clock signal. As a logic high, FETs M2 and M3 of the data gating circuit 510 are turned off to gate the data signal (d) so that it is not passed to the input of the data latch circuit 520. FETs M6 and M7 of the data latch circuit 520 are turned on; thereby closing the data latch circuit 520 to hold the data (q).

[0070] Figure 6 A schematic diagram illustrating an example slave latch 600 according to another aspect of this disclosure is shown. Slave latch 600 may be an example implementation of any of the slave latches 430-00 to 430-33 of latch array 400. In summary, slave latch 600 gates the data signal (d) in response to the write bit signal wbt being deasserted (meaning a write mask is being applied to slave latch 600); otherwise, the data signal (d) is gated in response to the slave clock. The data is transmitted. Specifically, the latch 600 includes a data gating circuit 610, a data latch circuit 620, and a signal buffer circuit 630.

[0071] The signal buffer circuit 630 is configured to be based on a complementary slave clock received via the corresponding word line. To generate internal non-complementary slave clock sclk i and internal complement from clock The signal buffer circuit 630 is also configured to be based on complementary write bit signals received via the corresponding write bit line. To generate the internal non-complementary write bit signal wbti and internal complementary write bit signal

[0072] More specifically, the signal buffer circuit 630 includes a first inverter 632, which includes components coupled to a corresponding write bit line to receive a complementary write bit signal. The input, and the signal used to generate the internal non-complementary write bit signal wbt. i The signal buffer circuit 630 includes a second inverter 636, which includes an input coupled to the output of the first inverter 632, and a signal for generating an internal complementary write bit signal. The output of the signal buffer circuit 630 includes a third inverter 634, which includes components coupled to a corresponding word line to receive a complementary slave clock signal. The input, and the input used to generate the internal non-complementary slave clock sclk. i The signal buffer circuit 630 includes a fourth inverter 638, which includes an input coupled to the output of the third inverter 634, and an input for generating an internal complementary slave clock. The output.

[0073] When latch 600 is transparent, data gating circuit 610 is configured to pass the data signal (d) received via the corresponding bit line to the output of data gating circuit 610 (and the input of data latch circuit 620). When latch 600 is opaque, data gating circuit 610 is configured to gate the data signal (d).

[0074] More specifically, the data gating circuit 610 includes a first FET M1, a second FET M2, a ninth FET M9, a tenth FET M10, a third FET M3, and a fourth FET M4, series coupled between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). The first FET M1, second FET M2, and ninth FET M9 can be implemented as PMOS FETs. The tenth FET M10, third FET M3, and fourth FET M4 can be implemented as NMOS FETs. The gates of the first FET M1 and fourth FET M4 are coupled together and to corresponding bit lines to receive the data signal (d). The gates of the second FET M2 and third FET M3 are coupled to the outputs of inverters 638 and 634 to receive internal complementary slave clocks, respectively. and internal non-complementary slave clock sclk i The gates of the ninth FET M9 and the tenth FET M10 are coupled to the outputs of inverters 636 and 632 to receive internal complementary write bit signals, respectively. and internal non-complementary write bit signal wbt iThe output of the data gate circuit 610 is located at the node between FET M9 and FET M10 (e.g., their drains).

[0075] When latch 600 is transparent, data latch circuit 620 opens to receive data signal (d) from the output of data gating circuit 610. When latch 600 is opaque, data latch circuit 620 closes to hold data (q).

[0076] More specifically, the data latch circuit 620 includes a fifth FET M5, a first pair of parallel FETs M6, a second pair of parallel FETs M7, and an eighth FET M8, series-coupled between the upper voltage rail Vdd and the lower voltage rail Vss. The fifth FET M5 and the first pair of parallel FETs M6 can be implemented as PMOS FETs. The second pair of parallel FETs M7 and the eighth FET M8 can be implemented as NMOSFETs. The input of the data latch circuit 620 is located at a node between the first and second pairs of FETs M6 and FET M7 (e.g., their drains), which is the same node as the output of the data gate circuit 610. The gates of FETs M5 and FET M8 are coupled together and coupled to the data output (q) from the latch 600, which is coupled to the input of a corresponding multiplexer (e.g., one of multiplexers 440-0 to 440-3). The first set of gates of the pair of FETs M6 and M7 are coupled to the outputs of inverters 634 and 638 to receive internal non-complementary slave clocks, respectively. i and internal complement from clock The second set of gates of FETs M6 and M7 are coupled to the outputs of inverters 632 and 636 to receive the internal non-complementary write bit signal wbt, respectively. i and internal complementary write bit signal The data latch circuit 620 also includes an inverter 622, which includes an input and an output coupled to the input and data output (q) of the data latch circuit 620, respectively.

[0077] During operation, when data is to be written to latch 600 (the latch is transparent), the complementary write bit signal is... Both the complementary and non-complementary clock signals are logic low. In response, the signal buffer circuit 630 generates an internal non-complementary write bit signal wbt. i and the internal non-complementary clock signal sclk i As a logic high, it generates internal complementary write bit signals. and internal complementary clock signal As a logic low, FETs M2, M9, M10, and M3 of the data gating circuit 610 are turned on to allow the data signal (d) to be passed to the input of the data latch circuit 620. Similarly, the paired FETs M6 and M7 of the data latch circuit 620 are turned off; thereby keeping the data latch circuit 620 open to receive the data signal (d) from the data gating circuit 610.

[0078] Under two conditions, the data will be held by the slave latch 600 (the slave latch is opaque): (1) Complementary slave clock. It is logic high; and / or (2) complementary write bit signal It is logic high. Under the first condition, the signal buffer circuit 630 generates an internal non-complementary clock sclk. i To generate an internal complementary clock signal for logic low. The logic is high. Therefore, FETs M2 and M3 of the data gating circuit 610 are turned off to gate the data signal (d) so that it is not passed to the input of the data latch circuit 620. The pair of FETs M6 and M7 of the data latch circuit 620 are turned on; thereby closing the data latch circuit 620 to hold the data (q). Under the second condition, the signal buffer circuit 630 generates the internal non-complementary write bit signal wbt. i To generate an internal complementary clock signal for logic low. The logic is high. Therefore, FETs M9 and M10 of the data gating circuit 610 are turned off to gate the data signal (d) so that it is not passed to the input of the data latch circuit 620. The pair of FETs M6 and M7 of the data latch circuit 620 are turned on; thereby closing the data latch circuit 620 to hold the data (q).

[0079] Figure 7 A schematic diagram illustrating an example slave latch 700 according to another aspect of this disclosure is shown. Slave latch 700 may be an example implementation of any of the slave latches 430-00 to 430-33 of the latch array 400. In summary, slave latch 700 feeds back the data (q) held by the slave latch in response to the write bit signal wbt being deasserted (meaning a write mask is being applied to slave latch 700); otherwise, the data signal (d) responds to the slave clock. The data is transmitted. Specifically, latch 700 includes multiplexer 710 (e.g., 2-to-1 multiplexer), data gating circuit 720, data latch circuit 730, and signal buffer circuit 740.

[0080] The signal buffer circuit 740 is configured to be based on a complementary slave clock received via the corresponding word line. To generate internal non-complementary slave clock sclk i and internal complement from clock The signal buffer circuit 740 is also configured to be based on the complementary write bit signal received via the corresponding write bit line. To generate the internal non-complementary write bit signal wbt i and internal complementary write bit signal

[0081] More specifically, the signal buffer circuit 740 includes a first inverter 742, which includes components coupled to a corresponding write bit line to receive a complementary write bit signal. The input, and the signal used to generate the internal non-complementary write bit signal wbt. i The signal buffer circuit 740 includes a second inverter 746, which includes an input coupled to the output of the first inverter 742, and a signal for generating an internal complementary write bit signal. The output of the signal buffer circuit 740 includes a third inverter 744, which includes components coupled to a corresponding word line to receive a complementary slave clock signal. The input, and the input used to generate the internal non-complementary slave clock sclk. i The signal buffer circuit 740 includes a fourth inverter 748, which includes an input coupled to the output of the third inverter 744, and an input for generating an internal complementary slave clock. The output.

[0082] When the write bit signal wbt is asserted, the multiplexer 710 passes the data signal (d) to the input of the data gate circuit 720, and when the write bit signal wbt is deasserted, the multiplexer 710 passes the output data signal (q) (the data previously stored in the latch 700) to the input of the data gate circuit 720.

[0083] More specifically, the multiplexer 710 includes a first transmit (transfer) gate M9 and a second transmit (transfer) gate M10. The first transmit gate M9 includes an input terminal coupled to a corresponding bit line to receive a data signal (d). The first transmit gate M9 also includes an internal non-complementary write bit signal wbt configured to receive the data signal wbt. i and internal complementary write bit signal The second transmit gate M10 includes non-complementary and complementary gates. The second transmit gate M10 includes an input terminal coupled to the data output (q) of the data latch circuit 730 from the latch 700. The second transmit gate M10 also includes internal non-complementary write bit signals wbt, respectively. i and internal complementary write bit signal The complementary and non-complementary gates. The first transmit gate M9 and the second transmit gate M10 include output terminals coupled together to form the output of the multiplexer 710.

[0084] When latch 700 is transparent, data gating circuit 720 is configured to pass data signal (d) or (q) from multiplexer 710 to the output of data gating circuit 720 (and the input of data latch circuit 730). When latch 700 is opaque, data gating circuit 720 is configured to gate data signal (d) or (q).

[0085] More specifically, the data gating circuit 720 includes a first FET M1, a second FET M2, a third FET M3, and a fourth FET M4 series coupled between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). The first FET M1 and the second FET M2 can be implemented as PMOS FETs. The third FET M3 and the fourth FET M4 can be implemented as NMOS FETs. The gates of the first FET M1 and the fourth FET M4 are coupled together and coupled to the output of the multiplexer 710. The gates of the second FET M2 and the third FET M3 are coupled to the outputs of inverters 748 and 744 to receive internal complementary slave clocks, respectively. and internal non-complementary slave clock sclk i The data gating circuit 720 includes an output between FET M2 and FET M3 (e.g., their drains).

[0086] When latch 700 is transparent, data latch circuit 730 is open to receive data signal (d) or (q) from the output of data gating circuit 720. When latch 700 is opaque, data latch circuit 730 is closed to hold data (q).

[0087] More specifically, the data latch circuit 730 includes a fifth FET M5, a sixth FET M6, a seventh FET M7, and an eighth FET M8 series coupled between the upper voltage rail Vdd and the lower voltage rail Vss. The fifth FET M5 and the sixth FET M6 can be implemented as PMOS FETs. The seventh FET M7 and the eighth FET M8 can be implemented as NMOS FETs. The input of the data latch circuit 730 is located at a node between FET M6 and FET M7 (e.g., their drains), which is the same node as the output of the data gate circuit 720. The gates of FET M5 and FET M8 are coupled together and coupled to a data output (q) from latch 700, which is coupled to the input of a corresponding multiplexer (e.g., one of multiplexers 440-0 to 440-3) and the input terminal of the second transmit gate M10 of multiplexer 710. The gates of FETs M6 and M7 are coupled to the outputs of inverters 744 and 748 to receive internal non-complementary slave clocks, respectively. i and internal complement from clock The data latch circuit 730 also includes an inverter 732, which includes an input and an output coupled to the input and data output (q) of the data latch circuit 730, respectively.

[0088] During operation, when the complementary write bit signal... When both the complementary and slave clocks are logic low, new data (d) will be written to slave latch 700 (the slave latch is transparent). In response, signal buffer circuit 740 generates an internal non-complementary write bit signal wbt. i and the internal non-complementary clock signal sclk i As a logic high, it generates internal complementary write bit signals. and internal complementary clock signal As a logic low, the first transmit gate M9 is turned on to pass the data signal (d) to the data gating circuit 720, and the second transmit gate M10 is turned off to gate the data (q) previously stored in the latch array 700. Additionally, FETs M2 and M3 of the data gating circuit 720 are turned on to allow the data signal (d) to be passed to the input of the data latch circuit 730. Similarly, FETs M6 and M7 of the data latch circuit 730 are turned off; thereby keeping the data latch circuit 730 open to receive the data signal (d) from the data gating circuit 720.

[0089] When complementary write bit signal When the logic clock is high and the complementary slave clock is low, the previously stored data (q) will be written to the slave latch 700 (the slave latch is transparent). In response, the signal buffer circuit 740 generates an internal non-complementary write bit signal wbt. i and the internal non-complementary clock signal sclk i As logic high and logic low, and generate internal complementary write bit signals. and internal complementary clock signal These are respectively designated as logic low and logic high. Therefore, the first transmit gate M9 is turned off to gate the data signal (d), and the second transmit gate M10 is turned on to pass the previously stored data (q) to the data gating circuit 720. Additionally, FETs M2 and M3 of the data gating circuit 720 are turned on to allow the previously stored data (q) to be passed to the input of the data latch circuit 730. Similarly, FETs M6 and M7 of the data latch circuit 730 are turned off; thereby keeping the data latch circuit 730 open to receive the previously stored data (q) from the data gating circuit 720.

[0090] When complement from clock When logic high, data is held by slave latch 700 (the slave latch is opaque). Under this condition, signal buffer circuit 740 generates an internal non-complementary clock sclk.i As a logic low, it generates an internal complementary clock signal. As a logic high, FETs M2 and M3 of the data gating circuit 720 are turned off to gate the data signal (d) or (q) so that it is not passed to the input of the data latch circuit 730. FETs M6 and M7 of the data latch circuit 730 are turned on; thereby closing the data latch circuit 730 to hold the data (q).

[0091] Figure 8 A flowchart illustrating an example method 800 for writing data to a latch array and a mask for writing data to a latch array according to another aspect of this disclosure is provided. Method 800 includes providing a deasserted write bit signal to a target slave latch in a set of slave latches (block 810). Examples of components for providing the deasserted write bit signal to the target slave latch in the set of slave latches include any one of a second set of master latches 450-0 to 450-3, each coupled to a corresponding slave latch 430-00 to 430-33 via a corresponding write bit line of that set of master latches WB0 to WB3.

[0092] Method 800 further includes providing a first set of data signals to the group of slave latches (block 820). Examples of components for providing the first set of data signals to the group of slave latches include a first set of master latches 420-0 to 420-3, respectively coupled via bit lines BL0 to BL3 to each of the column slave latches 430-00-430-30 to 430-03-430-33. Additionally, method 800 includes providing a first slave clock to the group of slave latches to write data to one or more of the group of slave latches based on one or more of the first set of data signals (block 830). Examples of components used to provide a first slave clock to the group of slave latches to write data to one or more of the group of slave latches based on one or more of the first group of data signals include a corresponding one of the group of clock gate circuits (CGC) 410-0 to 410-3, which are coupled to a corresponding one of the row slave latches 430-00-430-03 to 430-30-430-33 via a corresponding one of the group of word lines WL0 to WL3.

[0093] Additionally, method 800 includes, when a first slave clock causes data to be written to one or more of the group of slave latches based on one or more of the first group of data signals, operating the target slave latch in response to a de-asserted write bit signal to retain previously stored data (block 840). Examples of components for operating the target slave latch in response to a de-asserted write bit signal to retain previously stored data when a first slave clock causes data to be written to one or more of the group of slave latches based on one or more of the first group of data signals include any of the slave latches 500, 600, and 700 discussed earlier.

[0094] The operation of the target latch in method 800 may include gating a first slave clock in response to a de-asserted write bit signal to prevent it from being applied to the data gating circuitry and the data latch circuitry. An example of a component for gating the first slave clock in response to a de-asserted write bit signal to prevent it from being applied to the data gating circuitry and the data latch circuitry includes a clock gating circuitry 530 of the slave latch 500.

[0095] The operation of the latch in method 800 may include maintaining the data gating circuit in a gated state and closing the data latch circuit in response to a write bit signal that has been deasserted. Examples of components for maintaining the data gating circuit in a gated state and closing the data latch circuit in response to a write bit signal that has been deasserted include FETs M9-M10 of data gating circuit 610 having gates coupled to the outputs of inverters 636 and 632, respectively; and a pair of FETs M6-M7 having gates coupled to the outputs of inverters 632 and 636, respectively.

[0096] The operation of the target latch in method 800 may include feeding back previously stored data from the data output to the data input of the data latch circuit via a data gating circuit in response to a write bit signal that has been deasserted and a first slave clock. Examples of components for feeding back previously stored data from the data output to the data input of the data latch circuit via a data gating circuit in response to a write bit signal that has been deasserted and a first slave clock include a data latch circuit 730 having a data output (q) coupled to a data input (q) of a multiplexer 710 in response to a write bit signal; a multiplexer 710 having a data output coupled to a data input of a data gating circuit 720; and a data gating circuit 720 having a data output coupled to a data input of a data latch circuit 730.

[0097] Method 800 may further include providing an asserted write bit signal to the target slave latch. Examples of components for providing the asserted write bit signal to the target slave latch include any one of a second set of master latches 450-0 to 450-3, which are coupled to one of slave latches 430-00 to 430-33 via a corresponding one of the set of write bit lines WB0 to WB3, respectively.

[0098] Method 800 may further include providing a second set of data signals to the group of slave latches respectively. Examples of components for providing the second set of data signals to the group of slave latches include a first set of master latches 420-0 to 420-3, respectively coupled via the set of bit lines BL0 to BL3 to the respective columns of slave latches 430-00-430-30 to 430-03-430-33. Additionally, method 800 may include providing a second slave clock to the group of slave latches to write data to one or more of the group of slave latches based on one or more of the second set of data signals respectively. Examples of components used to provide a second slave clock to the group of slave latches to write data to one or more of the group of slave latches based on one or more of the second group of data signals include a corresponding one of the group of clock gate circuits (CGC) 410-0 to 410-3, which are coupled to a corresponding one of the row slave latches 430-00-430-03 to 430-30-430-33 via a corresponding one of the group of word lines WL0 to WL3.

[0099] Additionally, method 800 may include operating a target slave latch in response to an asserted write bit signal and a second slave clock to store data based on a corresponding one of a second set of data signals. Examples of components for operating a target slave latch in response to an asserted write bit signal and a second slave clock to store data based on a corresponding one of a second set of data signals include any of the slave latches 500, 600, and 700 discussed earlier.

[0100] The operation target of method 800 to store data from a latch may include passing a second clock to a data gating circuit and a data latch circuit in response to an asserted write bit signal. An example of components for passing a second clock to the data gating circuit and the data latch circuit in response to an asserted write bit signal includes a clock gating circuit 530 from latch 500.

[0101] The operation target of method 800 for storing data from a latch may include setting the data gating circuit to a non-gated state and the data latching circuit to an open state in response to an asserted write bit signal and a second slave clock. Examples of components for setting the data gating circuit to a non-gated state and the data latching circuit to an open state in response to an asserted write bit signal and a second slave clock include FETs M9 to M10 of data gating circuit 610 having gates coupled to the outputs of inverters 636 and 632, respectively; pairs of FETs M6-M7 having gates coupled to the outputs of inverters 632 and 636, respectively; FETs M2-M3 of data gating circuit 610 having gates coupled to the outputs of inverters 638 and 634, respectively; and pairs of FETs M6-M7 having gates coupled to the outputs of inverters 634 and 638, respectively.

[0102] The operational target of method 800 for storing data from a latch may include applying a corresponding one of a second set of data signals to a data gating circuit in response to an asserted write bit signal. Examples of components for applying a corresponding one of the second set of data signals to the data gating circuit in response to an asserted write bit signal include a multiplexer 710, which includes an input for receiving a data signal (d) and an output coupled to the data gating circuit 720, and is responsive to the write bit signal.

[0103] Figure 9 A block diagram illustrating an example wireless communication device 900 according to another aspect of this disclosure is shown. The wireless communication device 900 includes at least one antenna 960 (e.g., an antenna array), a transceiver 950 coupled to the at least one antenna 960, and an integrated circuit (IC) or system-on-a-chip (SOC) 910. The IC or SOC 910 further includes a latch array 920, and one or more signal processing cores 930 coupled to the latch array 920. The latch array 920 may be implemented as a latch array 400 including any of the latches 500, 600, and 700 previously discussed. One or more signal processing cores 930 are coupled to the transceiver 950.

[0104] Depending on the signal transmission application, one or more signal processing cores 930 may generate a transmit baseband (BB) signal based on data retrieved from a latch array 920. The one or more signal processing cores 930 provide the transmit baseband (BB) signal to a transceiver 950, which then generates a transmit radio frequency (RF) signal based on the transmit baseband (BB) signal. The transmit RF signal is provided to at least one antenna 960 for wireless transmission to one or more remote wireless devices.

[0105] According to the signal receiving application, at least one antenna 960 is configured to wirelessly receive received RF signals from one or more remote wireless devices. A transceiver 950 is configured to generate a received baseband (BB) signal in a second voltage domain based on the received RF signals. One or more signal processing cores 930 may be configured to process the received baseband (BB) signal to generate data. The one or more signal processing cores 930 may store the data in a latch array 920.

[0106] The following provides an overview of the various aspects of this disclosure:

[0107] Aspect 1: A latch array comprising: a first set of master latches, the first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches, the second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; and a slave latch array arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

[0108] Aspect 2: The latch array according to aspect 1 further includes a set of clock gating circuits, the set of clock gating circuits including a third set of clock inputs configured to receive the master clock and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines.

[0109] Aspect 3: The latch array according to Aspect 2, wherein each slave latch of the array comprises: a clock gating circuit including one of a second set of write bit inputs coupled to one of the set of write bit lines, one of a fourth set of clock inputs coupled to one of the set of word lines, and a complementary clock output; a data gating circuit including one of a second set of data inputs coupled to one of the set of bit lines, a first set of complementary clock inputs coupled to the complementary clock output of the clock gating circuit, and a first data output; and a data latch circuit including a second set of complementary clock inputs coupled to the complementary clock output of the clock gating circuit, a data input coupled to the first data output of the data gating circuit, and a second data output.

[0110] Aspect 4: A latch array according to Aspect 2, wherein each slave latch of the array comprises: a clock gating circuit comprising: a NOR gate, the NOR gate comprising a first input serving as a first input coupled to one of the second set of write bit inputs of the set of write bit lines, a second input serving as a second input coupled to one of the fourth set of clock inputs of the set of word lines, and an output; and a first inverter, the first inverter comprising an input coupled to the output of the NOR gate, and an output; a data gating circuit comprising: a first field-effect transistor (FET), the first FET comprising a first gate serving as a first gate coupled to one of the second set of data inputs of the set of bit lines; a second FET, the second FET comprising a second gate coupled to the output of the first inverter; a third FET, the third FET comprising a third gate coupled to the output of the NOR gate; and a fourth FET, the fourth FET comprising a third gate coupled to the first FET. The first gate of the ET has a fourth gate, wherein the first FET, the second FET, the third FET, and the fourth FET are series coupled between a first voltage rail and a second voltage rail; and a data latch circuit comprising: a fifth FET, the fifth FET including a fifth gate coupled to an output of the data latch circuit; a sixth FET, the sixth FET including a sixth gate coupled to the output of the NOR gate; a seventh FET, the seventh FET including a seventh gate coupled to the output of the first inverter; an eighth FET, the eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are series coupled between the first voltage rail and the second voltage rail; and a second inverter, the second inverter including an input coupled to a node between the sixth FET and the seventh FET, and an output coupled to the output of the data latch circuit.

[0111] Aspect 5: The latch array according to aspect 4, wherein the first FET, the second FET, the fifth FET and the sixth FET are p-channel metal-oxide-semiconductor field-effect transistors (PMOS FETs), and the third FET, the fourth FET, the seventh FET and the eighth FET are n-channel metal-oxide-semiconductor field-effect transistors (NMOS FETs).

[0112] Aspect 6: The latch array according to Aspect 2, wherein each slave latch of the array includes: a data gating circuit coupled to one of a second set of data inputs coupled to one of the set of bit lines, one of a fourth set of clock inputs coupled to one of the set of word lines, and one of a second set of write bit inputs coupled to one of the set of write bit lines, wherein the data gating circuit includes a first data output; and a data latch circuit coupled to the fourth set of clock inputs and the second set of write bit inputs, wherein the data latch circuit includes a data input coupled to the first data output of the data gating circuit and a second data output.

[0113] Aspect 7: A latch array according to Aspect 2, wherein each slave latch of the array includes: a signal buffer circuit, the signal buffer circuit including: a first inverter, the first inverter including an input and an output serving as a fourth set of clock inputs coupled to one of the word lines; a second inverter, the second inverter including an input and an output coupled to the output of the first inverter; a third inverter, the third inverter including an input and an output serving as a second set of write bit inputs coupled to one of the set of write bit lines; and a fourth inverter, the fourth inverter including an input and an output coupled to the third inverter. The inverter includes an input and an output; a data gating circuit comprising: a first field-effect transistor (FET) including a first gate coupled to one of the second set of data inputs coupled to one of the set of bit lines; a second FET including a second gate coupled to the output of the second inverter; a third FET including a third gate coupled to the output of the fourth inverter; a fourth FET including a fourth gate coupled to the output of the third inverter; a fifth FET including a fifth gate coupled to the output of the first inverter; a sixth FET including a sixth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FET are connected in series between a first voltage rail and a second voltage rail; and a data latch circuit comprising: a seventh FET including a seventh gate coupled to the output of the data latch circuit; a first pair of parallel FETs including gates coupled to the outputs of the first inverter and the third inverter, respectively. A first voltage rail, a second pair of parallel FETs, each including a gate coupled to the output of the second inverter and the fourth inverter, respectively; an eighth FET, each including an eighth gate coupled to the seventh gate of the seventh FET, wherein the seventh FET, the first pair of parallel FETs, the second pair of parallel FETs, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; and a fifth inverter, each including an input coupled to a node between the first pair of parallel FETs and the second pair of parallel FETs, and an output coupled to the output of the data latch circuit.

[0114] Aspect 8: The latch array according to aspect 7, wherein the first FET, the second FET, the third FET, the seventh FET and the first pair of parallel FETs each comprise a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET), and wherein the fourth FET, the fifth FET, the sixth FET, the eighth FET and the second pair of parallel FETs each comprise an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET).

[0115] Aspect 9: A latch array according to Aspect 2, wherein each slave latch of the array comprises: a multiplexer including one of a second set of data inputs coupled to one of the set of bit lines, one of a second set of write bit inputs coupled to one of the set of write bit lines, a first data input, and a first data output; a data gating circuit including a second data input coupled to the first data output of the multiplexer, and a second data output, wherein the data gating circuit is coupled to one of the fourth set of clock inputs coupled to one of the set of word lines; and a data latch circuit coupled to the fourth set of clock inputs, wherein the data latch circuit includes a third data input coupled to the second data output of the data gating circuit, and a third data output coupled to the first data input of the multiplexer.

[0116] Aspect 10: A latch array according to Aspect 2, wherein each slave latch of the array includes: a signal buffer circuit, the signal buffer circuit including: a first inverter, the first inverter including an input and an output serving as a coupling to one of the fourth set of clock inputs of the word lines; a second inverter, the second inverter including an input and an output coupled to the output of the first inverter; a third inverter, the third inverter including an input and an output serving as a coupling to one of the second set of write bit inputs of the set of write bit lines; and a fourth inverter, the fourth inverter including an input and an output coupled to the output of the third inverter; multiplexing The multiplexer includes: a first transmit gate, the first transmit gate including a first terminal coupled to one of a second set of data inputs coupled to one of the set of bit lines, a first set of complementary gates coupled to the outputs of the third inverter and the fourth inverter, and a second terminal; a second transmit gate, the second transmit gate including a third terminal, a second set of complementary gates coupled to the outputs of the third inverter and the fourth inverter, and a fourth terminal coupled to the second terminal to form an output; and a data gating circuit, the data gating circuit including: a first field-effect transistor (FET), the first FET including a first terminal coupled to the output of the multiplexer. A gate; a second FET, the second FET including a second gate coupled to the output of the second inverter; a third FET, the third FET including a third gate coupled to the output of the first inverter; and a fourth FET, the fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET and the fourth FET are series coupled between a first voltage rail and a second voltage rail; and a data latch circuit, the data latch circuit including: a fifth FET, the fifth FET including a fifth gate coupled to the output of the data latch circuit; and a sixth FET, the sixth FET including a fifth gate coupled to the first... The inverter has a sixth gate at its output; a seventh FET, the seventh FET including a seventh gate coupled to the output of the second inverter; an eighth FET, the eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET and the eighth FET are series coupled between the first voltage rail and the second voltage rail; and a fifth inverter, the fifth inverter including an input coupled to a node between the sixth FET and the seventh FET, and an output coupled to the output of the data latch circuit, wherein the output of the data latch circuit is coupled to the third terminal of the second transmit gate.

[0117] Aspect 11: The latch array according to aspect 10, wherein the first FET, the second FET, the fifth FET and the sixth FET each comprise a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET), and wherein the third FET, the fourth FET, the seventh FET and the eighth FET each comprise an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET).

[0118] Aspect 12: A latch array according to any one of Aspects 2 to 11, wherein the set of clock gating circuitry includes a set of enable inputs configured to receive a write address.

[0119] Aspect 13: The latch array according to any one of Aspects 1 to 12 further includes a set of multiplexers, the set of multiplexers including sets of inputs respectively coupled to the second set of data outputs from the latches of each column, a set of selection inputs configured to receive read addresses, and a third set of data outputs configured to generate the second set of data respectively.

[0120] Aspect 14: A method comprising: providing a de-asserted write bit signal to a target slave latch in a set of slave latches; providing a first set of data signals to the set of slave latches respectively; providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches respectively based on one or more of the first set of data signals; and while the first slave clock is causing the data to be written to one or more of the set of slave latches respectively based on one or more of the first set of data signals, operating the target slave latch in response to the de-asserted write bit signal to retain previously stored data.

[0121] Aspect 15: The method according to aspect 14, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein operating the target slave latch includes gating the first slave clock in response to the de-asserted write bit signal so that it is not applied to the data gating circuit and the data latch circuit.

[0122] Aspect 16: The method according to aspect 14, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein operating the target slave latch includes maintaining the data gating circuit in a gating state and closing the data latch circuit in response to the write bit signal that has been de-asserted.

[0123] Aspect 17: The method according to aspect 14, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein operating the target slave latch includes feeding back the previously stored data from the data output to the data input of the data latch circuit via the data gating circuit in response to the write bit signal that has been de-asserted and the first slave clock.

[0124] Aspect 18: The method according to any one of Aspects 14 to 17 further includes: providing an asserted write bit signal to the target slave latch; providing a second set of data signals to the set of slave latches respectively; providing a second slave clock to the set of slave latches to write data to at least the target slave latch based on a corresponding one of the second set of data signals respectively; and operating the target slave latch in response to the asserted write bit signal and the second slave clock to store data based on a corresponding one of the second set of data signals.

[0125] Aspect 19: The method according to aspect 18, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein operating the target slave latch to store the data includes passing a second slave clock to the data gating circuit and the data latch circuit in response to the asserted write bit signal.

[0126] Aspect 20: The method according to aspect 18, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein operating the target slave latch to store the data includes setting the data gating circuit to a non-gated state and setting the data latch circuit to an open state in response to the asserted write bit signal and the second slave clock.

[0127] Aspect 21: According to the method of aspect 18, wherein the target slave latch includes a data gating circuit and a data latching circuit, wherein operating the target slave latch to store the data includes passing the corresponding one of the second set of data signals to the data gating circuit in response to the asserted write bit signal.

[0128] Aspect 22: An apparatus comprising: means for providing a de-asserted write bit signal to a target slave latch in a set of slave latches; means for providing a first set of data signals to the set of slave latches respectively; means for providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches respectively based on one or more of the first set of data signals; and means for operating the target slave latch to retain previously stored data in response to the de-asserted write bit signal while the first slave clock is causing data to be written to one or more of the set of slave latches respectively based on one or more of the first set of data signals.

[0129] Aspect 23: The apparatus according to aspect 22, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein the component for operating the target slave latch includes a component for gating the first slave clock in response to the de-asserted write bit signal so that it is not applied to the data gating circuit and the data latch circuit.

[0130] Aspect 24: The apparatus according to aspect 22, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein the component for operating the target slave latch includes a component for maintaining the data gating circuit in a gated state and the data latch circuit in a closed state in response to the write bit signal that has been de-asserted.

[0131] Aspect 25: The apparatus according to aspect 22, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein the means for operating the target slave latch includes means for feeding back the previously stored data from the data output to the data input of the data latch circuit via the data gating circuit in response to the write bit signal that has been de-asserted and the first slave clock.

[0132] Aspect 26: The apparatus according to any one of aspects 22 to 25 further includes: means for providing an asserted write bit signal to the target slave latch; means for providing a second set of data signals to the set of slave latches respectively; means for providing a second slave clock to the set of slave latches to write data to at least the target slave latch based on a corresponding one of the second set of data signals respectively; and means for operating the target slave latch in response to the asserted write bit signal and the second slave clock to store data based on a corresponding one of the second set of data signals.

[0133] Aspect 27: The apparatus according to aspect 26, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein the component for operating the target slave latch to store the data includes passing a second slave clock to the data gating circuit and the data latch circuit in response to the asserted write bit signal.

[0134] Aspect 28: The apparatus according to aspect 26, wherein the target slave latch includes a data gating circuit and a data latch circuit, wherein the component for operating the target slave latch to store the data includes a component for setting the data gating circuit to a non-gated state and the data latch circuit to an open state in response to the asserted write bit signal and the second slave clock.

[0135] Aspect 29: The apparatus according to aspect 26, wherein the target slave latch includes a data gating circuit and a data latching circuit, wherein the component for operating the target slave latch to store the data includes a component for passing one of the corresponding second set of data signals to the data gating circuit in response to the asserted write bit signal.

[0136] Aspect 30: A wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a latch array coupled to the one or more signal processing cores, wherein the latch array comprises: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data respectively, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; and a slave latch array arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

[0137] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A latch array, comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of slave latches arranged in columns and rows, wherein the slave latches in the columns of the set of slave latches include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the set of slave latches include a fourth set of clock inputs respectively coupled to the set of word lines, wherein each slave latch of the set of slave latches includes: a clock gating circuit including one of the second set of write bit inputs coupled to one of the set of write bit lines, one of the fourth set of clock inputs coupled to one of the set of word lines, and a complementary clock output, a data gating circuit including one of the second set of data inputs coupled to one of the set of bit lines, a first set of complementary clock inputs respectively coupled to the complementary clock output of the clock gating circuit, and a first data output, and a data latch circuit including a second set of complementary clock inputs respectively coupled to the complementary clock output of the clock gating circuit, a data input coupled to the first data output of the data gating circuit, and a second data output.

2. The latch array of claim 1, wherein the set of clock gating circuits includes a set of enable inputs configured to receive a write address.

3. The latch array of claim 1, further comprising a set of multiplexers including respective sets of inputs respectively coupled to a second set of data outputs of the respective columns of slave latches, a set of select inputs configured to receive a read address, and a third set of data outputs configured to respectively produce a second set of data.

4. A latch array, comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of slave latches arranged in columns and rows, wherein the slave latches in the columns of the set of slave latches include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines; from latches, the from latches arranged in columns and rows, wherein the from latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs coupled to the set of write bit lines, respectively; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the from latches in the rows of the array include a fourth set of clock inputs coupled to the set of word lines, respectively, wherein each from latch of the array includes: a clock gating circuit including: a NOR gate including a first input serving as one of the second set of write bit inputs coupled to one of the set of write bit lines, a second input serving as one of the fourth set of clock inputs coupled to one of the set of word lines, and an output; and a first inverter including an input coupled to the output of the NOR gate, and an output; a data gating circuit including: a first field effect transistor (FET) including a first gate serving as one of the second set of data inputs coupled to one of the set of bit lines; a second FET including a second gate coupled to the output of the first inverter; a third FET including a third gate coupled to the output of the NOR gate; and a fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, and the fourth FET are coupled in series between a first voltage rail and a second voltage rail; and a data latch circuit including: a fifth FET including a fifth gate coupled to an output of the data latch circuit; a sixth FET including a sixth gate coupled to the output of the NOR gate; a seventh FET including a seventh gate coupled to the output of the first inverter; an eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; and a second inverter including an input coupled to a node between the sixth FET and the seventh FET, and an output coupled to the output of the data latch circuit.

5. The latch array of claim 4, wherein the first FET, the second FET, the fifth FET, and the sixth FET are p-channel metal-oxide-semiconductor field-effect transistors (PMOS FETs), and the third FET, the fourth FET, the seventh FET, and the eighth FET are n-channel metal-oxide-semiconductor field-effect transistors (NMOS FETs), respectively.

6. A latch array, comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of slave latches arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines, wherein each slave latch of the array includes: a data gating circuit coupled to one of the second set of data inputs coupled to one of the set of bit lines, one of the fourth set of clock inputs coupled to one of the set of word lines, and one of the second set of write bit inputs coupled to one of the set of write bit lines, wherein the data gating circuit includes a first data output; and a data latch circuit coupled to the one of the fourth set of clock inputs and the one of the second set of write bit inputs, wherein the data latch circuit includes a data input coupled to the first data output of the data gating circuit, and a second data output.

7. A latch array, comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of slave latches arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines, wherein each slave latch of the array includes: a data gating circuit coupled to one of the second set of data inputs coupled to one of the set of bit lines, one of the fourth set of clock inputs coupled to one of the set of word lines, and one of the second set of write bit inputs coupled to one of the set of write bit lines, wherein the data gating circuit includes a first data output; and a data latch circuit coupled to the one of the fourth set of clock inputs and the one of the second set of write bit inputs, wherein the data latch circuit includes a data input coupled to the first data output of the data gating circuit, and a second data output. from latches, the slave latches arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs coupled to the set of write bit lines, respectively; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs coupled to the set of word lines, respectively, wherein each slave latch of the array includes: a signal buffer circuit including: a first inverter including an input coupled to one of the fourth set of clock inputs coupled to one of the word lines, and an output; a second inverter including an input coupled to the output of the first inverter, and an output; a third inverter including an input coupled to one of the second set of write bit inputs coupled to one of the set of write bit lines, and an output; and a fourth inverter including an input coupled to the output of the third inverter, and an output; a data gating circuit including: a first field effect transistor (FET) including a first gate coupled to one of the second set of data inputs coupled to one of the set of bit lines; a second FET including a second gate coupled to the output of the second inverter; a third FET including a third gate coupled to the output of the fourth inverter; a fourth FET including a fourth gate coupled to the output of the third inverter; a fifth FET including a fifth gate coupled to the output of the first inverter; a sixth FET including a sixth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FET are coupled in series between a first voltage rail and a second voltage rail; and a data latch circuit including: a seventh FET including a seventh gate coupled to an output of the data latch circuit; a first pair of parallel FETs including gates coupled to the outputs of the first inverter and the third inverter, respectively; a second pair of parallel FETs including gates coupled to the outputs of the second inverter and the fourth inverter, respectively; an eighth FET including an eighth gate coupled to the seventh gate of the seventh FET, wherein the seventh FET, the first pair of parallel FETs, the second pair of parallel FETs, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; and a fifth inverter including an input coupled to a node between the first pair of parallel FETs and the second pair of parallel FETs, and an output coupled to the output of the data latch circuit.

8. The latch array of claim 7, wherein the first FET, the second FET, the third FET, the seventh FET, and the first pair of parallel FETs each comprise a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET), and wherein the fourth FET, the fifth FET, the sixth FET, the eighth FET, and the second pair of parallel FETs each comprise an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

9. A latch array, comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of slave latches arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines, wherein each slave latch of the array includes: a multiplexer including one of a second set of data inputs coupled to one of the set of bit lines, one of the second set of write bit inputs coupled to one of the set of write bit lines, a first data input, and a first data output; a data gating circuit including a second data input coupled to the first data output of the multiplexer, and a second data output, wherein the data gating circuit is coupled to one of the fourth set of clock inputs coupled to one of the set of word lines; and a data latch circuit coupled to the one of the fourth set of clock inputs, wherein the data latch circuit includes a third data input coupled to the second data output of the data gating circuit, and a third data output coupled to the first data input of the multiplexer.

10. A latch array, comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of slave latches arranged in columns and rows, wherein the slave latches in the columns of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines; and a set of clock gating circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines, wherein each slave latch of the array includes: a multiplexer including one of a second set of data inputs coupled to one of the set of bit lines, one of the second set of write bit inputs coupled to one of the set of write bit lines, a first data input, and a first data output; a data gating circuit including a second data input coupled to the first data output of the multiplexer, and a second data output, wherein the data gating circuit is coupled to one of the fourth set of clock inputs coupled to one of the set of word lines; and a data latch circuit coupled to the one of the fourth set of clock inputs, wherein the data latch circuit includes a third data input coupled to the second data output of the data gating circuit, and a third data output coupled to the first data input of the multiplexer. a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; a set of clock gate circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines, and a set of clock gate circuits including a third set of clock inputs configured to receive the master clock, and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs respectively coupled to the set of word lines, wherein each slave latch of the array includes: a signal buffer circuit including: a first inverter including an input coupled to one of the fourth set of clock inputs coupled to one of the word lines, and an output; a second inverter including an input coupled to the output of the first inverter, and an output; a third inverter including an input coupled to one of the second set of write bit inputs coupled to one of the set of write bit lines, and an output; and a fourth inverter including an input coupled to the output of the third inverter, and an output; a multiplexer including: a first pass gate including a first terminal coupled to one of the second set of data inputs coupled to one of the set of bit lines, a first set of complementary gates respectively coupled to the outputs of the third inverter and the fourth inverter, and a second terminal; a second pass gate including a third terminal, a second set of complementary gates respectively coupled to the outputs of the third inverter and the fourth inverter, and a fourth terminal coupled to the second terminal to form an output; and a data gate circuit including: a first field effect transistor (FET) including a first gate coupled to the output of the multiplexer; a second FET including a second gate coupled to the output of the second inverter; a third FET including a third gate coupled to the output of the first inverter; and a fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, and the fourth FET are coupled in series between a first voltage rail and a second voltage rail; and a data latch circuit including: a fifth FET including a fifth gate coupled to an output of the data latch circuit; a sixth FET including a sixth gate coupled to the output of the first inverter; a seventh FET including a seventh gate coupled to the output of the second inverter; an eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; and a fifth inverter including an input coupled to a node between the sixth FET and the seventh FET, and an output coupled to the output of the data latch circuit, wherein the output of the data latch circuit is coupled to the third terminal of the second pass gate.

11. The latch array of claim 10, wherein the first FET, the second FET, the fifth FET, and the sixth FET each comprise a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET), and wherein the third FET, the fourth FET, the seventh FET, and the eighth FET each comprise an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET).

12. A method performed by the latch array of one of claims 1-11, comprising: providing an un-asserted write bit signal to a target slave latch of a group of slave latches; providing a first set of data signals to the group of slave latches, respectively; providing a first slave clock to the group of slave latches to cause data to be written to one or more of the group of slave latches based on one or more of the first set of data signals, respectively; and operating the target slave latch to retain previously stored data in response to the un-asserted write bit signal while the first slave clock is causing data to be written to the one or more of the group of slave latches based on the one or more of the first set of data signals, respectively.

13. The method of claim 12, further comprising: providing an asserted write bit signal to the target slave latch; providing a second set of data signals to the group of slave latches, respectively; providing a second slave clock to the group of slave latches to cause data to be written to at least the target slave latch based on a corresponding one of the second set of data signals, respectively; and operating the target slave latch to store data based on the corresponding one of the second set of data signals in response to the asserted write bit signal and the second slave clock.

14. The method of claim 13, wherein operating the target slave latch to store the data comprises passing the second slave clock to the data gating circuit and the data latch circuit in response to the asserted write bit signal.

15. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and the latch array of one of claims 1-11. ​ ​

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