Microcontroller, operating system and control method

Abstract

A microcontroller, an operating system and a control method. The microcontroller is coupled to a sensing circuit. The sensing circuit generates a sensing signal. The microcontroller includes a processing circuit and an input / output circuit. The processing circuit generates an output signal according to the sensing signal. When the output signal is at a specific level, the processing circuit enables a reset signal. The input / output circuit includes a latch circuit and a counting circuit. The latch circuit latches the output signal to generate a latch signal. When the reset signal is enabled, the counting circuit starts to adjust a count value. When the count value is equal to a preset value, the counting circuit changes a level of the latch signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a microcontroller, an operating system and a control method, and more particularly to a microcontroller with an input / output circuit having a programmable time recovery function. BACKGROUND

[0002] With the advancement of technology, the types and functions of electronic devices are increasing. Generally, an electronic device has many electronic components inside. Most of the electronic components can operate in an operating mode or a power saving mode. In the operating mode, the electronic components are normally active. However, when the electronic components enter a power saving mode, the electronic components are temporarily inactive. At this time, the output signal of the electronic components can be fixed at a certain level. When the output signal of the electronic components is fixed at the same level for a long time, the subsequent circuit can not be able to operate normally. SUMMARY

[0003] An embodiment of the present application provides a microcontroller coupled with a sensing circuit. The sensing circuit generates a sensing signal. The microcontroller of the present application includes a processing circuit and an input / output circuit. The processing circuit generates an output signal according to the sensing signal. When the output signal is a certain level, the processing circuit enables a reset signal. The input / output circuit includes a latch circuit and a counting circuit. The latch circuit latches the output signal to generate a latch signal. When the reset signal is enabled, the counting circuit starts to adjust a count value. When the count value is equal to a preset value, the counting circuit changes the level of the latch signal.

[0004] The present application further provides an operating system including a sensing circuit, a microcontroller, a first inductive coil, a diode, a second inductive coil and a reading circuit. The sensing circuit is used to generate a sensing signal. The microcontroller includes a processing circuit and an input / output circuit. The processing circuit generates an output signal according to the sensing signal. When the output signal is a certain level, the processing circuit enables a reset signal. The input / output circuit includes a latch circuit and a counting circuit. The latch circuit latches the output signal to generate a latch signal. When the reset signal is enabled, the counting circuit starts to adjust a count value. When the count value is equal to a preset value, the counting circuit changes the level of the latch signal. The first inductive coil is used to sense an external signal and load the latch signal to the external signal to generate a load signal. The diode is coupled between the input / output circuit and the first inductive coil. The second inductive coil is used to output the external signal and receive the load signal. The reading circuit generates the external signal and operates according to the load signal.

[0005] The present application also provides a control method, which is suitable for an input / output circuit. The input / output circuit comprises a latch circuit and a counting circuit. The latch circuit latches an output signal to generate a latch signal. The control method of the present application comprises setting a preset value, wherein the preset value is stored in the counting circuit; performing a counting operation to adjust a counting value; judging whether the counting value is greater than the preset value; when the counting value is not greater than the preset value, disabling an overflow signal; and when the counting value is greater than the preset value, enabling the overflow signal to change the level of the latch signal.

[0006] The control method of the present application can be implemented by the microcontroller and the operating system of the present application, which are hardware or firmware capable of performing specific functions, or can be included in a storage medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded and executed by an electronic device, a processor, a computer or a machine, the electronic device, the processor, the computer or the machine become the microcontroller or the operating system for implementing the present application. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of the operating system of the present application.

[0008] Figure 2 FIG. 2 is a schematic diagram of the input / output circuit of the present application.

[0009] Figure 3 FIG. 3 is a control flowchart of the input / output circuit of the present application.

[0010] Figure 4 FIG. 4 is another schematic diagram of the operating system of the present application.

[0011] REFERENCE NUMERALS:

[0012] 100, 400: operating system

[0013] 110, 410: sensing circuit

[0014] 111: resistor

[0015] 112: capacitive sensor

[0016] 120, 420: microcontroller

[0017] 121, 123, 124, 421, 423, 424: input / output circuit

[0018] 122, 422: processing circuit

[0019] 130, 430: diode

[0020] 140, 150, 440, 450: inductive coil

[0021] 160, 460: reading circuit

[0022] SD: sensing signal

[0023] GND: ground source

[0024] SO: output signal

[0025] SRT: reset signal

[0026] SLH: latch signal

[0027] VC: charging voltage

[0028] VD: discharging voltage

[0029] SEX: external signal

[0030] SRY: load signal

[0031] 210: latch circuit

[0032] 220, 426: counting circuit

[0033] 211: D-type flip-flop

[0034] OC: overflow signal

[0035] CLK1, CLK2: clock signal

[0036] TCNT: count value

[0037] TOUT: preset value

[0038] 221: temporary register

[0039] 222: counter

[0040] 223, 425: comparison circuit

[0041] 230: buffer circuit

[0042] 231, 234, 235: inverter

[0043] 232: P-type transistor

[0044] 233: N-type transistor

[0045] 236: pin

[0046] VDD: operating voltage

[0047] SIV: inverting signal

[0048] IN: input signal

[0049] S311-S316: steps DETAILED DESCRIPTION

[0050] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below in conjunction with the accompanying drawings for detailed description. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0051] Figure 1 This is a schematic diagram of the operating system of the present invention. Figure 1 As shown, the operating system 100 includes a sensing circuit 110, a microcontroller 120, a diode 130, induction coils 140 and 150, and a readout circuit 160. The sensing circuit 110 generates a sensing signal SD. In one possible embodiment, the sensing circuit 110 has a sensor for sensing changes in a specific state, such as temperature, sound, light, or pressure. The present invention does not limit the architecture of the sensing circuit 110. In this embodiment, the sensing circuit 110 includes a resistor 111 and a capacitive sensor 112. The resistor 111 and the capacitive sensor 112 are connected in series between the microcontroller 120 and a ground source GND. When the physical phenomena of the external environment change, the capacitance of the capacitive sensor 112 changes accordingly. In one possible embodiment, the capacitive sensor 112 is a piezoelectric sensor.

[0052] The microcontroller 120 includes an input / output circuit 121 and a processing circuit 122. The processing circuit 122 generates an output signal SO based on a sensing signal SD. In this embodiment, when the output signal SO is at a specific level (such as a high level or a low level), the processing circuit 122 enables a reset signal SRT. After enabling the reset signal SRT, the processing circuit 122 may exit an operating mode and enter a power-down mode. In power-down mode, the processing circuit 122 is idle. Therefore, the processing circuit 122 stops providing the output signal SO. In other embodiments, when the processing circuit 122 receives a wake-up signal (not shown), the processing circuit 122 exits the power-down mode and enters an operating mode. In operating mode, the processing circuit 122 again generates the output signal SO based on the sensing signal SD. The present invention does not limit the architecture of the processing circuit 122. In one possible embodiment, the processing circuit 122 is a central processing unit (CPU).

[0053] The input / output circuit 121 latches the output signal SO to generate a latch signal SLH. In the present embodiment, the input / output circuit 121 performs a counting operation when the reset signal SRT is enabled. When the input / output circuit 121 performs the counting operation for a predetermined time, the input / output circuit 121 changes the level of the latch signal SLH. In a possible embodiment, the predetermined time is set by the processing circuit 122.

[0054] In the present embodiment, the processing circuit 122 enters a power saving mode whenever the processing circuit 122 generates the output signal SO. In the power saving mode, the processing circuit 122 is idle. At this time, since the output signal SO is temporarily stored in the input / output circuit 121, the input / output circuit 121 can maintain the level of the latch signal SLH even if the processing circuit 122 is idle. However, if the latch signal SLH is maintained at a certain level for a long time, subsequent circuits will malfunction, and therefore, before entering the power saving mode, the processing circuit 122 determines whether the level of the output signal SO is equal to a certain level (e.g., a high level or a low level). When the level of the output signal SO is equal to a certain level, the processing circuit 122 enables the reset signal SRT. The input / output circuit 121 performs a counting operation, and changes the level of the latch signal SLH after completing the counting operation.

[0055] For example, if the certain level is a low level, then when the processing circuit 122 outputs the output signal SO at a low level, the processing circuit 122 enables the reset signal SRT and enters the power saving mode. At this time, the input / output circuit 121 performs a counting operation, and changes the level of the latch signal SLH after completing the counting operation. Therefore, the latch signal SLH is not maintained at a low level for a long time. In this example, when the processing circuit 122 outputs the output signal SO at a high level, the processing circuit 122 enters the power saving mode without enabling the reset signal SRT. Therefore, the input / output circuit 121 stops performing a counting operation.

[0056] In other embodiments, the processing circuit 122 does not determine whether the level of the output signal SO is equal to a certain level. In this example, whenever the processing circuit 122 generates an output signal SO, the processing circuit 122 immediately enables the reset signal SRT and enters the power saving mode. When the reset signal SRT is enabled, the input / output circuit 121 performs a counting operation. When the input / output circuit 121 performs the counting operation for a predetermined time, the input / output circuit 121 changes the level of the latch signal SLH. Therefore, the latch signal SLH is not maintained at a high level or a low level for a long time.

[0057] In other embodiments, the microcontroller 120 further comprises an input / output circuit 123. In this case, the processing circuit 122 provides a charging voltage VC to the input / output circuit 123. The input / output circuit 123 outputs the charging voltage VC to the sensing circuit 110 for charging the capacitive sensor 112. The processing circuit 122 determines the amount of change of a particular state of the external environment based on the voltage change (i.e., the sensing signal SD) of the capacitive sensor 112.

[0058] In some embodiments, the microcontroller 120 further comprises an input / output circuit 124. The input / output circuit 124 is coupled to the sensing circuit 110 for receiving the sensing signal SD. The input / output circuit 124 provides the sensing signal SD to the processing circuit 122. The processing circuit 122 determines the amount of change of a particular state of the external environment based on the sensing signal SD. In other embodiments, the processing circuit 122 provides a discharging voltage VD to the input / output circuit 124. The input / output circuit 124 outputs the discharging voltage VD to the sensing circuit 110 for discharging the capacitive sensor 112.

[0059] In other embodiments, the microcontroller 120 further comprises a bus (not shown). The bus is coupled between the processing circuit 122 and the input / output circuits 121, 123 and 124. In this case, the processing circuit 122 transmits signals or voltages to the input / output circuits 121, 123 and 124 via the bus. In some embodiments, the bus has a plurality of transmission paths (not shown). Each transmission path is coupled between an input / output circuit (121, 123 or 124) and the processing circuit 122.

[0060] The diode 130 is coupled between the input / output circuit 121 and the inductive coil 140. The cathode of the diode 130 is coupled to the input / output circuit 121. The anode of the diode 130 is coupled to the inductive coil 140. The present application does not limit the type of the diode 130. In one possible embodiment, the diode 130 is a Zener diode.

[0061] The inductive coil 140 senses an external signal SEX and carries a latch signal SLH to the external signal SEX for generating a carried signal SRY. In one possible embodiment, the inductive coil 140 changes the amplitude of the external signal SEX based on the latch signal SLH. The changed signal is the carried signal SRY. In addition, the inductive coil 140 outputs the external signal SEX and receives the carried signal SRY. In one possible embodiment, the inductive coils 140 and 150 are antennas.

[0062] The reading circuit 160 generates an external signal SEX and outputs it through the induction coil 150. In this embodiment, the reading circuit 160 also receives a loading signal SRY through the induction coil 150. In this example, the reading circuit 160 operates according to the loading signal SRY. The reading circuit 160 may decode the loading signal SRY to determine the amount of change in a specific state, and then perform a corresponding action based on the amount of change, such as adjusting the volume of a speaker, displaying an image, or adjusting the brightness of a light source.

[0063] In some embodiments, the sensing circuit 110, microcontroller 120, diode 130, and sensing coil 140 are integrated into a peripheral input device, such as a mouse or touch panel. To detect changes in a specific state of the external environment, the microcontroller 120 decodes the sensing signal SD to generate an output signal SO. Therefore, the microcontroller 120 consumes a significant amount of power. To reduce power consumption, the microcontroller 120 immediately enters a power-saving mode after generating the output signal SO. In power-saving mode, the microcontroller 120 is idle. When the microcontroller 120 receives a wake-up signal, it leaves the power-saving mode and enters an operating mode. In operating mode, the microcontroller 120 decodes the sensing signal SD to generate a new output signal SO. After generating the new output signal SO, the microcontroller 120 re-enters the power-saving mode.

[0064] Figure 2 This is a schematic diagram of the input / output circuit 121 of the present invention. Figure 2 As shown, the input / output circuit 121 includes a latching circuit 210 and a counting circuit 220. The latching circuit 210 latches the output signal SO to generate a latching signal SLH. In this embodiment, the latching circuit 210 includes a D-type flip-flop 211. The D-type flip-flop 211 includes an input terminal D, a clock terminal CK, an output terminal Q, and a setting terminal SET. The input terminal D receives the output signal SO. The clock terminal CK receives a clock signal CLK2. The output terminal Q outputs the latching signal SLH. The setting terminal SET receives an overflow signal OC.

[0065] The present application is not limited to the source of the clock signal CLK2. In one possible embodiment, the clock signal CLK2 is provided by the processing circuit 122. In this embodiment, the processing circuit 122 provides the clock signal CLK2 to the D-type flip-flop 211 when the processing circuit 122 operates in an operational mode. Accordingly, the D-type flip-flop 211 reads the output signal SO according to the clock signal CLK2. For example, the D-type flip-flop 211 is triggered whenever the clock signal CLK2 changes from a first level to a second level. Accordingly, the D-type flip-flop 211 reads the output signal SO and provides the reading as the latch signal SLH. However, the processing circuit 122 stops providing the clock signal CLK2 to the D-type flip-flop 211 when the processing circuit 122 operates in a power saving mode. At this time, the D-type flip-flop 211 maintains the level of the latch signal SLH. The latch signal SLH can be maintained at a high level or a low level.

[0066] In other embodiments, the clock signal CLK2 is provided by a clock generation circuit (not shown). In this embodiment, the processing circuit 122 enables the clock generation circuit when the processing circuit 122 enters an operational mode. Accordingly, the clock generation circuit generates the clock signal CLK2. However, the processing circuit 122 does not enable the clock generation circuit when the processing circuit 122 enters a power saving mode. Accordingly, the clock generation circuit stops providing the clock signal CLK2. In some embodiments, the clock generation circuit can be integrated in the input / output circuit 121 or independent of the input / output circuit 121.

[0067] The counting circuit 220 is coupled to the latch circuit 210 and receives the reset signal SRT. When the reset signal SRT is enabled, the counting circuit 220 performs a counting operation. In one possible embodiment, the counting circuit 220 counts the number of pulses of a clock signal CLKl and adjusts a count value TCNT according to the counting result. In this embodiment, the frequency of the clock signal CLKl remains unchanged when the processing circuit 122 enters the operational mode and the power saving mode. Accordingly, the counting circuit 220 can operate normally even when the processing circuit 122 enters the power saving mode. In addition, the frequency of the clock signal CLKl is less than the frequency of the clock signal CLK2 when the processing circuit 122 enters the operational mode. However, the frequency of the clock signal CLKl is greater than the frequency of the clock signal CLK2 when the processing circuit 122 enters the power saving mode.

[0068] When the count value TCNT equals the preset value TOUT, it indicates that the time for the counting circuit 220 to perform the timing operation has reached a preset time. Therefore, the counting circuit 220 changes the level of the latch signal SLH. The present application does not limit how the counting circuit 220 changes the level of the latch signal SLH. In the present embodiment, when the count value TCNT equals the preset value TOUT, the counting circuit 220 enables the overflow signal OC. Since the set terminal SET of the D-type flip-flop 211 receives the overflow signal OC, the D-type flip-flop 211 changes the level of the latch signal SLH when the overflow signal OC is enabled. At this time, the latch signal SLH can change from a low level to a high level. In other embodiments, when the overflow signal OC is provided to a clear terminal (not shown) of the D-type flip-flop 211, the D-type flip-flop 211 changes the level of the latch signal SLH when the overflow signal OC is enabled. At this time, the latch signal SLH can change from a high level to a low level.

[0069] In the present embodiment, in order to reduce the power consumption of the processing circuit 122, after the processing circuit 122 generates the output signal SO, the processing circuit 122 enters a power saving mode. At this time, since the processing circuit 122 no longer provides the clock signal CLK2, the level of the latch signal SLH remains unchanged. However, when the level of the latch signal SLH remains unchanged for a long time, it can affect the operation of the subsequent circuit. Therefore, before entering the power saving mode, the processing circuit 122 first determines whether the output signal SO equals a specific level. If the output signal SO equals the specific level, the processing circuit 122 enables the reset signal SRT. After enabling the reset signal SRT, the processing circuit 122 enters the power saving mode. At this time, since the reset signal SRT is enabled, the counting circuit 220 starts adjusting the count value TCNT. When the count value TCNT equals the preset value TOUT, the counting circuit 220 changes the level of the latch signal SLH, such as changing from a low level to a high level, or changing from a high level to a low level.

[0070] The present application does not limit the architecture of the counting circuit 220. In the present embodiment, the counting circuit 220 includes a register 221, a counter 222, and a comparison circuit 223. The register 221 is used to store the preset value TOUT. In a possible embodiment, the processing circuit 122 writes the preset value TOUT into the register 221.

[0071] The counter 222 counts the number of pulses of the clock signal CLK1 to generate a count result, and uses the count result as the count value TCNT. In the present embodiment, when the reset signal SRT is enabled, the counter 222 resets the count value TCNT so that the count value TCNT equals an initial value, such as 0. Then, the counter 222 changes the count value TCNT according to the number of pulses of the clock signal CLK1.

[0072] The comparison circuit 223 compares the count value TCNT with the preset value TOUT. When the count value TCNT is greater than the preset value TOUT, the comparison circuit 223 enables the overflow signal OC. At this time, the overflow signal OC can be equal to a high level. However, when the count value TCNT is not greater than the preset value TOUT, the comparison circuit 223 does not enable the overflow signal OC. At this time, the overflow signal OC can be equal to a low level.

[0073] In other embodiments, the input / output circuit 121 further includes a buffer circuit 230. The buffer circuit 230 includes inverters 231, 234, 235, a P-type transistor 232, and an N-type transistor 233. The inverter 231 inverts the latch signal SLH to generate an inverted signal SIV. When the latch signal SLH is a low level, the inverted signal SIV is a high level. Thus, the N-type transistor 233 is turned on. At this time, the voltage of a pin 236 is equal to the voltage of the ground source GND, such as 0 V. However, when the latch signal SLH is a high level, the inverted signal SIV is a low level. Thus, the P-type transistor 232 is turned on. At this time, the voltage of the pin 236 is equal to an operating voltage VDD.

[0074] The input end of the inverter 234 is coupled to the pin 236. The output end of the inverter 234 is coupled to the input end of the inverter 235. The output end of the inverter 235 provides an input signal IN. In a possible embodiment, the inverter 235 provides the input signal IN to the processing circuit 122. In this case, the processing circuit 122 processes the sensing signal SD according to the input signal IN to generate the output signal SO.

[0075] In some embodiments, the buffer circuit 230 can be omitted. When the buffer circuit 230 is omitted, the output end Q of the D-type flip-flop 211 is directly coupled to the cathode of the diode 130. When the input / output circuit 121 has the buffer circuit 230, then the pin 236 is coupled to the cathode of the diode 130.

[0076] Figure 3 A flowchart of the control procedure of the input / output circuit 121 of the present application is shown. First, a preset value TOUT is set (step S311). In a possible embodiment, the preset value TOUT is provided by the processing circuit 122. In this case, the processing circuit 122 writes the preset value TOUT into the register 221.

[0077] Next, a counting operation is performed to adjust the count value TCNT (step S312). In one possible embodiment, the counter 222 starts to perform a counting operation when the processing circuit 122 enables the reset signal SRT. In this embodiment, each time the processing circuit 122 provides an output signal SO to the latch circuit 210, the processing circuit 122 determines whether to enable the reset signal SRT according to the output signal SO. When the level of the output signal SO is equal to a specific level, the processing circuit 122 enables the reset signal SRT. After enabling the reset signal SRT, the processing circuit 122 enters a power saving mode. However, when the level of the output signal SO is not equal to the specific level, the processing circuit 122 does not enable the reset signal SRT. At this time, the processing circuit 122 also enters the power saving mode. In this embodiment, since the processing circuit 122 does not enable the reset signal SRT, the counter 222 does not perform a counting operation. In other embodiments, the processing circuit 122 does not determine whether the level of the output signal SO is equal to the specific level. In this embodiment, each time the processing circuit 122 provides the output signal SO to the latch circuit 210, the processing circuit 122 immediately enables the reset signal SRT to instruct the counter 222 to perform a counting operation.

[0078] Next, it is determined whether the count value TCNT is greater than the preset value TOUT (step S313). When the count value TCNT is not greater than the preset value TOUT, the comparison circuit 223 does not enable the overflow signal OC (step S314), and returns to step S312 to continue the counting operation. However, when the count value TCNT is greater than the preset value TOUT, the comparison circuit 223 enables the overflow signal OC (step S315). Thus, the level of the latch signal SLH is changed (step S316). In one possible embodiment, the level of the latch signal SLH can be changed from a low level to a high level, or from a high level to a low level.

[0079] In some embodiments, when the processing circuit 122 enters an operation mode, the input / output circuit 121 performs step S311 to store the preset value TOUT. In the operation mode, the input / output circuit 121 latches the output signal SO generated by the processing circuit 122, and outputs the latch signal SLH. At this time, the latch signal SLH is equal to the output signal SO.

[0080] When the processing circuit 122 exits the operation mode and enters the power saving mode, the input / output circuit 121 starts to perform step S312. In the power saving mode, since the processing circuit 122 stops generating the output signal SO, the input / output circuit 121 maintains the level of the latch signal SLH according to the level of the last output signal provided by the processing circuit 122 before entering the power saving mode. If the latch signal SLH is maintained at a certain level for a long time, the subsequent circuit can malfunction. Therefore, the processing circuit 122 enables the reset signal SRT before entering the power saving mode, to command the input / output circuit 121 to change the level of the latch signal SLH after a preset time.

[0081] Figure 4 Another schematic diagram of the operating system of the present application is shown in FIG. 4. As shown, the operating system 400 includes a sensing circuit 410, a microcontroller 420, a diode 430, inductive coils 440, 450, and a reading circuit 460. Since the characteristics of the sensing circuit 410, the diode 430, the inductive coils 440, 450, and the reading circuit 460 are similar to those of the sensing circuit 110, the diode 130, the inductive coils 140, 150, and the reading circuit 160 of the operating system 100 of the present application, they are not described again. Figure 1

[0082] The microcontroller 420 includes input / output circuits 421, 423, 424, a processing circuit 422, a comparison circuit 425, and a counting circuit 426. The input / output circuit 421 receives the output signal SO and the reset signal SRT. The input / output circuit 421 latches the output signal SO to generate the latch signal SLH. When the reset signal SRT is enabled, the input / output circuit 421 changes the level of the latch signal SLH. Since the characteristics of the input / output circuit 421 are similar to those of the input / output circuit 121 of the operating system 100 of the present application, they are not described again. Figure 1

[0083] ​​The processing circuit 422 outputs the charging voltage VC to the sensing circuit 410 through the input / output circuit 423. The input / output circuit 424 receives the sensing signal SD and provides the sensing signal SD to the comparison circuit 425. The comparison circuit 425 compares the sensing signal SD with a reference signal vref to generate a comparison signal SCM. The present application does not limit the architecture of the comparison circuit 425. In one possible embodiment, the comparison circuit 425 is an analog comparator (ACMP). The counting circuit 426 calculates the time for the comparison signal SCM to reach a preset level from an initial level to generate a counting result. After generating the counting result, the counting circuit 426 sends an interrupt signal INT. The processing circuit 422 reads and processes the counting result generated by the counting circuit 426 according to the interrupt signal INT to generate the output signal SO. In this example, since the counting result generated by the counting circuit 426 is related to the sensing signal SD, which is related to the change of the physical quantity of the external environment, the processing circuit 422 can deduce the physical quantity of the external environment according to the counting result generated by the counting circuit 426.

[0084] In other embodiments, the microcontroller 420 further includes memories 427 and 428. The memory 427 is a non-volatile memory, such as a read only memory (ROM). The memory 428 is a volatile memory, such as a static random access memory (SRAM). The microcontroller 420 operates according to the program code stored in the memories 427 and 428.

[0085] The control method of the present application, or a specific form or part thereof, can exist in the form of program code. The program code can be stored in a physical storage medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or is not limited to an external form of computer program product, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes an input / output circuit participating in the present application. The program code can also be transmitted through some transmission medium, such as a wire or cable, an optical fiber, or any transmission form, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes an input / output circuit participating in the present application. When implemented in a general-purpose processing unit, the program code combines the processing unit to provide a unique device whose operation is similar to that of an application-specific logic circuit.

[0086] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein. Although the terms "first," "second," etc. can be used herein to describe various elements or

[0087] While the application has been described by way of example with reference to preferred embodiments, it is to be understood that persons skilled in the art can make modifications and improvements to the application without departing from the spirit and scope thereof. For example, the system, device or method described in the embodiments of the application can be implemented in hardware, software or a combination of hardware and software. The scope of the application is therefore to be limited only by the claims as set forth below.

Claims

1. A microcontroller, characterized by a sensing circuit coupled to generate a sensing signal, the microcontroller comprising: a processing circuit to generate an output signal based on the sensing signal, wherein the processing circuit enables a reset signal when the output signal is at a particular level; and an input / output circuit comprising: a latch circuit to latch the output signal to generate a latched signal; and a first counting circuit to start adjusting a count value when the reset signal is enabled, and to change a level of the latched signal when the count value is equal to a preset value.

2. The microcontroller of claim 1, wherein, The sensing circuit has a piezoelectric sensor.

3. The microcontroller of claim 1, wherein, The first counting circuit counts pulses of a first clock signal to adjust the count value when the reset signal is enabled.

4. The microcontroller of claim 3, wherein, The latch circuit comprises: a D-type flip-flop comprising an input terminal, a clock terminal, an output terminal, and a set terminal, the input terminal receives the output signal, the clock terminal receives a second clock signal, the output terminal outputs the latched signal, and the set terminal receives an overflow signal.

5. The microcontroller of claim 4, wherein, The first counting circuit enables the overflow signal to change the level of the latched signal when the count value is equal to the preset value.

6. The microcontroller of claim 4, wherein, The processing circuit exits an operation mode and enters a power saving mode after enabling the reset signal, in the operation mode, the processing circuit generates the output signal based on the sensing signal, and in the power saving mode, the processing circuit stops generating the output signal.

7. The microcontroller of claim 6, wherein, The processing circuit provides the second clock signal in the operation mode, and stops providing the second clock signal in the power saving mode.

8. An operating system, characterized by comprising: a sensing circuit to generate a sensing signal; a microcontroller comprising: a processing circuit to generate an output signal based on the sensing signal, wherein the processing circuit enables a reset signal when the output signal is at a particular level; and an input / output circuit comprising: a latch circuit to latch the output signal to generate a latched signal; and a first counting circuit to start adjusting a count value when the reset signal is enabled, and to change a level of the latched signal when the count value is equal to a preset value. a first inductive coil to sense an external signal, and to load the latched signal to the external signal to generate a loaded signal; a diode coupled between the input / output circuit and the first inductive coil; a second inductive coil to output the external signal, and to receive the loaded signal; and a reading circuit to generate the external signal, and to act based on the loaded signal.

9. The operating system of claim 8, wherein, further comprising: a comparison circuit to compare the sensing signal with a reference signal to generate a comparison signal; and a second counting circuit to calculate a time for the comparison signal to reach a preset level from an initial level to generate a count result; wherein the processing circuit processes the count result to generate the output signal. ​ 10. A control method characterized by, A control method is suitable for an input / output circuit, the input / output circuit includes a latch circuit and a counting circuit, the latch circuit latches an output signal to generate a latch signal, the control method includes: setting a preset value, wherein the preset value is stored in the counting circuit; when a reset signal is enabled, performing a counting operation to adjust a counting value, wherein the reset signal is enabled by a processing circuit, the processing circuit generates an output signal according to a sensing signal generated by a sensing circuit, when the output signal is a specific level, the processing circuit enables the reset signal; determining whether the counting value is greater than the preset value; when the counting value is not greater than the preset value, not enabling an overflow signal; and when the counting value is greater than the preset value, enabling the overflow signal to change the level of the latch signal.

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