Cpu power consumption control method for circuit board based on pcie interface for interface expansion

Abstract

The application discloses a CPU power consumption control method of a circuit board based on PCIE interface expansion, a storage medium and the circuit board. The circuit board comprises a CPU and a PCIE interface, the PCIE interface comprises at least two PCIE sub-interfaces, the CPU is internally provided with at least two PCIE controllers, a first PCIE controller is connected with a first part of PCIE sub-interfaces of the PCIE port, and a second PCIE controller is connected with a second part of PCIE sub-interfaces of the PCIE interface. The CPU power consumption control method comprises the following steps: A. receiving a user inputted disable control instruction, wherein the disable control instruction comprises disable information used for determining PCIE controllers to be disabled; and B. controlling the corresponding PCIE controllers to be disabled according to the disable control instruction. If all the PCIE sub-interfaces of a certain part are idle, the user can make the CPU execute the power consumption control method to control the corresponding PCIE controllers to be disabled, and no enable signal is sent to the idle PCIE sub-interfaces, so that the CPU power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a CPU power consumption control method, storage medium, and circuit board for a circuit board with interface expansion based on a PCIe interface. Background Technology

[0002] Circuit boards typically require various types of interfaces for connecting external devices. These interfaces are usually located around the edges of the circuit board for easy cable insertion. To minimize space usage, circuit boards need to maximize integration and reduce size. Since the placement of the edges is limited by the circuit board's size, a smaller board cannot accommodate the required number of interfaces. Therefore, the requirement for a certain number of interfaces restricts the miniaturization of circuit boards. Currently, there are four types of PCIe interfaces: x16, x8, x4, and x2. Some circuit boards need to accommodate multiple types of external devices with different PCIe interfaces, requiring multiple different types of PCIe interfaces to be placed on the board. This results in a large number of interfaces, making it difficult to reduce the circuit board size. To address this, the industry has proposed a PCIe interface expansion scheme. This scheme uses a CPU PCIe controller to route PCIe signals to an x16 PCIe slot, and then divides the x16 PCIe slot into one or more of the three types of PCIe interfaces: x8, x4, and x2. Specific combinations include: (1) two x8 PCIe sub-interfaces; (2) four x4 PCIe sub-interfaces; (3) one x8 PCIe sub-interface and two x4 PCIe sub-interfaces; (4) one x8 PCIe sub-interface, one x4 PCIe sub-interface, and two x2 PCIe sub-interfaces; and so on. Sometimes, the circuit board only needs to use some of the various PCIe sub-interfaces, leaving the remaining PCIe sub-interfaces idle. Since the CPU's PCIe controller controls all PCIe sub-interfaces, it sends enable signals to both the currently used and idle PCIe sub-interfaces. However, the idle PCIe sub-interfaces do not actually require enable signals, resulting in unnecessary power consumption for the CPU. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a CPU power consumption control method for a circuit board with interface expansion based on PCIe interface, a computer-readable storage medium storing a computer program that implements the method when executed, and a circuit board to which the method can be applied. The method can reduce CPU power consumption caused by idle PCIe sub-interfaces.

[0004] To address the aforementioned technical problems, this invention provides a CPU power consumption control method for a circuit board with interface expansion based on a PCIe interface, comprising the following steps executed by the CPU:

[0005] A. Receive user-input disable control command, which includes disable information for determining the PCIe controller to be disabled;

[0006] B. Disable the corresponding PCIe controller according to the disable control command.

[0007] Furthermore, the disabled information is either information about the idle sub-interface or information about the PCIe controller corresponding to the idle sub-interface.

[0008] The present invention also provides a computer-readable storage medium having an executable computer program stored thereon, which, when executed by a CPU, implements the CPU power consumption control method for a circuit board with interface expansion based on a PCIe interface as described above.

[0009] The present invention also provides a circuit board for interface expansion based on a PCIe interface, including a CPU and a PCIe interface. The PCIe interface includes at least two PCIe sub-interfaces. The CPU has at least two built-in PCIe controllers. The first PCIe controller is connected to the first part of the PCIe sub-interface of the PCIe port, and the second PCIe controller is connected to the second part of the PCIe sub-interface of the PCIe interface.

[0010] Furthermore, the system includes a PCIe conversion module. Specifically, the CPU's second PCIe controller is connected to the second part of the PCIe sub-interface of the PCIe port via this conversion module. Specifically, the PCIe controller is connected to the PCIe signal input terminal of the PCIe conversion module, and the PCIe signal output terminal of the PCIe conversion module is connected to the second part of the PCIe sub-interface of the PCIe interface. The PCIe interface also includes a USB sub-interface, and the PCIe conversion module correspondingly has a USB signal output terminal connected to this USB sub-interface. A PCIe to USB unit is connected between the PCIe signal input terminal and the USB signal output terminal of the PCIe conversion module.

[0011] Furthermore, the Phytium X100 chipset is used as the PCIe conversion module.

[0012] Furthermore, the PCIe interface is an X16 PICE slot.

[0013] Furthermore, the PCIe sub-interface is one or more of the following: x8 PCIe interface, x4 PCIe interface, and x2 PCIe interface.

[0014] Furthermore, the second PCIe controller is specifically connected to all the remaining PCIe sub-interfaces of the PCIe interface, and / or the CPU has two built-in PCIe controllers.

[0015] Further, it includes the computer-readable storage medium as described in claim 3, the computer-readable storage medium being connected to the CPU.

[0016] The circuit board provided in this invention has a CPU connected to different PCIe sub-interfaces of the PCIe interface through two PCIe controllers. If a certain number of PCIe sub-interfaces are all idle, the user can have the CPU execute the CPU power consumption control method described above to control the corresponding PCIe controller to disable it and not send an enable signal to the idle PCIe sub-interfaces, thereby reducing CPU power consumption. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of a circuit board for interface expansion based on a PCIe interface provided in this embodiment.

[0018] Figure 2 This is a pin diagram of the X16 PCIe slot provided in this embodiment. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments.

[0020] The circuit board structure for interface expansion based on the PCIe interface is as follows: Figure 1 As shown, it includes a CPU FT-2000 / 4 and an x16 PCIe slot (i.e., a PCIe interface). In this embodiment, the x16 PCIe slot is divided into one x8 PCIe sub-interface, one x4 PCIe sub-interface, one x2 PCIe sub-interface, and one USB sub-interface. Therefore, the signal pins of the x16 PCIe slot are as follows... Figure 2 As shown, the pin group is divided into X8 PCIe sub-interface pin group 1, X4 PCIe sub-interface pin group 2, X2 PCIe sub-interface pin group 3, and USB sub-interface pin group 4. Figure 1As shown, the CPU FT-2000 / 4 has two built-in PCIe controllers. The first PCIe controller is connected to the X8 PCIe sub-interface pin group 1 and X4 PCIe sub-interface pin group 2 of the X16 PCIe slot. The circuit board also includes a Phytium X100 chipset as a PCIe conversion module. The second PCIe controller is connected to the PCIe signal input terminal of the X100 chipset, and the PCIe signal output terminal of the X100 chipset is connected to the X2 PCIe sub-interface pin group 3 of the X16 PCIe slot. The X100 chipset has a USB signal output terminal, and a PCIe to USB unit is connected between the aforementioned PCIe signal input terminal and the USB signal output terminal. This USB signal output terminal is connected to the USB sub-interface pin group 4 of the X16 PCIe slot. The above is only one way of dividing the X16 PCIe slot into sub-interface combinations given in this embodiment. It can be changed to, for example, dividing it into 3 X4 PCIe sub-interfaces, 1 X2 PCIe sub-interface, and 1 USB sub-interface, or other division methods can be used.

[0021] The circuit board provided in this embodiment includes a computer-readable storage medium (not shown) connected to a CPU. This storage medium stores an executable computer program, which the CPU can execute to implement a CPU power consumption control method. The following example illustrates the execution process of the CPU power consumption control method on the above circuit board:

[0022] like Figure 1As shown, the X8 and X4 PCIe sub-interfaces of the X16 PCIe slot are in use, with pin groups 1 and 2 connected to the corresponding PCIe network cards. The X2 PCIe and USB sub-interfaces, however, are not connected to any external devices and are idle. In this situation, the X2 PCIe and USB sub-interfaces are controlled by a second PCIe controller. The user can send a disable command containing information about the second PCIe controller to the circuit board's communication module (not shown) via an external communication device. The CPU on the circuit board receives this disable command through the communication module and accordingly disables the second PCIe controller, preventing it from sending enable signals to the X2 PCIe and USB sub-interfaces, thus reducing CPU power consumption. This embodiment uses PCIe controller information as the disable information. However, this is not preferred; it can be replaced with information about idle sub-interfaces. Specifically, the power consumption control method pre-stores the correspondence between each sub-interface and the PCIe controller in a computer-readable storage medium. The user sends a disable command containing information about idle X2 PCIe sub-interfaces and USB sub-interfaces. The CPU receives this disable command, queries the correspondence between each sub-interface and the PCIe controller based on the information of the idle X2 PCIe and USB sub-interfaces, determines that the X2 PCIe and USB sub-interfaces correspond to a second PCIe controller, and then disables the second PCIe controller, preventing it from sending enable signals to the X2 PCIe and USB sub-interfaces, thus reducing CPU power consumption. Correspondingly, when the X8 PCIe and X4 PCIe sub-interfaces are idle, while the X2 PCIe and USB sub-interfaces are in use, the user can instruct the CPU to disable the first PCIe controller, preventing it from sending enable signals to the X8 and X4 PCIe sub-interfaces.

[0023] This embodiment uses an X16 PCIe slot for interface expansion. Instead of using the standard pin signal definitions for X16 PCIe, it mimics the standard pin signal definitions of X8, X4, X2, and USB interfaces. Pin groups for X8, X4, X2, and USB sub-interfaces are defined within the X16 PCIe slot, respectively. This allows for the creation of PCIe and USB sub-interfaces on the X16 PCIe slot, ensuring compatibility with both PCIe and USB bus protocols. This provides customers with the flexibility to choose between PCIe or USB sub-interfaces and simultaneously adapts to external devices or equipment using both PCIe and USB bus protocols, demonstrating high compatibility.

[0024] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection. Any non-substantial changes or substitutions made by those skilled in the art based on the present invention will still fall within the scope of patent protection.

Claims

1. A method for controlling CPU power consumption on a circuit board with interface expansion based on a PCIe interface, characterized by: The circuit board includes a CPU and a PCIe interface. The PCIe interface includes at least two PCIe sub-interfaces. The CPU has at least two built-in PCIe controllers. The first PCIe controller is connected to the first part of the PCIe sub-interface of the PCIe port, and the second PCIe controller is connected to the second part of the PCIe sub-interface of the PCIe port. The system includes a PCIe conversion module. Specifically, the CPU's second PCIe controller is connected to the second part of the PCIe sub-interface of the PCIe port via this conversion module. Specifically, the PCIe controller is connected to the PCIe signal input terminal of the PCIe conversion module, and the PCIe signal output terminal of the PCIe conversion module is connected to the second part of the PCIe sub-interface of the PCIe interface. The PCIe interface also includes a USB sub-interface, and the PCIe conversion module correspondingly has a USB signal output terminal connected to this USB sub-interface. A PCIe to USB unit is connected between the PCIe signal input terminal and the USB signal output terminal of the PCIe conversion module. The Phytium X100 chipset is used as the PCIe conversion module. The method includes the following steps executed by the CPU: A. Receive user input disable control command, which includes disable information for determining the PCIe controllers that need to be disabled, and the disable information is information about idle sub-interfaces; B. Based on the information of the idle sub-interface in the disable control instruction, query the correspondence between the sub-interface and the PCIe controller to determine the PCIe controller corresponding to the idle sub-interface, disable the PCIe controller, and do not send an enable signal to the aforementioned idle sub-interface to reduce CPU power consumption.

2. The CPU power consumption control method for a circuit board with interface expansion based on a PCIe interface as described in claim 1, characterized in that, The disabled information is either information about an idle sub-interface or information about the PCIe controller corresponding to the idle sub-interface.

3. The CPU power consumption control method for a circuit board with interface expansion based on a PCIe interface as described in claim 1, characterized in that, The PCIe interface is an x16 PICE slot.

4. The CPU power consumption control method for a circuit board with interface expansion based on a PCIe interface as described in claim 3, characterized in that, The PCIe sub-interface is one or more of the following: x8 PCIe interface, x4 PCIe interface, and x2 PCIe interface.

5. The CPU power consumption control method for a circuit board with interface expansion based on a PCIe interface as described in claim 1, characterized in that, The second PCIe controller is specifically connected to all the remaining PCIe sub-interfaces of the PCIe interface, and / or the number of built-in PCIe controllers in the CPU is two.

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