FPGA-based nandflash autonomous bad block management method and system

Abstract

The application provides a FPGA-based Nandflash autonomous bad block management method and system, comprising the following steps: 1, when the chip is shipped, performing bad block factory search; 2, maintaining bad block information; 3, performing block address mapping; 4, performing mutual exclusion scheduling on the Nandflash interface. The application moves the bad block management to the FPGA to reduce the burden of the CPU, so that the CPU can better complete other system-level tasks, fully utilizes the advantages of the FPGA fast response and parallel processing, and efficiently and reliably completes the storage playback function of the Nandflash.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of bad block management, in particular to a Nandflash autonomous bad block management method and system based on FPGA. BACKGROUND

[0002] The CPU and FPGA are commonly used as core architecture of a spaceborne computer to complete functions such as storage and control on the satellite. In the past functional framework, the Nandflash is used as a storage device, and the interface logic control of erasing, reading and writing is completed by the FPGA, and the CPU completes the control of the storage data and the reliability control (redundancy design or bad block management) of the Nandflash.

[0003] The patent document CN104765695A (application number: CN201510158107.3) discloses a NAND FLASH bad block management system, which comprises a NAND FLASH interface control unit, a bad block management unit, a non-volatile memory interface control unit and a non-volatile memory. The NAND FLASH interface control unit is connected with a NAND FLASH array, the NAND FLASH interface control unit is connected with the bad block management unit, and the bad block management unit is connected with the non-volatile memory through the non-volatile memory interface control unit. The non-volatile memory is an EEPROM. The bad block management unit is based on FPGA.

[0004] With the increasing complexity of the functions on the satellite, the work burden of the CPU is also increasing. Moving the bad block management to the FPGA for implementation not only reduces the burden of the CPU and enables the CPU to better complete other system-level tasks, but also fully utilizes the advantages of the FPGA in fast response and parallel processing, and efficiently and reliably completes the storage playback function of the Nandflash. The present application solves the specific problems of how to implement the functions such as bad block factory search, bad block information maintenance and block address dynamic mapping of the Nandflash on the satellite in the FPGA. SUMMARY

[0005] In view of the defects in the prior art, the present application aims to provide a Nandflash autonomous bad block management method and system based on FPGA.

[0006] The Nandflash autonomous bad block management method based on FPGA provided by the present application comprises the following steps.

[0007] Step 1: performing bad block factory search when the chip is factory-finished;

[0008] Step 2: maintaining the bad block information;

[0009] Step 3: performing block address mapping;

[0010] Step 4: mutual exclusive scheduling for Nandflash interface.

[0011] Preferably, the step 1 comprises:

[0012] Marking the first page of each bad block at Byte 4096 with a mark value of 0x00 and a normal value of 0xFF.

[0013] After chip initialization and before erase programming, all blocks of the Nandflash are searched and retrieved; the block index number information corresponding to 0x00 is stored in the non-bad block block0.

[0014] Preferably, the step 2 comprises:

[0015] Step 2.1: a BLOCK RAM space is opened for caching and updating bad block list information, and the bad block index number in block0 is moved to the random access memory RAM for address mapping.

[0016] Step 2.2: during the process of the fixed operation, the state reading is performed after erasing or page programming, according to the device manual, when the bit0 of the state word is 1, it indicates that the operation fails, and it is considered that there is a new bad block, the first page Byte 4096 of the block is written with 0x00 as the mark of the bad block information according to the way of the chip factory, and the bad block information in block0 is updated after re-searching the bad block.

[0017] Preferably, the step 3 comprises: storing the bad block index number information in BlockRAM according to the address from low to high, and initializing the RAM to fill with all 1 data, and when the module works, the data is read out from address 0, and the original block index number is compared with it, if it is greater than or equal to the data output Dout of the RAM, the read address is added by 1, and the comparison is continued, until it is less than Dout, the loop is stopped, and finally the mapped index number is the original block index number plus the read address of the RAM plus 1.

[0018] Preferably, the step 4 comprises:

[0019] Step 4.1: setting the channel number polling through FPGA to receive access requests;

[0020] Step 4.2: when the current channel is idle, responding to the access request to give an access response, at this time the channel occupies the use right of Nandflash;

[0021] Step 4.3: when the Nandflash operation is completed, the use right of the current channel is released.

[0022] The FPGA-based Nandflash autonomous bad block management system provided by the application comprises:

[0023] Module M1: bad block factory search is performed when the chip is factory-produced;

[0024] Module M2: bad block information is maintained;

[0025] Module M3: block address mapping is performed;

[0026] Module M4: Nandflash interface is mutually scheduled.

[0027] Preferably, the module M1 comprises:

[0028] The first page of each bad block is marked, the marking position is Byte 4096, the marking value is 0x00, and the normal value is 0xFF;

[0029] After the chip is initialized, all blocks of the Nandflash are searched, and then the block index number information corresponding to 0x00 is stored in the non-bad block block 0.

[0030] Preferably, the module M2 comprises:

[0031] Module M2.1: a BLOCK RAM space is opened for caching and updating bad block list information, the bad block index number in the block 0 is moved to the random access memory RAM, so as to be used in address mapping;

[0032] Module M2.2: during the process of the fixed operation, the state reading is performed after erasing or page programming, according to the device manual, when the state word bit 0 is 1, it is indicated that the operation fails, it is considered that there is a new bad block, the first page Byte 4096 of the block is written with 0x00 as a bad block information mark in the way of the chip factory production, after the marking is completed, the bad block is searched again, and the bad block information in the block 0 is updated.

[0033] Preferably, the module M3 comprises: the bad block index number information is stored in the BlockRAM according to the address from low to high, and the RAM is initialized to fill all 1 data, in the module work, the data is read out according to the address from 0, the original block index number is compared with Dout, if greater than or equal to the data output Dout of the RAM, the read address is added by 1, the comparison is continued, until it is less than Dout, the cycle is stopped, and finally the index number mapped is the original block index number plus the read address of the RAM and then plus 1.

[0034] Preferably, the module M4 comprises:

[0035] Module M4.1: the channel number polling is set through the FPGA, and the access request is received;

[0036] Module M4.2: when the current channel is idle, give access response in response to the access request, at this time the channel occupies the Nandflash use permission;

[0037] Module M4.3: when the Nandflash operation is completed, release the use permission of the current channel.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] (1) The present application moves the bad block management to FPGA to realize, which not only reduces the burden of CPU, makes it better to complete other system level tasks, but also makes full use of the advantages of FPGA fast response and parallel processing, and efficiently and reliably completes the storage playback function of Nandflash;

[0040] (2) The present application solves the specific problems of how to implement the bad block factory search, bad block information maintenance, block address dynamic mapping and other functions of Nandflash on FPGA. BRIEF DESCRIPTION OF DRAWINGS

[0041] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments with reference to the attached drawings:

[0042] Figure 1 is a work flow chart of the present application;

[0043] Figure 2 is a block address mapping working principle diagram. DETAILED DESCRIPTION

[0044] The present application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be pointed out that, for those skilled in the art, without departing from the concept of the present application, a number of changes and improvements can be made. These all belong to the protection scope of the present application.

[0045] Embodiment:

[0046] In addition to realizing the basic initialization, erasing, page programming, page reading and other basic interface timing of Nandflash (Nand flash, which is a kind of flash memory), the present application also needs to complete the bad block management and related functions:

[0047] (1) bad block factory search;

[0048] (2) bad block information maintenance;

[0049] (3) block address mapping;

[0050] (4) Mutual scheduling of Nandflash interface.

[0051] The workflow diagram of the present application is shown in Figure 1 The specific method of the present application is divided into the following steps:

[0052] 1. Bad block traversal search (BBCHK);

[0053] Taking MT29F8G08 as an example, the first page of each bad block is marked when the chip is shipped, the marking position is Byte 4096, and the marking value is 0x00, and the normal value is 0xFF.

[0054] After the chip is initialized, before erasing and programming, all blocks of the Nandflash need to be searched; then the block index number information searched to 0x00 is stored in block0, because block0 will not be a bad block.

[0055] 2. Bad block information maintenance:

[0056] (1) Update bad block list (UPDATE);

[0057] FPGA will allocate a BLOCK RAM space for caching bad block list information. The purpose of updating the bad block list is to move the bad block index number in block0 to the random access memory RAM for use in the subsequent address mapping.

[0058] (2) Mark bad block (MARK);

[0059] During the process of the solid state operation, after erasing or page programming, a step of reading the state will follow. According to the device manual, when the read state bit0 is '1', it indicates that the operation fails, and it is considered that there is a new bad block. At this time, the first page Byte 4096 of the block will be written with 0x00 as a bad block information mark in a similar way as the chip is shipped. After the marking is completed, the bad blocks will be searched again, and the bad block information in block0 will be updated.

[0060] 3. Block address mapping (BLOCKMAP);

[0061] The purpose of block address mapping is to bypass the bad block and provide a usable block index number for subsequent solid state operation. The working principle of the module is shown in Figure 2

[0062] ​The bad block index number information is stored in the BlockRAM in address from low to high, and the RAM is initialized to fill all '1' data, and when the module works, the data is read out from address 0, that is, the index number of the first bad block, and the original block index number is compared with the data output Dout of the RAM, if it is greater than or equal to Dout, the read address is added by 1, that is, the index number of the second bad block is read out, the comparison is continued, and when it is less than Dout, the loop is stopped, and finally the mapped index number is the original block index number plus the read address of the RAM and +1.

[0063] For example, if the RAM stores two bad block index numbers 6 and 10, if the accessed block index number is 3, after the mapping of the module, the index number becomes 4, because block0 is used to store the bad block information and is occupied, and the index number is added by 1.

[0064] If the accessed block index number is 7, after the mapping of the module, the index number becomes 9.

[0065] 4, mutual scheduling of Nandflash interface;

[0066] In order to meet the needs of multiple channels to access the Nandflash, the access interface of the Nandflash needs to be mutually scheduled, such as setting a virtual channel 8, which can meet the needs of 8 users to simultaneously access and use the Nandflash, and the scheduling of the channel is completed through time-sharing mutual exclusion.

[0067] (1) access request (CHN_REQ);

[0068] The FPGA sets the channel number polling, and can receive the access request.

[0069] (2) access response (CHN_ACK);

[0070] When the current channel is idle, the access request is responded, and the access response is given, and at this time, the channel occupies the use right of the Nandflash.

[0071] (3) access switching (CHN_SW);

[0072] When the Nandflash operation is completed, the use right of the current channel is released.

[0073] According to the Nandflash self bad block management system based on FPGA provided by the application, the module M1 is used for performing bad block factory search when the chip is factory-produced, the module M2 is used for maintaining the bad block information, the module M3 is used for performing block address mapping, and the module M4 is used for mutually scheduling the Nandflash interface.

[0074] The module M1 includes: marking at the first page of each bad block, the marking position is Byte 4096, the marking value is 0x00, and the normal value is 0xFF; after the chip is initialized, the all blocks of the Nandflash are searched and retrieved before being erased and programmed; and then the block index number information corresponding to 0x00 retrieved is stored in the non-bad block block0. The module M2 includes: module M2.1: opening a BLOCK RAM space for caching and updating the bad block list information, moving the bad block index number in the block0 to the random access memory RAM, so as to use in address mapping; module M2.2: during the process of the solid storage operation, reading the state after being erased or programmed, according to the device manual, when the bit0 of the state word is 1, it indicates that the operation fails, and it is considered that there is a new bad block, the first page Byte 4096 of the block is written with 0x00 as the bad block information mark according to the way of the chip factory, after the marking is completed, the bad block is searched and retrieved again, and the bad block information in the block0 is updated. The module M3 includes: storing the bad block index number information in the BlockRAM according to the address from low to high, and initializing the RAM to fill all 1 data, when the module works, the data is read out from 0 according to the address, the original block index number is compared with it, if it is greater than or equal to the data output Dout of the RAM, the read address is added by 1, the comparison is continued, until it is less than Dout, the loop is stopped, and finally the mapped index number is the original block index number plus the read address of the RAM plus 1. The module M4 includes: module M4.1: setting the channel number polling through the FPGA, receiving the access request; module M4.2: when the current channel is idle, responding to the access request, giving the access response, at this time, the channel occupies the use right of the Nandflash; module M4.3: when the Nandflash operation is completed, releasing the use right of the current channel.

[0075] Those skilled in the art know that, in addition to implementing the system, device and each module thereof provided by the present application in the form of pure computer readable program code, the same program can also be realized in the form of logic gate, switch, special integrated circuit, programmable logic controller and embedded microcontroller by logically programming the method steps. Therefore, the system, device and each module thereof provided by the present application can be considered as a hardware component, and the modules included therein for realizing various programs can also be considered as structures in the hardware component; the modules for realizing various functions can also be considered as both software programs for realizing methods and structures in the hardware component.

[0076] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be combined with each other at will without conflict.

Claims

1. A method for autonomous bad block management of Nandflash based on FPGA, characterized in that, include: Step 1: Perform a factory defect detection during chip manufacturing; Step 2: Maintain bad block information; Step 3: Perform block address mapping; Step 4: Perform mutual exclusion scheduling on the Nandflash interface; Step 1 includes: Mark each bad block on the first page of the block, at position Byte4096, with a mark value of 0x00; the normal value is 0xFF. After chip initialization and before erase programming, all blocks of the Nandflash are traversed and searched; then the block index number information corresponding to 0x00 is stored in the non-bad block block0. Step 2 includes: Step 2.1: Allocate a block RAM space to cache and update bad block list information, and move the bad block index number in block0 to the random access memory RAM for use during address mapping; Step 2.2: During the solid-state operation, after erasing or page programming, the status is read. According to the device datasheet, when the status word bit0 is read as 1, it indicates that the operation has failed and it is considered that a new bad block has been added. Write 0x00 to the first page Byte4096 of the block as a bad block information marker according to the chip's factory method. After marking, re-traverse the bad blocks and update the bad block information in block0. Step 3 includes: storing bad block index information in BlockRAM from low to high address, and initializing the RAM with all 1s. When the module is working, data is read from address 0 and compared with the original block index. If the data is greater than or equal to the data in the RAM, output Dout. Then, the read address is incremented by 1, and the comparison continues until it is less than Dout. The final mapped index is the original block index plus the read address of the RAM plus 1. Step 4 includes: Step 4.1: Poll via FPGA using the channel number to receive access requests; Step 4.2: When the current channel is idle, respond to the access request and provide an access response. At this time, the channel occupies the Nandflash usage rights. Step 4.3: When the Nandflash operation is complete, release the usage rights of the current channel.

2. An FPGA-based autonomous bad block management system for Nandflash, characterized in that, include: Module M1: Performs a factory defect detection for bad blocks when the chip leaves the factory; Module M2: Maintains bad block information; Module M3: Performs block address mapping; Module M4: Performs mutual exclusion scheduling on the Nandflash interface; The module M1 includes: Mark each bad block on the first page of the block, at position Byte4096, with a mark value of 0x00; the normal value is 0xFF. After chip initialization and before erase programming, all blocks of the Nandflash are traversed and searched; then the block index number information corresponding to 0x00 is stored in the non-bad block block0. The module M2 includes: Module M2.1: Allocates a block RAM space for caching and updating bad block list information, and moves the bad block index number in block0 to random access memory RAM for use during address mapping; Module M2.2: During the solid-state operation, after erasure or page programming, the status is read. According to the device datasheet, when the status word bit0 is read as 1, it indicates that the operation has failed and that a new bad block has been added. The first page Byte4096 of the block is written with 0x00 as a bad block information marker, according to the chip's factory method. After marking, the bad blocks are retraced and the bad block information in block0 is updated. The module M3 includes: storing bad block index information in BlockRAM in ascending order of address, and initializing the RAM with all 1s; when the module is working, reading data starting from address 0, comparing it with the original block index; if the data is greater than or equal to the data in the RAM, outputting Dout, then incrementing the read address by 1, and continuing the loop comparison until it is less than Dout, then stopping the loop; the final mapped index is the original block index plus the read address in the RAM plus 1. Therefore, module M4 includes: Module M4.1: Polls via FPGA channel number settings to receive access requests; Module M4.2: When the current channel is idle, it responds to access requests and provides an access response. At this time, the channel occupies the Nandflash usage rights. Module M4.3: Releases the usage rights of the current channel when the Nandflash operation is complete.

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