A method and device for refreshing a cache memory

Abstract

The present application provides a method and apparatus for refreshing a cache. In the present application, when it is necessary to refresh the cache, if it is detected that there is no full stripe in the cache, dirty cache blocks are obtained from the cache, and the configured refresh valid linked list is used to find all the refresh valid cache blocks in the same stripe as the dirty cache blocks, so as to form a full stripe or a non-full stripe with the obtained dirty cache blocks, and based on the formed full stripe or non-full stripe, the full stripe or non-full stripe is written to the RAID. After completing the writing of the full stripe or non-full stripe to the RAID, the data stored in the cache blocks within the full stripe or non-full stripe is kept valid, and the refresh valid linked list is updated based on the cache blocks within the full stripe or non-full stripe. It can be seen that the present application can reduce the overhead caused by stripe conflicts and data read-back under the RAID and improve the availability of the cache.

Description

Technical Field

[0001] This application relates to the field of storage, and particularly to a method and device for refreshing a cache memory CACHE. Background Art

[0002] Currently, in a storage device, when a LUN (Logical Unit Number) receives a write request, it first writes the data requested by the write request into the CACHE, rather than directly writing it into the RAID (Redundant Array of Independent Disks) and the disk. When a set condition is reached, the CACHE constructs a refresh write request to asynchronously refresh the cached data to the RAID, and the RAID then writes it to the disk through the RAID algorithm. In this way, the high-speed cache characteristics of the CACHE can be fully utilized to solve the problem of insufficient disk read and write performance, thereby improving the overall performance of the storage. However, when the pressure on the front-end to process read and write requests is relatively high, the CACHE needs to be continuously refreshed to receive new read and write requests. However, the refresh performance will affect the performance of the entire storage device in processing read and write requests. In a storage device, since data needs to be written to the disk through the RAID, the composition and algorithm of the RAID also have a great impact on the refresh performance of the CACHE.

[0003] In related technical solutions, the dirty data in the write CACHE is usually refreshed to the RAID when the dirty CACHE blocks reach a set ratio according to a set refresh mechanism, or when the dirty CACHE blocks written into the CACHE reach a set aging time, so that after the written dirty CACHE blocks are refreshed, the data stored in these written dirty CACHE blocks is initialized, and the written dirty CACHE blocks are correspondingly released and become idle CACHEs to be provided for newly received read and write requests to use. It can be seen that in the above technical solutions, the written dirty CACHE blocks are released after the dirty data is written to the disk through refreshing and cannot be hit by subsequent read and write requests. They can only be used to reapply for reading or writing new data. In fact, the data in the CACHE is still valid. Such an implementation method of the CACHE that becomes idle after being released greatly reduces the availability of the CACHE.

[0004] In addition, after the dirty CACHE blocks reach the set ratio, the dirty CACHE blocks are flushed to the RAID. When the RAID processes the read and write requests sent by the CACHE, for the full stripes sent by the CACHE, they will be directly written to the disk. For the non-full stripes sent by the CACHE, the read and write requests need to be split according to the RAID stripes first, and it is necessary to determine whether there is a stripe conflict between the split read and write requests and the read and write requests being processed, and whether the size of the write request is stripe-aligned. Multiple access requests with stripe conflicts need to be executed serially, and the unaligned write requests will trigger a write penalty, resulting in multiple read-backs and parity writes, thus reducing the processing efficiency of the read and write requests and increasing the RAID processing stripe overhead. Summary of the Invention

[0005] In view of this, the present application provides a method and device for flushing a cache memory (CACHE), so as to improve the availability of the CACHE while reducing the RAID processing stripe overhead.

[0006] Specifically, the present application is implemented through the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a method for flushing a cache memory (CACHE), which is applied to a storage device. The method includes:

[0008] When it is necessary to flush the CACHE, if it is detected that there is no full stripe in the CACHE, dirty CACHE blocks are obtained from the CACHE, and valid data identifiers associated with all the refreshed valid CACHE blocks within the same stripe as the dirty CACHE blocks are searched in the configured refreshed valid linked list, so as to use the refreshed valid CACHE blocks associated with the searched valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe; the refreshed valid linked list includes valid data identifiers, and the valid data identifiers are used to associate the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are flushed;

[0009] It is determined whether there is a formed full stripe in the CACHE. If there is, the full stripe is written to the RAID. After the full stripe is written to the RAID, the data stored in the CACHE blocks within the full stripe is kept valid, and the valid data identifiers in the refreshed valid linked list are updated based on the CACHE blocks within the full stripe;

[0010] If not, the formed non-full stripe is written to the RAID. After the non-full stripe is written to the RAID, the data stored in the CACHE blocks within the non-full stripe is kept valid, and the valid data identifiers in the refreshed valid linked list are updated based on the CACHE blocks within the non-full stripe.

[0011] Second aspect, an embodiment of the present application provides a cache (CACHE) refreshing device, which is applied to a storage device. The device includes:

[0012] A stripe construction unit, configured to, when it is necessary to refresh the CACHE, if it is detected that there is no full stripe in the CACHE, obtain dirty CACHE blocks from the CACHE, and find valid data identifiers associated with all refreshed valid CACHE blocks in the same stripe as the dirty CACHE blocks from a configured refreshed valid linked list, so as to use the refreshed valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe; determine whether there is a formed full stripe in the CACHE, if so, trigger a first full stripe refreshing unit, if not, trigger a non-full stripe refreshing unit; the refreshed valid linked list includes valid data identifiers, and the valid data identifiers are used to associate the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are refreshed;

[0013] The first full stripe refreshing unit is configured to write the full stripe to the RAID, after completing writing the full stripe to the RAID, keep the data stored in the CACHE blocks in the full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks in the full stripe;

[0014] The non-full stripe refreshing unit is configured to write the formed non-full stripe to the RAID, after completing writing the non-full stripe to the RAID, keep the data stored in the CACHE blocks in the non-full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks in the non-full stripe.

[0015] As can be seen from the above, the embodiments of the present application provide a method for refreshing a cache. In the present application, when it is necessary to refresh the cache, if it is detected that there is no full stripe in the cache, the dirty cache block is obtained from the cache, and the configured refresh valid linked list is used to find all the refresh valid cache blocks in the same stripe as the dirty cache block, so as to form a full stripe or a non-full stripe with the obtained dirty cache block, and write the full stripe or the non-full stripe to the RAID based on the formed full stripe or non-full stripe. After completing the writing of the full stripe or the non-full stripe to the RAID, the data stored in the cache blocks within the full stripe or the non-full stripe is kept valid, and the refresh valid linked list is updated based on the cache blocks within the full stripe or the non-full stripe. It can be seen that the technical solution provided by the embodiments of the present application uses the configured refresh valid linked list for recording the refresh valid cache blocks after the dirty cache blocks in the cache are refreshed, to form a full stripe or a non-full stripe with the single cache block being refreshed and the refresh valid cache blocks recorded in the refresh valid linked list, so that when writing to the RAID, more full stripe writes can be performed, reducing the overhead caused by stripe conflicts and data read-back under the RAID, enabling the cache to be recycled, having higher availability, and optimizing the performance of cache disk flushing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram showing a full stripe;

[0017] Figure 2 is a flowchart of a method for refreshing a cache according to an exemplary embodiment of the present application;

[0018] Figure 3 is a schematic structural diagram of a full stripe structure according to an exemplary embodiment of the present application;

[0019] Figure 4 is a schematic structural diagram of a non-full stripe structure according to an exemplary embodiment of the present application;

[0020] Figure 5 is a flowchart of a method for processing a read request according to an exemplary embodiment of the present application;

[0021] Figure 6 is a flowchart of a method for processing a write request according to an exemplary embodiment of the present application;

[0022] Figure 7 is a schematic structural diagram of a cache refreshing device according to an exemplary embodiment of the present application;

[0023] Figure 8This is a schematic structural diagram of an electronic device provided by this application. Detailed implementation manners

[0024] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0025] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0026] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0027] Currently, in storage devices, the data in a LUN is ultimately mapped to disks through set logical relationships. However, due to the slow read and write speeds of disks, the performance requirements of business read and writes cannot be met. Usually, read and write CACHEs are allocated for LUNs according to performance requirements to cache the data of LUNs. When a LUN receives a write request, it first writes the data requested by the write request into the CACHE, rather than directly writing it into the RAID (Redundant Array of Independent Disks) and disks. When the set conditions are met, the CACHE constructs a flush write request to asynchronously flush the cached data to the RAID, and the RAID then writes it to the disk through the RAID algorithm. In this way, the high-speed caching characteristics of the CACHE can be fully utilized to solve the problem of insufficient disk read and write performance, thereby improving the overall performance of storage. However, when the pressure on the front-end to process read and write requests is high, the CACHE needs to be continuously refreshed to receive new read and write requests. However, the performance of the refresh will affect the performance of the entire storage device in processing read and write requests. In storage devices, since data needs to be written to disks through the RAID, the composition and algorithm of the RAID also have a great impact on the refresh performance of the CACHE.

[0028] RAID usually consists of multiple data disks and parity disks. Taking a RAID composed of 5 disks as an example, as Figure 1 shown, a stripe contains four fixed-size data blocks H1, data block H2, data block H3, and data block H4, and also contains a parity block P of the same size. The parity blocks in different stripes (such as Figure 1 the hatched blocks in) are discretely distributed on different physical disks according to the set rules. The parity data is obtained by performing an exclusive OR operation on the four data blocks in the same stripe. If data is to be written to data block H1, it is necessary to first read out the other 3 data blocks in the same stripe and then calculate the parity data. However, if complete data is written to H1, H2, H3, and H4 at the same time, no old data needs to be read, and the corresponding new parity can be calculated using the new data. Such a write is called a "full stripe write".

[0029] The process of the RAID handling write requests is as follows: The CACHE refreshes and constructs read / write requests and sends them to the RAID. The RAID will check whether the read / write request conflicts with the stripe of the read / write request being processed. If so, it will wait for the conflicting read / write being processed to complete. If not, it will check the stripe alignment situation to determine whether the read / write request is stripe-aligned. If so, it will perform verification according to the RAID algorithm and read / write the disk. If not, it will perform a read-back and verify according to the RAID algorithm. It can be seen that if a read / write request is stripe-aligned, that is, it forms a full stripe, it can reduce the overhead of stripe conflicts and data read-back. For the RAID and the disk, it is the most efficient and has the best performance. Therefore, based on the above analysis, when the CACHE refreshes, full stripe write I / O should be formed as much as possible and sent to the RAID, which has the least overhead and the best performance for the RAID.

[0030] In the related technical solutions, the dirty data written into the CACHE is usually refreshed to the RAID according to the set refresh mechanism when the dirty CACHE blocks reach the set proportion, or when the dirty CACHE blocks written into the CACHE reach the set aging time, so that after the written dirty CACHE blocks are refreshed, the data stored in these written dirty CACHE blocks is initialized, and the written dirty CACHE blocks are correspondingly released and become idle CACHEs to be provided for newly received read / write requests. The specific process is as follows: When the CACHE refreshes, the CACHE will judge whether there is a full stripe. If not, it will take out a dirty CACHE block and brush it into the RAID in a non-full stripe. After brushing, it will release the CACHE block and set the CACHE block to invalid. If so, it will brush it into the RAID in a full stripe. After brushing, it will release the CACHE block and set the CACHE block to invalid. It can be seen that in the above technical solutions, the written dirty CACHE blocks are released after writing the dirty data into the disk through refreshing and cannot be hit by subsequent read / write requests. They can only be used to re-apply for reading or writing new data. In fact, the data in the CACHE is still valid. This implementation method of the CACHE that becomes idle after being released greatly reduces the availability of the CACHE.

[0031] In addition, after the dirty CACHE blocks reach the set ratio, the dirty CACHE blocks are flushed to the RAID. When the RAID processes the read and write requests sent by the CACHE, for the full stripes sent by the CACHE, they will be directly written to the disk. For the non-full stripes sent by the CACHE, the read and write requests need to be split according to the RAID stripes first, and it is necessary to determine whether there is a stripe conflict between the split read and write requests and the read and write requests being processed, and whether the size of the write request is aligned with the stripe. Multiple access requests with stripe conflicts need to be executed serially, and the unaligned write requests will trigger a write penalty, and multiple readbacks and verification writes will be performed, thus reducing the processing efficiency of the read and write requests and increasing the stripe overhead of the RAID processing.

[0032] To solve the above technical problems, an embodiment of the present application provides a method for flushing a cache memory CACHE, which is applied to a storage device. The method includes: when it is necessary to flush the CACHE, if it is detected that there is no full stripe in the CACHE, obtain the dirty CACHE blocks from the CACHE, and find the valid data identifiers associated with all the refreshed valid CACHE blocks within the same stripe as the dirty CACHE blocks from the configured refreshed valid linked list, so as to use the refreshed valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe; the refreshed valid linked list includes valid data identifiers, and the valid data identifiers are used to associate the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are flushed; determine whether there is a formed full stripe in the CACHE. If so, write the full stripe to the RAID. After completing the writing of the full stripe to the RAID, keep the data stored in the CACHE blocks within the full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks within the full stripe; if not, write the formed non-full stripe to the RAID. After completing the writing of the non-full stripe to the RAID, keep the data stored in the CACHE blocks within the non-full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks within the non-full stripe.

[0033] As can be seen from the above, the technical solution provided by the embodiment of the present application uses the configured refreshed valid linked list for recording the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are flushed, to form a full stripe or a non-full stripe for the single CACHE block being refreshed and the refreshed valid CACHE blocks recorded in the refreshed valid linked list, so that more full stripe writes can be performed when writing to the RAID, reducing the overhead caused by stripe conflicts and data readbacks under the RAID, enabling the CACHE to be recycled, having higher availability, and optimizing the performance of CACHE disk flushing.

[0034] The above CACHE refresh method will be described with specific embodiments as follows:

[0035] Refer to Figure 2 , Figure 2 which is a flowchart of a method for refreshing a cache memory CACHE shown in an embodiment of the present application. This method is applied to a storage device.

[0036] The above Figure 2 shown flowchart includes the following steps:

[0037] Step 201, when it is necessary to refresh the CACHE, if it is detected that there is no full stripe in the CACHE, then step 202 is executed.

[0038] In this step, no full stripe in the CACHE is detected, which means that the full stripes in the CACHE have been flushed or do not exist. In such a case, step 202 is executed.

[0039] As an embodiment, if it is detected that there is a full stripe in the CACHE, the full stripe is written to the RAID. After completing the writing of the full stripe to the RAID, the data stored in the CACHE blocks within the full stripe is kept valid, and the valid data identifier in the refresh valid linked list is updated based on the CACHE blocks within the full stripe.

[0040] In the present application, the refresh valid linked list includes valid data identifiers, which are used to associate the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are refreshed.

[0041] In practical applications, the data stored in the CACHE blocks after the CACHE blocks within the full stripe are written to the RAID is still valid and can be recycled. Based on this, the concept of a refresh valid linked list is introduced in the embodiments of the present application.

[0042] It can be seen that in the embodiments of the present application, after writing the full stripe to the RAID, the data stored in the CACHE blocks within the full stripe is still kept valid, and the refresh valid linked list is updated based on the CACHE blocks within the full stripe to supplement the refreshed valid CACHE blocks in the refresh valid linked list, so that the refresh valid linked list can obtain sufficient refreshed valid CACHE blocks for subsequent construction of full stripes or non-full stripes.

[0043] Step 202, obtain the dirty CACHE blocks from the CACHE, and find the valid data identifiers associated with all the refreshed valid CACHE blocks in the same stripe as the dirty CACHE blocks from the configured refresh valid linked list, so as to use the refreshed valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe.

[0044] The dirty CACHE block in this embodiment is a CACHE block for storing data in the CACHE. There are many ways to obtain the dirty CACHE block from the CACHE. For example, according to the configured dirty data linked list, the dirty data linked list includes dirty data block identifiers, and the dirty data block identifiers are used to associate the dirty CACHE blocks storing dirty data in the CACHE. Based on the dirty data linked list, select the dirty data block identifier, and obtain the dirty CACHE block associated with the selected dirty data block identifier from the CACHE. It is also possible to obtain the dirty CACHE block from the CACHE according to the configured dirty data file. The above-mentioned dirty data linked list or dirty data file is used to record the dirty CACHE blocks storing dirty data in the CACHE.

[0045] The dirty CACHE block in this embodiment can be one or at least two. If it is one dirty CACHE block, this embodiment will not limit it further. Subsequently, it will be described in detail how to obtain the dirty CACHE block from the CACHE, and this dirty CACHE block is a valid CACHE block.

[0046] All the CACHE blocks obtained from the CACHE in this step are single CACHE blocks of non-full stripes, and all the refreshed valid CACHE blocks in the same stripe as the dirty CACHE block are found from the configured refreshed valid linked list, and the found refreshed valid CACHE blocks are supplemented into the stripe to which the CACHE block being refreshed belongs. If a full stripe can be completed, a full stripe brush can be constructed. If a full stripe cannot be completed, a non-full stripe brush is still constructed. Compared with before constructing the non-full stripe, there is more valid CACHE data in the constructed non-full stripe, and the read-back loss of the RAID can still be reduced, thereby reducing the overhead of the RAID.

[0047] Step 203, determine whether there is a formed full stripe in the CACHE. If so, execute step 204. If not, execute step 205.

[0048] Step 204, write the full stripe to the RAID. After completing writing the full stripe to the RAID, keep the data stored in the CACHE blocks in the full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks in the full stripe.

[0049] After writing the full stripe to the RAID in this step, the data stored in these written dirty CACHE blocks is not initialized, that is, the data stored in the CACHE blocks within the stripe is not released, so as to keep the data stored in the CACHE blocks within the full stripe valid. At the same time, the valid data identifiers in the refresh valid linked list are updated based on the valid data in the CACHE blocks within the full stripe, so that the valid data identifiers in the refresh valid linked list are more abundant and sufficient, so as to be able to read more valid data into the refresh valid CACHE subsequently, in order to construct full stripes and non-full stripes when using the refresh CACHE.

[0050] Step 205: Write the formed non-full stripe to the RAID. After writing the non-full stripe to the RAID, keep the data stored in the CACHE blocks within the non-full stripe valid, and update the valid data identifiers in the refresh valid linked list based on the CACHE blocks within the non-full stripe.

[0051] After writing the non-full stripe to the RAID in this step, the data stored in these written dirty CACHE blocks is not initialized, that is, the data stored in the CACHE blocks within the stripe is not released, so as to keep the data stored in the CACHE blocks within the full stripe valid. At the same time, the valid data identifiers in the refresh valid linked list are updated based on the CACHE blocks within the non-full stripe, so that the valid data identifiers in the refresh valid linked list are more abundant and sufficient, so as to be able to read more valid data into the refresh valid CACHE subsequently, in order to construct full stripes and non-full stripes when using the refresh CACHE.

[0052] Thus far, the Figure 2 process steps are completed.

[0053] As can be seen from the above, the embodiments of the present application provide a method for refreshing a cache. In the present application, when it is necessary to refresh the cache, if it is detected that there is no full stripe in the cache, a dirty cache block is obtained from the cache, and a configured refresh valid linked list is used to find all the refresh valid cache blocks in the same stripe as the dirty cache block, so as to form a full stripe or a non-full stripe with the obtained dirty cache block. Then, based on the formed full stripe or non-full stripe, the full stripe or non-full stripe is written to the RAID. After completing the writing of the full stripe or non-full stripe to the RAID, the data stored in the cache blocks within the full stripe or non-full stripe is kept valid, and the refresh valid linked list is updated based on the cache blocks within the full stripe or non-full stripe. It can be seen that the technical solution provided by the embodiments of the present application uses a configured refresh valid linked list for recording the refresh valid cache blocks after the dirty cache blocks in the cache are refreshed, to form a full stripe or a non-full stripe with the single cache block being refreshed and the refresh valid cache blocks recorded in the refresh valid linked list, so that more full stripe writes can be performed when writing to the RAID, reducing the overhead caused by stripe conflicts and data read-back under the RAID, enabling the cache to be recycled, having higher availability, and optimizing the performance of cache disk flushing.

[0054] After completing Figure 2 the steps performed, as an embodiment, the specific steps for implementing obtaining a dirty cache block from the cache in step 201 include:

[0055] Step A, select the dirty data block identifier associated with the valid dirty cache block recorded in the same stripe from the configured dirty data linked list, and obtain the associated dirty cache block from the cache based on the selected dirty data block identifier.

[0056] The dirty cache block in this embodiment can be one or at least two, and this embodiment does not limit this.

[0057] The dirty cache blocks associated with the dirty data block identifiers in the dirty data linked list are all unrefreshed cache blocks, that is, the cache blocks not written to the RAID.

[0058] If there is only one dirty CACHE block to be refreshed, the currently needed dirty CACHE block can be directly obtained from the CACHE. Alternatively, based on the dirty data block identifier in the dirty data linked list already configured in the CACHE, the currently needed dirty CACHE block can be directly obtained from the CACHE using the hyperlink available in the dirty data linked list. If there are at least two dirty CACHE blocks to be refreshed, select and obtain the dirty data table identifiers of the dirty CACHE blocks that are located in the same stripe record and are valid from the dirty data linked list already configured in the CACHE, and based on the selected dirty data block identifiers, obtain the associated dirty CACHE blocks from the CACHE, and then perform step B. For the dirty data block identifiers associated with each dirty CACHE block that cannot be found in the CACHE to obtain the dirty CACHE blocks located in the same stripe record, step B can be performed based on the stripe where the current single dirty CACHE block is located.

[0059] Based on step A, the specific steps to implement finding, in the already configured refresh valid linked list, the valid data identifiers associated with all the refresh valid CACHE blocks in the same stripe as the dirty CACHE block in step 201, so as to use the refresh valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe may include:

[0060] Step B: Based on the logical address LBA of the logical unit number LUN corresponding to the obtained dirty CACHE block, find, in the already configured refresh valid linked list, the valid data identifiers associated with all the refresh valid CACHE blocks in the same stripe as the dirty CACHE block, obtain all the refresh valid CACHE blocks associated with the found valid data identifiers from the CACHE, and according to the LBA of the LUN corresponding to all the obtained refresh valid CACHE blocks, fill in all the obtained refresh valid CACHE blocks into the stripe to which the obtained dirty CACHE block belongs to form a full stripe or a non-full stripe.

[0061] A stripe is composed of multiple CACHE blocks with consecutive LBAs. There are two conditions for forming a full stripe. One condition is that all CACHE blocks in the stripe can be found, and the other is that the data in all CACHE blocks must be completely valid. Assume that a full stripe is composed of n CACHE blocks, and the LBAs of these n CACHE blocks corresponding to the LUN are consecutive. If the LBA (Logical Block Address) of the first CACHE block in a stripe is L1, then the LBA (L2) of the second CACHE block is L1 + the size of the CACHE block, and so on. The LBA (Ln) of the nth CACHE block is L1 + the size of the CACHE block * (n - 1), where n is the serial number of the CACHE blocks in a stripe. For exampleFigure 3 As shown, the dirty CACHE linked list includes the identifiers of dirty data blocks. According to the LBA corresponding to the dirty CACHE block associated with the identifier of the dirty data block, such as the CACHE block D1 with LBA L1, the CACHE block D3 with LBA L3,..., the CACHE block Ds with LBA Ls, where s is the serial number of the CACHE block recorded in the dirty CACHE linked list. Based on refreshing the valid data identifiers in the valid CACHE linked list, the dirty CACHE blocks associated with these valid data identifiers are obtained. The LBAs of the LUNs corresponding to these obtained refreshed valid CACHE blocks are, such as the refreshed valid CACHE block FV1 with LBA L2, the refreshed valid CACHE block FV2 with LBA L4,..., the refreshed valid CACHE block FVg with LBA Lg, where g is the serial number of the refreshed valid CACHE block recorded in the refreshed valid CACHE linked list. Taking n as 4 as an example, during refreshing, first, the identifiers of dirty data blocks within the same stripe are obtained from the dirty CACHE linked list, and the dirty CACHE blocks D1 and D2 associated with these dirty data blocks are determined. The corresponding LBAs are L1 and L3 respectively, and all the data stored in the dirty CACHE blocks D1 and D2 are valid. The valid data identifiers associated with the refreshed valid CACHE blocks whose LBAs corresponding to the dirty CACHE blocks D1 and D2 are within the same stripe are searched from the refreshed valid linked list. Based on these valid data identifiers, the refreshed valid CACHE blocks FV1 and FV2 are obtained from the CACHE, and according to the LBAs of the LUNs corresponding to all the obtained refreshed valid CACHE blocks, the refreshed valid CACHE blocks FV1 and FV2 are supplemented in the stripe where the dirty CACHE blocks D1 and D2 are located. In this way, the dirty CACHE block D1, the refreshed valid CACHE block FV1, the dirty CACHE block D2, and the refreshed valid CACHE block FV2 can form a full stripe. The currently refreshed single CACHE or non-full stripe can be formed into a full stripe with the refreshed valid CACHE and then sent to the RAID under this solution.

[0062] The technical solution for using the refreshed valid CACHE linked list to form a non-full stripe is as Figure 4As shown, still taking n = 4 as an example. During the refresh, first, based on the dirty data block identifiers in the dirty CACHE linked list, the dirty CACHE block D3 associated with the dirty data block identifier within the same stripe is retrieved from the CACHE, and the corresponding LBA is L4. Since a full stripe consists of 4 CACHEs at this time, the dirty CACHE block D3 cannot form a full stripe. Then, the valid data identifier associated with the refreshed valid CACHE block FV3 located in the same stripe as the dirty CACHE block D3 is found in the refreshed valid CACHE linked list. All the refreshed valid CACHE blocks associated with the found valid data identifier are obtained from the CACHE, and the LBA of the LUN corresponding to the refreshed valid CACHE block associated with the valid data identifier is determined, such as L3. The respective LBAs of the dirty CACHE block D3 and the refreshed valid CACHE block are L3 and L4, and all the data in the dirty CACHE block D3 and the refreshed valid CACHE block FV3 are valid. At this time, the dirty CACHE block D3 and the refreshed valid CACHE block FV3 can form a non-full stripe.

[0063] It should be noted that if all the CACHE blocks within the stripe are found, but the data stored in these CACHE blocks are not all valid, a read / write request for a full stripe cannot be formed either.

[0064] As an embodiment, as Figure 5 shown, before step 201, the method further includes the following steps:

[0065] Step 2011, receive a read request. If all the data requested to be read by the read request hits the first refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list, then execute step 2012; if part of the data requested to be read by the read request hits the second refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list, then execute step 2013.

[0066] All the data requested to be read by the read request hits the first refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list, which means that all the data requested to be read by the read request is in the refreshed valid CACHE block and can be directly obtained from the CACHE.

[0067] The first refreshed valid CACHE block and the second refreshed valid CACHE block do not specifically refer to two fixed refreshed valid CACHE blocks, but can be any two refreshed valid CACHE blocks on the CACHE. This will not be repeated in the subsequent embodiments of this application.

[0068] The read request hits the second refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list for the data part to be read by the read request. This means that part of the data to be read by the read request is in the CACHE, and the remaining part has been refreshed by the CACHE and sent to the RAID.

[0069] Step 2012, read the valid data stored in the first refreshed valid CACHE block from the CACHE.

[0070] Step 2013, read the valid data stored in the second refreshed valid CACHE block, and read the first target data in the data to be read by the read request that does not hit the refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list from the RAID, store the first target data in the specified refreshed valid CACHE block, and update the valid data identifier in the refreshed valid linked list based on the refreshed valid CACHE block where the first target data has been stored.

[0071] The first target data is only named for the convenience of distinguishing it from other target data in the following text, and is not used to limit a certain target data.

[0072] For the case of partial misses, this also means that part of the data is not in the refreshed valid CACHE block, and the missed data needs to be obtained from the RAID and stored in the refreshed valid CACHE block. In this way, the valid data in the refreshed valid CACHE is replenished so that more valid data can be read out to the refreshed valid cache later, in order to make up more full stripes.

[0073] In this embodiment, the first target data and the data read from the second refreshed valid CACHE block are the data to be read by the read request.

[0074] The technical solution of refreshing after the read request uses the refreshed valid CACHE can be understood as follows: if the read request hits the refreshed valid CACHE linked list, if all the data to be read by the read request is stored in the CACHE, directly return the data to be read by the read request; if all the data to be read by the read request is not stored in the CACHE, then new data will be read from the RAID into the refreshed valid CACHE block so that more valid data can be saved in the CACHE. During the refresh, steps 201 to 205 can still be followed to form a full stripe or a non-full stripe with the dirty CACHE blocks to be refreshed in the same stripe using the refreshed valid CACHE block.

[0075] As another embodiment, if all the data requested to be read by a read request misses the valid refresh linked list, then read the data requested to be read by the read request from the RAID, store the read data in a specified valid refresh CACHE block, and update the valid data identifier in the valid refresh linked list based on the valid refresh CACHE block storing the read data. This embodiment can supplement the valid data in the valid refresh CACHE.

[0076] Thus, in the technical solution provided by this embodiment, a read request hitting and using a valid refresh CACHE block does not affect the refresh. Instead, it can fill in the missing part of the data in the valid refresh CACHE.

[0077] As an embodiment, as Figure 6 shown, before step 201, the method further includes the following steps:

[0078] Step 2014, receive a write request. If the data requested to be written by the write request hits the third valid refresh CACHE block associated with the valid data identifier in the valid refresh linked list, then execute step 2015.

[0079] Here, the third valid refresh CACHE block is only named for the convenience of distinguishing it from other valid refresh CACHE blocks in the following text, and is not used to limit a certain valid refresh CACHE block.

[0080] The data requested to be written by the write request hits the third valid refresh CACHE block associated with the valid data identifier in the valid refresh linked list, which means that the CACHE has written the data stored in the third valid refresh CACHE block to the RAID.

[0081] Step 2015, remove the record of the third valid refresh CACHE block from the valid refresh linked list, change the third valid refresh CACHE block into a dirty CACHE block, and write the data to be written corresponding to the write request into the dirty CACHE block.

[0082] In this embodiment, if a write request hits a valid refresh CACHE block, then the valid refresh CACHE block moves from the valid refresh linked list to the dirty CACHE linked list, which means that the valid refresh CACHE block becomes a dirty CACHE block and new data will be written to it. Then this dirty CACHE block will also be actively refreshed.

[0083] The write request uses the following refresh scheme after refreshing the valid CACHE linked list: When the write request hits the valid CACHE linked list, the valid CACHE block hit by the write request is removed from the valid CACHE linked list and added to the dirty data linked list, and at the same time, new dirty data is written, that is, the original data is updated or new dirty data is added. When refreshing, steps 201 to 205 are executed.

[0084] Thus, the description of the embodiment is completed.

[0085] The device provided by the present application will be described below:

[0086] See Figure 7 , Figure 7 FIG. is a schematic structural diagram of a cache CACHE refresh device 700 provided by the present application, which is applied to a storage device. The device includes:

[0087] A stripe construction unit 701, configured to, when it is necessary to refresh the CACHE, if it is detected that there is no full stripe in the CACHE, obtain dirty CACHE blocks from the CACHE, and find valid data identifiers associated with all valid CACHE blocks in the same stripe as the dirty CACHE blocks from the configured valid CACHE linked list, so as to form a full stripe or a non-full stripe with the obtained dirty CACHE blocks using the valid CACHE blocks associated with the found valid data identifiers; determine whether there is a formed full stripe in the CACHE. If so, trigger the first full stripe refresh unit 702. If not, trigger the non-full stripe refresh unit 703; the valid CACHE linked list includes valid data identifiers, and the valid data identifiers are used to associate the valid CACHE blocks after the dirty CACHE blocks in the CACHE are refreshed.

[0088] The first full stripe refresh unit 702 is configured to write the full stripe to the RAID. After writing the full stripe to the RAID, keep the data stored in the CACHE blocks in the full stripe valid, and update the valid data identifiers in the valid CACHE linked list based on the CACHE blocks in the full stripe.

[0089] The non-full stripe refresh unit 703 is configured to write the formed non-full stripe to the RAID. After writing the non-full stripe to the RAID, keep the data stored in the CACHE blocks in the non-full stripe valid, and update the valid data identifiers in the valid CACHE linked list based on the CACHE blocks in the non-full stripe.

[0090] As an embodiment, the stripe construction unit 701 includes a dirty CACHE block unit configured to obtain dirty CACHE blocks from the CACHE, specifically:

[0091] Select the dirty data block identifiers associated with valid dirty CACHE blocks that are on the same stripe record from the configured dirty data linked list, and obtain the associated dirty CACHE blocks from the CACHE based on the selected dirty data block identifiers; wherein, the dirty data linked list includes dirty data block identifiers, and the dirty data block identifiers are used to associate the dirty CACHE blocks storing dirty data in the CACHE;

[0092] The stripe construction unit searches the configured refresh valid linked list for valid data identifiers associated with all refresh valid CACHE blocks within the same stripe as the dirty CACHE block, so as to form a full stripe or a non-full stripe with the refresh valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE block. Specifically, it is used for:

[0093] Based on the logical address LBA of the logical unit number LUN corresponding to the obtained dirty CACHE block, search the configured refresh valid linked list for valid data identifiers associated with all refresh valid CACHE blocks within the same stripe as the dirty CACHE block, and obtain all the refresh valid CACHE blocks associated with the valid data identifiers from the CACHE according to the LBA of the LUN corresponding to all the refresh valid CACHE blocks associated with the found valid data identifiers, so as to fill up all the obtained refresh valid CACHE blocks into the stripe to which the obtained dirty CACHE block belongs to form a full stripe or a non-full stripe.

[0094] As an embodiment, the device further includes: a second full stripe writing subunit, specifically used for:

[0095] If it is detected that there is a full stripe in the CACHE, write the full stripe to the RAID. After completing the writing of the full stripe to the RAID, keep the data stored in the CACHE blocks within the full stripe valid, and update the valid data identifiers in the refresh valid linked list based on the CACHE blocks within the full stripe.

[0096] As an embodiment, the device further includes:

[0097] A request processing unit, configured to receive a read request. If all the data requested to be read by the read request hits the first refresh valid CACHE block associated with the valid data identifier in the refresh valid linked list, trigger the first reading unit; if some of the data requested to be read by the read request hits the second refresh valid CACHE block associated with the valid data identifier in the refresh valid linked list, trigger the second reading unit;

[0098] The first reading unit is configured to read the valid data stored in the first refresh valid CACHE block from the CACHE;

[0099] The second reading unit is configured to read the stored valid data from the second refreshed valid CACHE block, and read the first target data in the data requested to be read by the read request from the RAID that does not hit the refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list, store the first target data in a specified refreshed valid CACHE block, and update the valid data identifier in the refreshed valid linked list based on the refreshed valid CACHE block storing the first target data. As an embodiment, the apparatus further includes:

[0100] A write request processing unit, configured to receive a write request. If the data requested to be written by the write request hits the third refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list, remove the record of the third refreshed valid CACHE block from the refreshed valid linked list, change the third refreshed valid CACHE block into a dirty CACHE block, and write the data to be written corresponding to the write request into the dirty CACHE block.

[0101] So far, the Figure 7 description shown is completed.

[0102] Thus, it can be seen that in the technical solution of the embodiment of the present application,

[0103] When it is necessary to refresh the CACHE, if it is detected that there is no full stripe in the CACHE, obtain the dirty CACHE block from the CACHE, and use the configured refreshed valid linked list to find all the refreshed valid CACHE blocks in the same stripe as the dirty CACHE block, so as to form a full stripe or a non-full stripe with the obtained dirty CACHE block, and write the full stripe or the non-full stripe to the RAID based on the formed full stripe or non-full stripe. After completing the writing of the full stripe or non-full stripe to the RAID, keep the data stored in the CACHE blocks in the full stripe or non-full stripe valid, and update the refreshed valid linked list based on the CACHE blocks in the full stripe or non-full stripe. It can be seen that the technical solution provided by the embodiment of the present application uses the configured refreshed valid linked list for recording the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are refreshed, to form a full stripe or a non-full stripe for the single CACHE block being refreshed and the refreshed valid CACHE blocks recorded in the refreshed valid linked list, so that more full stripe writes can be performed when writing to the RAID, reducing the overhead caused by stripe conflicts and data read-back under the RAID, enabling the CACHE to be recycled, having higher availability, and optimizing the performance of CACHE disk flushing.

[0104] The implementation processes of the functions and roles of each unit in the above apparatus are specifically described in the implementation processes of the corresponding steps in the above method, and will not be elaborated here.

[0105] For the electronic device provided by the embodiment of the present application, from the hardware level, the schematic diagram of the hardware architecture can be seen in Figure 8 the figure shown. It includes: a machine-readable storage medium and a processor, where: the machine-readable storage medium stores machine-executable instructions that can be executed by the processor; the processor is used to execute the machine-executable instructions to implement the CACHE refresh operation disclosed in the above example.

[0106] The machine-readable storage medium provided by the embodiment of the present application stores machine-executable instructions. When the machine-executable instructions are called and executed by the processor, the machine-executable instructions cause the processor to implement the CACHE refresh operation disclosed in the above example.

[0107] Here, the machine-readable storage medium can be any electronic, magnetic, optical or other physical storage device that can contain or store information such as executable instructions, data, etc. For example, the machine-readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or a combination thereof.

[0108] The systems, devices, modules or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, and the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver device, a game console, a tablet computer, a wearable device, or a combination of any several of these devices.

[0109] For the convenience of description, when describing the above devices, they are described separately as various units according to functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0110] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce a means for implementing the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more of the blocks.

[0112] Furthermore, these computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction means that implements the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more of the blocks.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more of the blocks.

[0114] For the apparatus embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial descriptions of the method embodiments. The apparatus embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0115] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for refreshing a cache memory CACHE, characterized in that, Applied to a storage device, the method includes: When it is necessary to refresh the CACHE, if it is detected that there is no full stripe in the CACHE, obtain dirty CACHE blocks from the CACHE, and find valid data identifiers associated with all refreshed valid CACHE blocks in the same stripe as the dirty CACHE blocks from the configured refreshed valid linked list, so as to use the refreshed valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe; the refreshed valid linked list includes valid data identifiers, and the valid data identifiers are used to associate the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are refreshed; Judge whether there is a formed full stripe in the CACHE. If so, write the full stripe to the RAID. After completing the writing of the full stripe to the RAID, keep the data stored in the CACHE blocks in the full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks in the full stripe; If not, write the formed non-full stripe to the RAID. After completing the writing of the non-full stripe to the RAID, keep the data stored in the CACHE blocks in the non-full stripe valid, and update the valid data identifiers in the refreshed valid linked list based on the CACHE blocks in the non-full stripe.

2. The method according to claim 1, wherein The obtaining of the dirty CACHE blocks from the CACHE includes: Select the dirty data block identifiers associated with the valid dirty CACHE blocks recorded in the same stripe from the configured dirty data linked list, and obtain the associated dirty CACHE blocks from the CACHE based on the selected dirty data block identifiers; wherein, the dirty data linked list includes dirty data block identifiers, and the dirty data block identifiers are used to associate the dirty CACHE blocks storing dirty data in the CACHE; The finding of the valid data identifiers associated with all refreshed valid CACHE blocks in the same stripe as the dirty CACHE blocks from the configured refreshed valid linked list, so as to use the refreshed valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe, includes: Based on the logical address LBA of the logical unit number LUN corresponding to the obtained dirty CACHE block, find the valid data identifiers associated with all refreshed valid CACHE blocks in the same stripe as the dirty CACHE blocks from the configured refreshed valid linked list, obtain all refreshed valid CACHE blocks associated with the found valid data identifiers from the CACHE, and fill in all the obtained refreshed valid CACHE blocks into the stripe to which the obtained dirty CACHE block belongs according to the LBA of the LUN corresponding to all the obtained refreshed valid CACHE blocks, so as to form a full stripe or a non-full stripe.

3. The method according to claim 1, characterized in that If it is detected that there is a full stripe in the CACHE, the method further includes: Write the full stripe to the RAID. After completing the write of the full stripe to the RAID, keep the data stored in the CACHE blocks within the full stripe valid, and update the valid data identifiers in the refresh valid linked list based on the CACHE blocks within the full stripe.

4. The method according to any one of claims 1 to 3, characterized in that, Before this method, this method further includes: Receive a read request. If all the data requested to be read in the read request hits the first refreshed valid CACHE blocks associated with the valid data identifiers in the refresh valid linked list, then read the valid data stored in the first refreshed valid CACHE blocks from the CACHE. If some of the data requested to be read in the read request hits the second refreshed valid CACHE blocks associated with the valid data identifiers in the refresh valid linked list, then read the valid data stored in the second refreshed valid CACHE blocks, and read the first target data in the data requested to be read in the read request that does not hit the refreshed valid CACHE blocks associated with the valid data identifiers in the refresh valid linked list from the RAID. Store the first target data in a specified refreshed valid CACHE block, and update the valid data identifiers in the refresh valid linked list based on the refreshed valid CACHE block in which the first target data has been stored.

5. The method according to any one of claims 1 to 3, characterized in that Before this method, it further includes: Receive a write request. If the data requested to be written in the write request hits the third refreshed valid CACHE blocks associated with the valid data identifiers in the refresh valid linked list, then remove the records of the third refreshed valid CACHE blocks from the refresh valid linked list, turn the third refreshed valid CACHE blocks into dirty CACHE blocks, and write the data to be written corresponding to the write request into the dirty CACHE blocks.

6. A cache refresh device, characterized in that, Applied to a storage device, the device includes: A stripe construction unit, which is used to, when it is necessary to refresh the CACHE, if it detects that there is no full stripe in the CACHE, obtain dirty CACHE blocks from the CACHE, and find the valid data identifiers associated with all the refreshed valid CACHE blocks within the same stripe as the dirty CACHE blocks from the configured refresh valid linked list, so as to use the refreshed valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe; determine whether there is a formed full stripe in the CACHE. If there is, trigger the first full stripe refresh unit. If not, trigger the non-full stripe refresh unit; the refresh valid linked list includes valid data identifiers, and the valid data identifiers are used to associate the refreshed valid CACHE blocks after the dirty CACHE blocks in the CACHE are refreshed. The first full stripe refresh unit is used to write the full stripe to the RAID. After completing the write of the full stripe to the RAID, keep the data stored in the CACHE blocks within the full stripe valid, and update the valid data identifiers in the refresh valid linked list based on the CACHE blocks within the full stripe. The non-full stripe refresh unit is used to write the formed non-full stripe to the RAID. After completing the writing of the non-full stripe to the RAID, it keeps the data stored in the CACHE blocks within the non-full stripe valid, and updates the valid data identifiers in the refresh valid linked list based on the CACHE blocks within the non-full stripe.

7. The device according to claim 6, characterized in that, The stripe construction unit includes a dirty CACHE block unit for obtaining dirty CACHE blocks from the CACHE, specifically for: Selecting, from the configured dirty data linked list, the dirty data block identifiers associated with the valid dirty CACHE blocks recorded in the same stripe, and obtaining the associated dirty CACHE blocks from the CACHE based on the selected dirty data block identifiers; wherein, the dirty data linked list includes dirty data block identifiers for associating the dirty CACHE blocks storing dirty data in the CACHE. In the stripe construction unit, it searches the configured refresh valid linked list for the valid data identifiers associated with all the refresh valid CACHE blocks in the same stripe as the dirty CACHE block, so as to use the refresh valid CACHE blocks associated with the found valid data identifiers and the obtained dirty CACHE blocks to form a full stripe or a non-full stripe, specifically for: Based on the logical address LBA of the logical unit number LUN corresponding to the obtained dirty CACHE block, searching the configured refresh valid linked list for the valid data identifiers associated with all the refresh valid CACHE blocks in the same stripe as the dirty CACHE block, obtaining all the refresh valid CACHE blocks associated with the found valid data identifiers from the CACHE, and padding all the obtained refresh valid CACHE blocks to the stripe to which the obtained dirty CACHE block belongs according to the LBA of the LUN corresponding to all the obtained refresh valid CACHE blocks, so as to form a full stripe or a non-full stripe.

8. The device according to claim 6, characterized in that, The device further includes: a second full stripe writing subunit, specifically for: If it detects that there is a full stripe in the CACHE, writing the full stripe to the RAID. After completing the writing of the full stripe to the RAID, it keeps the data stored in the CACHE blocks within the full stripe valid, and updates the valid data identifiers in the refresh valid linked list based on the CACHE blocks within the full stripe.

9. The device according to any one of claims 6 to 8, characterized in that The device further includes: A request processing unit for receiving a read request. If all the data requested to be read in the read request hits the first refresh valid CACHE blocks associated with the valid data identifiers in the refresh valid linked list, it triggers the first reading unit; if some of the data requested to be read in the read request hits the second refresh valid CACHE blocks associated with the valid data identifiers in the refresh valid linked list, it triggers the second reading unit; The first reading unit is used to read the valid data stored in the first refresh valid CACHE block from the CACHE. The second reading unit is configured to read the stored valid data from the second refreshed valid CACHE block, and read the first target data that is not in the refreshed valid CACHE block associated with the valid data identifier in the read request from the RAID, store the first target data in a specified refreshed valid CACHE block, and update the valid data identifier in the refreshed valid linked list based on the refreshed valid CACHE block in which the first target data has been stored.

10. The device according to any one of claims 6 to 8, characterized in that, The apparatus further includes: A write request processing unit, configured to receive a write request. If the data to be written in the write request hits a third refreshed valid CACHE block associated with the valid data identifier in the refreshed valid linked list, remove the record of the third refreshed valid CACHE block from the refreshed valid linked list, change the third refreshed valid CACHE block into a dirty CACHE block, and write the data to be written corresponding to the write request into the dirty CACHE block.

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