An adder array

Abstract

This invention relates to an adder array, specifically in the field of adders, comprising 16 input signal terminals, 11 full adders, and 4 half adders. Each input signal terminal is used to input a 1-bit input signal. Each full adder includes three input terminals and two output terminals. The three input terminals of a full adder are used to input 1-bit data. The first output terminal of a full adder is used to output the sum bit, and the second output terminal is used to output the carry. Each half adder includes two input terminals and two output terminals. The two input terminals of a half adder are used to input 1-bit data. The first output terminal of a half adder is used to output the sum bit, and the second output terminal is used to output the carry. This array achieves the sum of 16 1-bit input signals to output a 5-bit output signal. The adder array, composed of multiple full adders and multiple half adders, reduces the delay along the addition path and improves the operation speed.

Description

Technical Field

[0001] This invention relates to the field of adder technology, and in particular to an adder array. Background Technology

[0002] In the context of the booming development of artificial intelligence networks, the traditional von Neumann architecture is no longer suitable for the data transmission requirements of convolutional neural networks. In-memory computing architecture has a natural advantage in handling large amounts of data, as it avoids the additional power consumption waste caused by data movement.

[0003] In the rapidly developing in-memory computing architecture, a new type of all-digital in-memory computing offers full precision. However, in this architecture, adder arrays account for a significant portion of the power consumption and suffer from slow processing speeds. Therefore, research on adder arrays has become indispensable. Summary of the Invention

[0004] The purpose of this invention is to provide an adder array that reduces latency on the addition path and improves computation speed.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] An adder array includes 16 input signal terminals, 11 full adders, and 4 half adders. Each input signal terminal is used to input a 1-bit input signal. The 16 input signal terminals are designated as the first input signal terminal, the second input signal terminal, the third input signal terminal, the fourth input signal terminal, the fifth input signal terminal, the sixth input signal terminal, the seventh input signal terminal, the eighth input signal terminal, the ninth input signal terminal, the tenth input signal terminal, the eleventh input signal terminal, the twelfth input signal terminal, the thirteenth input signal terminal, the fourteenth input signal terminal, the fifteenth input signal terminal, and the sixteenth input signal terminal. The 11 full adders are designated as the first full adder, the second full adder, the third full adder, the fourth full adder, the fifth full adder, the sixth full adder, the seventh full adder, the eighth full adder, the ninth full adder, the tenth full adder, and the eleventh full adder. The 4 half adders are designated as the first half adder, the second half adder, the third half adder, and the fourth half adder.

[0007] Each of the full adders includes three input terminals and two output terminals. Each of the three input terminals of the full adder is used to input 1 bit of data. The first output terminal of the full adder is used to output the sum bit, and the second output terminal of the full adder is used to output the carry. Each of the half adders includes two input terminals and two output terminals. Each of the two input terminals of the half adder is used to input 1 bit of data. The first output terminal of the half adder is used to output the sum bit, and the second output terminal of the half adder is used to output the carry.

[0008] The first input signal terminal is connected to the first input terminal of the first full adder; the second input signal terminal is connected to the second input terminal of the first full adder; the third input signal terminal is connected to the third input terminal of the first full adder; the fourth input signal terminal is connected to the first input terminal of the second full adder; the fifth input signal terminal is connected to the second input terminal of the second full adder; the sixth input signal terminal is connected to the third input terminal of the second full adder; the seventh input signal terminal is connected to the first input terminal of the third full adder; the eighth input signal terminal is connected to the second input terminal of the third full adder; the ninth input signal terminal is connected to the third input terminal of the third full adder; the tenth input signal terminal is connected to the first input terminal of the fourth full adder; the eleventh input signal terminal is connected to the second input terminal of the fourth full adder; the twelfth input signal terminal is connected to the third input terminal of the fourth full adder; the thirteenth input signal terminal is connected to the first input terminal of the fifth full adder; the fourteenth input signal terminal is connected to the second input terminal of the fifth full adder; and the fifteenth input signal terminal is connected to the third input terminal of the fifth full adder.

[0009] The first output terminal of the first full adder is connected to the first input terminal of the sixth full adder; the first output terminal of the second full adder is connected to the second input terminal of the sixth full adder; the first output terminal of the third full adder is connected to the third input terminal of the sixth full adder; the first output terminal of the fourth full adder is connected to the first input terminal of the seventh full adder; the first output terminal of the fifth full adder is connected to the second input terminal of the seventh full adder; and the sixteenth input signal terminal is connected to the third input terminal of the seventh full adder.

[0010] The first output terminal of the sixth full adder is connected to the first input terminal of the first half adder, and the first output terminal of the seventh full adder is connected to the second input terminal of the first half adder.

[0011] The second output terminal of the first full adder is connected to the first input terminal of the eighth full adder, the second output terminal of the second full adder is connected to the second input terminal of the eighth full adder, and the second output terminal of the sixth full adder is connected to the third input terminal of the eighth full adder;

[0012] The second output terminal of the third full adder is connected to the first input terminal of the ninth full adder, the second output terminal of the first half adder is connected to the second input terminal of the ninth full adder, and the second output terminal of the fourth full adder is connected to the third input terminal of the ninth full adder.

[0013] The second output terminal of the fifth full adder is connected to the first input terminal of the second half adder, and the second output terminal of the seventh full adder is connected to the second input terminal of the second half adder.

[0014] The first output terminal of the eighth full adder is connected to the first input terminal of the tenth full adder, the first output terminal of the second half adder is connected to the second input terminal of the tenth full adder, and the first output terminal of the ninth full adder is connected to the third input terminal of the tenth full adder.

[0015] The second output terminal of the eighth full adder is connected to the first input terminal of the eleventh full adder, the second output terminal of the ninth full adder is connected to the second input terminal of the eleventh full adder, and the second output terminal of the second half adder is connected to the third input terminal of the eleventh full adder.

[0016] The first output terminal of the eleventh full adder is connected to the first input terminal of the third half adder; the second output terminal of the tenth full adder is connected to the second input terminal of the third half adder.

[0017] The second output terminal of the eleventh full adder is connected to the first input terminal of the fourth half adder; the second output terminal of the third half adder is connected to the second input terminal of the fourth half adder.

[0018] The signals output sequentially from the first output terminal of the first half-adder, the first output terminal of the tenth full adder, the first output terminal of the third half-adder, the first output terminal of the fourth half-adder, and the second output terminal of the fourth half-adder are used as the 5-bit output result from the least significant bit to the most significant bit of the adder array.

[0019] Optionally, each input signal is the result of multiplying the input stimulus of each SRAM in the SRAM array by the weight stored in the corresponding SRAM bit by bit.

[0020] Optionally, the 11 full adders have the same structure, and each full adder includes tubes P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10 and N11;

[0021] The source of transistor P1 is connected to power supply VDD. The gate of transistor P1 is connected to the gate of transistor N1, the gate of transistor P2, and the drain of transistor P3. The drain of transistor P1 is connected to the drain of transistor N1, the gate of transistor N2, and the drain of transistor N3. The drain of transistor P2 is connected to the drain of transistor N2, the gate of transistor P3, the gate of transistor N3, the source of transistor P5, and the source of transistor N6. The source of transistor P2 is connected to the source of transistor N2, the source of transistor P3, the source of transistor N3, the gate of transistor P4, the gate of transistor N4, the gate of transistor P5, the gate of transistor N5, the drain of transistor P8, and the gate of transistor N9. The source of transistor N1 is grounded. The source of transistor P4 is connected to power supply VDD. The drain of transistor P4 is connected to the drain of transistor N4, the gate of transistor P9, the drain of transistor N8, the gate of transistor P6, and the gate of transistor N6. The source of transistor N4 is grounded. Ground; the drain of transistor P5 is connected to the drains of transistors N5, P6, and N6, the gate of transistor P7, and the gate of transistor N7, respectively; the source of transistor P6 is connected to the source of transistor N5, the drain of transistor P9, the drain of transistor N9, the gate of transistor P8, and the gate of transistor N8, respectively; the source of transistor P9 is connected to the source of transistor N9, the source of transistor P8, the source of transistor N8, the gate of transistor P11, and the gate of transistor N11, respectively. The gate is connected, the source of transistor P11 is connected to power supply VDD, the drain of transistor P11 is connected to the drain of transistor N11, the source of transistor P7 and the source of transistor P10 are both connected to power supply VDD, the drain of transistor P7 is connected to the drain of transistor N7, the gate of transistor P10 and the gate of transistor N10 respectively, the drain of transistor P10 is connected to the drain of transistor N10, and the source of transistor N7, the source of transistor N10 and the source of transistor N11 are all grounded.

[0022] The connection between the gate of transistor P3 and the drain of transistor P2 is the first input terminal of the full adder; the connection between the gate of transistor P1 and the gate of transistor N1 is the second input terminal of the full adder; the connection between the drain of transistor P11 and the drain of transistor N11 is the first output terminal of the full adder; and the connection between the drain of transistor P10 and the drain of transistor N10 is the second output terminal of the full adder.

[0023] Optionally, transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, and P11 are all P-type MOSFETs;

[0024] Transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, and N11 are all N-type MOS transistors.

[0025] Optionally, the four half-adders have the same structure, and each half-adder includes tubes P1', P2', P3', P4', P5', P6', P7', N1', N2', N3', N4', N5', N6' and N7'.

[0026] The sources of transistors P1', P2', P5', and P7' are all connected to the power supply VDD. The gate of transistor P1' is connected to the gate of transistor N1'. The drain of transistor P1' is connected to the gates of transistors P5', N5', N1', P3', N3', P4', and N4'. The gate of transistor P2' is connected to the gates of transistors N2', P3', and P4'. The drain of transistor P2' is connected to the drain of transistor N2' and the gate of transistor N3'. The drain of transistor N4', the gate of transistor P6', and the gate of transistor N6' are connected. The drain of transistor P3' is connected to the source of transistor N3', the source of transistor P4', the source of transistor N4', the gate of transistor P7', and the gate of transistor N7'. The drain of transistor P7' is connected to the drain of transistor N7'. The drain of transistor P5' is connected to the source of transistor P6'. The drain of transistor P6' is connected to the drain of transistor N6' and the drain of transistor N5'. The sources of transistors N1', N2', N5', N6', and N7' are all grounded.

[0027] The connection between the gate of transistor P1' and the gate of transistor N1' is the first input terminal of the half-adder; the connection between the gate of transistor P2' and the gate of transistor N2' is the second input terminal of the half-adder; the connection between the gate of transistor P7' and the gate of transistor N7' is the first output terminal of the half-adder; and the connection between the drain of transistor P6' and the drain of transistor N6' is the second output terminal of the half-adder.

[0028] Optionally, transistors P1', P2', P3', P4', P5', P6', and P7' are all P-type MOSFETs;

[0029] Transistors N1', N2', N3', N4', N5', N6', and N7' are all N-type MOS transistors.

[0030] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] This invention discloses an adder array that adds 16 1-bit input signals to output a 5-bit output signal. Compared with traditional serial carry adders, this invention's adder array, composed of multiple full adders and multiple half adders, reduces the delay on the addition path and improves the operation speed. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of an adder array structure according to the present invention;

[0034] Figure 2 This is a schematic diagram of the full adder structure of the present invention;

[0035] Figure 3 This is a schematic diagram of the half-adder structure of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The purpose of this invention is to provide an adder array that reduces latency on the addition path and improves computation speed.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Figure 1 This is a schematic diagram of an adder array structure according to the present invention, as shown below. Figure 1 As shown, an adder array is characterized by comprising 16 input signal terminals, 11 full adders, and 4 half adders. Each of the input signal terminals is used to input a 1-bit input signal. The 16 input signal terminals are respectively the first input signal terminal, the second input signal terminal, the third input signal terminal, the fourth input signal terminal, the fifth input signal terminal, the sixth input signal terminal, the seventh input signal terminal, the eighth input signal terminal, the ninth input signal terminal, the tenth input signal terminal, the eleventh input signal terminal, the twelfth input signal terminal, the thirteenth input signal terminal, the fourteenth input signal terminal, the fifteenth input signal terminal, and the sixteenth input signal terminal. The 11 full adders are respectively the first full adder, the second full adder, the third full adder, the fourth full adder, the fifth full adder, the sixth full adder, the seventh full adder, the eighth full adder, the ninth full adder, the tenth full adder, and the eleventh full adder. The 4 half adders are respectively the first half adder, the second half adder, the third half adder, and the fourth half adder.

[0040] Figure 1 In the diagram, Mul

[15] represents the sixteenth input signal terminal, Mul

[14] represents the fifteenth input signal terminal, Mul

[13] represents the fourteenth input signal terminal, Mul

[12] represents the thirteenth input signal terminal, Mul

[11] represents the twelfth input signal terminal, Mul

[10] represents the eleventh input signal terminal, Mul[9] represents the tenth input signal terminal, Mul[8] represents the ninth input signal terminal, Mul[7] represents the eighth input signal terminal, Mul[6] represents the seventh input signal terminal, Mul[5] represents the sixth input signal terminal, Mul[4] represents the fifth input signal terminal, Mul[3] represents the fourth input signal terminal, Mul[2] represents the third input signal terminal, Mul[1] represents the second input signal terminal, and Mul[0] represents the first input signal terminal.

[0041] Each input signal is the result of multiplying the input excitation of each SRAM in the SRAM array by the corresponding weight stored in the SRAM bit by bit.

[0042] Each of the full adders includes three input terminals and two output terminals. The three input terminals of the full adder are each used to input 1 bit of data. The first output terminal of the full adder is used to output the sum bit, and the second output terminal of the full adder is used to output the carry. Each of the half adders includes two input terminals and two output terminals. The two input terminals of the half adder are each used to input 1 bit of data. The first output terminal of the half adder is used to output the sum bit, and the second output terminal of the half adder is used to output the carry.

[0043] The first input signal terminal is connected to the first input terminal of the first full adder; the second input signal terminal is connected to the second input terminal of the first full adder; the third input signal terminal is connected to the third input terminal of the first full adder; the fourth input signal terminal is connected to the first input terminal of the second full adder; the fifth input signal terminal is connected to the second input terminal of the second full adder; the sixth input signal terminal is connected to the third input terminal of the second full adder; the seventh input signal terminal is connected to the first input terminal of the third full adder; the eighth input signal terminal is connected to the second input terminal of the third full adder; the ninth input signal terminal is connected to the third input terminal of the third full adder; the tenth input signal terminal is connected to the first input terminal of the fourth full adder; the eleventh input signal terminal is connected to the second input terminal of the fourth full adder; the twelfth input signal terminal is connected to the third input terminal of the fourth full adder; the thirteenth input signal terminal is connected to the first input terminal of the fifth full adder; the fourteenth input signal terminal is connected to the second input terminal of the fifth full adder; and the fifteenth input signal terminal is connected to the third input terminal of the fifth full adder.

[0044] The first output terminal of the first full adder is connected to the first input terminal of the sixth full adder; the first output terminal of the second full adder is connected to the second input terminal of the sixth full adder; the first output terminal of the third full adder is connected to the third input terminal of the sixth full adder; the first output terminal of the fourth full adder is connected to the first input terminal of the seventh full adder; the first output terminal of the fifth full adder is connected to the second input terminal of the seventh full adder; and the sixteenth input signal terminal is connected to the third input terminal of the seventh full adder.

[0045] The first output terminal of the sixth full adder is connected to the first input terminal of the first half adder, and the first output terminal of the seventh full adder is connected to the second input terminal of the first half adder.

[0046] The second output terminal of the first full adder is connected to the first input terminal of the eighth full adder, the second output terminal of the second full adder is connected to the second input terminal of the eighth full adder, and the second output terminal of the sixth full adder is connected to the third input terminal of the eighth full adder.

[0047] The second output of the third full adder is connected to the first input of the ninth full adder, the second output of the first half adder is connected to the second input of the ninth full adder, and the second output of the fourth full adder is connected to the third input of the ninth full adder.

[0048] The second output terminal of the fifth full adder is connected to the first input terminal of the second half adder, and the second output terminal of the seventh full adder is connected to the second input terminal of the second half adder.

[0049] The first output terminal of the eighth full adder is connected to the first input terminal of the tenth full adder, the first output terminal of the second half adder is connected to the second input terminal of the tenth full adder, and the first output terminal of the ninth full adder is connected to the third input terminal of the tenth full adder.

[0050] The second output terminal of the eighth full adder is connected to the first input terminal of the eleventh full adder, the second output terminal of the ninth full adder is connected to the second input terminal of the eleventh full adder, and the second output terminal of the second half adder is connected to the third input terminal of the eleventh full adder.

[0051] The first output terminal of the eleventh full adder is connected to the first input terminal of the third half adder; the second output terminal of the tenth full adder is connected to the second input terminal of the third half adder.

[0052] The second output terminal of the eleventh full adder is connected to the first input terminal of the fourth half adder; the second output terminal of the third half adder is connected to the second input terminal of the fourth half adder.

[0053] The signals output sequentially from the first output terminal of the first half-adder, the first output terminal of the tenth full adder, the first output terminal of the third half-adder, the first output terminal of the fourth half-adder, and the second output terminal of the fourth half-adder are used as the 5-bit output result from the least significant bit to the most significant bit of the adder array. Figure 1 As shown, S[4], S[3], S[2], S[1] and S[0] are the outputs.

[0054] The 11 full adders of this invention have the same structure, such as... Figure 2 As shown, each of the full adders includes tubes P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, and N11.

[0055] The source of transistor P1 is connected to power supply VDD. The gate of transistor P1 is connected to the gate of transistor N1, the gate of transistor P2, and the drain of transistor P3. The drain of transistor P1 is connected to the drain of transistor N1, the gate of transistor N2, and the drain of transistor N3. The drain of transistor P2 is connected to the drain of transistor N2, the gate of transistor P3, the gate of transistor N3, the source of transistor P5, and the source of transistor N6. The source of transistor P2 is connected to the source of transistor N2, the source of transistor P3, the source of transistor N3, the gate of transistor P4, the gate of transistor N4, the gate of transistor P5, the gate of transistor N5, the drain of transistor P8, and the gate of transistor N9. The source of transistor N1 is grounded. The source of transistor P4 is connected to power supply VDD. The drain of transistor P4 is connected to the drain of transistor N4, the gate of transistor P9, the drain of transistor N8, the gate of transistor P6, and the gate of transistor N6. The source of transistor N4 is grounded. Ground; the drain of transistor P5 is connected to the drains of transistors N5, P6, and N6, the gate of transistor P7, and the gate of transistor N7, respectively; the source of transistor P6 is connected to the source of transistor N5, the drain of transistor P9, the drain of transistor N9, the gate of transistor P8, and the gate of transistor N8, respectively; the source of transistor P9 is connected to the source of transistor N9, the source of transistor P8, the source of transistor N8, the gate of transistor P11, and the gate of transistor N11, respectively. The gates are connected, the source of transistor P11 is connected to the power supply VDD, the drain of transistor P11 is connected to the drain of transistor N11, the source of transistor P7 and the source of transistor P10 are both connected to the power supply VDD, the drain of transistor P7 is connected to the drain of transistor N7, the gate of transistor P10 and the gate of transistor N10 respectively, the drain of transistor P10 is connected to the drain of transistor N10, and the source of transistor N7, the source of transistor N10 and the source of transistor N11 are all grounded.

[0056] The connection between the gate of transistor P3 and the drain of transistor P2 is the first input terminal of the full adder; the connection between the gate of transistor P1 and the gate of transistor N1 is the second input terminal of the full adder; the connection between the drain of transistor P11 and the drain of transistor N11 is the first output terminal of the full adder; and the connection between the drain of transistor P10 and the drain of transistor N10 is the second output terminal of the full adder.

[0057] Figure 2 In the diagram, A represents the first input terminal of the full adder, B represents the second input terminal of the full adder, CIN represents the third input terminal of the full adder, SUN represents the sum bit (the first output terminal of the full adder), and COUT represents the carry bit (the second output terminal of the full adder).

[0058] Transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, and P11 are all P-type MOSFETs. Transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, and N11 are all N-type MOSFETs.

[0059] The full adder of the present invention includes five inverters: the first inverter is composed of tubes P1 and N1, the second inverter is composed of tubes P4 and N4, the third inverter is composed of tubes P7 and N7, the fourth inverter is composed of tubes P10 and N10, and the fifth inverter is composed of tubes P11 and N11.

[0060] Tubes P2 and N2 form the first transmission gate, and tubes P9 and N9 form the second transmission gate.

[0061] P2, P3, N2, and N3 form a transmission gate-type XOR gate, while P8, P9, N8, and N9 form a transmission gate-type XOR gate.

[0062] Pipes P5, P6, N5, and N6 together form a MUX multiselector.

[0063] Figure 2 In the diagram, VDD is the power supply, VSS is ground, BN is the inverted signal of B (the second input of the full adder), SUMN is the inverted signal of SUM (the first output of the full adder), SUM is the sum signal, COUTN is the inverted signal of COUT (the second output of the full adder), COUT is the carry signal, COUTninv is the carry signal without inverter drive, XOR is the result of XORing A (the first input of the full adder) and B, XNOR is the result of XORing A and B, A and B are the addend signals, and CIN is the carry signal.

[0064] The four half-adders of this invention have the same structure, such as... Figure 3As shown, each of the half-adders includes tubes P1', P2', P3', P4', P5', P6', P7', N1', N2', N3', N4', N5', N6', and N7'.

[0065] The sources of transistors P1', P2', P5', and P7' are all connected to the power supply VDD. The gate of transistor P1' is connected to the gate of transistor N1'. The drain of transistor P1' is connected to the gates of transistors P5', N5', N1', P3', N3', P4', and N4'. The gate of transistor P2' is connected to the gates of transistors N2', P3', and P4'. The drain of transistor P2' is connected to the drain of transistor N2' and the gate of transistor N3'. The drain of transistor N4', the gate of transistor P6', and the gate of transistor N6' are connected. The drain of transistor P3' is connected to the source of transistor N3', the source of transistor P4', the source of transistor N4', the gate of transistor P7', and the gate of transistor N7'. The drain of transistor P7' is connected to the drain of transistor N7'. The drain of transistor P5' is connected to the source of transistor P6'. The drain of transistor P6' is connected to the drain of transistor N6' and the drain of transistor N5'. The sources of transistors N1', N2', N5', N6', and N7' are all grounded.

[0066] The connection between the gate of transistor P1' and the gate of transistor N1' is the first input terminal of the half-adder; the connection between the gate of transistor P2' and the gate of transistor N2' is the second input terminal of the half-adder; the connection between the gate of transistor P7' and the gate of transistor N7' is the first output terminal of the half-adder; and the connection between the drain of transistor P6' and the drain of transistor N6' is the second output terminal of the half-adder.

[0067] Figure 3 In the diagram, A' represents the first input terminal of the half adder, B' represents the second input terminal of the half adder, SUN' represents the sum bit (the first output terminal of the half adder), and COUT' represents the carry bit (the second output terminal of the half adder).

[0068] P1', P2', P3', P4', P5', P6', and P7' are all P-type MOSFETs. N1', N2', N3', N4', N5', N6', and N7' are all N-type MOSFETs.

[0069] Figure 3In this circuit, transistors P1' and N1' form the sixth inverter, P2' and N2' form the seventh inverter, and P7' and N7' form the eighth inverter. P3' and N3' form a transmission gate. P3', P4', N3', and N4' form a transmission gate-type XOR gate. N5', N6', P5', and P6' form a NOR gate. VDD is the power supply, VSS is ground, AN' is the inverted signal of A', BN' is the inverted signal of B', SUMN' is the inverted signal of SUM', A' and B' are the addend signals, COUT' is the carry signal, and SUM' is the sum signal.

[0070] This invention relates to an adder array that can be applied in digital in-memory computing architectures to receive the multiplication results of input stimuli and weights that have already been calculated in an SRAM array. After receiving 16 1-bit multiplication results, the entire adder array begins to operate, ultimately obtaining a 5-bit sum, which is then output to subsequent circuits for further calculations.

[0071] To minimize power consumption and latency while ensuring adder driving capability, the adder array used reduces the number of adder stages compared to the serial carry adder, thus increasing speed. At the same time, the full adder and half adder were redesigned, which not only did not reduce the adder driving capability, but also improved the power consumption of each bit addition operation.

[0072] In the 1-bit full adder, the sum bit is generated by two stages of XOR gates of the transmission gate type, and the sum bit is generated by a new type of MUX. At the same time, in order to avoid the problem of reduced load capacity, inverters are added to both the carry output and the sum bit output. In the 1-bit half adder, the sum bit is generated by the first stage of XOR of the addend, and the sum bit is generated by the inverse NOR of the addend. Similar to the full adder, the output stage here also uses inverters to increase the driving capability.

[0073] Compared to traditional CMOS structures, this invention uses a hybrid logic of transmission gates and CMOS to reduce power consumption to some extent. Compared to traditional serial carry adder structures, the use of adder array structures can reduce delays on critical paths, thereby speeding up computation. For general low-power adders, structures with weak driving capabilities are usually adopted to reduce power consumption, while the structure of this invention increases the circuit's load capacity by using inverters.

[0074] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0075] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An adder array, characterized in that, It includes 16 input signal terminals, 11 full adders, and 4 half adders. Each of the input signal terminals is used to input a 1-bit input signal. The 16 input signal terminals are respectively the first input signal terminal, the second input signal terminal, the third input signal terminal, the fourth input signal terminal, the fifth input signal terminal, the sixth input signal terminal, the seventh input signal terminal, the eighth input signal terminal, the ninth input signal terminal, the tenth input signal terminal, the eleventh input signal terminal, the twelfth input signal terminal, the thirteenth input signal terminal, the fourteenth input signal terminal, the fifteenth input signal terminal, and the sixteenth input signal terminal. The 11 full adders are respectively the first full adder, the second full adder, the third full adder, the fourth full adder, the fifth full adder, the sixth full adder, the seventh full adder, the eighth full adder, the ninth full adder, the tenth full adder, and the eleventh full adder. The 4 half adders are respectively the first half adder, the second half adder, the third half adder, and the fourth half adder. Each of the full adders includes three input terminals and two output terminals. Each of the three input terminals of the full adder is used to input 1 bit of data. The first output terminal of the full adder is used to output the sum bit, and the second output terminal of the full adder is used to output the carry. Each of the half adders includes two input terminals and two output terminals. Each of the two input terminals of the half adder is used to input 1 bit of data. The first output terminal of the half adder is used to output the sum bit, and the second output terminal of the half adder is used to output the carry. The first input signal terminal is connected to the first input terminal of the first full adder; the second input signal terminal is connected to the second input terminal of the first full adder; the third input signal terminal is connected to the third input terminal of the first full adder; the fourth input signal terminal is connected to the first input terminal of the second full adder; the fifth input signal terminal is connected to the second input terminal of the second full adder; the sixth input signal terminal is connected to the third input terminal of the second full adder; the seventh input signal terminal is connected to the first input terminal of the third full adder; the eighth input signal terminal is connected to the second input terminal of the third full adder; the ninth input signal terminal is connected to the third input terminal of the third full adder; the tenth input signal terminal is connected to the first input terminal of the fourth full adder; the eleventh input signal terminal is connected to the second input terminal of the fourth full adder; the twelfth input signal terminal is connected to the third input terminal of the fourth full adder; the thirteenth input signal terminal is connected to the first input terminal of the fifth full adder; the fourteenth input signal terminal is connected to the second input terminal of the fifth full adder; and the fifteenth input signal terminal is connected to the third input terminal of the fifth full adder. The first output terminal of the first full adder is connected to the first input terminal of the sixth full adder; the first output terminal of the second full adder is connected to the second input terminal of the sixth full adder; the first output terminal of the third full adder is connected to the third input terminal of the sixth full adder; the first output terminal of the fourth full adder is connected to the first input terminal of the seventh full adder; the first output terminal of the fifth full adder is connected to the second input terminal of the seventh full adder; and the sixteenth input signal terminal is connected to the third input terminal of the seventh full adder. The first output terminal of the sixth full adder is connected to the first input terminal of the first half adder, and the first output terminal of the seventh full adder is connected to the second input terminal of the first half adder. The second output terminal of the first full adder is connected to the first input terminal of the eighth full adder, the second output terminal of the second full adder is connected to the second input terminal of the eighth full adder, and the second output terminal of the sixth full adder is connected to the third input terminal of the eighth full adder; The second output terminal of the third full adder is connected to the first input terminal of the ninth full adder, the second output terminal of the first half adder is connected to the second input terminal of the ninth full adder, and the second output terminal of the fourth full adder is connected to the third input terminal of the ninth full adder. The second output terminal of the fifth full adder is connected to the first input terminal of the second half adder, and the second output terminal of the seventh full adder is connected to the second input terminal of the second half adder. The first output terminal of the eighth full adder is connected to the first input terminal of the tenth full adder, the first output terminal of the second half adder is connected to the second input terminal of the tenth full adder, and the first output terminal of the ninth full adder is connected to the third input terminal of the tenth full adder. The second output terminal of the eighth full adder is connected to the first input terminal of the eleventh full adder, the second output terminal of the ninth full adder is connected to the second input terminal of the eleventh full adder, and the second output terminal of the second half adder is connected to the third input terminal of the eleventh full adder. The first output terminal of the eleventh full adder is connected to the first input terminal of the third half adder; the second output terminal of the tenth full adder is connected to the second input terminal of the third half adder. The second output terminal of the eleventh full adder is connected to the first input terminal of the fourth half adder; the second output terminal of the third half adder is connected to the second input terminal of the fourth half adder. The signals output sequentially from the first output terminal of the first half-adder, the first output terminal of the tenth full adder, the first output terminal of the third half-adder, the first output terminal of the fourth half-adder, and the second output terminal of the fourth half-adder are used as the 5-bit output result from the least significant bit to the most significant bit of the adder array.

2. The adder array according to claim 1, characterized in that, Each input signal is the result of multiplying the input excitation of each SRAM in the SRAM array by the corresponding weight stored in the SRAM bit by bit.

3. The adder array according to claim 1, characterized in that, The 11 full adders have the same structure, and each full adder includes tubes P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10 and N11; The source of transistor P1 is connected to power supply VDD. The gate of transistor P1 is connected to the gate of transistor N1, the gate of transistor P2, and the drain of transistor P3. The drain of transistor P1 is connected to the drain of transistor N1, the gate of transistor N2, and the drain of transistor N3. The drain of transistor P2 is connected to the drain of transistor N2, the gate of transistor P3, the gate of transistor N3, the source of transistor P5, and the source of transistor N6. The source of transistor P2 is connected to the source of transistor N2, the source of transistor P3, the source of transistor N3, the gate of transistor P4, the gate of transistor N4, the gate of transistor P5, the gate of transistor N5, the drain of transistor P8, and the gate of transistor N9. The source of transistor N1 is grounded. The source of transistor P4 is connected to power supply VDD. The drain of transistor P4 is connected to the drain of transistor N4, the gate of transistor P9, the drain of transistor N8, the gate of transistor P6, and the gate of transistor N6. The source of transistor N4 is grounded. Ground; the drain of transistor P5 is connected to the drains of transistors N5, P6, and N6, the gate of transistor P7, and the gate of transistor N7, respectively; the source of transistor P6 is connected to the source of transistor N5, the drain of transistor P9, the drain of transistor N9, the gate of transistor P8, and the gate of transistor N8, respectively; the source of transistor P9 is connected to the source of transistor N9, the source of transistor P8, the source of transistor N8, the gate of transistor P11, and the gate of transistor N11, respectively. The gate is connected, the source of transistor P11 is connected to power supply VDD, the drain of transistor P11 is connected to the drain of transistor N11, the source of transistor P7 and the source of transistor P10 are both connected to power supply VDD, the drain of transistor P7 is connected to the drain of transistor N7, the gate of transistor P10 and the gate of transistor N10 respectively, the drain of transistor P10 is connected to the drain of transistor N10, and the source of transistor N7, the source of transistor N10 and the source of transistor N11 are all grounded. The connection between the gate of transistor P3 and the drain of transistor P2 is the first input terminal of the full adder; the connection between the gate of transistor P1 and the gate of transistor N1 is the second input terminal of the full adder; the connection between the drain of transistor P11 and the drain of transistor N11 is the first output terminal of the full adder; and the connection between the drain of transistor P10 and the drain of transistor N10 is the second output terminal of the full adder.

4. The adder array according to claim 3, characterized in that, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10 and P11 are all P-type MOSFETs; Transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, and N11 are all N-type MOS transistors.

5. The adder array according to claim 1, characterized in that, The four half-adders have the same structure, and each half-adder includes tubes P1', P2', P3', P4', P5', P6', P7', N1', N2', N3', N4', N5', N6' and N7'. The sources of transistors P1', P2', P5', and P7' are all connected to the power supply VDD. The gate of transistor P1' is connected to the gate of transistor N1'. The drain of transistor P1' is connected to the gates of transistors P5', N5', N1', P3', N3', P4', and N4'. The gate of transistor P2' is connected to the gates of transistors N2', P3', and P4'. The drain of transistor P2' is connected to the drain of transistor N2' and the gate of transistor N3'. The drain of transistor N4', the gate of transistor P6', and the gate of transistor N6' are connected. The drain of transistor P3' is connected to the source of transistor N3', the source of transistor P4', the source of transistor N4', the gate of transistor P7', and the gate of transistor N7'. The drain of transistor P7' is connected to the drain of transistor N7'. The drain of transistor P5' is connected to the source of transistor P6'. The drain of transistor P6' is connected to the drain of transistor N6' and the drain of transistor N5'. The sources of transistors N1', N2', N5', N6', and N7' are all grounded. The connection between the gate of transistor P1' and the gate of transistor N1' is the first input terminal of the half-adder; the connection between the gate of transistor P2' and the gate of transistor N2' is the second input terminal of the half-adder; the connection between the gate of transistor P7' and the gate of transistor N7' is the first output terminal of the half-adder; and the connection between the drain of transistor P6' and the drain of transistor N6' is the second output terminal of the half-adder.

6. The adder array according to claim 5, characterized in that, P1', P2', P3', P4', P5', P6' and P7' are all P-type MOSFETs; Transistors N1', N2', N3', N4', N5', N6', and N7' are all N-type MOS transistors.

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