A method and apparatus for processing data

Abstract

The application provides a method and device for processing data, the method comprising: obtaining first digital data and second digital data, the base value of the base of the first digital data and the second digital data being a first value X, X being a positive integer; performing single-bit conversion on the first digital data according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the first value X; performing single-bit conversion on the second digital data according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X; performing convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results; and determining the product of the first digital data and the second digital data according to the plurality of first convolution results, which can improve the efficiency of multiplication processing of large numbers while meeting high precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processing data, and more particularly, to a method and device for processing data. BACKGROUND

[0002] At present, computers are generally 64-bit systems, that is, the maximum length of an integer that can be processed at a time is 64 bits. However, in cryptography, it is often necessary to perform multiplication processing on digital data that exceeds the expression type of computer data. Such digital data that exceeds the expression capacity of computer data types can be referred to as a large number. At present, algorithms such as analog primary school multiplication, fast Fourier transform, and booth algorithm are commonly used to perform multiplication processing on large numbers. These algorithms can reduce the complexity of multiplication processing on large numbers to a certain extent, maintain high precision of multiplication, but their performance will decrease with the increase of the number of bits of multiplication, and cannot meet the requirements of efficiency.

[0003] Therefore, there is an urgent need for a method for processing data that can improve the efficiency of multiplication processing on large numbers while meeting high precision. SUMMARY

[0004] The present application provides a method and device for processing data that can improve the efficiency of multiplication processing on large numbers while meeting high precision.

[0005] In a first aspect, a device for processing data is provided, which includes a transceiver unit and a processing unit. The transceiver unit is configured to obtain first digital data and second digital data, wherein the base value of the base of the first digital data and the second digital data is a first value X, and the X is a positive integer. The processing unit is configured to perform single-bit conversion on the first digital data according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the first value X. The processing unit is also configured to perform single-bit conversion on the second digital data according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X. The processing unit is also configured to perform convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results. The processing unit is also configured to determine the product of the first digital data and the second digital data according to the plurality of first convolution results.

[0006] Thus, in the present application, the first digital data and the second digital data are both converted into single-bit arrays, thereby avoiding carry processing in convolution calculation, and thus improving the efficiency of multiplication processing on large numbers while meeting high precision.

[0007] With reference to the first aspect, in some implementations of the first aspect, the processing unit is specifically configured to: perform convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays in an optical convolution calculation manner to generate a plurality of first convolution results.

[0008] The processing unit can include an optical processing unit, and a modulation precision of the optical processing unit is 1 bit.

[0009] Optionally, a detection precision of the optical processing unit is determined according to the first value X.

[0010] Optionally, a pixel point of the optical processing unit is determined according to the first value X.

[0011] Optionally, a base corresponding to the first digital data and the second digital data is converted into the first value X according to the detection precision of the optical processing unit.

[0012] Therefore, in the present application, the first single-bit array and the second single-bit array can be subjected to convolution calculation by using an optical convolution system, and the multiplication calculation in the multiplication of large numbers is transferred to the optical convolution system, and only addition calculation is performed in the electrical system, so that the performance of multiplication processing of large numbers can be improved. Further, when the convolution calculation is performed in the optical convolution calculation manner, the multi-dimensional characteristics of light can be utilized, and the time of the optical convolution system calculation is constant time, i.e., the time of one modulation, when the bit number does not exceed the modulation range of the optical convolution system, so that in the present application, the performance of multiplication processing of large numbers does not linearly decrease with the increase of the bit number of digital data, that is, the present application still has good performance when the bit number of digital data is large.

[0013] With reference to the first aspect, in some implementations of the first aspect, the processing unit is also configured to perform sequence splitting on the first digital data to generate a plurality of first sequences, and the number of the first sequences is determined according to the bit number of the first digital data and the bit number of the first sequence, and the processing unit is also specifically configured to perform single-bit conversion on the plurality of first sequences according to the first value X to generate a plurality of first single-bit arrays, and the number of the first single-bit arrays corresponds to the first value X and the number of the first sequences.

[0014] In some implementations of the first aspect, the processing unit is further configured to perform sequence splitting on the second digital data to generate a plurality of second sequences, a number of the second sequences being determined according to a bit number of the second digital data and a bit number of the second sequences, and to perform single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, a number of the second single-bit arrays corresponding to the first value X and the number of the second sequences.

[0015] Thus, in the present application, sequence splitting can be performed on the first digital data, sequence splitting can be performed on the second digital data, or sequence splitting can be performed on both the first digital data and the second digital data, so that the precision requirement of the processing unit performing convolution calculation can be reduced.

[0016] In some implementations of the first aspect, the processing unit is further configured to determine a target digital data, the target digital data being the digital data with a smaller bit number between the first digital data and the second digital data, and to perform sequence splitting on the target digital data to generate a plurality of first sequences or a plurality of second sequences, a number of the first sequences being determined according to a bit number of the first digital data and a bit number of the first sequences, and a number of the second sequences being determined according to a bit number of the second digital data and a bit number of the second sequences, and in a case where the target digital data is the first digital data, the processing unit is further configured to perform single-bit conversion on the plurality of first sequences according to the first value X to generate a plurality of first single-bit arrays, a number of the first single-bit arrays corresponding to the first value X and the number of the first sequences, and in a case where the target digital data is the second digital data, the processing unit is further configured to perform single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, a number of the second single-bit arrays corresponding to the first value X and the number of the second sequences.

[0017] Thus, in the present application, the processing of sequence splitting on one digital data can be determined according to the bit number of the first digital data and the bit number of the second digital data, so that the efficiency of multiplication processing on large numbers can be improved.

[0018] In some implementations of the first aspect, the processing unit is further configured to perform sequence splitting on the second digital data to generate a plurality of second sequences, a number of the second sequences being determined according to a bit number of the second digital data and a bit number of the second sequences, and to perform single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, a number of the second single-bit arrays corresponding to the first value X and the number of the second sequences.

[0019] Optionally, the first convolution result is added bit by bit according to the number of bits of the first sequence and / or the number of bits of the second sequence in a partition manner to determine the product of the first digital data and the second digital data.

[0020] Therefore, in the present application, only addition operation is needed in the process of converting the convolution result into the product, so that the efficiency of multiplication processing of large numbers can be improved.

[0021] In a second aspect, a method for processing data is provided, which includes: obtaining first digital data and second digital data, the base value of the base of the first digital data and the second digital data being a first value X, the X being a positive integer; performing single-bit conversion on the first digital data according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the first value X; performing single-bit conversion on the second digital data according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X; performing convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results; and determining the product of the first digital data and the second digital data according to the plurality of first convolution results.

[0022] Therefore, in the present application, the first digital data and the second digital data are both converted into single-bit arrays, so that the carry processing in the convolution calculation is avoided, and the efficiency of multiplication processing of large numbers can be improved while meeting high precision.

[0023] In combination with the second aspect, in some implementations of the second aspect, performing convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results includes: performing convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays in an optical convolution calculation manner to generate a plurality of first convolution results.

[0024] In combination with the second aspect, in some implementations of the second aspect, the method further includes: performing sequence splitting on the first digital data to generate a plurality of first sequences, the number of the first sequences being determined according to the number of bits of the first digital data and the number of bits of the first sequence; and performing single-bit conversion on the first digital data according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the first value X, includes: performing single-bit conversion on the plurality of first sequences according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the first value X and the number of the first sequences.

[0025] In some implementations of the second aspect, the method further includes: performing sequence splitting on the second digital data to generate a plurality of second sequences, a number of the second sequences being determined according to a bit number of the second digital data and a bit number of the second sequences; and performing the single-bit conversion on the second digital data according to the first value X to generate a plurality of second single-bit arrays, wherein a number of the second single-bit arrays corresponds to the first value X, includes: performing single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, wherein a number of the second single-bit arrays corresponds to the first value X and the number of the second sequences.

[0026] In some implementations of the second aspect, the method further includes: determining target digital data, the target digital data being the digital data with a smaller bit number between the first digital data and the second digital data; performing sequence splitting on the target digital data to generate a plurality of first sequences or a plurality of second sequences, a number of the first sequences being determined according to a bit number of the first digital data and a bit number of the first sequences, and a number of the second sequences being determined according to a bit number of the second digital data and a bit number of the second sequences; and performing the single-bit conversion on the first digital data according to the first value X to generate a plurality of first single-bit arrays, wherein a number of the first single-bit arrays corresponds to the first value X, in a case where the target digital data is the first digital data, includes: performing single-bit conversion on the plurality of first sequences according to the first value X to generate a plurality of first single-bit arrays, wherein a number of the first single-bit arrays corresponds to the first value X and the number of the first sequences; and performing the single-bit conversion on the second digital data according to the first value X to generate a plurality of second single-bit arrays, wherein a number of the second single-bit arrays corresponds to the first value X, in a case where the target digital data is the second digital data, includes: performing single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, wherein a number of the second single-bit arrays corresponds to the first value X and the number of the second sequences.

[0027] In some implementations of the second aspect, the determining the product of the first digital data and the second digital data according to the plurality of first convolution results includes: performing bit-by-bit addition processing according to the bit number of the first sequences and / or the bit number of the second sequences and the first convolution results to determine the product of the first digital data and the second digital data. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic flowchart of processing data provided by the present application;

[0029] Figure 2 is a schematic structural diagram of an optical convolution system for convolution calculation by projection method;

[0030] Figure 3 is a schematic diagram of phase addition;

[0031] Figure 4 is a schematic structural diagram of a data processing device provided by the present application;

[0032] Figure 5 is a schematic structural diagram of another data processing device provided by the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0034] Figure 1 shows a schematic flowchart of processing data.

[0035] S110, obtaining first digital data A and second digital data B.

[0036] The base value of the base of the first digital data A and the second digital data B is a first value X, and X is a positive integer.

[0037] Wherein, the number of bits of the first digital data A and / or the number of bits of the second digital data B is greater than the number of bits that the computer can process, or the result of the multiplication of the first digital data A and the second digital data B is greater than the number of bits that the computer can process.

[0038] In a possible implementation, S120, the first digital data A is sequentially split.

[0039] to generate a plurality of first sequences, the number of first sequences being determined according to the number of bits of the first digital data and the number of bits of the first sequence.

[0040] It should be noted that the number of bits of the first sequence is determined.

[0041] For example, the first digital data A is split every Q bits from low to high to generate P first sequences with a length of Q, P and Q being positive integers.

[0042] It should be noted that each of the P first sequences includes Q numbers, and if the length of the first sequence generated by the last sequence splitting is less than Q, zero is added to the high bit to make up Q bits.

[0043] For example, the first digital data A is "12345678901234567890", and the first digital data A is split into sequences every 9 bits from low to high, to generate 3 first sequences of length 9, which are "234567890", "345678901", and "000000012" respectively.

[0044] In a possible implementation, S130, the second digital data B is split into sequences.

[0045] to generate a plurality of second sequences, the number of second sequences being determined according to the number of bits of the second digital data and the number of bits of the second sequence.

[0046] It should be noted that the number of bits of the second sequence is determined.

[0047] For example, the second digital data B is split into sequences every R bits from low to high, to generate S second sequences of length R, S and R being positive integers.

[0048] It should be noted that each of the S second sequences includes R numbers, and if the length of the second sequence generated by the last sequence splitting is less than R, zero is added to the high bits to make up R bits.

[0049] The numbers Q and R can be the same or different, and can be determined according to the base of the digital data A and the digital data B, for example, if the first value X of the base of the first digital data A and the second digital data B is 10, R can be taken as 9 and Q can be taken as 9, that is, the value of R = X-1 and / or Q = X-1 can be taken, so that the number of carries in the subsequent calculation process can be reduced.

[0050] Optionally, a target digital data is determined, the target digital data being the digital data with fewer bits among the first digital data and the second digital data, and the target digital data is split into sequences to generate P first sequences or S second sequences, P being determined according to the number of bits of the first digital data and the number of bits of the first sequence, and S being determined according to the number of bits of the second digital data and the number of bits of the second sequence.

[0051] That is, the digital data with fewer bits among the first digital data A and the second digital data B can be selected for sequence splitting processing. When calculating the product of the digital data A and the digital data B, one of the digital data can be subjected to sequence splitting processing, for example, the digital data with fewer bits can be subjected to sequence splitting processing, or both of the digital data can be subjected to sequence splitting processing, so that the complexity of the computer in calculating the multiplication of large numbers can be reduced.

[0052] S140, single-bit conversion is performed on the first digital data A according to the first value X.

[0053] to generate a plurality of first single-bit arrays.

[0054] For example, if the first digital data A is not subjected to sequence splitting, X-1 first single-bit arrays are generated. If the first digital data A is subjected to sequence splitting to generate P first sequences, P first array sets are generated, each of which includes X-1 first single-bit arrays.

[0055] S150, single-bit conversion is performed on the second digital data B according to the first value X.

[0056] to generate a plurality of second single-bit arrays.

[0057] For example, if the second digital data B is not subjected to sequence splitting, X-1 second single-bit arrays are generated. If the second digital data B is subjected to sequence splitting to generate S second sequences, S second array sets are generated, each of which includes X-1 second single-bit arrays.

[0058] For the sake of clarity, the following takes the first digital data A as an example for sequence splitting processing.

[0059] Single-bit conversion is performed on the first digital data A, which can be understood as performing single-bit conversion on P first sequences each having a length of Q to generate P first array sets, each of which includes X-1 first single-bit arrays, and each first single-bit array has a bit number of Q.

[0060] For example, the first digital data A is subjected to sequence splitting to become P first sequences A0, A1, …, AP-1, each of which is subjected to single-bit conversion to generate X-1 first single-bit arrays. P-1 Each first sequence generates X-1 first single-bit arrays, that is, the first digital data A can generate P times X-1 first single-bit arrays.

[0061] For the sake of clarity, the following takes single-bit conversion of the second digital data B as an example, and the second digital data B is not subjected to sequence splitting processing.

[0062] Single-bit conversion is performed on the second digital data B to generate X-1 second single-bit arrays, each of which has a length of M, which is a positive integer, of the second digital data.

[0063] In a possible implementation, the second digital data B can be subjected to single-bit conversion by using the proportion representation method.

[0064] X-1 all-0 arrays each having a length of M are created.

[0065] For example, if the second number B = 654310418, the first base of the second number X = 10, and the number of bits M = 9, then create 9 arrays of all zeros with a length of 9:

[0066] B0 = [0,0,0,0,0,0,0,0,0];

[0067] B1 = [0,0,0,0,0,0,0,0,0];

[0068] …

[0069] B8 = [0,0,0,0,0,0,0,0,0].

[0070] Determine the (i+1)th array B among X-1 arrays. i The j-th element B ij The value of .

[0071] i starts from 0. If i is less than the j-th digit of the second number B, then B ij =1, otherwise, B ij =0.

[0072] Determine B 32 Taking the value of B as an example 32 Let i be the value of the second element in the fourth array B3. The second digit of the second data B is 5. Since i = 3 < 5, B 32 =1; then determine B 45 Taking the value of B as an example 45 Let i be the value of the 5th element in the 5th array B4. The 5th digit of the second data B is 1. Since i = 4 > 1, B... 45 =0, therefore, after performing single-bit conversion on the second digital data B, the generated 9 second single-bit arrays are:

[0073] B0 = [1,1,1,1,1,0,1,1,1];

[0074] B1 = [1,1,1,1,0,0,1,0,1];

[0075] B2 = [1,1,1,1,0,0,1,0,1];

[0076] B3 = [1,1,1,0,0,0,1,0,1];

[0077] B4 = [1,1,0,0,0,0,0,0,1];

[0078] B5 = [1,0,0,0,0,0,0,0,1];

[0079] B6=[0, 0, 0, 0, 0, 0, 0, 0, 1];

[0080] B7=[0, 0, 0, 0, 0, 0, 0, 0, 1];

[0081] B8=[0, 0, 0, 0, 0, 0, 0, 0, 0].

[0082] The manner of single-bit conversion of the first digital data A is similar, and is not described here for brevity.

[0083] It should be noted that the above examples are only illustrative, and the present application does not limit the manner of single-bit conversion, which can be performed by the above-mentioned ratio representation method, the binary representation method, or other methods.

[0084] S160, performing convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays.

[0085] to generate a plurality of first convolution results.

[0086] Optionally, an electrical convolution system can be used to perform convolution calculation on each of the plurality of first single-bit arrays and each of the plurality of second single-bit arrays.

[0087] Optionally, the embodiment of the present application can also use an optical convolution system to perform convolution calculation on each of the plurality of first single-bit arrays and each of the plurality of second single-bit arrays.

[0088] For example, in combination with Figure 2 the manner of convolution calculation in Figure 1 , an optical convolution system using a projection method for convolution calculation is shown. Figure 2

[0089] Suppose that the first digital data A is split into sequences and converted into P first array sets after single-bit conversion, each first array set including X-1 first single-bit arrays: A 00 ,…,A 0(X-1) ,A 10 ,…,A 1(X -1),…,A P0 ,…,A P(X-1) , each first single-bit array having a length of Q, and the second digital data B is not split into sequences and converted into X-1 second single-bit arrays B0,…,B X-1 , each second bit array having a length of M.

[0090] ​The optical convolution system comprises a first plane P1, a second plane P2, a cylindrical lens, and a detection plane P3.

[0091] The first single-bit arrays are modulated onto the first plane P1.

[0092] Optionally, the first single-bit arrays can be modulated onto the first plane P1 by using single-dimension modulation, or can be modulated onto the first plane P1 by using multi-dimension modulation of the light.

[0093] It should be noted that the modulation manner can be determined according to the size of the modulation plane and the number of pixel points. If the modulation plane is large and the pixel points are more, single-dimension modulation can be used. If the modulation plane is small and the pixel points are less, multi-dimension modulation can be used. The multi-dimension modulation can use the characteristics of multiple dimensions, such as spatial position, wavelength, amplitude, angular momentum, etc. Or the same dimension can be used to distinguish the physical characteristics, such as wavelength modulation with equidistantly divided wavelength modulation range.

[0094] The second single-bit arrays are modulated onto the second plane P2.

[0095] Optionally, the second single-bit arrays can be modulated onto the second plane P1 by using single-dimension modulation, or can be modulated onto the second plane P1 by using multi-dimension modulation of the light.

[0096] It should be noted that the first single-bit arrays can be modulated onto the second plane P2, and the second single-bit arrays can be modulated onto the first plane P1. The present application does not make any limitation in this regard.

[0097] The modulated first single-bit arrays and the modulated second single-bit arrays are convolved by physical characteristics, and are projected onto the detection plane through the cylindrical lens. At this time, a detector for detecting different dimensions can be used, such as a detector for detecting the amplitude intensity of different wavelengths. The light intensity of each point is recorded, which is the convolution result of each array.

[0098] It should be noted that the above is only an example of obtaining the first convolution result. The present application does not make any limitation on the convolution calculation manner. An electrical convolution system can be used, an optical convolution system (such as a 4F system, an 8F system, and a projection method system as shown in FIG. 8) can be used, or other new calculation systems can be used. Figure 2

[0099] ​Assuming that the optical convolution system is used, because the array for convolution calculation is a single-bit array, the requirement for modulation accuracy of the optical convolution system is 1 bit. The requirement for detection accuracy of the optical convolution system is related to the base of the first digital data and the second digital data, for example, if the base of the first digital data and the second digital data is 10, the requirement for detection accuracy is 4 bits. Therefore, in the present application, the requirement for the optical convolution system used for convolution calculation can be reduced.

[0100] In addition, assuming that the detection accuracy of the existing optical convolution system is higher than the required accuracy, the base of the first digital data and the second digital data can be increased correspondingly, for example, assuming that the detection accuracy of the optical convolution system is 10 bits, the actually supportable base is 1024, then the base of the first digital data and the second digital data can be converted to a higher base before sequence splitting or single-bit conversion, and then the large number multiplication processing is performed, so that the number of pixel points required by the modulation plane in the optical convolution system can be reduced.

[0101] S170, determining the product of the first digital data A and the second digital data B according to the first convolution result.

[0102] If the first convolution result is obtained in the optical convolution system, the first convolution result can be sent to an electrical calculation system, such as a processor, for processing.

[0103] In a possible implementation, if the first digital data A and the second digital data B are not subjected to single-bit conversion after sequence splitting, the first convolution result is reorganized into a natural number according to the high and low position correspondence, and the 0 in the high position is ignored. For example, the first convolution result of one of the first single-bit arrays A2 corresponding to the first digital data A and one of the second single-bit arrays B5 corresponding to the second digital data B is [0, 0, 1, 4, 1, 1, 4, 6, 8, 0, 0, 0], the first convolution result is reorganized according to the high and low position correspondence to obtain a natural number A2B5 = 1411468000, which can be understood as the product of the first single-bit array A2 and the second single-bit array B5. Thus, the (X-1) 2 first convolution results can obtain (X-1) 2 natural numbers A0B0,…, A0B X-1 1,…, A1B0,…, A1B X-1 ,…, A X-1 B0,…, A X-1 B X-1 . The product of the first digital data A and the second digital data B is the sum of the (X-1) 2 natural numbers.

[0104] In another possible implementation, if the first digital data A is split into sequences and then converted to single bits, while the second digital data B is not split into sequences and then converted to single bits, the first digital data A, after being converted to single bits, generates P sets of first arrays, each set containing X-1 first single-bit arrays. The second digital data, after being converted to single bits, generates X-1 second single-bit arrays. Multiplying the P sets by the X-1 first single-bit arrays and then convolving them with the X-1 second single-bit arrays generates P sets of first convolution result sets, each set containing (X-1)... 2 The first convolution result is obtained by recombining the high and low positions of the multiple first convolution results to obtain P multiplied by (X-1). 2 There are _n_ natural numbers, where the i-th group is A. i0 B0,…,A i0 B X-1 A i1 B0,…,A i1 B X-1 ,…,A i(X-1) B0,…,A i(X-1) B X-1 .

[0105] Summing each of the P groups of natural numbers yields A0B, ..., A i B,…,A P-1 B, and perform positional addition, for example, refer to Figure 3 The A0B and A1B are arranged vertically in a manner that places them at the lowest position, while A1B is shifted Q positions higher up. In other words, A... i B is successively compared to A i-1 B is shifted away from the higher bits by Q bits, and the result of adding the bits is the product of the first digital data A and the second digital data B.

[0106] It should be noted that since the first digital data A is split into Q bits at a time during sequence splitting, the Q bits need to be staggered sequentially when summing the bits.

[0107] Optionally, the addition can be performed by partitioning the data. For example, it can be partitioned according to every Q bits, or according to the number of bits of data that the computer can process. For example, if the computer can process 64 bits of data, the vertical addition can be partitioned into 64-bit sections from the least significant bit to the most significant bit. Partitioning according to the number of bits of data that the computer can process can obtain the fewest combinations, thereby improving the efficiency of the calculation.

[0108] Add the natural numbers in each partitioned area digit by digit, handle the carry-over as normal addition, and then put the results of each area together to form the product of the first number A and the second number B.

[0109] In another possible implementation, if the first digital data A is subjected to single-bit conversion after sequence splitting, and the second digital data B is also subjected to single-bit conversion after sequence splitting, the first digital data A generates P first array sets after single-bit conversion, each of which includes X-1 first single-bit arrays, and the second digital data B generates S second array sets after single-bit conversion, each of which includes X-1 second single-bit arrays, then P×S×(X-1) 2 first convolution results are obtained through high-low position corresponding reorganization, thereby P×S×(X-1) 2 first convolution results are obtained through high-low position corresponding reorganization, thereby P×S×(X-1) 2 natural numbers, wherein the natural number corresponding to the first convolution result of the i-th first array set in the P first array sets and the j-th second array set in the S second array sets is A i0 B j0 ,…,A i0 B j(X-1) ,A i1 B j0 ,…,A i1 B j(X -1),…,A i(X-1) B j0 ,…,A i(X-1) B j(X-1) .

[0110] respectively, and then summing each group of natural numbers to obtain A0B0,…,A0B S-1 ,…,A P-1 B0,…,A P-1 B S-1 , optionally, (A0B0,…,A0B S-1 ), (A1B0,…,A1B S-1 ), …, (A P-1 B0,…,A P-1 B S-1 ) can be sequentially subjected to bit-by-bit addition to obtain A0B,…,A i B,…,A P-1 B, the bit-by-bit addition manner is similar to the above-described bit-by-bit addition manner, which will not be described here again, but it needs to be noted that, because the second digital data B is split every R bits in sequence splitting, the vertical direction is staggered by R bits when staggered. A0B,…,A i B,…,A P-1 B is subjected to bit-by-bit addition again, thereby the product of the first digital data A and the second digital data B can be obtained.

[0111] Optionally, (A0B0,…,A P-1B0), (A0B1, …, A P-1 B1), …, (A0B S-1 ,…,A P- 1B S-1 ) to obtain AB0, …, AB i ,…,AB S-1 , and then performing a bit-by-bit addition on AB0, …, AB i ,…,AB S-1 to obtain the product of the first digital data A and the second digital data B.

[0112] Thus, in the present application, both the first digital data and the second digital data are converted into single-bit arrays, thereby avoiding the carry processing in the convolution calculation, and thus being able to improve the efficiency of the multiplication processing on large numbers while meeting high precision.

[0113] Figure 4 is a device 200 for processing data provided by an embodiment of the present application. Referring to Figure 4 , the device 200 can include a processing unit 210 and a transceiver unit 220.

[0114] Optionally, the device 200 can correspond to the device for processing data in the above method embodiment, and can include an electrical processing system, an optical processing system, a chip, or a chip system.

[0115] It should be understood that the device 200 can correspond to the device for processing data in the method according to the embodiment of the present application, and the device 200 can include units for executing the method in Figure 1 . Moreover, each unit in the device 200 and the other operations and / or functions described above are respectively implemented to realize the corresponding flow in Figure 1 .

[0116] When the device 1000 is used to execute the method in Figure 3 , the transceiver unit 220 is configured to obtain first digital data and second digital data, the base value of the base of the first digital data and the second digital data being a first value X, the X being a positive integer; the processing unit 210 is configured to perform single-bit conversion on the first digital data according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the first value X; and is further configured to perform single-bit conversion on the second digital data according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X; and is further configured to perform convolution calculation on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results; and is further configured to determine the product of the first digital data and the second digital data according to the plurality of first convolution results.

[0117] Figure 5 is another schematic block diagram of the apparatus 300 provided by the embodiments of the present application. As shown in the figure, the apparatus 300 includes a processor 310, a transceiver 320 and a memory 330. Among them, the processor 310, the transceiver 320 and the memory 330 communicate with each other through internal connection paths, the memory 330 is used to store instructions, and the processor 310 is used to execute the instructions stored in the memory 330 to control the transceiver 320 to send signals and / or receive signals. Optionally, the processor 310 and the memory 330 can also be integrated together. Figure 5

[0118] It should be understood that the apparatus 300 can correspond to the apparatus for processing data in the above-mentioned method embodiments, and can be used to execute the steps and / or processes in the above-mentioned method embodiments. Optionally, the memory 330 can include read-only memory and random access memory, and provide instructions and data to the processor. A part of the memory can also include non-volatile random access memory. The memory 330 can be one separate device, or can be integrated in the processor 310. The processor 310 can be used to execute the instructions stored in the memory 330, and when the processor 310 executes the instructions stored in the memory, the processor 310 is used to execute the steps and / or processes of the above-mentioned method embodiments.

[0119] Among them, the transceiver 320 can include a transmitter and a receiver. The transceiver 320 can further include an antenna, and the number of antennas can be one or more. The processor 310 and the memory 330 and the transceiver 320 can be devices integrated on different chips. For example, the processor 310 and the memory 330 can be integrated in a baseband chip, and the transceiver 320 can be integrated in a radio frequency chip. The processor 310 and the memory 330 and the transceiver 320 can also be devices integrated on the same chip. The present application does not make any limitation in this regard.

[0120] Optionally, the apparatus 300 is a component, such as a circuit, an optical device, a chip, a chip system, etc., configured in the apparatus for processing data.

[0121] Among them, the transceiver 320 can also be a communication interface, such as an input / output interface, a circuit, etc. The transceiver 320, the processor 310 and the memory 330 can be integrated in the same chip, such as a baseband chip.

[0122] The present application also provides a processing apparatus, including at least one processor, the at least one processor is used to execute a computer program stored in a memory, so that the processing apparatus executes the method performed by the terminal device or the access network device in any one of the above-mentioned method embodiments.

[0123] ​The embodiment of the present application further provides a processing device, comprising a processor and a communication interface. The communication interface is coupled with the processor. The communication interface is used for inputting and / or outputting information. The information comprises at least one of instructions and data. The processor is used for executing a computer program, so that the processing device executes the method performed by the terminal device or the access network device in any of the method embodiments.

[0124] The embodiment of the present application further provides a processing device, comprising a processor and a memory. The memory is used for storing a computer program, and the processor is used for calling and running the computer program from the memory, so that the processing device executes the method performed by the terminal device or the access network device in any of the method embodiments.

[0125] It should be understood that the processing device described above can be one or more chips. For example, the processing device can be a field programmable gate array (FPGA), can be an application specific integrated circuit (ASIC), can also be a system on chip (SoC), can also be a central processor unit (CPU), can also be a network processor (NP), can also be a digital signal processor (DSP), can also be a micro controller unit (MCU), can also be a programmable logic device (PLD) or other integrated chip.

[0126] In the implementation process, each step of the above method can be completed by integrated logic circuits of hardware in the processor or instructions in the form of software. The steps of the method disclosed in the embodiment of the present application can be directly embodied as hardware processor execution completion, or executed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory, an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0127] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the above method embodiments can be completed by an integrated logic circuit or an instruction in the form of software in the processor. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the storage, and the processor reads the information in the storage, and combines the hardware to complete the steps of the above method.

[0128] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct memory bus random access memory (DRAM). It should be noted that the memory of the system and method described herein is intended to include but not limited to these and any other suitable types of memory.

[0129] According to the method provided in the embodiments of the present application, the present application further provides a computer program product, which comprises computer program codes, and when the computer program codes are run on a computer, the computer is caused to execute the method of Figure 3 The method executed by the terminal device or the method executed by the network device in the embodiments shown.

[0130] According to the method provided in the embodiments of the present application, the present application further provides a computer readable storage medium, which stores program codes, and when the program codes are run on a computer, the computer is caused to execute the method of Figure 3 The method executed by the terminal device or the method executed by the network device in the embodiments shown.

[0131] According to the method provided in the embodiments of the present application, the present application further provides a system, which comprises the electrical processing system and the optical processing system.

[0132] The method embodiments in each of the above apparatus embodiments correspond completely, and the corresponding steps are executed by the corresponding modules or units, for example, the communication unit (transceiver) executes the steps of receiving or transmitting in the method embodiments, and the other steps except transmitting and receiving can be executed by the processing unit (processor). The functions of the specific units can refer to the corresponding method embodiments. The processor can be one or more.

[0133] In this specification, the terms "component", "module", "system" and the like are used to represent a computer-related entity, hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution, and a component can be localized on one computer and / or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from programs, data included in a management information base, etc.), such as data in a signal formed by applying the signal to the comparable physical jacks.

[0134] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0135] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0136] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0137] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0138] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0139] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0140] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing apparatus, the apparatus comprising a transceiver unit and a processing unit, The transceiver unit is used to acquire first digital data and second digital data, wherein the base value of the first digital data and the second digital data is a first value X, and X is a positive integer; The processing unit is configured to perform single-bit conversion on the first digital data according to the first value X to generate multiple first single-bit arrays, wherein... The number of the first single-bit array corresponds to the first value X. It is also used to perform single-bit conversion on the second digital data according to the first value X to generate multiple second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X. It is also used to perform convolution calculations on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results. It is also used to determine the product of the first digital data and the second digital data based on the plurality of first convolution results; The processing unit is specifically used for: Optical convolution is used to perform convolution calculations on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results.

2. The apparatus as claimed in claim 1, characterized in that, The processing unit is further configured to perform sequence splitting on the first digital data to generate multiple first sequences, wherein the number of first sequences is determined based on the number of bits in the first digital data and the number of bits in the first sequence. Specifically, it is used to perform single-bit conversion on the plurality of first sequences according to the first value X to generate a plurality of first single-bit arrays, wherein the number of the first single-bit arrays corresponds to the number of the first value X and the number of the first sequences.

3. The apparatus as described in claim 1 or 2, characterized in that, The processing unit is further configured to perform sequence splitting on the second digital data to generate multiple second sequences, the number of which is determined based on the number of bits in the second digital data and the number of bits in the second sequences. Specifically, it is used to perform single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the number of the first value X and the number of the second sequences.

4. The apparatus as claimed in claim 1, characterized in that, The processing unit is further configured to determine target numerical data, wherein the target numerical data is the numerical data with the smaller median value between the first numerical data and the second numerical data. It is also used to perform sequence splitting on the target digital data to generate multiple first sequences or multiple second sequences, wherein the number of first sequences is determined based on the number of bits in the first digital data and the number of bits in the first sequence, and the number of second sequences is determined based on the number of bits in the second digital data and the number of bits in the second sequence. When the target digital data is the first digital data, it is further specifically used to perform single-bit conversion on the plurality of first sequences according to the first value X to generate a plurality of first single-bit arrays, wherein the number of first single-bit arrays corresponds to the number of the first value X and the number of the first sequences. When the target digital data is the second digital data, it is further specifically used to perform single-bit conversion on the plurality of second sequences according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the number of the first value X and the number of the second sequences.

5. The apparatus as described in any one of claims 2 to 4, characterized in that, The processing unit is specifically used for: The product of the first digital data and the second digital data is determined by bitwise addition based on the number of bits in the first sequence and / or the number of bits in the second sequence, as well as the first convolution result.

6. A method for processing data, characterized in that, The method includes: Acquire first digital data and second digital data, wherein the base value of the first digital data and the second digital data is a first value X, wherein X is a positive integer; The first digital data is converted into a single bit based on the first value X to generate a plurality of first single bit arrays, wherein the number of the first single bit arrays corresponds to the first value X. The second digital data is converted into a single bit based on the first value X to generate multiple second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X. Convolution calculations are performed on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results; The product of the first digital data and the second digital data is determined based on the plurality of first convolution results; Specifically, convolution calculations are performed on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results, including: Optical convolution is used to perform convolution calculations on the plurality of first single-bit arrays and the plurality of second single-bit arrays to generate a plurality of first convolution results.

7. The method as described in claim 6, characterized in that, The method further includes: The first digital data is split into multiple first sequences, the number of which is determined by the number of bits in the first digital data and the number of bits in the first sequence. The step of performing single-bit conversion on the first digital data according to the first value X to generate multiple first single-bit arrays, wherein the number of first single-bit arrays corresponds to the first value X, includes: The plurality of first sequences are converted into single bits according to the first value X to generate a plurality of first single-bit arrays, wherein the number of first single-bit arrays corresponds to the number of the first value X and the number of the first sequences.

8. The method as described in claim 6 or 7, characterized in that, The method further includes: The second digital data is split into multiple second sequences, the number of which is determined by the number of bits in the second digital data and the number of bits in the second sequence. The step of performing single-bit conversion on the second digital data according to the first value X to generate multiple second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the first value X, includes: The plurality of second sequences are converted into single bits according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the number of the first value X and the number of the second sequences.

9. The method as described in claim 6, characterized in that, The method further includes: Determine the target numerical data, which is the numerical data with the smaller median value between the first numerical data and the second numerical data; The target digital data is split into sequences to generate multiple first sequences or multiple second sequences. The number of first sequences is determined based on the number of bits in the first digital data and the number of bits in the first sequence. The number of second sequences is determined based on the number of bits in the second digital data and the number of bits in the second sequence. When the target digital data is the first digital data, the step of performing single-bit conversion on the first digital data according to the first value X to generate multiple first single-bit arrays, wherein the number of first single-bit arrays corresponds to the first value X, includes: The plurality of first sequences are converted into single bits according to the first value X to generate a plurality of first single-bit arrays, wherein the number of first single-bit arrays corresponds to the number of the first value X and the number of the first sequences; When the target digital data is the second digital data, the step of performing single-bit conversion on the second digital data according to the first value X to generate multiple second single-bit arrays, wherein the number of second single-bit arrays corresponds to the first value X, includes: The plurality of second sequences are converted into single bits according to the first value X to generate a plurality of second single-bit arrays, wherein the number of the second single-bit arrays corresponds to the number of the first value X and the number of the second sequences.

10. The method according to any one of claims 7 to 9, characterized in that, Determining the product of the first digital data and the second digital data based on the plurality of first convolution results includes: The product of the first digital data and the second digital data is determined by bitwise addition based on the number of bits in the first sequence and / or the number of bits in the second sequence, as well as the first convolution result.

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