Instruction execution method and apparatus, electronic device, and storage medium
By integrating CPU instructions into memory instructions and optimizing the instruction execution process, the performance gap between computing and storage under the von Neumann architecture was resolved, improving the computer's instruction processing efficiency and energy efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA TELECOM CORP LTD
- Filing Date
- 2022-08-08
- Publication Date
- 2026-05-19
AI Technical Summary
The performance differences between data computation and storage in existing Von Neumann architecture computers have resulted in "memory walls" and "power walls" that lead to increased computational load and instruction processing efficiency that does not meet actual needs.
By integrating some CPU instructions from the CPU instruction set into memory instructions to form a memory instruction set, and executing CPU instructions and memory instructions simultaneously according to the instruction order and the integration order, the instruction execution process is optimized.
It improves instruction execution efficiency, reduces computational energy consumption, reduces the number of data transfers, and enhances the computer's computational efficiency.
Smart Images
Figure CN115269007B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and in particular to an instruction execution method, apparatus, electronic device, and storage medium. Background Technology
[0002] In the current big data cloud environment, there is a need to store and process massive amounts of data, which places higher demands on the speed of data processing.
[0003] General-purpose computers commonly employ the von Neumann architecture, which separates computation from storage, with data moving back and forth between the two. This allows for a greater focus on expanding memory and making the CPU (Central Processing Unit) more complex to flexibly handle intricate instructions. However, with the rapid development of industries requiring high computing power, such as artificial intelligence and big data, the "memory wall" bottleneck caused by the performance difference between computation and storage in the von Neumann architecture, and the "power wall" bottleneck, which consumes a significant portion of energy due to repeated data transfers, have become increasingly pronounced. This has led to increased computational demands and instruction processing efficiency failing to meet actual needs.
[0004] Therefore, improving the efficiency of instruction processing has become an urgent technical problem to be solved.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] This disclosure provides an instruction execution method, apparatus, electronic device, and storage medium, which at least to some extent overcomes the problem of low instruction processing efficiency in related technologies.
[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0008] According to one aspect of this disclosure, an instruction execution method is provided, comprising: acquiring a CPU instruction set containing multiple central processing unit (CPU) instructions to be processed, and recording the instruction order of the CPU instructions in the CPU instruction set; integrating CPU instructions in the CPU instruction set that meet preset conditions into memory instructions, while retaining the original CPU instructions, and recording the integration order of the memory instructions to obtain a memory instruction set, wherein the preset conditions are that the CPU instructions have the condition of being convertible into memory instructions; and executing the CPU instruction set and the memory instruction set according to the instruction order and the integration order.
[0009] In one embodiment of this disclosure, executing the CPU instruction set and the memory instruction set according to the instruction order and the integration order includes: executing the CPU instruction set according to the instruction order; and executing the memory instruction set according to the integration order.
[0010] In one embodiment of this disclosure, executing the set of memory instructions according to the integration order includes: determining the current memory instruction to be executed according to the integration order; determining whether the current memory instruction is an invalid instruction, wherein the invalid instruction is a memory instruction whose corresponding CPU instruction has been executed; if yes, skipping the current memory instruction and processing the next memory instruction; if no, executing the current memory instruction.
[0011] In one embodiment of this disclosure, the method further includes: traversing the memory instruction set, and when all memory instructions in the memory instruction set have been executed, ending the execution of memory instructions.
[0012] In one embodiment of this disclosure, executing the CPU instruction set according to the instruction order includes: determining the current memory instruction to be executed according to the integration order; determining whether there is a corresponding memory instruction for the current CPU instruction; and if not, executing the current CPU instruction.
[0013] In one embodiment of this disclosure, the method further includes: if a corresponding memory instruction exists for the current CPU instruction, determining whether the memory instruction corresponding to the current CPU instruction has been executed; if yes, skipping the current CPU instruction and processing the next CPU instruction; if no, executing the current CPU instruction and marking the memory instruction corresponding to the current CPU instruction as an invalid instruction.
[0014] In one embodiment of this disclosure, the method further includes: traversing the CPU instruction set, and when all CPU instructions in the CPU instruction set have been executed, ending the execution of CPU instructions.
[0015] According to another aspect of this disclosure, an instruction execution apparatus is provided, comprising: an instruction acquisition module, configured to acquire a set of CPU instructions to be processed, including multiple central processing unit (CPU) instructions, and record the instruction order of the CPU instructions in the CPU instruction set; an instruction integration module, configured to integrate CPU instructions in the CPU instruction set that meet preset conditions into memory instructions, while retaining the original CPU instructions, and record the integration order of the memory instructions to obtain a memory instruction set, wherein the preset conditions are that the CPU instructions have the condition of being convertible into memory instructions; and an instruction execution module, configured to execute the CPU instruction set and the memory instruction set according to the instruction order and the integration order.
[0016] In one embodiment of this disclosure, the instruction execution module is further configured to execute the CPU instruction set according to the instruction order; and execute the memory instruction set according to the integration order.
[0017] In one embodiment of this disclosure, the instruction execution module is further configured to determine the current memory instruction to be executed according to the integration order; determine whether the current memory instruction is an invalid instruction, wherein the invalid instruction is a memory instruction whose corresponding CPU instruction has been executed; if so, skip the current memory instruction and process the next memory instruction; if not, execute the current memory instruction.
[0018] In one embodiment of this disclosure, the instruction execution module is further configured to traverse the memory instruction set, and terminate the execution of memory instructions when all memory instructions in the memory instruction set have been executed.
[0019] In one embodiment of this disclosure, the instruction execution module is further configured to determine the current CPU instruction to be executed according to the instruction sequence; determine whether there is a corresponding memory instruction for the current CPU instruction; and if not, execute the current CPU instruction.
[0020] In one embodiment of this disclosure, the instruction execution module is further configured to determine whether the memory instruction corresponding to the current CPU instruction has been executed if a corresponding memory instruction exists for the current CPU instruction; if yes, skip the current CPU instruction and process the next CPU instruction; if no, execute the current CPU instruction and mark the memory instruction corresponding to the current CPU instruction as an invalid instruction.
[0021] In one embodiment of this disclosure, the instruction execution module is further configured to traverse the CPU instruction set, and terminate the execution of CPU instructions when all CPU instructions in the CPU instruction set have been executed.
[0022] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the instruction execution method described above by executing the executable instructions.
[0023] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the above-described instruction execution method.
[0024] The embodiments of this disclosure provide an instruction execution method, apparatus, electronic device, and storage medium. The method involves acquiring a CPU instruction set containing multiple CPU instructions to be processed, recording the instruction order of the CPU instructions in the CPU instruction set, integrating CPU instructions that meet preset conditions into memory instructions while retaining the original CPU instructions, recording the integration order of the memory instructions, and obtaining a memory instruction set. The preset condition is that the CPU instructions can be converted into memory instructions. The CPU instruction set and the memory instruction set are then executed according to the instruction order and the integration order. This disclosure improves instruction execution efficiency by integrating a portion of the CPU instructions in the CPU instruction set into memory instructions, obtaining a memory instruction set, and simultaneously executing the CPU instructions and memory instructions according to the instruction order and the integration order.
[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0027] Figure 1 This diagram illustrates the architecture of an instruction execution system according to an embodiment of the present disclosure.
[0028] Figure 2 This diagram illustrates a flowchart of an instruction execution method according to an embodiment of the present disclosure;
[0029] Figure 3 This diagram illustrates an instruction execution method according to an embodiment of the present disclosure.
[0030] Figure 4 This diagram illustrates another instruction execution method in an embodiment of the present disclosure.
[0031] Figure 5 This diagram illustrates another instruction execution method in an embodiment of the present disclosure.
[0032] Figure 6 This diagram illustrates another instruction execution method in an embodiment of the present disclosure.
[0033] Figure 7 This diagram illustrates another instruction execution method in an embodiment of the present disclosure.
[0034] Figure 8 This diagram illustrates another instruction execution method flowchart in an embodiment of the present disclosure;
[0035] Figure 9 A schematic diagram of an instruction execution device according to an embodiment of the present disclosure is shown; and
[0036] Figure 10 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation
[0037] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0038] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0039] As mentioned in the background section, in the von Neumann architecture, both instructions and data are stored in memory. The CPU retrieves the next instruction or data from memory based on the address of the instruction. With the rapid development of industries requiring high computing power, such as artificial intelligence and big data, the "memory wall" bottleneck caused by the performance difference between computing and storage in the von Neumann architecture, and the "power wall" bottleneck, which causes a large proportion of energy consumption due to repeated data transfer, are becoming increasingly significant. This leads to increased computational load and instruction processing efficiency failing to meet actual needs.
[0040] Research shows that the current von Neumann architecture of computers has the following problems:
[0041] 1) Under the current von Neumann architecture, data is repeatedly moved between the CPU and memory, and the energy wasted in data movement is about 200 times that of actual computing energy.
[0042] 2) Due to the separation of memory and computation, the CPU needs to move data from memory at a specified address to a register before it can start computation. The result of the computation needs to be moved back to memory. About 20% of the instructions executed by the CPU are data moving instructions.
[0043] 3) Most of the instructions executed by the CPU are simple calculation instructions, which do not use the CPU's complex calculation structure.
[0044] 4) The CPU's execution speed is much faster than the memory's I / O (Input / Output) speed, and the CPU needs to wait for memory to fetch instructions.
[0045] Based on this, the present disclosure provides an instruction execution method, apparatus, electronic device, and storage medium. By integrating a portion of the CPU instructions in the CPU instruction set into memory instructions, a memory instruction set is obtained. The CPU instructions and memory instructions are executed simultaneously according to the instruction order and the integration order. When the CPU encounters an integrated CPU instruction and the corresponding memory instruction has already been executed, the CPU can skip the CPU instruction and process the next instruction, thereby optimizing the instruction execution process and improving instruction execution efficiency.
[0046] Figure 1 A schematic diagram of the architecture of an instruction execution system applicable to embodiments of this disclosure is shown.
[0047] like Figure 1 As shown, the system may include a CPU 110, an instruction integration module 120, an instruction execution module 130, a CPU calculation pointer 140, a memory calculation pointer 150, a memory-to-memory computing module 160, a memory execution module 170, and a memory-to-memory computing unit 180.
[0048] CPU 110 is used to fetch CPU instructions from memory, execute CPU instructions according to the execution order provided by CPU calculation pointer 140, and fetch or write data from memory according to CPU instructions. When encountering a CPU instruction that is to be integrated, if the memory instruction corresponding to the CPU instruction has been executed by memory execution module 170, the CPU instruction is skipped and the next CPU instruction is executed. If the memory instruction corresponding to the CPU instruction has not been executed by memory execution module 170, the CPU instruction is executed and the memory instruction corresponding to the CPU instruction is marked as an invalid instruction.
[0049] The instruction integration module 120 is used to integrate CPU instructions that can be executed in memory from CPU instructions that are pre-stored in memory into memory instructions, wherein the memory instructions are instructions that can be executed by the memory execution module 170.
[0050] The instruction execution module 130 is used to define the operation state between the in-memory computing units 180 based on the memory instructions integrated from the CPU instructions in memory.
[0051] CPU calculation pointer 140 is used to provide CPU 110 with the execution order of CPU instructions;
[0052] The memory calculation pointer 150 is used to provide the execution order of memory instructions to the memory execution module 170;
[0053] The in-memory computing module 160 is used to store data. The operation relationship is defined by the instruction execution module 130, and the operation relationship continues until the instruction execution module 130 actively cancels it.
[0054] The memory execution module 170 is used to execute memory instructions according to the execution order provided by the memory calculation pointer 150. When an invalid memory instruction is encountered, the memory instruction is skipped and the next memory instruction is processed.
[0055] The in-memory computing unit 180 is a unit used to provide storage data for the in-memory computing module 160. Computational relationships can be defined between the units, and the number of in-memory computing units 180 is unlimited.
[0056] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.
[0057] First, this disclosure provides an instruction execution method that can be executed by any electronic device with computing capabilities.
[0058] Figure 2 This diagram illustrates a flowchart of an instruction execution method according to an embodiment of the present disclosure, such as... Figure 2 As shown, the instruction execution method provided in this embodiment includes the following steps:
[0059] S202, Obtain the CPU instruction set containing multiple central processing unit (CPU) instructions to be processed, and record the instruction order of the CPU instructions in the CPU instruction set;
[0060] It's important to note that CPU instructions are instructions that can be executed by the CPU. Typically, a CPU instruction includes an opcode and an address code. The opcode is the instruction sequence number, used to indicate the execution order of instructions, while the address code mainly includes the source operand, the destination address, and the address of the next instruction. Here, a CPU instruction can be one of several types, such as arithmetic and logical operation instructions, floating-point operation instructions, and bit manipulation instructions. The CPU instruction set is a collection of instructions used by the CPU to calculate, store, and control the computer system.
[0061] CPU instructions can be obtained by compiling user-inputted code into CPU instructions, and a CPU instruction set can be obtained by compiling multiple user-inputted codes into different CPU instructions. The instruction order of CPU instructions in the CPU instruction set can be recorded according to the order in which the CPU instructions are obtained.
[0062] S204 integrates CPU instructions that meet preset conditions from the CPU instruction set into memory instructions, while retaining the original CPU instructions, and records the integration order of the memory instructions to obtain a memory instruction set. The preset condition is that the CPU instructions have the conditions to be converted into memory instructions.
[0063] It's important to note that memory instructions are instructions or commands that can be executed from memory. CPU instructions from the CPU instruction set can be input into memory. Memory then determines whether a CPU instruction can be integrated into a memory instruction, combining those executable in memory and retaining all CPU instructions. Here, when a memory instruction is executed, it can execute commands on memory locations that require memory address manipulation.
[0064] S206 executes the CPU instruction set and memory instruction set according to the instruction order and integration order.
[0065] It should be noted that memory instructions in the memory instruction set can be executed by memory in an integrated order, while CPU instructions in the CPU instruction set can be executed in an instruction order.
[0066] During the execution of memory instructions, when the CPU instruction corresponding to the memory instruction is not executed by the CPU, the memory operation state is defined according to the memory instruction. During the operation state maintenance period, refreshing the data will update the operation state. When the CPU instruction corresponding to the memory instruction is executed by the CPU, the memory instruction is skipped, and the next memory instruction in the memory instruction set is processed according to the integration order.
[0067] During the execution of CPU instructions, the CPU first checks whether a corresponding memory instruction exists. If it does not exist, the CPU instruction is executed directly. If it does exist, the CPU then checks whether the corresponding memory instruction has been executed by memory. If it has not been executed, the CPU executes the instruction and marks the corresponding memory instruction as invalid. If it has already been executed, the CPU instruction is skipped, and the next CPU instruction in the instruction set is processed according to the instruction order.
[0068] The instruction execution method provided in this disclosure integrates some CPU instructions in the CPU instruction set into memory instructions to obtain a memory instruction set. Then, it executes CPU instructions and memory instructions simultaneously according to the instruction order and the integration order. When the CPU encounters an integrated CPU instruction and the corresponding memory instruction has already been executed, the CPU can skip the CPU instruction and process the next instruction, thereby optimizing the instruction execution process and improving instruction execution efficiency.
[0069] In one embodiment of this disclosure, executing a CPU instruction set and a memory instruction set simultaneously according to instruction order and integration order includes: executing the CPU instruction set according to instruction order; and executing the memory instruction set according to integration order.
[0070] In one embodiment of this disclosure, see Figure 3 The diagram illustrates an instruction execution method. According to the instruction order and integration order, the CPU instruction set and the memory instruction set are executed. After executing a memory instruction, the CPU cancels the calculation state of the CPU instruction corresponding to that memory instruction.
[0071] In one embodiment of this disclosure, executing a set of memory instructions according to the integration order includes: determining the current memory instruction to be executed according to the integration order; determining whether the current memory instruction is an invalid instruction, wherein an invalid instruction is a memory instruction whose corresponding CPU instruction has already been executed; if yes, skipping the current memory instruction and processing the next memory instruction; if no, executing the current memory instruction.
[0072] In one embodiment of this disclosure, the method further includes: traversing the memory instruction set, and when all memory instructions in the memory instruction set have been executed, ending the execution of memory instructions.
[0073] In one embodiment of this disclosure, executing a set of CPU instructions according to the instruction order includes: determining the current CPU instruction to be executed according to the instruction order; determining whether the current CPU instruction has a corresponding memory instruction; and if not, executing the current CPU instruction.
[0074] It should be noted that the execution process of a CPU instruction may include: instruction fetch, instruction decoding, instruction execution, memory access, and result write-back.
[0075] Instruction fetching is the process of loading a CPU instruction from main memory into the instruction register. The value in the program counter (PC) indicates the current location of the instruction in main memory. After an instruction is fetched, the value in the PC automatically increments according to the instruction word length: if it is a single-word instruction, then (PC) + 1 -> PC; if it is a double-word instruction, then (PC) + 2 -> PC, and so on.
[0076] After the instruction is fetched, the computer enters the instruction compilation stage. Instruction decoding involves breaking down and interpreting the fetched instruction, identifying and distinguishing different instruction categories and various operands to be fetched.
[0077] Executing instructions refers to completing the various operations specified by the instructions, specifically implementing the functions of the instructions. To this end, different parts of the CPU are connected to execute the required operations.
[0078] Memory access refers to obtaining the address of the operand in main memory based on the instruction address code, and then reading the operand from main memory for computation.
[0079] Write-back refers to "writing back" the execution result data of the instruction execution stage to a certain storage form: the result data is often written to the CPU's internal registers so that it can be quickly accessed by subsequent instructions.
[0080] In one embodiment of this disclosure, the method further includes: if a corresponding memory instruction exists for the current CPU instruction, determining whether the memory instruction corresponding to the current CPU instruction has been executed; if yes, skipping the current CPU instruction and processing the next CPU instruction; if no, executing the current CPU instruction and marking the memory instruction corresponding to the current CPU instruction as an invalid instruction.
[0081] In one embodiment of this disclosure, the method further includes: traversing the CPU instruction set, and when all CPU instructions in the CPU instruction set have been executed, ending the execution of CPU instructions.
[0082] The instruction execution method provided in this disclosure allows the memory to predefine the operation state between the data to be processed before the CPU. The CPU can skip this part of the operation. Since this type of operation occurs frequently and involves a large number of data transfers, skipping this part of the operation can greatly improve the operation efficiency and reduce the operation power consumption.
[0083] In one embodiment of this disclosure, the instruction execution method disclosed in this embodiment can be provided by... Figure 1 For the publicly available system execution, see [link / reference]. Figure 4 The diagram illustrates another instruction execution method. First, the user-input code is compiled into CPU instructions. Each CPU instruction contains an opcode and operands. The opcode contains specific CPU operation information, and the operands indicate the location of the data to be operated on in the registers. After obtaining a CPU instruction set containing multiple CPU instructions, some instructions can be stored in memory. The instruction integration module then integrates the CPU instructions executable by the memory execution module into memory instructions.
[0084] For example, the CPU instructions before integration were:
[0085] Move data from address 1 to register 1 # Move the data at address 1 to register 1;
[0086] Move data from address 2 to register 2 # Move the data at address 2 to register 2;
[0087] Operation Register 1 Register 2 Register 3 # Perform an operation between register 1 and register 2, and store the result in register 3;
[0088] Move register 3 to address 3 # Write the data from register 3 to address 3;
[0089] The integrated memory instructions are:
[0090] Operation on address 1 Address 2 Address 3 # Perform an operation between the data at address 1 and the data at address 2, and store the result in address 3;
[0091] The CPU executes CPU instructions in the CPU instruction set according to the execution order provided by the CPU compute pointer. The memory execution module executes memory instructions in the memory instruction set according to the execution order provided by the memory execution pointer. The instruction execution module can also perform operations between stored data according to the memory instruction definition.
[0092] In one embodiment of this disclosure, a memory computing unit is provided on memory to offload the task of processing some instructions from the CPU to memory for execution. See [link to relevant documentation]. Figure 5 The diagram illustrates another instruction execution method. The instruction integration module integrates some instructions into instructions that can be executed in memory. The instruction execution unit executes the integrated computational instructions in parallel with the CPU. The storage units in memory are in-memory computing units that can perform operations on each other. The computational state between in-memory computing units is defined by memory instructions.
[0093] In one embodiment of this disclosure, the structure of the in-memory computing module provided in this disclosure can be referred to Figure 6 and Figure 7 As shown, see Figure 6 and Figure 7 The diagram shows another instruction execution method. The memory instruction operation is that address A is operated on address B and the result is stored in address C. In the corresponding arithmetic unit, address A, address B and address C are selected. The storage units of address A and address B are directly connected to perform the specified operation and the result is stored in address C.
[0094] The data stored at addresses A and B are continuously linked by operations. If data at addresses A and B is rewritten, it will synchronously cause the data at address C to be updated. In this way, even if the memory has preprocessed some instructions, it can still update its state synchronously with the CPU. When the CPU executes an instruction that skips this instruction, the operation ends, the selected switch is turned off, and the circuit connection is canceled.
[0095] Another instruction execution method is also provided in one embodiment of this disclosure, see [link to relevant documentation]. Figure 8 The flowchart shown represents another instruction execution method, which may include:
[0096] S802, obtain a CPU instruction set containing multiple CPU instructions, and record the instruction order of the CPU instructions in the CPU instruction set;
[0097] S804 integrates CPU instructions that meet preset conditions from the CPU instruction set into memory instructions, while retaining the original CPU instructions and recording the integration order of the memory instructions to obtain the memory instruction set.
[0098] S806 executes the CPU instruction set according to the instruction sequence;
[0099] S808 determines the current CPU instruction to be processed based on the instruction sequence;
[0100] S810: Determine if there is a corresponding memory instruction for the current CPU instruction. If yes, execute S812; otherwise, execute S814.
[0101] S812 determines whether the memory instruction corresponding to the current CPU instruction has been executed. If yes, execute S816; otherwise, execute S814.
[0102] S814 executes the current CPU instruction and marks the memory instruction corresponding to the current CPU instruction as an invalid instruction;
[0103] S816, skips the current CPU instruction;
[0104] S818 checks if there are any remaining CPU instructions in the CPU instruction set that have not been executed. If yes, S808 is executed; otherwise, the process ends.
[0105] The S820 executes a set of memory instructions according to the integration order;
[0106] S822 determines the current memory instruction that needs to be processed based on the instruction sequence;
[0107] S824: Determine if the current memory instruction is an invalid instruction. If yes, execute S828; otherwise, execute S826.
[0108] S826, executes the current memory instruction;
[0109] S828 checks if there are any remaining unexecuted memory instructions in the memory instruction set. If yes, execute S822; otherwise, end the process.
[0110] The other instruction execution method disclosed in this embodiment solves the same technical problem as the instruction execution method described above, and also achieves the same technical effect, so it will not be described in detail here.
[0111] Based on the same inventive concept, this disclosure also provides an instruction execution device, as shown in the following embodiment. Since the principle by which this device embodiment solves the problem is similar to that of the above-described method embodiment, the implementation of this device embodiment can refer to the implementation of the above-described method embodiment, and repeated details will not be described again.
[0112] Figure 9 This diagram illustrates an instruction execution device according to an embodiment of the present disclosure, such as... Figure 9 As shown, the device includes:
[0113] The instruction acquisition module 910 is used to acquire a set of CPU instructions to be processed, which contains multiple central processing unit (CPU) instructions, and to record the instruction order of the CPU instructions in the set of CPU instructions.
[0114] The instruction integration module 920 is used to integrate CPU instructions that meet preset conditions into memory instructions, while retaining the original CPU instructions, recording the integration order of memory instructions, and obtaining a set of memory instructions. The preset condition is that the CPU instructions have the conditions to be converted into memory instructions.
[0115] The instruction execution module 930 is used to execute the CPU instruction set and the memory instruction set according to the instruction order and the integration order.
[0116] In one embodiment of this disclosure, the instruction execution module 930 is further configured to execute a set of CPU instructions according to the instruction order and execute a set of memory instructions according to the integration order.
[0117] In one embodiment of this disclosure, the instruction execution module 930 is further configured to determine the current memory instruction to be executed according to the integration order; determine whether the current memory instruction is an invalid instruction, wherein an invalid instruction is a memory instruction whose corresponding CPU instruction has been executed; if so, skip the current memory instruction and process the next memory instruction; if not, execute the current memory instruction.
[0118] In one embodiment of this disclosure, the instruction execution module 930 is further configured to traverse the memory instruction set and terminate the execution of memory instructions when all memory instructions in the memory instruction set have been executed.
[0119] In one embodiment of this disclosure, the instruction execution module 930 is further configured to determine the current CPU instruction to be executed according to the instruction sequence; determine whether there is a corresponding memory instruction for the current CPU instruction; and if not, execute the current CPU instruction.
[0120] In one embodiment of this disclosure, the instruction execution module 930 is further configured to determine whether the memory instruction corresponding to the current CPU instruction has been executed if a corresponding memory instruction exists for the current CPU instruction; if yes, skip the current CPU instruction and process the next CPU instruction; if no, execute the current CPU instruction and mark the memory instruction corresponding to the current CPU instruction as an invalid instruction.
[0121] In one embodiment of this disclosure, the instruction execution module 930 is further configured to traverse the CPU instruction set and terminate the execution of CPU instructions when all CPU instructions in the CPU instruction set have been executed.
[0122] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."
[0123] The following reference Figure 10 To describe an electronic device 1000 according to such an embodiment of the present disclosure. Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.
[0124] like Figure 10 As shown, the electronic device 1000 is manifested in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one storage unit 1020, and a bus 1030 connecting different system components (including storage unit 1020 and processing unit 1010).
[0125] The storage unit stores program code, which can be executed by the processing unit 1010, causing the processing unit 1010 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 1010 can perform the following steps of the above method embodiment: obtaining a CPU instruction set containing multiple central processing unit (CPU) instructions to be processed, and recording the instruction order of the CPU instructions in the CPU instruction set; integrating CPU instructions in the CPU instruction set that meet preset conditions into memory instructions, while retaining the original CPU instructions, recording the integration order of the memory instructions, and obtaining a memory instruction set, wherein the preset condition is that the CPU instructions have the conditions to be converted into memory instructions; and executing the CPU instruction set and the memory instruction set according to the instruction order and the integration order.
[0126] In some embodiments of the electronic device provided in this disclosure, the processing unit 1010 is further configured to: execute a set of CPU instructions according to the instruction order; and execute a set of memory instructions according to the integration order.
[0127] In some embodiments, in the electronic device provided in this disclosure, the processing unit 1010 is further configured to: determine the current memory instruction to be executed according to the integration order; determine whether the current memory instruction is an invalid instruction, wherein the invalid instruction is a memory instruction whose corresponding CPU instruction has been executed; if yes, skip the current memory instruction and process the next memory instruction; if no, execute the current memory instruction.
[0128] In some embodiments of the present disclosure, the processing unit 1010 in the electronic device is further configured to: traverse the memory instruction set, and when all memory instructions in the memory instruction set have been executed, terminate the execution of the memory instructions.
[0129] In some embodiments of the present disclosure, the processing unit 1010 in the electronic device is further configured to: determine the current CPU instruction to be executed according to the instruction sequence; determine whether the current CPU instruction has a corresponding memory instruction; and if not, execute the current CPU instruction.
[0130] In some embodiments, in the electronic device provided in this disclosure, the processing unit 1010 is further configured to: determine whether the memory instruction corresponding to the current CPU instruction has been executed if the current CPU instruction has a corresponding memory instruction; if yes, skip the current CPU instruction and process the next CPU instruction; if no, execute the current CPU instruction and mark the memory instruction corresponding to the current CPU instruction as an invalid instruction.
[0131] In some embodiments of the present disclosure, the processing unit 1010 in the electronic device is further configured to: traverse the CPU instruction set, and when all CPU instructions in the CPU instruction set have been executed, terminate the execution of the CPU instructions.
[0132] Storage unit 1020 may include readable media in the form of volatile storage units, such as random access memory (RAM) 10201 and / or cache memory 10202, and may further include read-only memory (ROM) 10203.
[0133] Storage unit 1020 may also include a program / utility 10204 having a set (at least one) program module 10205, such program module 10205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.
[0134] Bus 1030 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the multiple bus structures.
[0135] Electronic device 1000 can also communicate with one or more external devices 1040 (e.g., keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with electronic device 1000, and / or any device that enables electronic device 1000 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1050. Furthermore, electronic device 1000 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1060. As shown, network adapter 1060 communicates with other modules of electronic device 1000 via bus 1030. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0136] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.
[0137] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. A program product capable of implementing the methods described above is stored thereon. In some possible implementations, various aspects of this disclosure may also be implemented as a program product including program code. When the program product is run on a terminal device, the program code causes the terminal device to execute the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, when a computer program stored on a computer-readable storage medium in an embodiment of this disclosure is executed by a processor, the following steps of the following method can be implemented: obtaining a set of CPU instructions to be processed, containing multiple central processing unit (CPU) instructions, and recording the instruction order of the CPU instructions in the CPU instruction set; integrating CPU instructions in the CPU instruction set that meet preset conditions into memory instructions, while retaining the original CPU instructions, recording the integration order of the memory instructions, and obtaining a set of memory instructions, wherein the preset condition is that the CPU instructions have the condition of being convertible into memory instructions; and executing the CPU instruction set and the memory instruction set according to the instruction order and the integration order.
[0138] In some embodiments of this disclosure, when a computer program stored on a computer-readable storage medium is executed by a processor, the following steps of the following method can also be implemented: executing a set of CPU instructions according to the instruction order; executing a set of memory instructions according to the integration order.
[0139] In some embodiments of this disclosure, when a computer program stored on a computer-readable storage medium is executed by a processor, the following steps of the following method can also be implemented: determining the current memory instruction to be executed according to the integration order; determining whether the current memory instruction is an invalid instruction, wherein an invalid instruction is a memory instruction whose corresponding CPU instruction has been executed; if yes, skipping the current memory instruction and processing the next memory instruction; if no, executing the current memory instruction.
[0140] In some embodiments of this disclosure, when a computer program stored on a computer-readable storage medium is executed by a processor, the following steps of the following method can also be implemented: traversing the memory instruction set, and when all memory instructions in the memory instruction set have been executed, ending the execution of the memory instructions.
[0141] In some embodiments of this disclosure, when a computer program stored on a computer-readable storage medium is executed by a processor, the following steps of the following method can also be implemented: determining the current CPU instruction to be executed according to the instruction sequence; determining whether there is a corresponding memory instruction for the current CPU instruction; if not, executing the current CPU instruction.
[0142] In some embodiments of this disclosure, when a computer program stored on a computer-readable storage medium is executed by a processor, the following steps of the following method can also be implemented: if a corresponding memory instruction exists for the current CPU instruction, determine whether the memory instruction corresponding to the current CPU instruction has been executed; if yes, skip the current CPU instruction and process the next CPU instruction; if no, execute the current CPU instruction and mark the memory instruction corresponding to the current CPU instruction as an invalid instruction.
[0143] In some embodiments of this disclosure, when a computer program stored on a computer-readable storage medium is executed by a processor, the following steps of the following method can also be implemented: traversing the CPU instruction set, and when all CPU instructions in the CPU instruction set have been executed, ending the execution of CPU instructions.
[0144] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0145] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.
[0146] Optionally, the program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.
[0147] In practical implementation, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java and C++, and conventional procedural programming languages such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).
[0148] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.
[0149] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.
[0150] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.
[0151] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for executing instructions, characterized in that, include: Obtain a set of CPU instructions to be processed, which contains multiple central processing unit (CPU) instructions, and record the instruction order of the CPU instructions in the set of CPU instructions; The CPU instructions that meet the preset conditions in the CPU instruction set are integrated into memory instructions, while the original CPU instructions are retained. The integration order of the memory instructions is recorded to obtain a memory instruction set. The preset condition is that the CPU instructions have the condition of being convertible into memory instructions. The CPU instruction set and the memory instruction set are executed according to the instruction order and the integration order. The step of executing the CPU instruction set and the memory instruction set according to the instruction order and the integration order includes: executing the CPU instruction set according to the instruction order; The set of memory instructions is executed according to the integration order.
2. The instruction execution method according to claim 1, characterized in that, According to the integration order, the set of memory instructions is executed, including: Based on the integration order, determine the current memory instruction to be executed; Determine whether the current memory instruction is an invalid instruction, wherein the invalid instruction is a memory instruction whose corresponding CPU instruction has been executed; If so, skip the current memory instruction and process the next memory instruction; If not, execute the current memory instruction.
3. The instruction execution method according to claim 2, characterized in that, The method further includes: The set of memory instructions is traversed, and the execution of memory instructions ends when all memory instructions in the set have been executed.
4. The instruction execution method according to claim 1, characterized in that, According to the instruction sequence, the CPU instruction set is executed, including: Based on the instruction sequence, determine the current CPU instruction to be executed; Determine if a corresponding memory instruction exists for the current CPU instruction; If not, execute the current CPU instruction.
5. The instruction execution method according to claim 4, characterized in that, The method further includes: If a corresponding memory instruction exists for the current CPU instruction, determine whether the memory instruction corresponding to the current CPU instruction has been executed. If so, skip the current CPU instruction and process the next CPU instruction; If not, execute the current CPU instruction and mark the memory instruction corresponding to the current CPU instruction as an invalid instruction.
6. The instruction execution method according to claim 4, characterized in that, The method further includes: The CPU instruction set is traversed, and the execution of CPU instructions ends when all CPU instructions in the CPU instruction set have been executed.
7. An instruction execution device, characterized in that, include: The instruction acquisition module is used to acquire a set of CPU instructions to be processed, which contains multiple central processing unit (CPU) instructions, and to record the instruction order of the CPU instructions in the set of CPU instructions. The instruction integration module is used to integrate CPU instructions that meet preset conditions in the CPU instruction set into memory instructions, while retaining the original CPU instructions, recording the integration order of the memory instructions, and obtaining a memory instruction set. The preset condition is that the CPU instructions have the condition of being convertible into memory instructions. An instruction execution module is configured to execute the CPU instruction set and the memory instruction set according to the instruction order and the integration order; The step of executing the CPU instruction set and the memory instruction set according to the instruction order and the integration order includes: executing the CPU instruction set according to the instruction order; and executing the memory instruction set according to the integration order.
8. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the instruction execution method of any one of claims 1 to 6 by executing the executable instructions.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the instruction execution method according to any one of claims 1 to 6.