An instruction construction method and device supporting processing function extension
By storing function descriptors in the processor's source operands and resolving them with the accelerator, the decoding complexity caused by instruction set expansion is solved, enabling flexible expansion of processor functionality and scalability of the architecture.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGNAN INST OF COMPUTING TECH
- Filing Date
- 2022-08-12
- Publication Date
- 2026-05-19
AI Technical Summary
In existing processor designs, extending the instruction set functionality requires increasing the instruction length, which increases decoding complexity and limits the scalability of the processor architecture.
The target function descriptors are stored in the processor's source operands, and the accelerator parses these descriptors to identify the instruction function, thereby expanding the function without extending the instruction length.
It enables the expansion of processor functionality without increasing instruction decoding complexity, improving the processor's scalability and flexibility, and supporting custom function extensions.
Smart Images
Figure CN115269010B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-performance microprocessor design technology, and more specifically, to an instruction construction method and apparatus that supports extended processing capabilities. Background Technology
[0002] The instruction set defines the functions provided by the processor and serves as the interface between the processor's hardware and software. Typically, each instruction defines a function; for example, the addition instruction `add ra,rb,rd` means `ra + rb -> rd`, that is, the sum of `ra` and `rb` is assigned to `rd`. Here, `ra`, `rb`, and `rd` are register file identifiers, referred to as operands in the instruction, and `add` is the instruction function. A processor usually defines hundreds or even thousands of instructions, each encoded as a string of binary numbers. Different instructions can have the same or different encoding lengths. Generally, for the sake of decoding simplicity, the instruction width is usually the same, and within the same instruction width, different uses are defined at fixed positions. For example, participation... Figure 4 The RISC-V 32-bit instruction format uses opcode to encode instruction functions, such as add and sub; rs1 and rs2 to define source operands; rd to define destination operands; and funct to define more detailed functions.
[0003] The integration of artificial intelligence (AI) technology and the Internet of Things (IoT) in real-world applications has ushered in the AIoT era. This era will see another surge in processor demand, but it will also be one of fragmented demand. Different fields and industries will have different chip requirements, such as integrating different sensors and accelerators. How to address this fragmented demand will be a challenge. For processor design, especially instruction set design, how to handle the integration of different accelerators is a crucial issue. Different accelerators often implement different functions; while expanding instruction sets to support these different functions, how can the impact on instruction code length and processor decoding complexity be minimized?
[0004] Existing feature-extending instructions are typically based on traditional instruction encoding methods, adding new codes to the instruction opcode (such as the opcode in RISC-V instruction encoding) to extend functionality. However, once the instruction width and format are determined in a traditional instruction set design, the instruction encoding space is largely fixed, and the definable instruction functionality cannot grow indefinitely. Therefore, the common practice is to increase the instruction width, for example, from 32-bit instructions to 64-bit instructions, such as ARM's SVE instruction, which increases instruction length to support more features. However, increasing the instruction length increases the pressure on the processor's instruction buffer, increases the complexity of instruction decoding, and also limits the scalability design of the processor architecture. Summary of the Invention
[0005] To address the aforementioned issues, embodiments of this application provide a method and apparatus for constructing instructions that support extended processing capabilities.
[0006] Firstly, this application provides a method for constructing instructions that supports extended processing capabilities, comprising the following steps:
[0007] S1: Obtain the target source operand from the processor;
[0008] S2: Store the target function descriptor in the target source operand;
[0009] S3: Control the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function.
[0010] Preferably, before step S1, the method includes: receiving extended information sent by the input terminal, reading the name information and function information of the target source operand in the extended information respectively, and converting the function information into a target function descriptor.
[0011] Preferably, step S1 specifically includes:
[0012] Read the registers on the processor sequentially in the preset direction. If the name of a register is the name of the target source operand, then use that register as the target source operand.
[0013] Preferably, step S1 further includes:
[0014] Get the number of function descriptors in the target source operand. If the number is 0, continue execution. If the number is greater than or equal to 1, stop execution.
[0015] Secondly, embodiments of this application provide an instruction construction apparatus that supports extended processing capabilities, including...
[0016] The filtering module is used to obtain the target source operands from the processor;
[0017] The storage module is used to store the target function descriptor in the target source operand;
[0018] The parsing module controls the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function.
[0019] Preferably, it also includes
[0020] The information receiving module is used to receive extended information sent by the input terminal, read the name information and function information of the target source operand in the extended information respectively, and convert the function information into a target function descriptor.
[0021] Preferably, the filtering module includes:
[0022] The search unit is used to sequentially read registers on the processor along a preset direction. If the name of a register is the name of the target source operand, then that register is used as the target source operand.
[0023] Preferably, the filtering module further includes;
[0024] The decision unit is used to obtain the number of function descriptors in the target source operand. If the number is 0, execution continues; if the number is greater than or equal to 1, execution stops.
[0025] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method provided as in the first aspect or any possible implementation of the first aspect.
[0026] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method provided as in the first aspect or any possible implementation thereof.
[0027] The beneficial effects of the present invention are: 1) The target function descriptor is stored in the target source operand to realize the description instruction function. The accelerator parses the input function descriptor to identify the instruction function. Therefore, the function of the instruction can be further extended without extending the instruction length.
[0028] 2) Since instruction decoding only translates the opcode and not the target source operand, the complexity of instruction decoding is not affected while keeping the opcode unchanged.
[0029] 3) Since the function described by the target source operand is completely parsed and identified by the integrated accelerator, the design and implementation of the main processor can be completed even before the accelerator function is determined, thus facilitating the expansion of the functional structure. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 A flowchart illustrating an instruction construction method supporting extended processing functions provided in an embodiment of this application;
[0032] Figure 2 A schematic diagram of an instruction construction apparatus that supports extended processing functions, provided for an embodiment of this application;
[0033] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0034] Figure 4 This is a schematic diagram of the 32-bit wide instruction format of RISC-V in the embodiments of this application;
[0035] Figure 5 This is a schematic diagram of a 64-bit processor in an embodiment of this application. Detailed Implementation
[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0037] In the following description, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The following description provides multiple embodiments of this application, which can be substituted or combined with each other. Therefore, this application can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then this application should also be considered to include embodiments containing one or more other possible combinations of A, B, C, and D, even if such embodiments are not explicitly described in the following text.
[0038] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of this application. Various processes or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.
[0039] Please see Figure 1 . Figure 1 This is a flowchart illustrating a method for constructing instructions that supports extended processing capabilities, provided in an embodiment of this application. In this embodiment, the method includes the following steps:
[0040] S1: Obtain the target source operand from the processor;
[0041] S2: Store the target function descriptor in the target source operand;
[0042] S3: Control the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function.
[0043] In this embodiment, the instruction encoding space of existing processors is determined upon completion of manufacturing. Instruction functions can only be added by adding new codes to the processor's instruction opcodes. However, the number and size of instruction opcodes for each processor are fixed values. Therefore, once an instruction opcode is occupied, the instruction width needs to be increased when defining a new instruction function. Increasing the instruction width affects the instruction buffer and makes instruction decoding more complex. This application creatively proposes storing the target function descriptor in the target source operand. While maintaining the existing instruction width, by placing the extended processing function in the source operand, more functions can be greatly expanded. Furthermore, since this is an extended instruction specifically designed for accelerators, and the accelerator's function is not yet determined, this method of extending instruction functions through the data source operand offers considerable flexibility. It can be customized, as long as the added acceleration components can correctly identify and parse it. The overall characteristics of this instruction construction technology for extending instruction functions are strong scalability, good flexibility, and allow for custom functions. The function descriptor is stored in the source operand to describe the instruction function. The target function descriptor is a binary number representing a specific meaning. This application relates to a method for constructing instructions by redefining data as a processing function indication, and an acceleration device or extended function device using this processing function indication.
[0044] In one possible implementation, before step S1, the method includes: receiving extended information sent by the input terminal, reading the name information and function information of the target source operand in the extended information respectively, and converting the function information into a target function descriptor.
[0045] In this embodiment, the input terminal can be a keyboard or a mouse. The user inputs extended information at the input terminal. This extended information can be information such as storing function information in the source operand Ra. The system receives the extended information, reads the name information Ra and function information from the extended information, converts the function information into a binary number, i.e., converts it into a target function descriptor. In step S1, the target source operand Ra is located in the processor based on the name information Ra. In step S2, the binary number, i.e., the target function descriptor, is stored in the target source operand Ra.
[0046] In one possible implementation, step S1 specifically includes:
[0047] Read the registers on the processor sequentially in the preset direction. If the name of a register is the name of the target source operand, then use that register as the target source operand.
[0048] In the embodiments of this application, see Figure 5 In a 64-bit processor, a certain acceleration instruction uses 32-bit instruction encoding. This instruction uses two source operands, Ra and Rb, each 64 bits wide. To extend the instruction's functionality, both Ra and Rb are used to store extended information. For example, the 64-bit Ra can store necessary configuration information (such as accelerator configuration to complete a certain function), or it can store the expected function to be executed (which can be one or multiple functions, such as finding the maximum value of multiple results while performing accelerated calculations, etc.). If the name of the target source operand read from the extended information is Ra, the processor registers are read sequentially from 0 to 31 to obtain the name of each register. If the register name is not Ra, the reading continues in that direction. If the register name is the name of the target source operand, then that register is used as the target source operand.
[0049] In one possible implementation, step S1 further includes:
[0050] Get the number of function descriptors in the target source operand. If the number is 0, continue execution. If the number is greater than or equal to 1, stop execution.
[0051] In this embodiment, a source operand can only store one function descriptor. If the number of function descriptors in the target source operand is 0, it means that no function descriptor is stored in the target source operand, and the target function descriptor can be stored in the target source operand. If the number of function descriptors in the target source operand is greater than or equal to 1, it means that at least one function descriptor is stored in the target source operand, and the target function descriptor cannot be stored in the target source operand. The source operand is a general-purpose register, which is specified by the user during program writing. It can be any general-purpose register, as long as it stores the constructed function descriptor.
[0052] The following will be combined with the appendix Figure 2 This application provides a detailed description of the instruction construction apparatus that supports extended processing functions, as provided in the embodiments of this application. It should be noted that the appendix... Figure 2 The instruction building apparatus shown supports extended processing capabilities and is used to execute this application. Figure 1 The methods shown in the embodiments are for illustrative purposes only, illustrating the parts relevant to the embodiments of this application. For specific technical details not disclosed, please refer to this application. Figure 1 The example shown.
[0053] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of an instruction construction device that supports extended processing functions, provided in an embodiment of this application. Figure 2 As shown, the device includes
[0054] The filtering module 201 is used to obtain the target source operands from the processor;
[0055] Storage module 202 is used to store the target function descriptor in the target source operand;
[0056] The parsing module 203 is used to control the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function.
[0057] In this embodiment, the filtering module 201 searches through various registers in the processor to obtain the target source operand. After obtaining the target function descriptor, the storage module 202 stores the target function descriptor in the target source operand. The parsing module 203 controls the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function. This further extends the function of the instruction without extending the instruction length, without increasing the complexity of instruction decoding, and supports a better extended function structure of the processor architecture. It achieves further extension of the instruction function without extending the instruction length, and stores the function descriptor in the source operand to describe the instruction function.
[0058] In one possible implementation, an information receiving module 204 is further included, which is used to receive extended information sent by the input terminal, read the name information and function information of the target source operand in the extended information respectively, and convert the function information into a target function descriptor.
[0059] In one possible implementation, the filtering module 201 includes:
[0060] The search unit is used to sequentially read registers on the processor along a preset direction. If the name of a register is the name of the target source operand, then that register is used as the target source operand.
[0061] In one possible implementation, the filtering module 201 further includes;
[0062] The decision unit is used to obtain the number of function descriptors in the target source operand. If the number is 0, execution continues; if the number is greater than or equal to 1, execution stops.
[0063] Those skilled in the art will clearly understand that the technical solutions of the embodiments of this application can be implemented by means of software and / or hardware. In this specification, "unit" and "module" refer to software and / or hardware that can independently complete or cooperate with other components to complete a specific function, wherein the hardware may be, for example, a field-programmable gate array (FPGA), an integrated circuit (IC), etc.
[0064] Each processing unit and / or module in the embodiments of this application can be implemented by analog circuits that implement the functions of the embodiments of this application, or by software that executes the functions of the embodiments of this application.
[0065] See Figure 3 It shows a schematic diagram of the structure of an electronic device according to an embodiment of this application, which can be used to implement... Figure 1 The method in the illustrated embodiment. (As shown) Figure 3 As shown, the electronic device 300 may include: at least one central processing unit 301, at least one network interface 304, user interface 303, memory 305, and at least one communication bus 302.
[0066] The communication bus 302 is used to enable communication between these components.
[0067] The user interface 303 may include a display screen and a camera. Optionally, the user interface 303 may also include a standard wired interface and a wireless interface.
[0068] The network interface 304 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).
[0069] The central processing unit 301 may include one or more processing cores. The central processing unit 301 connects to various parts within the electronic device 300 using various interfaces and lines. It executes various functions of the terminal 300 and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 305, and by calling data stored in the memory 305. Optionally, the central processing unit 301 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The central processing unit 301 may integrate one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the central processing unit 301.
[0070] The memory 305 may include random access memory (RAM) or read-only memory. Optionally, the memory 305 may include a non-transitory computer-readable storage medium. The memory 305 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 305 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 305 may also be at least one storage device located remotely from the aforementioned central processing unit 301. Figure 3 As shown, the memory 305, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and program instructions.
[0071] exist Figure 3 In the illustrated electronic device 300, the user interface 303 is mainly used to provide an input interface for the user and to acquire user input data; while the central processing unit 301 can be used to call instructions stored in the memory 305 that support processing function expansion to build applications and specifically perform the following operations:
[0072] S1: Obtain the target source operand from the processor;
[0073] S2: Store the target function descriptor in the target source operand;
[0074] S3: Control the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function.
[0075] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.
[0076] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.
[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0078] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.
[0079] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0080] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.
[0082] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.
[0083] The above are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.
Claims
1. A method for constructing instructions that supports extended processing capabilities, characterized in that, Includes the following steps: S1: Obtain the target source operand from the processor; S2: Store the target function descriptor in the target source operand; S3: Control the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function; Before step S1, the process includes: receiving extended information sent by the input terminal, reading the name information and function information of the target source operand in the extended information respectively, and converting the function information into a target function descriptor; In step S1, the target source operand is located in the processor based on the name information.
2. The instruction construction method supporting extended processing functions as described in claim 1, characterized in that, Step S1 specifically includes: Read the registers on the processor sequentially in the preset direction. If the name of a register is the name of the target source operand, then use that register as the target source operand.
3. The instruction construction method supporting extended processing functions as described in claim 1, characterized in that, Step S1 also includes: Get the number of function descriptors in the target source operand. If the number is 0, continue execution. If the number is greater than or equal to 1, stop execution.
4. An instruction construction apparatus that supports extended processing functions, characterized in that: include The filtering module is used to obtain the target source operands from the processor; The storage module is used to store the target function descriptor in the target source operand; The parsing module controls the accelerator to parse the target function descriptor in the target source operand to obtain the target instruction function.
5. The instruction construction apparatus for supporting extended processing functions as described in claim 4, characterized in that: Also includes The information receiving module is used to receive extended information sent by the input terminal, read the name information and function information of the target source operand in the extended information respectively, and convert the function information into a target function descriptor.
6. An instruction construction apparatus for supporting extended processing functions as described in claim 4 or 5, characterized in that, The filtering module includes: The search unit is used to sequentially read registers on the processor along a preset direction. If the name of a register is the name of the target source operand, then that register is used as the target source operand.
7. An instruction construction apparatus for supporting extended processing functions as described in claim 4 or 5, characterized in that: The filtering module also includes; The decision unit is used to obtain the number of function descriptors in the target source operand. If the number is 0, execution continues; if the number is greater than or equal to 1, execution stops.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-3.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-3.