Voltage Regulator Biasing Test Adjustment Circuit and Its Biasing Test Method

Abstract

The present invention provides a voltage regulator offset test adjustment circuit and an offset test method thereof. The adjustment circuit includes: a voltage regulator having an input pin, an output pin, a ground pin, and a feedback pin; a first resistor and a second resistor, the first resistor being connected between the output pin and the feedback pin, and the second resistor being connected between the feedback pin and the ground pin; a multiplexer having an output port, a plurality of input ports, an enable port, and a plurality of control ports, the feedback pin being connected to the output port; a third resistor and a fourth resistor, wherein the third resistor is connected between the output pin and one of the plurality of input ports, and the fourth resistor is connected between the ground pin and another one of the plurality of input ports; and a CPLD connected to the enable port and the plurality of control ports, the CPLD controlling the on / off states of the switches in the multiplexer via the enable port and the control ports to change the parallel states of the third and fourth resistors with the first and second resistors, thereby pulling down or pulling up the output voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, in particular to the technical field of server testing, and specifically to the technical field of offset testing in the overall server testing. Background Art

[0002] In the overall server testing, it is necessary to lower or raise the output voltage of some voltage regulators VR (Voltage Regulator) to verify the working stability of the server, that is, the offset testing.

[0003] The current offset testing is achieved by welding and replacing the voltage regulating resistors of the voltage regulator VR. Each replacement can only achieve raising or lowering, with inconvenient operation and low efficiency, resulting in a very long cycle for the offset testing.

[0004] Figure 1 The schematic diagram of the voltage regulator VR and its existing regulating circuit is shown. Basically, the voltage regulator VR is composed of an input pin V IN , an output pin V O , a ground pin AGND, and a feedback pin FB.

[0005] In the existing solution, such as Figure 1 shown, the voltage regulating resistors R1 and R2 in the regulating circuit of the voltage regulator VR need to be manually welded and replaced, and then the offset testing is carried out. Figure 1 In

[0006]

[0007] wherein, V FB is a constant reference value (also called V ref ). Therefore, by only changing the resistance value of the first resistor R1 or the second resistor R2, the output voltage V O can be changed. For example, by replacing the second resistor R2 with a resistor of a smaller resistance value, the output voltage V O can be raised.

[0008] In the conventional offset testing, although the existing method of manually replacing the voltage regulating resistors can also complete the testing, the biggest disadvantage is low efficiency and long time consumption. First, usually there are 4 voltages that need to be offset. Second, the lowering test and the raising test need to be completed in two times, and the resistors need to be replaced twice. Third, the voltage regulating resistors are usually in 0402 package, with a small size, inconvenient for manual welding, and prone to poor welding.

[0009] Due to the above three factors, the number of times of replacing the resistors is large, and the time consumption for each replacement is long. Therefore, the method of manually replacing the voltage regulating resistors has very low efficiency.

[0010] Therefore, in view of the above-mentioned disadvantages and problems in the prior art, an optimized voltage regulator offset test adjustment circuit and a corresponding test method need to be proposed to solve the problem that the offset test circuit in the prior art requires manual soldering and replacement of voltage regulating resistors, resulting in low efficiency. Summary of the Invention

[0011] In view of this, the purpose of the present invention is to propose an improved voltage regulator offset test adjustment circuit, a multi-channel voltage regulator offset test adjustment circuit and a corresponding offset test method to solve the problem that the offset test circuit in the prior art requires manual soldering and replacement of voltage regulating resistors, resulting in low efficiency.

[0012] Based on the above purpose, on the one hand, the present invention provides a voltage regulator offset test adjustment circuit, wherein the voltage regulator offset test adjustment circuit includes:

[0013] A voltage regulator VR, the voltage regulator VR has an input pin V IN 、an output pin V O 、a ground pin AGND and a feedback pin FB;

[0014] A first resistor R1 and a second resistor R2, wherein the first resistor R1 is connected between the output pin V O and the feedback pin FB, and the second resistor R2 is connected between the feedback pin FB and the ground pin AGND;

[0015] A multiplexer MAX, the multiplexer has an output port, a plurality of input ports, an enable port and a plurality of control ports, wherein the feedback pin FB of the voltage regulator VR is connected to the output port;

[0016] A third resistor R3 and a fourth resistor R4, wherein the third resistor R3 is connected between the output pin V O of the voltage regulator VR and one of the plurality of input ports of the multiplexer MAX, and the fourth resistor R4 is connected between the ground pin AGND of the voltage regulator VR and another one of the plurality of input ports of the multiplexer MAX; and

[0017] A CPLD, the CPLD is connected to the enable port and the plurality of control ports of the multiplexer MAX, wherein the CPLD controls the on-off state of the switches in the multiplexer MAX via the enable port and the plurality of control ports to change the parallel state of the third resistor R3 and the fourth resistor R4 with the first resistor R1 and the second resistor R2, thereby pulling down or pulling up the voltage output from the output pin V O of the voltage regulator VR.

[0018] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the switches in the multiplexer MAX to be in an open state by outputting a high level to the enable port, so that the output pin V of the voltage regulator VR O outputs a set voltage.

[0019] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD makes the on / off state of the switches in the multiplexer MAX controlled by the signals received by the multiple control ports of the multiplexer MAX by outputting a low level to the enable port.

[0020] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off state of the switches in the multiplexer MAX by outputting a pull-down control signal to the multiple control ports, so that the third resistor R3 is in parallel with the first resistor R1, so that the output pin V of the voltage regulator VR O outputs a voltage lower than the set voltage.

[0021] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off state of the switches in the multiplexer MAX by outputting a pull-up control signal to the enable port and the multiple control ports, so that the fourth resistor R4 is in parallel with the second resistor R2, so that the output pin V of the voltage regulator VR O outputs a voltage higher than the set voltage.

[0022] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the multiplexer MAX is a single-pole multi-throw multiplexing switch.

[0023] On the other hand, the present invention also provides a multi-channel voltage regulator offset test adjustment circuit, wherein the multi-channel voltage regulator offset test adjustment circuit includes:

[0024] Multiple voltage regulators VR1, VR2, VR3, VR4, each voltage regulator VR having an input pin V IN , an output pin V O , a ground pin AGND, and a feedback pin FB;

[0025] The first resistors R1, R5, R9, R13 and the second resistors R2, R6, R10, R14 assigned to each of the voltage regulators VR1, VR2, VR3, VR4, wherein the first resistors R1, R5, R9, R13 are connected between the output pin V O and the feedback pin FB of the corresponding voltage regulators VR1, VR2, VR3, VR4, and the second resistors R2, R6, R10, R14 are connected between the feedback pin FB of the corresponding voltage regulators VR1, VR2, VR3, VR4 and the ground pin AGND;

[0026] A multiplexer MAX, which has a plurality of output ports, a plurality of input ports corresponding to each output port, an enable port, and a plurality of control ports, wherein the feedback pins FB of the corresponding voltage regulators VR1, VR2, VR3, VR4 are respectively connected to one of the plurality of output ports;

[0027] The third resistors R3, R7, R11, R15 and the fourth resistors R4, R8, R12, R16 assigned to each of the voltage regulators VR1, VR2, VR3, VR4, wherein the third resistors R3, R7, R11, R15 are connected between the output pin V O and one of the plurality of input ports corresponding to the corresponding output port of the multiplexer MAX, and the fourth resistors R4, R8, R12, R16 are connected between the ground pin AGND of the corresponding voltage regulators VR1, VR2, VR3, VR4 and the other of the plurality of input ports corresponding to the corresponding output port of the multiplexer MAX; and

[0028] A CPLD, which is connected to the enable port and the plurality of control ports of the multiplexer MAX, wherein the CPLD controls the on - off state of the switches in the multiplexer MAX via the enable port and the plurality of control ports to change the parallel state of the third resistors R3, R7, R11, R15 and the fourth resistors R4, R8, R12, R16 with the first resistors R1, R5, R9, R13 and the second resistors R2, R6, R10, R14, so as to pull down or pull up the voltage output from the output pin V O of the voltage regulators VR1, VR2, VR3, VR4.

[0029] In some embodiments of the multi - voltage regulator biasing test adjustment circuit according to the present invention, the CPLD controls the switches in the multiplexer MAX to be all in the open state by outputting a high level to the enable port, so that the output pin VO Output the set voltage.

[0030] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the CPLD makes the on / off state of the switches in the multiplexer MAX controlled by the signals received by the multiple control ports of the multiplexer MAX by outputting a low level to the enable port.

[0031] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off state of the switches in the multiplexer MAX by outputting a pull-down control signal to the multiple control ports, so that the third resistors R3, R7, R11, R15 are in parallel with the first resistors R1, R5, R9, R13, so that the output pins V of the corresponding voltage regulators VR1, VR2, VR3, VR4 O The output voltage is lower than the set voltage.

[0032] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off state of the switches in the multiplexer MAX by outputting a pull-up control signal to the enable port and the multiple control ports, so that the fourth resistors R4, R8, R12, R16 are in parallel with the second resistors R2, R6, R10, R14, so that the output pins V of the corresponding voltage regulators VR1, VR2, VR3, VR4 O The output voltage is higher than the set voltage.

[0033] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the multiplexer MAX is a multi-channel single-pole multi-throw multiplexing switch.

[0034] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the multiplexed voltage regulator offset test adjustment circuit includes a plurality of multiplexers MAX, and each multiplexer MAX is assigned two voltage regulators VR1, VR2, VR3, VR4.

[0035] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the corresponding enable ports and corresponding control ports of the plurality of multiplexers MAX are all connected to the same CPLD.

[0036] In another aspect of the present invention, there is also provided an offset test method, wherein the method is executed based on any one of the voltage regulator offset test adjustment circuits according to the present invention or based on any one of the multiplexed voltage regulator offset test adjustment circuits according to the present invention, and the method includes the following steps:

[0037] In response to the CPLD outputting a high level to the enable port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a set voltage;

[0038] In response to the CPLD outputting a low level to the enable port of the multiplexer, the offset test mode is activated, where:

[0039] In response to the CPLD outputting a pull-down control signal to the control port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a voltage lower than the set voltage;

[0040] In response to the CPLD outputting a pull-up control signal to the control port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a voltage higher than the set voltage.

[0041] The present invention has at least the following beneficial technical effects: The present invention improves the drawback that the existing offset test circuit for offset testing needs to be manually welded and the voltage regulating resistor needs to be replaced, which leads to low efficiency. A regulating circuit for offset testing implemented by CPLD programming is proposed. By using this regulating circuit, the control of the circuit is achieved through CPLD programming, which is convenient for operation. At the same time, manual welding and resistor replacement are avoided, thereby improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0043] In the figure:

[0044] Figure 1 A schematic diagram of the voltage regulator VR and the existing regulating circuit is shown;

[0045] Figure 2 A schematic diagram of an embodiment of the voltage regulator offset test regulating circuit according to the present invention is shown;

[0046] Figure 3 A schematic diagram of an embodiment of the multi-channel voltage regulator offset test regulating circuit according to the present invention is shown;

[0047] Figure 4 A schematic block diagram of an embodiment of the offset test method according to the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] To make the objectives, technical solutions, and advantages of the present invention more clear and understandable, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0049] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for differentiating two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, a voltage regulator offset test adjustment circuit, a system, a product, or a device that includes a series of steps or units inherently includes other steps or units.

[0050] For this reason, in the first aspect of the present invention, a voltage regulator offset test adjustment circuit is provided. Figure 2 The schematic diagram of an embodiment of the voltage regulator offset test adjustment circuit according to the present invention is shown. In the Figure 2 embodiment shown, the voltage regulator offset test adjustment circuit includes:

[0051] A voltage regulator VR, the voltage regulator VR having an input pin V IN , an output pin V O , a ground pin AGND, and a feedback pin FB;

[0052] A first resistor R1 and a second resistor R2, wherein the first resistor R1 is connected between the output pin V O and the feedback pin FB, and the second resistor R2 is connected between the feedback pin FB and the ground pin AGND;

[0053] A multiplexer MAX, the multiplexer having an output port, a plurality of input ports, an enable port, and a plurality of control ports, wherein the feedback pin FB of the voltage regulator VR is connected to the output port;

[0054] A third resistor R3 and a fourth resistor R4, wherein the third resistor R3 is connected between the output pin V O of the voltage regulator VR and one of the plurality of input ports of the multiplexer MAX, and the fourth resistor R4 is connected between the ground pin AGND of the voltage regulator VR and another one of the plurality of input ports of the multiplexer MAX; and

[0055] A CPLD is connected to the enable port and the multiple control ports of the multiplexer MAX, where the CPLD controls the on / off states of the switches in the multiplexer MAX via the enable port and the multiple control ports to change the parallel states of the third resistor R3 and the fourth resistor R4 with the first resistor R1 and the second resistor R2, thereby pulling down or pulling up the output pin V of the voltage regulator VR O The output voltage.

[0056] Specifically, compared with the prior art, two regulating resistors, namely the third resistor R3 and the fourth resistor R4, are added to the voltage regulator offset test adjustment circuit according to the present invention, and a multiplexer and a CPLD for controlling the multiplexer are added.

[0057] On the basis that the first resistor R1 and the second resistor R2 are connected to the voltage regulator VR, the feedback pin FB of the voltage regulator VR is connected to the output port (such as Figure 2 the output port X shown). The added third resistor R3 is connected between the output pin V of the voltage regulator VR and one of the multiple input ports of the multiplexer MAX (such as O the input port X1 shown). The added fourth resistor R4 is connected between the ground pin AGND of the voltage regulator VR and another one of the multiple input ports of the multiplexer MAX (such as Figure 2 the input port X4 shown). Figure 2 The CPLD is connected to the enable port (such as

[0058] the enable port ENABLE shown) and the multiple control ports (such as Figure 2 the control ports A, B, C shown) of the multiplexer MAX. Figure 2 The CPLD is connected to the enable port (such as

[0059] the enable port ENABLE shown) and the multiple control ports (such as Figure 2 the control ports A, B, C shown) of the multiplexer MAX.

[0060] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls all the switches in the multiplexer MAX to be in an open state by outputting a high level to the enable port, so that the output pin V of the voltage regulator VR O outputs the set voltage. Specifically, refer to Figure 2, when EN / C / B / A output by the CPLD = 1RRR, all switches are open, the third resistor R3 and the fourth resistor R4 are not in parallel with the first resistor R1 and the second resistor R2, and the output voltage of the voltage regulator VR is the normal set voltage.

[0061] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD makes the on / off state of the switches in the multiplexer MAX controlled by the signals received by the multiple control ports of the multiplexer MAX by outputting a low level to the enable port. That is to say, only when the enable port of the multiplexer receives the low level signal output by the CPLD, the offset function of the circuit is started. At this time, the switches in the multiplexer MAX are controlled by the signals received by the multiple control ports of the multiplexer MAX and enter the open or closed state.

[0062] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off state of the switches in the multiplexer MAX by outputting a pull-down control signal to the multiple control ports, so that the third resistor R3 is in parallel with the first resistor R1, so that the output pin V of the voltage regulator VR O The output voltage is lower than the set voltage. See Figure 2 , when EN / C / B / A output by the CPLD = 0001, only X1 and X are conducted. At this time, the third resistor R3 is in parallel with the first resistor R1, and the resistance value after parallel connection is smaller than that of the first resistor R1. Therefore, it can be seen from (Formula 1) that the output voltage of the voltage regulator VR will be pulled down.

[0063] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off state of the switches in the multiplexer MAX by outputting a pull-up control signal to the enable port and the multiple control ports, so that the fourth resistor R4 is in parallel with the second resistor R2, so that the output pin V of the voltage regulator VR O The output voltage is higher than the set voltage. See Figure 2 , when EN / C / B / A output by the CPLD = 0100, only X4 and X are conducted. At this time, the fourth resistor R4 is in parallel with the second resistor R2, and the resistance value after parallel connection is smaller than that of the second resistor R2. Therefore, it can be seen from (Formula 1) that the output voltage of the voltage regulator VR will be pulled up.

[0064] In some embodiments of the voltage regulator offset test adjustment circuit according to the present invention, the multiplexer MAX is a single-pole multi-throw multiplexing switch. Such as Figure 2As shown, preferably, the multiplexer can be an 8-channel multiplexing switch, such as the MAX4617. It has advantages such as high speed, low voltage, and CMOS analog integrated circuit.

[0065] In a second aspect of the present invention, a pull bias test adjustment circuit for a multi-channel voltage regulator is also provided. Figure 3 The schematic diagram of an embodiment of the pull bias test adjustment circuit for a multi-channel voltage regulator according to the present invention is shown.

[0066] When a pull bias test needs to be performed on multiple voltage regulators VR, in addition to separately building the pull bias test adjustment circuit of the foregoing embodiment, the pull bias test can also be performed on multiple voltage regulators VR simultaneously according to the pull bias test adjustment circuit of the second aspect of the present invention.

[0067] For the purpose of being clear, concise, and sufficient to explain the pull bias test adjustment circuit for a multi-channel voltage regulator according to the present invention, Figure 3 the pull bias test adjustment circuit for a four-channel voltage regulator shown is taken as an example. However, it should be noted that this example should not be construed as a limitation of the present invention, that is, the pull bias test adjustment circuit for a multi-channel voltage regulator according to the present invention may not be limited to the four channels shown, but may include less than four channels or more than four channels of voltage regulators.

[0068] As Figure 3 shown, the pull bias test adjustment circuit for a multi-channel voltage regulator according to the present invention includes:

[0069] Multiple voltage regulators VR1, VR2, VR3, VR4, each of the voltage regulators VR1, VR2, VR3, VR4 having an input pin V IN , an output pin V O , a ground pin AGND, and a feedback pin FB;

[0070] The first resistors R1, R5, R9, R13 and the second resistors R2, R6, R10, R14 assigned to each of the voltage regulators VR1, VR2, VR3, VR4, wherein the first resistors R1, R5, R9, R13 are connected between the output pin V O and the feedback pin FB of the corresponding voltage regulators VR1, VR2, VR3, VR4, and the second resistors R2, R6, R10, R14 are connected between the feedback pin FB of the corresponding voltage regulators VR1, VR2, VR3, VR4 and the ground pin AGND;

[0071] Multiplexer MAX, which has multiple output ports, multiple input ports corresponding to each output port, an enable port, and multiple control ports, where the feedback pins FB of the corresponding voltage regulators VR1, VR2, VR3, VR4 are respectively connected to one of the multiple output ports;

[0072] The third resistors R3, R7, R11, R15 and the fourth resistors R4, R8, R12, R16 assigned to each of the voltage regulators VR1, VR2, VR3, VR4, where the third resistors R3, R7, R11, R15 are connected between the output pins V of the corresponding voltage regulators VR1, VR2, VR3, VR4 O and one of the multiple input ports of the multiplexer MAX corresponding to the corresponding output port, and the fourth resistors R4, R8, R12, R16 are connected between the ground pins AGND of the corresponding voltage regulators VR1, VR2, VR3, VR4 and the other of the multiple input ports of the multiplexer MAX corresponding to the corresponding output port; and

[0073] CPLD, which is connected to the enable port and the multiple control ports of the multiplexer MAX, where the CPLD controls the on - off state of the switches in the multiplexer MAX via the enable port and the multiple control ports to change the parallel state of the third resistors R3, R7, R11, R15 and the fourth resistors R4, R8, R12, R16 with the first resistors R1, R5, R9, R13 and the second resistors R2, R6, R10, R14, thereby pulling down or pulling up the voltage output from the output pins V of the voltage regulators VR1, VR2, VR3, VR4 O Output voltage.

[0074] In the present invention, "the multiplexer has multiple output ports, multiple input ports corresponding to each output port" should be understood by taking Figure 3 as an example that the output port Y of the multiplexer corresponds to the input ports Y0 to Y3, and the output port X corresponds to the input ports X0 to X3. However, it should be noted that it should not be limited that the output port X only corresponds to the input ports X0 to X3, because in the implementation as Figure 2 shown, the output port X of the multiplexer actually corresponds to the input ports X0 to X7. This is determined by the internal structure and logic of the multiplexer used.

[0075] In the present invention, "the feedback pins FB of the corresponding voltage regulators VR1, VR2, VR3, VR4 are respectively connected to one of the multiple output ports" and "the multiple input ports of the multiplexer MAX corresponding to the corresponding output port" should be understood as, for exampleFigure 3 As shown, when the feedback pin FB of the voltage regulator VR1 is connected to one of the output ports (such as Figure 3 the output port Y of the multiplexer U1 shown), the multiplexer MAX (such as Figure 3 the multiplexer U1 shown) corresponding to the corresponding output port (such as Figure 3 the output port Y of the multiplexer U1 shown) of the multiple input ports refer to the input ports Y0 to Y3 of the multiplexer U1 shown in Figure 3 Figure.

[0076] In the adjustment circuit shown in Figure 3 Figure, the connection of the voltage regulators VR1 to VR4, the respective adjustment resistors R1 to R16 and the multiplexer is substantially similar to the (single-channel) voltage regulator offset test adjustment circuit according to the first aspect of the present invention, and thus will not be described in detail. However, here, the multiplexer is no longer individually associated with a voltage regulator, but is simultaneously associated with multiple voltage regulators. In the embodiment shown in Figure 3 Figure, through CPLD programming, the on / off states of the switches in the multiplexers U1 and U2 can be controlled, so that by means of resistor parallel connection, the voltage regulating resistor of the voltage regulator VR can be changed to realize the adjustment of the output voltage of the voltage regulator VR.

[0077] Furthermore, in some embodiments of the multi-channel voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the switches in the multiplexer MAX to be all in the open state by outputting a high level to the enable port, so that the output pins V of the voltage regulators VR1, VR2, VR3, VR4 O output the set voltage. Specifically, referring to Figure 3 Figure, when EN / B / A = 1RR output by the CPLD, all switches are open, and the third resistors R3, R7, R11, R15 and the fourth resistors R4, R8, R12, R16 are not in parallel with the first resistors R1, R5, R9, R13 and the second resistors R2, R6, R10, R14, and the output voltages of the voltage regulators VR1 to VR3 are the normal set voltages.

[0078] Subsequently, in some embodiments of the multi-channel voltage regulator offset test adjustment circuit according to the present invention, the CPLD makes the on / off states of the switches in the multiplexer MAX controlled by the signals received by the multiple control ports of the multiplexer MAX by outputting a low level to the enable port. That is, the offset function of the circuit is only started when the enable port of the multiplexer receives the low level signal output by the CPLD. At this time, the switches in the multiplexer MAX are controlled by the signals received by the multiple control ports of the multiplexer MAX and enter the open or closed state.

[0079] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off states of the switches in the multiplexer MAX by outputting pull-down control signals to the multiple control ports, so that the third resistors R3, R7, R11, R15 are connected in parallel with the first resistors R1, R5, R9, R13, so that the output pins V of the corresponding voltage regulators VR1, VR2, VR3, VR4 O output a voltage lower than the set voltage. See Figure 3 , when EN / B / A output by the CPLD is 000, X and X0, Y and Y0 in the multiplexers U1 and U2 are turned on, and the upper voltage regulating resistors (i.e., the third resistors R3, R7, R11, R15 and the first resistors R1, R5, R9, R13) of the 4 voltage regulators VR1, VR2, VR3, VR4 are connected in parallel to reduce the resistance value, thereby pulling down the output voltages of the 4 voltage regulators VR1, VR2, VR3, VR4.

[0080] In addition, in some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, the CPLD controls the on / off states of the switches in the multiplexer MAX by outputting pull-up control signals to the enable port and the multiple control ports, so that the fourth resistors R4, R8, R12, R16 are connected in parallel with the second resistors R2, R6, R10, R14, so that the output pins V of the corresponding voltage regulators VR1, VR2, VR3, VR4 O output a voltage higher than the set voltage. See Figure 3 , when EN / B / A output by the CPLD is 001, X and X1, Y and Y1 in the multiplexers U1 and U2 are turned on, and the lower voltage regulating resistors (i.e., the fourth resistors R4, R8, R12, R16 and the second resistors R2, R6, R10, R14) of the 4 voltage regulators VR1, VR2, VR3, VR4 are connected in parallel to reduce the resistance value, thereby pulling up the output voltages of the 4 voltage regulators VR1, VR2, VR3, VR4.

[0081] In some embodiments of the multiplexed voltage regulator offset test adjustment circuit according to the present invention, it is characterized in that the multiplexer MAX is a multi-channel single-pole multi-throw multiplexing switch. In addition to the multiplexers mentioned above, as Figure 3 shown, preferably, the multiplexer used in the multiplexed voltage regulator offset test adjustment circuit can also be a dual-channel 4-channel multiplexing switch, taking MAX4618 as an example. It has the advantages of high speed, low voltage, CMOS analog integrated circuit, etc.

[0082] In some embodiments of the multi-channel voltage regulator offset test adjustment circuit according to the present invention, the multi-channel voltage regulator offset test adjustment circuit includes a plurality of multiplexers MAX, and two voltage regulators VR1, VR2, VR3, VR4 are allocated to each multiplexer MAX. As Figure 3 shown, two multiplexers U1 and U2 are adopted in the four-channel voltage regulator offset test adjustment circuit in this embodiment. Among them, the voltage regulators VR1, VR2 and their corresponding adjustment resistors R1 to R4, R5 to R8 are all connected to the multiplexer U1, and the voltage regulators VR3, VR4 and their corresponding adjustment resistors R9 to R12, R13 to R16 are all connected to this multiplexer U1.

[0083] In some embodiments of the multi-channel voltage regulator offset test adjustment circuit according to the present invention, the corresponding enable ports and corresponding control ports of the plurality of multiplexers MAX are all connected to the same CPLD. As Figure 3 shown, the corresponding enable ports ENABLE and corresponding control ports A, B of the two multiplexers U1 and U2 adopted in the four-channel voltage regulator offset test adjustment circuit in this embodiment are all connected to the output ports of the CPLD U3.

[0084] In a third aspect of the present invention, an offset test method is also provided. Figure 4 The schematic block diagram showing an embodiment of the offset test method according to the present invention is shown. As Figure 4 shown, in this embodiment, the method is executed based on any one of the voltage regulator offset test adjustment circuits according to the present invention or based on any one of the multi-channel voltage regulator offset test adjustment circuits according to the present invention, and the method includes the following steps:

[0085] S100: In response to the CPLD outputting a high level to the enable port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a set voltage;

[0086] S200: In response to the CPLD outputting a low level to the enable port of the multiplexer, the offset test mode is activated, wherein:

[0087] S210: In response to the CPLD outputting a pull-down control signal to the control port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a voltage lower than the set voltage

[0088] voltage;

[0089] S220: In response to the CPLD outputting a pull-up control signal to the control port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a voltage higher than the set voltage.

[0090] In addition, the following points should also be noted in the voltage regulator offset test adjustment circuit and the corresponding offset test method according to the present invention:

[0091] I. In terms of circuit design:

[0092] 1) The parallel resistor should be calculated and selected according to the voltage regulating resistor of the voltage regulator VR and the offset requirements.

[0093] 2) The parallel resistor, multiplexer and CPLD should be correctly connected.

[0094] II. In terms of software logic:

[0095] 1) In the default state, EN = 1, so that the output voltage of the voltage regulator VR is the set value (i.e., the normal set voltage).

[0096] 2) When an offset test is required, the state of EN / (C / )B / A is changed through CPLD programming to achieve the offset of the output voltage of the voltage regulator VR.

[0097] III. In terms of application:

[0098] 1) The voltage regulator offset test adjustment circuit and the corresponding offset test method according to the present invention are preferably applicable to the collection offset test of servers.

[0099] 2) Without departing from the concept of the present invention, the voltage regulator offset test adjustment circuit and the corresponding offset test method according to the present invention can also be used in other scenarios where the output voltage of the voltage regulator VR needs to be changed.

[0100] The above are the exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the claims according to the disclosed embodiments herein do not need to be performed in any specific order. In addition, although the elements disclosed by the embodiments of the present invention can be described or claimed in individual form, they can also be understood as multiple unless explicitly limited to the singular.

[0101] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular form "a" is also intended to include the plural form. It should also be understood that "and / or" as used herein refers to any and all possible combinations of one or more of the associated listed items. The above serial numbers of the disclosed embodiments of the present invention are only for description and do not represent the superiority or inferiority of the embodiments.

[0102] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope (including the claims) disclosed by the embodiments of the present invention is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. A voltage regulator offset test adjustment circuit, characterized in that The voltage regulator offset test adjustment circuit includes: Voltage regulator, the voltage regulator having an input pin (V IN ), an output pin (V O ), a ground pin (AGND) and a feedback pin (FB); The first resistor (R1) and the second resistor (R2), wherein the first resistor (R1) is connected between the output pin (V O ) and the feedback pin (FB), and the second resistor (R2) is connected between the feedback pin (FB) and the ground pin (AGND); A multiplexer (MAX), which has an output port, multiple input ports, an enable port, and multiple control ports. The feedback pin (FB) of the voltage regulator is connected to the output port. A third resistor (R3) and a fourth resistor (R4), wherein the third resistor (R3) is connected between the output pin (V O ) of the voltage regulator and one of the plurality of input ports of the multiplexer (MAX), and the fourth resistor (R4) is connected between the ground pin (AGND) of the voltage regulator and another one of the plurality of input ports of the multiplexer (MAX); and A CPLD, where the CPLD is connected to the enable port and the multiple control ports of the multiplexer (MAX), and the CPLD controls the on / off states of the switches in the multiplexer (MAX) via the enable port and the multiple control ports to change the parallel states of the third resistor (R3) and the fourth resistor (R4) with the first resistor (R1) and the second resistor (R2), thereby pulling down or pulling up the voltage output by the output pin (V O ) of the voltage regulator.

2. The voltage regulator offset test adjustment circuit according to claim 1, characterized in that, The CPLD controls the switches in the multiplexer (MAX) to be in an open state by outputting a high level to the enable port, so that the output pin (V O ) of the voltage regulator outputs a set voltage.

3. The voltage regulator offset test adjustment circuit according to claim 2, wherein The CPLD makes the on / off state of the switches in the multiplexer (MAX) controlled by the signals received by the multiple control ports of the multiplexer (MAX) by outputting a low level to the enable port.

4. The voltage regulator offset test adjustment circuit according to claim 3, characterized in that The CPLD controls the on / off states of the switches in the multiplexer (MAX) by outputting a pull-down control signal to the multiple control ports, so that the third resistor (R3) is in parallel with the first resistor (R1), so that the voltage output by the output pin (V O ) of the voltage regulator is lower than the set voltage.

5. The voltage regulator offset test adjustment circuit according to claim 3, characterized in that The CPLD controls the on / off states of the switches in the multiplexer (MAX) by outputting a pull-up control signal to the enable port and the multiple control ports, so that the fourth resistor (R4) is in parallel with the second resistor (R2), enabling the output pin (V O ) of the voltage regulator to output a voltage higher than the set voltage.

6. The voltage regulator offset test adjustment circuit according to any one of claims 1 to 5, characterized in that The multiplexer (MAX) is a single-pole multi-throw multiplexing switch.

7. A pulling bias test and adjustment circuit for a multi-channel voltage regulator, characterized in that, The multi-channel voltage regulator offset test adjustment circuit includes: Multiple voltage regulators, each of the voltage regulators having an input pin (V IN ), an output pin (V O ), a ground pin (AGND), and a feedback pin (FB); The first resistors (R1, R5, R9, R13) and the second resistors (R2, R6, R10, R14) assigned to each of the said voltage regulators, wherein the first resistors (R1, R5, R9, R13) are connected between the output pin (V O ) and the feedback pin (FB) of the corresponding voltage regulator, and the second resistors (R2, R6, R10, R14) are connected between the feedback pin (FB) of the corresponding voltage regulator and the ground pin (AGND); A multiplexer (MAX), which has multiple output ports, multiple input ports corresponding to each output port, an enable port, and multiple control ports. The feedback pin (FB) of the corresponding voltage regulator is connected to one of the multiple output ports respectively. The third resistors (R3, R7, R11, R15) and the fourth resistors (R4, R8, R12, R16) assigned to each of the voltage regulators, wherein the third resistors (R3, R7, R11, R15) are connected between the output pin (V O ) of the corresponding voltage regulator and one of the plurality of input ports of the multiplexer (MAX) corresponding to the corresponding output port, and the fourth resistors (R4, R8, R12, R16) are connected between the ground pin (AGND) of the corresponding voltage regulator and the other of the plurality of input ports of the multiplexer (MAX) corresponding to the corresponding output port; and A CPLD, the CPLD is connected to the enable port and the multiple control ports of the multiplexer (MAX), wherein the CPLD controls the on / off states of the switches in the multiplexer (MAX) via the enable port and the multiple control ports to change the parallel states of the third resistors (R3, R7, R11, R15) and the fourth resistors (R4, R8, R12, R16) with the first resistors (R1, R5, R9, R13) and the second resistors (R2, R6, R10, R14), thereby pulling down or pulling up the voltage at the output pin (V O ) of the voltage regulator.

8. The multi-channel voltage regulator offset test adjustment circuit according to claim 7, wherein, The CPLD controls the switches in the multiplexer (MAX) to be all in the open state by outputting a high level to the enable port, so that the output pin (V O ) of the voltage regulator outputs a set voltage.

9. The multi-channel voltage regulator offset test adjustment circuit according to claim 8, wherein, The CPLD makes the on / off state of the switches in the multiplexer (MAX) controlled by the signals received by the multiple control ports of the multiplexer (MAX) by outputting a low level to the enable port.

10. The multi-channel voltage regulator offset test adjustment circuit according to claim 9, characterized in that, The CPLD controls the on / off states of the switches in the multiplexer (MAX) by outputting a pull-down control signal to the multiple control ports, so that the third resistors (R3, R7, R11, R15) are in parallel with the first resistors (R1, R5, R9, R13), so that the output pin (V O ) of the corresponding voltage regulator outputs a voltage lower than the set voltage.

11. The multi-channel voltage regulator offset test adjustment circuit according to claim 9, characterized in that The CPLD controls the on / off states of the switches in the multiplexer (MAX) by outputting a pull-up control signal to the enable port and the multiple control ports, so that the fourth resistors (R4, R8, R12, R16) are in parallel with the second resistors (R2, R6, R10, R14), so that the output pin (V O ) of the corresponding voltage regulator outputs a voltage higher than the set voltage.

12. The multi-channel voltage regulator offset test adjustment circuit according to any one of claims 7 to 11, characterized in that, The multiplexer (MAX) is a multi-channel single-pole multi-throw multiplexing switch.

13. The multi-channel voltage regulator offset test adjustment circuit according to any one of claims 7 to 11, characterized in that, The multi-channel voltage regulator offset test adjustment circuit includes multiple multiplexers (MAX), and two voltage regulators are allocated to each multiplexer (MAX).

14. The multi-channel voltage regulator offset test adjustment circuit according to claim 13, characterized in that, The corresponding enable ports and corresponding control ports of the multiple multiplexers (MAX) are all connected to the same CPLD.

15. A bias test method, characterized in that, The method is executed based on the voltage regulator offset test adjustment circuit according to any one of claims 1 to 6 or based on the multi-channel voltage regulator offset test adjustment circuit according to any one of claims 7 to 14. The method includes the following steps: In response to the CPLD outputting a high level to the enable port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a set voltage. In response to the CPLD outputting a low level to the enable port of the multiplexer, the offset test mode is activated, where: In response to the CPLD outputting a pull-down control signal to the control port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a voltage lower than the set voltage. In response to the CPLD outputting a pull-up control signal to the control port of the multiplexer, the output pin of the voltage regulator of the multiplexer outputs a voltage higher than the set voltage.

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