Data reading method and device of flash memory device, terminal device and storage medium

Abstract

The application discloses a data reading method and device of a flash memory device, a terminal device and a computer storage medium, and comprises the following steps: receiving a read command sent by a host, wherein the read command comprises a logical address to be read of data to be read; judging whether the read command hits a first primary mapping table in a read-only memory according to the logical address to be read and a preset block address bitmap; if the first primary mapping table is not hit, finding a second logical address of a second primary mapping table located in a flash memory according to a preset secondary mapping table, and finding the data to be read corresponding to the logical address to be read according to the second primary mapping table. The application can improve the hit rate of the read command in the flash memory device and improve the reading performance of the flash memory device.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a data reading method, apparatus, terminal device, and computer storage medium for a flash memory device. Background Technology

[0002] Because flash memory devices have significantly different read / write characteristics compared to hard disks, a computer's file system cannot directly manipulate the storage space of a flash memory device. Therefore, a flash translation layer (FTL) is established between the file system and the flash memory device. The FTL includes a mapping table for translating between logical and physical addresses. When the FTL receives a read / write operation request for the flash memory device, it determines the physical address in the flash memory device based on the mapping table and the logical address in the access request, and then performs the read / write operation on the logical address to be read.

[0003] To ensure response speed, the mapping table is typically stored in the RAM of the flash memory device. Generally, a 1TB SSD's mapping table occupies at least 0.1% of RAM space. For example, with 12 4TB SSDs, approximately 12 * 4TB * 0.1% = 48GB of RAM is required. However, in DRAM-less (Dynamic Random Access Memory-less) products, due to limited memory resources, the mapping table is only partially cached in RAM, leading to slower read speeds for the flash memory device. Therefore, improving read and write performance in DRAM-less products is a pressing issue. Summary of the Invention

[0004] The main objective of this invention is to provide a data reading method, apparatus, terminal device, and computer storage medium for flash memory devices, aiming to address the problem of low read performance in DRAM-less flash memory devices due to limited memory resources.

[0005] To achieve the above objectives, the present invention provides a data reading method for a flash memory device, the data reading method for the flash memory device comprising the following steps:

[0006] Receive a read command sent by the host, wherein the read command includes the logical address of the data to be read;

[0007] Based on the logical address to be read and the preset block address bitmap, determine whether the read command hits the first-level mapping table in the read-only memory;

[0008] If the first level mapping table is hit, then the first logical address of the first level mapping table is found according to the preset address sequence table, and the data to be read corresponding to the logical address to be read is found according to the first level mapping table.

[0009] Based on the first logical address, update the preset address sequence table and the first level mapping table, and send the data to be read to the host;

[0010] If the first-level mapping table is not hit, the second logical address of the second-level mapping table located in the Flash memory is searched according to the preset second-level mapping table, and the data to be read corresponding to the logical address to be read is searched according to the second-level mapping table.

[0011] Based on the second logical address, update the preset address sequence table, the second-level mapping table, and the preset block address bitmap, and send the data to be read to the host.

[0012] Optionally, the step of updating the preset address sequence table and the first-level mapping table according to the first logical address, and sending the data to be read to the host, includes:

[0013] Obtain the third logical address located at the beginning of the preset address sequence table;

[0014] The positions of the first logical address and the third logical address are swapped to obtain the updated first target address sequence table;

[0015] Update the first-level mapping table according to the first target address sequence table, and send the data to be read to the host.

[0016] Optionally, the step of updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and sending the data to be read to the host, includes:

[0017] Obtain the fourth logical address located at the end of the preset address sequence table;

[0018] The fourth logical address is replaced with the second logical address to obtain the updated second target address sequence table;

[0019] According to the second target address sequence table, update the second level mapping table and the preset block address bitmap, and send the data to be read to the host.

[0020] Optionally, the step of updating the second-level mapping table and the preset block address bitmap according to the second target address sequence table includes:

[0021] Based on the updated preset address sequence table, the second-level mapping table is updated and the bits in the preset block address bitmap are updated, wherein the preset block address bitmap is a set of bits indicating whether the first-level mapping table exists in the read-only memory.

[0022] Optionally, the step of determining whether the read command hits the first-level mapping table in the read-only memory based on the logical address to be read and the preset block address bitmap includes:

[0023] Based on the logical address to be read and the preset block size, the index value of the logical address to be read in the preset block address bitmap is obtained;

[0024] Perform a bitwise AND operation between the index value and the preset block address bitmap to obtain the operation result;

[0025] Based on the calculation result, determine whether the read command hits the first-level mapping table in the read-only memory.

[0026] Optionally, the result of the operation includes 1 and 0;

[0027] The step of determining whether the read command hits the first-level mapping table in the read-only memory based on the calculation result includes:

[0028] If the result of the operation is 1, then it is determined that the read command hits the first level mapping table in the read-only memory;

[0029] If the result of the operation is 0, it is determined that the read command did not hit the first-level mapping table in the read-only memory.

[0030] Optionally, the step of finding the second logical address of the second-level mapping table located in the Flash memory according to the preset second-level mapping table includes:

[0031] Based on the correspondence between the logical address to be read in the preset secondary mapping table and the second-level mapping table, the second-level mapping table corresponding to the logical address to be read is located in the Flash memory.

[0032] Obtain the second logical address of the second-level mapping table.

[0033] In addition, to achieve the above objectives, the present invention also provides a data reading device, the data reading device including a receiving module for receiving a read command sent by a host, the read command including the logical address of the data to be read;

[0034] The judgment module is used to determine whether the read command hits the first-level mapping table in the read-only memory based on the logical address to be read and the preset block address bitmap.

[0035] The lookup module is used to look up the first logical address of the first-level mapping table according to a preset address sequence table, and to look up the data to be read corresponding to the logical address to be read according to the first-level mapping table; and

[0036] It is used to find the second logical address of the second level mapping table located in the Flash memory according to the preset second level mapping table, and to find the data to be read corresponding to the logical address to be read according to the second level mapping table;

[0037] The execution module is configured to update the preset address sequence table and the first-level mapping table according to the first logical address, and send the data to be read to the host; and

[0038] It is used to update the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and to send the data to be read to the host.

[0039] In addition, to achieve the above objectives, the present invention also provides a terminal device, the terminal device comprising: a memory, a processor, and a flash memory device data reading program stored in the memory and executable on the processor, wherein when the flash memory device data reading program is executed by the processor, it implements the steps of the flash memory device data reading method as described above.

[0040] In addition, to achieve the above objectives, the present invention also provides a computer storage medium storing a data reading program for a flash memory device, wherein the data reading program for the flash memory device, when executed by a processor, implements the steps of the data reading method for the flash memory device as described above.

[0041] This invention proposes a data reading method, apparatus, terminal device, and computer storage medium for flash memory devices. The data reading method for flash memory devices includes the following steps: receiving a read command sent by a host, the read command including a logical address of data to be read; determining whether the read command hits a first-level mapping table in a read-only memory based on the logical address to be read and a preset block address bitmap; if the first-level mapping table is hit, searching for a first logical address in the first-level mapping table according to a preset address sequence table, and searching for the data to be read corresponding to the logical address to be read according to the first-level mapping table; updating the preset address sequence table and the first-level mapping table according to the first logical address, and sending the data to be read to the host; if the first-level mapping table is not hit, searching for a second logical address in a second-level mapping table located in the flash memory according to a preset second-level mapping table, and searching for the data to be read corresponding to the logical address to be read according to the second-level mapping table; updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and sending the data to be read to the host.

[0042] By employing the above method, this invention avoids the need to traverse the preset address sequence table to find the first-level mapping table by using a preset block address bitmap, thus improving the efficiency of determining whether the first-level mapping table exists in the read-only memory of the flash memory device. By setting the first-level mapping table, the second-level mapping table, and the virtual address sequence table, and by using the second mapping table to find the data corresponding to the read command when the first-level mapping table is not hit, the hit rate of the host in reading data from the DRAM-less flash memory device is improved, thereby increasing the read efficiency of the flash memory device and optimizing its performance. Finally, after reading the data to be read, updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap improves the read speed and performance of the flash memory device for the next read operation. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the hardware operation of the terminal device involved in the embodiment of the present invention;

[0044] Figure 2 This is a flowchart illustrating an embodiment of a data reading method for a flash memory device according to the present invention;

[0045] Figure 3 This is a schematic diagram of the structural relationship of a data reading device according to the present invention.

[0046] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0047] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0048] like Figure 1 As shown, Figure 1 This is a schematic diagram of the hardware operating environment of the terminal device involved in the embodiment of the present invention.

[0049] It should be noted that, Figure 1 This can be a schematic diagram of the hardware operating environment of the terminal device. In this embodiment of the invention, the terminal device can be a device that executes the data reading method for the flash memory device provided by this invention, specifically for a memory based on NAND flash as the storage medium. The terminal device can be a mobile terminal, a data storage control terminal, a PC, or a portable computer, etc.

[0050] like Figure 1 As shown, the terminal device may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be non-volatile memory (such as Flash memory), high-speed RAM, or stable memory (such as disk storage). Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0051] Those skilled in the art will understand that Figure 1 The terminal device structure shown does not constitute a limitation on the terminal device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0052] like Figure 1 As shown, the memory 1005, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and a data reading program for the flash memory device. The operating system is a program that manages and controls the hardware and software resources of the sample terminal device, supporting the operation of the data reading program for the flash memory device and other software or programs.

[0053] exist Figure 1 In the terminal device shown, the user interface 1003 is mainly used for data communication with various terminals; the network interface 1004 is mainly used for connecting to the backend server and communicating with the backend server; and the processor 1001 can be used to call the data reading program of the flash memory device stored in the memory 1005 and perform the following operations:

[0054] Receive a read command sent by the host, wherein the read command includes the logical address of the data to be read;

[0055] Based on the logical address to be read and the preset block address bitmap, determine whether the read command hits the first-level mapping table in the read-only memory;

[0056] If the first level mapping table is hit, then the first logical address of the first level mapping table is found according to the preset address sequence table, and the data to be read corresponding to the logical address to be read is found according to the first level mapping table.

[0057] Based on the first logical address, update the preset address sequence table and the first level mapping table, and send the data to be read to the host;

[0058] If the first-level mapping table is not hit, the second logical address of the second-level mapping table located in the Flash memory is searched according to the preset second-level mapping table, and the data to be read corresponding to the logical address to be read is searched according to the second-level mapping table.

[0059] Based on the second logical address, update the preset address sequence table, the second-level mapping table, and the preset block address bitmap, and send the data to be read to the host.

[0060] Furthermore, the processor 1001 can call the data reading program of the flash memory device stored in the memory 1005, and also perform the following operations:

[0061] Obtain the third logical address located at the beginning of the preset address sequence table;

[0062] The positions of the first logical address and the third logical address are swapped to obtain the updated first target address sequence table;

[0063] Update the first-level mapping table according to the first target address sequence table, and send the data to be read to the host.

[0064] Furthermore, the processor 1001 can call the data reading program of the flash memory device stored in the memory 1005, and also perform the following operations:

[0065] Obtain the fourth logical address located at the end of the preset address sequence table;

[0066] The fourth logical address is replaced with the second logical address to obtain the updated second target address sequence table;

[0067] According to the second target address sequence table, update the second level mapping table and the preset block address bitmap, and send the data to be read to the host.

[0068] Furthermore, the processor 1001 can call the data reading program of the flash memory device stored in the memory 1005, and also perform the following operations:

[0069] Based on the updated preset address sequence table, the second-level mapping table is updated and the bits in the preset block address bitmap are updated, wherein the preset block address bitmap is a set of bits indicating whether the first-level mapping table exists in the read-only memory.

[0070] Furthermore, the processor 1001 can call the data reading program of the flash memory device stored in the memory 1005, and also perform the following operations:

[0071] Based on the logical address to be read and the preset block size, the index value of the logical address to be read in the preset block address bitmap is obtained;

[0072] Perform a bitwise AND operation between the index value and the preset block address bitmap to obtain the operation result;

[0073] Based on the calculation result, determine whether the read command hits the first-level mapping table in the read-only memory.

[0074] Furthermore, the processor 1001 can call the data reading program of the flash memory device stored in the memory 1005, and also perform the following operations:

[0075] If the result of the operation is 1, then it is determined that the read command hits the first level mapping table in the read-only memory;

[0076] If the result of the operation is 0, it is determined that the read command did not hit the first-level mapping table in the read-only memory.

[0077] Furthermore, the processor 1001 can call the data reading program of the flash memory device stored in the memory 1005, and also perform the following operations:

[0078] Based on the correspondence between the logical address to be read in the preset secondary mapping table and the second-level mapping table, the second-level mapping table corresponding to the logical address to be read is located in the Flash memory.

[0079] Obtain the second logical address of the second-level mapping table.

[0080] Based on the above structure, various embodiments of the data reading method for the flash memory device of the present invention are proposed.

[0081] It should be noted that in this embodiment, due to the rapid development of flash memory technology in recent years, flash memory such as NAND flash (a type of flash memory) has been rapidly adopted in embedded systems and has become the mainstream high-performance storage technology due to its advantages such as high performance, non-volatility, and low power consumption. However, because the read and write characteristics of flash memory devices differ significantly from those of hard disks, the computer's file system cannot directly operate on the storage space of flash memory devices. Therefore, a flash translation layer (FTL) is established between the file system and the flash memory device. The FTL includes a mapping table for converting between logical addresses and physical addresses. When the FTL receives a read / write operation request for the flash memory device, it determines the physical address in the flash memory device based on the mapping table and the logical address in the access request, and then performs the read / write operation on the logical address to be read.

[0082] To ensure response speed, the mapping table is typically stored in the RAM of the flash memory device. Generally, a 1TB SSD's mapping table occupies at least 0.1% of RAM space. For example, with 12 4TB SSDs, the total RAM required is approximately 12 * 4TB * 0.1% = 48GB. However, in DRAM-less (Dynamic Random Access Memory-less) products, due to limited memory resources, the mapping table is only partially cached in RAM, leading to slower read speeds for the flash memory device. Therefore, improving read and write performance in DRAM-less products is a crucial issue that needs to be addressed.

[0083] Based on this, the present invention provides a method for reading a flash memory device, comprising the steps of: receiving a read command sent by a host, the read command including a logical address of data to be read; determining whether the read command hits a first-level mapping table in a read-only memory based on the logical address to be read and a preset block address bitmap; if the first-level mapping table is hit, searching for a first logical address in the first-level mapping table according to a preset address sequence table, and searching for the data to be read corresponding to the logical address to be read according to the first-level mapping table; updating the preset address sequence table and the first-level mapping table according to the first logical address, and sending the data to be read to the host; if the first-level mapping table is not hit, searching for a second logical address in a second-level mapping table located in the flash memory according to a preset second-level mapping table, and searching for the data to be read corresponding to the logical address to be read according to the second-level mapping table; updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and sending the data to be read to the host.

[0084] By employing the above method, this invention avoids the need to traverse the preset address sequence table to find the first-level mapping table by using a preset block address bitmap, thus improving the efficiency of determining whether the first-level mapping table exists in the read-only memory of the flash memory device. By setting the first-level mapping table, the second-level mapping table, and the virtual address sequence table, and by using the second mapping table to find the data corresponding to the read command when the first-level mapping table is not hit, the hit rate of the host in reading data from the DRAM-less flash memory device is improved, thereby increasing the read efficiency of the flash memory device and optimizing its performance. Finally, after reading the data to be read, updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap improves the read speed and performance of the flash memory device for the next read operation.

[0085] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the data reading method for the flash memory device of the present invention.

[0086] This invention provides an embodiment of a data reading method for a flash memory device. This method is applied in the aforementioned terminal device to read data from a memory based on NAND flash memory as the storage medium. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0087] In this embodiment, the data reading method of the flash memory device of the present invention includes:

[0088] Step S10: Receive a read command sent by the host, wherein the read command includes the logical address of the data to be read;

[0089] The host refers to a device that needs to read data from a flash memory device, such as a computer. The read command is a data read command sent by the host to the flash memory device, which includes the logical address of the data to be read.

[0090] It should be noted that the flash memory device in this embodiment specifically includes a read-only memory (ROM) and a flash memory, and the flash memory is Nand Flash. The read-only memory is used to read data located in the flash memory; the flash memory is used to store data, that is, the flash memory stores all the data of the flash memory device.

[0091] Step S20: Based on the logical address to be read and the preset block address bitmap, determine whether the read command hits the first-level mapping table in the read-only memory;

[0092] The preset block address bitmap is a bitmap table that stores a set of several bits, each of which can be represented by 0 or 1. In this embodiment, it is used to determine whether a read command hits the first-level mapping table located in the read-only memory (ROM), i.e., whether the first-level mapping table is located in the ROM. The first-level mapping table is a table used to describe the specific location of data in the flash memory. Since this application is applied to a DRAM-less flash memory device, the storage space in the ROM is limited, and only a small portion of the first-level mapping table can be stored, while the rest needs to be stored in the flash memory. Only when the first-level mapping table is stored in the ROM can the data corresponding to the logical address to be read be read through the first-level mapping table. In this embodiment, the first-level mapping table located in the ROM is the first-level mapping table; the first-level mapping table located in the flash memory is the second-level mapping table.

[0093] Specifically, in one embodiment, step S20 includes:

[0094] Step A21: Based on the logical address to be read and the preset block size, obtain the index value of the logical address to be read in the preset block address bitmap;

[0095] Step A22: Perform a bitwise AND operation between the index value and the preset block address bitmap to obtain the operation result;

[0096] In this embodiment, the preset block size is a constant, specifically determined based on the capacity of the flash memory device, or fixed at 4M. The index value is the quotient between the logical address to be read and the preset block size, used to determine the status of the first-level mapping table corresponding to the logical address to be read on the preset block address bitmap, and this status includes 1 or 0; the preset block address bitmap is used to determine whether the first-level mapping table corresponding to the logical address to be read is in the read-only memory. If it is, the corresponding bit in the preset block address bitmap is 1; if it is not, the corresponding bit is 0. It should be noted that the number of bits in the preset block address bitmap is also determined based on the capacity of the flash memory device, recording whether each first-level mapping table in the flash memory device exists in the read-only memory, and each bit corresponds to one first-level mapping table.

[0097] Step A23: Based on the calculation result, determine whether the read command hits the first-level mapping table in the read-only memory.

[0098] In one embodiment, step A23 further includes:

[0099] Step A231: If the result of the operation is 1, then it is determined that the read command hits the first level mapping table in the read-only memory;

[0100] Step A232: If the result of the operation is 0, it is determined that the read command did not hit the first level mapping table in the read-only memory.

[0101] In this embodiment, the calculation result includes 1 and 0. If the result of ANDing the index with the preset interval address bitmap is 1, it means that the logical address to be read corresponding to the index exists in the read-only memory. If it is 0, it means that it does not exist in the read-only memory, but in the Flash memory.

[0102] Step S30: If the first level mapping table is hit, then the first logical address of the first level mapping table is found according to the preset address sequence table, and the data to be read corresponding to the logical address to be read is found according to the first level mapping table.

[0103] A hit in the first-level mapping table means that the logical address to be read exists in the first-level mapping table of the read-only memory. The preset address sequence table records the starting logical address of each first-level mapping table, and the first logical address is the starting logical address of the first-level mapping table corresponding to the logical address to be read in the preset address sequence table.

[0104] It should be noted that the preset address sequence table exists in the read-only memory. If the logical address to be read exists in the first-level mapping table, then the first-level mapping table corresponding to the logical address to be read needs to be found in the preset address sequence table, and then the corresponding data to be read in the Flash memory needs to be found according to the first-level mapping table.

[0105] Step S40: Update the preset address sequence table and the first level mapping table according to the first logical address, and send the data to be read to the host;

[0106] Since the preset address sequence table records the starting logical address of each first-level mapping table, after finding the first logical address, it needs to be updated as hot data to the front of the preset address sequence table. It should be noted that the preset address sequence table is a linked storage structure; data at the front is hot data (data accessed more frequently), while data at the back is cold data (data accessed less frequently). In this embodiment, updating the preset address sequence table essentially means updating the first logical address of the first-level mapping table to the front of the preset address sequence table. Updating the first-level mapping table is the process of moving the first-level mapping table within the preset address sequence table.

[0107] Specifically, in one embodiment, step S40 further includes:

[0108] Step A41: Obtain the third logical address located at the beginning of the preset address sequence table;

[0109] The third logical address is the logical address corresponding to the first-level mapping table at the very beginning of the preset address sequence table.

[0110] Step A42: Swap the positions of the first logical address and the third logical address to obtain the updated first target address sequence table;

[0111] Since the preset address sequence table is a linked storage structure, the positions of the third logical address at the front and the address of the first-level mapping table corresponding to the logical address to be read are directly swapped, so that the first-level mapping table hit by the logical address to be read is at the front of the preset address sequence table, resulting in an updated first target address sequence table, which is convenient for subsequent reading.

[0112] Step A43: Update the first-level mapping table according to the first target address sequence table, and send the data to be read to the host.

[0113] The update process of the first-level mapping table is the process of moving the first-level mapping table within the preset address sequence table.

[0114] Step S50: If the first level mapping table is not hit, then the second logical address of the second level mapping table located in the Flash memory is searched according to the preset second level mapping table, and the data to be read corresponding to the logical address to be read is searched according to the second level mapping table.

[0115] In one embodiment, step S50 further includes:

[0116] Step A51: Based on the correspondence between the logical address to be read in the preset secondary mapping table and the second-level mapping table, find the second-level mapping table in the Flash memory that corresponds to the logical address to be read.

[0117] Step A52: Obtain the second logical address of the second-level mapping table.

[0118] In this embodiment, the secondary mapping table is used to represent the location of the primary mapping table corresponding to the logical address to be read in the Flash memory. Since the primary mapping table is not hit, it indicates that the primary mapping table corresponding to the logical address to be read is not in the read-only memory, i.e., it is in the Flash memory. In this case, it is necessary to obtain the secondary mapping table of the logical address to be read in the Flash memory, and the second logical address of the secondary mapping table in the Flash memory.

[0119] Step S60: Update the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and send the data to be read to the host.

[0120] After obtaining the second logical address of the second-level mapping table, as described in the above embodiments, since it is not possible to directly call the second-level mapping table in the Flash memory to find the data corresponding to the logical address to be read, it is necessary to update the second-level mapping table corresponding to the logical address to be read to the preset address sequence table in the read-only memory so that the corresponding data to be read can be found according to the logical address to be read. Furthermore, since the preset block address bitmap describes whether the first-level mapping table is in the read-only memory, after updating the second-level mapping table to the read-only memory, the first-level mapping table corresponding to the logical address to be read will exist in the read-only memory, so the preset block address bitmap also needs to be updated.

[0121] Specifically, in one embodiment, step S60 further includes:

[0122] Step A61: Obtain the fourth logical address located at the end of the preset address sequence table;

[0123] Step A62: Replace the fourth logical address with the second logical address to obtain the updated second target address sequence table;

[0124] In this embodiment, the second logical address is the address of the second-level mapping table located in the Flash memory. Replacing the fourth logical address with the second logical address indicates that the second-level mapping table located in the Flash memory is updated to the read-only memory, so that the data corresponding to the logical address to be read can be read, thereby improving the read hit rate and read speed of the read command in the flash memory device.

[0125] Step A63: Update the second-level mapping table and the preset block address bitmap according to the second target address sequence table, and send the data to be read to the host.

[0126] In one embodiment, step A63 further includes:

[0127] Step A631: Update the second-level mapping table and update the bits in the preset block address bitmap according to the updated preset address sequence table, wherein the preset block address bitmap is a set of bits indicating whether the first-level mapping table exists in the read-only memory.

[0128] In this embodiment, updating the second-level mapping table is the process of moving the second-level mapping table from the Flash memory to the read-only memory. For updating the preset block address bitmap, since the block address bitmap is a collection of multiple bits used to describe whether the first-level mapping table is in the address sequence table in the read-only memory, and each bit can only be 1 or 0, a bit being 1 indicates the presence of the first-level mapping table in that bit, and vice versa. After updating the second-level mapping table to the preset address sequence table, since the last first-level mapping table in the preset address sequence table needs to be replaced, it indicates that the original last first-level mapping table is no longer in the address sequence table. Therefore, the state of the corresponding bit of the first-level mapping table needs to be updated to 0, and the state of the corresponding bit of the second-level mapping table in the updated address sequence table needs to be updated to 1.

[0129] This invention proposes a data reading method for flash memory devices. By using a preset block address bitmap, this method avoids the need to traverse a preset address sequence table to find the first-level mapping table, thus improving the efficiency of determining whether the first-level mapping table exists in the read-only memory of the flash memory device. By setting up a first-level mapping table, a second-level mapping table, and a virtual address sequence table, and by using the second mapping table to find the data corresponding to the read command when the first-level mapping table is not hit, the hit rate of the host in reading data from the DRAM-less flash memory device is improved, thereby increasing the read efficiency and optimizing the performance of the flash memory device. Finally, after reading the data, updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap improves the read speed and overall performance of the flash memory device for the next read operation.

[0130] In addition, please refer to Figure 3 The present invention also proposes a data reading device, which includes:

[0131] The receiving module 10 is used to receive a read command sent by the host, wherein the read command includes the logical address of the data to be read;

[0132] The judgment module 20 is used to determine whether the read command hits the first level mapping table in the read-only memory based on the logical address to be read and the preset block address bitmap;

[0133] The lookup module 30 is used to look up the first logical address of the first-level mapping table according to a preset address sequence table, and to look up the data to be read corresponding to the logical address to be read according to the first-level mapping table; and

[0134] It is used to find the second logical address of the second level mapping table located in the Flash memory according to the preset second level mapping table, and to find the data to be read corresponding to the logical address to be read according to the second level mapping table;

[0135] Execution module 40 is configured to update the preset address sequence table and the first-level mapping table according to the first logical address, and send the data to be read to the host; and

[0136] It is used to update the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and to send the data to be read to the host.

[0137] The steps implemented by each functional module of the data reading device of the present invention during the operation of the controller can be referred to the embodiments of the data reading method of the flash memory device of the present invention described above, and will not be repeated here.

[0138] Furthermore, this invention also proposes a terminal device, which includes: a memory, a processor, and a flash memory data reading program stored in the memory and executable on the processor. When the flash memory data reading program is executed by the processor, it implements the steps of the flash memory data reading method described above.

[0139] The steps implemented when the data reading program of the flash memory device running on the processor is executed can be referred to in various embodiments of the data reading method of the flash memory device of the present invention, and will not be repeated here.

[0140] Furthermore, this invention also proposes a computer storage medium for use in a computer. The computer storage medium can be a non-volatile computer-readable storage medium, on which a data reading program for a flash memory device is stored. When the data reading program for the flash memory device is executed by a processor, it implements the steps of the data reading method for the flash memory device as described above.

[0141] The steps implemented when the data reading program of the flash memory device running on the processor is executed can be referred to in various embodiments of the data reading method of the flash memory device of the present invention, and will not be repeated here.

[0142] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0143] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0144] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a computer storage medium (such as Flash memory, ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a controller in a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to control the data read and write operations of the storage medium to execute the methods described in the various embodiments of the present invention.

[0145] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for reading data from a flash memory device, characterized in that, The flash memory device includes a read-only memory and a flash memory, and the method for reading the flash memory device includes the following steps: Receive a read command sent by the host, wherein the read command includes the logical address of the data to be read; Based on the logical address to be read and the preset block address bitmap, determine whether the read command hits the first-level mapping table in the read-only memory. This includes obtaining the index value of the logical address to be read in the preset block address bitmap based on the logical address to be read and the preset block size; performing a bitwise AND operation between the index value and the preset block address bitmap to obtain the operation result; and determining whether the read command hits the first-level mapping table in the read-only memory based on the operation result. If the first level mapping table is hit, then the first logical address of the first level mapping table is found according to the preset address sequence table, and the data to be read corresponding to the logical address to be read is found according to the first level mapping table. Based on the first logical address, update the preset address sequence table and the first level mapping table, and send the data to be read to the host, including obtaining the third logical address located at the beginning of the preset address sequence table; swapping the positions of the first logical address and the third logical address to obtain an updated first target address sequence table; updating the first level mapping table based on the first target address sequence table, and sending the data to be read to the host; If the first-level mapping table is not hit, the second logical address of the second-level mapping table located in the Flash memory is searched according to the preset second-level mapping table, and the data to be read corresponding to the logical address to be read is searched according to the second-level mapping table. Based on the second logical address, update the preset address sequence table, the second-level mapping table, and the preset block address bitmap, and send the data to be read to the host, including obtaining the fourth logical address located at the end of the preset address sequence table; replacing the fourth logical address with the second logical address to obtain the updated second target address sequence table; updating the second-level mapping table and the preset block address bitmap based on the second target address sequence table, and sending the data to be read to the host.

2. The data reading method for a flash memory device as described in claim 1, characterized in that, The step of updating the second-level mapping table and the preset block address bitmap according to the second target address sequence table includes: Based on the updated preset address sequence table, the second-level mapping table is updated and the bits in the preset block address bitmap are updated, wherein the preset block address bitmap is a set of bits indicating whether the first-level mapping table exists in the read-only memory.

3. The data reading method for a flash memory device as described in claim 1, characterized in that, The result of the operation includes 1 and 0; The step of determining whether the read command hits the first-level mapping table in the read-only memory based on the calculation result includes: If the result of the operation is 1, then it is determined that the read command hits the first level mapping table in the read-only memory; If the result of the operation is 0, it is determined that the read command did not hit the first-level mapping table in the read-only memory.

4. The data reading method for a flash memory device as described in claim 3, characterized in that, The step of finding the second logical address of the second-level mapping table located in the Flash memory according to the preset second-level mapping table includes: Based on the correspondence between the logical address to be read in the preset secondary mapping table and the second-level mapping table, the second-level mapping table corresponding to the logical address to be read is located in the Flash memory. Obtain the second logical address of the second-level mapping table.

5. A data reading device, characterized in that, The data reading device is applied to a data reading method for a flash memory device, and the data reading device includes: The receiving module is used to receive a read command sent by the host, wherein the read command includes the logical address of the data to be read; The judgment module is used to determine whether the read command hits the first-level mapping table in the read-only memory based on the logical address to be read and the preset block address bitmap. This includes obtaining the index value of the logical address to be read in the preset block address bitmap based on the logical address to be read and the preset block size; performing a bitwise AND operation between the index value and the preset block address bitmap to obtain the operation result; and determining whether the read command hits the first-level mapping table in the read-only memory based on the operation result. The lookup module is configured to, if the first level mapping table is matched, search for the first logical address of the first level mapping table according to a preset address sequence table, and search for the data to be read corresponding to the logical address to be read according to the first level mapping table; if the first level mapping table is not matched, search for the second logical address of the second level mapping table located in the Flash memory according to a preset second level mapping table, and search for the data to be read corresponding to the logical address to be read according to the second level mapping table. An execution module is configured to update the preset address sequence table and the first-level mapping table according to the first logical address, and send the data to be read to the host, including obtaining the third logical address located at the beginning of the preset address sequence table; swapping the positions of the first logical address and the third logical address to obtain an updated first target address sequence table; updating the first-level mapping table according to the first target address sequence table, and sending the data to be read to the host; updating the preset address sequence table, the second-level mapping table, and the preset block address bitmap according to the second logical address, and sending the data to be read to the host, including obtaining the fourth logical address located at the end of the preset address sequence table; replacing the fourth logical address with the second logical address to obtain an updated second target address sequence table; updating the second-level mapping table and the preset block address bitmap according to the second target address sequence table, and sending the data to be read to the host.

6. A terminal device, characterized in that, The terminal device includes: a memory, a processor, and a data reading program for a flash memory device stored in the memory and executable on the processor. When the data reading program for the flash memory device is executed by the processor, it implements the steps of the data reading method for the flash memory device as described in any one of claims 1 to 4.

7. A computer storage medium, characterized in that, The computer storage medium stores a data reading program for a flash memory device, which, when executed by a processor, implements the steps of the data reading method for a flash memory device as described in any one of claims 1 to 4.

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