Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: forming a sidewall film conformally covering an offset sidewall, a gate structure, and a substrate, and a first sidewall located on the sidewall of the sidewall film on the sidewall of the offset sidewall; forming a source region and a drain region in the substrate on one side and the other side of the gate structure in a first device region; forming a protective film conformally covering the top surface, sidewall, and sidewall of the first sidewall; removing the protective film on the first sidewall on the side of the first device region near the source region to form a protective layer; using the protective layer as a mask, removing the first sidewall on the side of the source region; removing the sidewall film and protective layer exposed by the first sidewall; forming a first lightly doped region in the substrate between the source region and the offset sidewall in the first device region; and forming a metal silicide layer on the source region, the drain region, the first lightly doped region, and the top surface of the gate structure. Embodiments of the present invention improve the performance of TFET devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Traditional CMOS (Complementary Metal Oxide Semiconductor) devices, subject to the Boltzmann limit, have a minimum subthreshold swing at room temperature. Consequently, as CMOS device sizes continue to shrink, static power consumption increases exponentially with decreasing operating voltage. Consequently, CMOS is typically used in high-performance computing, where dynamic power consumption dominates.

[0003] Unlike conventional CMOS, the source and drain regions of TFET (Tunneling Field-effect Transistor) have different doping types. TFET replaces the source-channel-drain structure with a PIN structure and uses band-to-band tunneling as the conduction mechanism. It can break through the subthreshold swing limitation and achieve extremely low static leakage current and lower operating voltage, thereby reducing static power consumption.

[0004] Therefore, TFET devices with excellent subthreshold characteristics can be hybrid integrated with traditional CMOS devices to reduce the overall power consumption of the circuit. The high-frequency part of the circuit is completed by conventional CMOS devices, and the low-frequency part is completed by TFET devices. This hybrid integration method is widely used in the Internet of Things.

[0005] However, the performance of TFET devices still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of TFET devices.

[0007] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region for forming a tunneling field effect transistor; forming a gate structure on the substrate, wherein an offset sidewall is formed on the sidewall of the gate structure; forming a sidewall film located on the top surface and sidewall of the offset sidewall, the top surface of the gate structure and the top surface of the substrate, and a first sidewall located on the sidewall of the sidewall film of the offset sidewall; after forming the first sidewall, in the first device region, forming a source region in the substrate on one side of the gate structure, and forming a drain region in the substrate on the other side of the gate structure, wherein the doping type of the drain region is different from that of the source region; forming a protective film conformally covering the top surface and sidewall of the first sidewall, the offset sidewall and the gate structure and the sidewall film on the top surface of the substrate; in the first device area, the protective film on the first sidewall close to the source area is removed, and the remaining protective film is used as a protective layer; using the protective layer as a mask, the first sidewall close to the source area is removed; after removing the first sidewall close to the source area, the protective layer and the sidewall film exposed by the first sidewall are removed, and the remaining sidewall film located between the offset sidewall and the first sidewall, and between the substrate and the first sidewall is used as a second sidewall; in the first device area, a first lightly doped region is formed in the substrate between the source area and the offset sidewall, and the first lightly doped region has the same doping type as the source area; a metal silicide layer is formed on the source area, the drain area, the first lightly doped region and the top surface of the gate structure.

[0008] Optionally, in the step of providing a substrate, the substrate also includes a second device region for forming a metal oxide semiconductor field effect transistor; the method for forming the semiconductor structure also includes: after forming the first side wall and before forming the protective film, forming a source-drain doped region in the substrate on both sides of the gate structure and the first side wall of the second device region; in the step of forming the metal silicide layer, the metal silicide layer is also formed on the top surface of the source-drain doped region.

[0009] Optionally, the method for forming the semiconductor structure further includes: after forming the offset sidewall and before forming the sidewall film, forming a second lightly doped region in the substrate on both sides of the gate structure and the offset sidewall of the second device region.

[0010] Optionally, after forming the first sidewall spacer and before forming the source region and the drain region, source and drain doped regions are formed in the substrate on both sides of the gate structure and the first sidewall spacer of the second device region.

[0011] Optionally, the material of the protective film is the same as that of the sidewall film; in the same step, the sidewall film and the protective layer exposed by the first sidewall are removed.

[0012] Optionally, in the step of forming the protective film, the material of the protective film includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride or boron carbonitride.

[0013] Optionally, in the step of forming the protective film, the thickness of the protective film is the same as the thickness of the sidewall film.

[0014] Optionally, the first side wall and the offset side wall are made of the same material.

[0015] Optionally, the material of the first side wall includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and carbon silicon oxynitride; the material of the offset side wall includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and carbon silicon oxynitride.

[0016] Optionally, in the first device area, the step of removing the protective film on the first side wall close to the source area includes: forming a mask layer on the protective film, the mask layer having a mask opening, and the mask opening being located above the top surface and side wall of the first side wall close to the source area of the first device area; using the mask layer as a mask, removing the protective film exposed by the mask opening; and removing the mask layer.

[0017] Optionally, the process of removing the protective film on the first sidewall adjacent to the source region includes a wet etching process.

[0018] Optionally, the process of removing the first sidewall spacer on the side of the first device region close to the source region includes a wet etching process.

[0019] Optionally, the process of removing the spacer film and the protective layer exposed by the first spacer includes a wet etching process.

[0020] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0021] Optionally, the material of the gate layer includes polysilicon or amorphous silicon.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] In the method for forming a semiconductor structure provided by an embodiment of the present invention, before forming the protective film, the sidewall film located on the top surface of the offset sidewall and the gate structure is retained. Accordingly, in the step of forming the protective film, the protective film can conformally cover the top surface and sidewall of the first sidewall, as well as the sidewall film on the offset sidewall and the gate structure and the top surface of the substrate. Therefore, compared with only the protective film formed on the sidewall of the first sidewall, the film layer on the top surface of the offset sidewall and the gate structure is a stacked structure composed of the sidewall film and the protective film, and the film layer on the top surface of the offset sidewall and the gate structure is thicker. Therefore, in the step of removing the protective film on the sidewall of the first sidewall close to the source region, after removing the protective film on the sidewall of the first sidewall close to the source region, the film layer on the top of the gate structure and the offset sidewall is still The film layer that can retain a certain thickness and is located on the top of the gate structure and the offset side wall can protect the offset side wall during the step of removing the first side wall close to the source region, so as to prevent the offset side wall close to the source region in the first device region from being damaged. This is beneficial to ensuring the integrity of the offset side wall close to the source region, and reducing the risk of partial exposure of the side wall of the gate structure due to the reduction of the offset side wall close to the source region, thereby preventing the metal silicide layer from forming on the exposed side wall of the gate structure, and preventing the metal silicide layer from affecting the electric field distribution inside the gate structure, and preventing the problem of short circuit with the metal silicide layer located on the first lightly doped region and the source region due to the extension of the metal silicide layer along the side wall of the gate structure, thereby optimizing the performance of the semiconductor structure.

[0024] In addition, the embodiment of the present invention retains the sidewall film located on the offset sidewall and the top of the gate structure before forming the protective film, without introducing additional film layers and process steps, thereby avoiding major changes to the process flow, which is correspondingly beneficial to improving process compatibility and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0026] Figures 11 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background art, the performance of TFET devices currently needs to be improved. The reasons why the performance of TFET devices needs to be improved are now analyzed in conjunction with a method for forming a semiconductor structure. Figures 1 to 10 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0028] refer to Figure 1 , providing a substrate 10, including a first device region 10i for forming a TFET device and a second device region 10ii for forming a MOS device; forming a gate structure 20 on the substrate 10, and forming an offset spacer 25 on the sidewall of the gate structure 20.

[0029] Continue to refer Figure 1 A spacer film 26 is formed on the top surface of the substrate 10 , the top surfaces of the gate structure 20 and the offset spacer 25 , and the sidewalls of the offset spacer 25 .

[0030] refer to Figure 2 , forming a first sidewall spacer 27 on the sidewall of the sidewall spacer film 26 located on the sidewall of the offset sidewall spacer 25 .

[0031] refer to Figure 3 , source-drain doped regions 11 are formed in the substrate 10 on both sides of the gate structure 20 of the second device region 10 ii.

[0032] refer to Figure 4 After forming the source and drain doped regions 11, the sidewall film 26 located on the substrate 10, the gate structure 20 and the top surface of the offset sidewall 25 is removed, and the remaining sidewall film 26 located between the offset sidewall 25 and the first sidewall 27 and between the top surface of the substrate 10 and the first sidewall 26 is used as the second sidewall 29.

[0033] Continue to refer Figure 4 In the first device region 10 i , a source region 31 is formed in the substrate 10 on one side of the gate structure 20 , and a drain region 32 is formed in the substrate 10 on the other side of the gate structure 20 .

[0034] refer to Figure 5 A protection film 12 is formed on the top surface of the substrate 10 , the sidewalls and top surface of the first spacer 27 , the second spacer 29 and the top surface of the gate structure 20 .

[0035] refer to Figure 6 In the first device region 10i, the protective film 12 on the top surface and sidewall of the first sidewall 28, the top surface of the second sidewall 29, and part of the top surface of the gate structure 20 located on the side close to the source region 31 is removed, and the remaining protective film is used as a protective layer 13.

[0036] refer to Figure 7 , using the protection layer 13 as a mask, remove the first sidewall spacer 27 on the side of the first device region 10 i close to the source region 31 .

[0037] refer to Figure 8The protection layer 13 and the second sidewall spacer 29 located on the side of the first device region 10 i close to the source region 31 are removed to expose the substrate 10 between the source region 31 of the first device region 10 i and the offset sidewall spacer 25 .

[0038] refer to Figure 9 A lightly doped region 40 is formed in the substrate 10 between the source region 31 and the offset spacer 25 .

[0039] refer to Figure 10 A metal silicide layer 45 is formed on the source / drain doped region 11 , the top surface of the source region 31 , the drain region 32 , the top surface of the lightly doped region 40 , and the exposed surface of the gate structure 20 .

[0040] In the formation method, in order to ensure that the photolithography process has a sufficient photolithography process window, in the step of forming the protection layer 13, in the first device region 10i, not only the protection film 12 on the top surface and side wall of the first sidewall 27 located on the side close to the source region 31 is removed, but also the protection film 12 on the top surface of the second sidewall 29 located on the side close to the source region 31 and the partial top surface of the gate structure 20 are removed, thereby exposing the top surface of the second sidewall 29 located on the side close to the source region 31 and the partial top surface of the gate structure 20. In the step of removing the first sidewall 28 located on the side close to the source region 31 of the first device region 10i using the protection layer 13 as a mask, the top surface of the offset sidewall 25 is exposed, which can easily cause damage to the offset sidewall 25. The height of the offset sidewall 25 on the side close to the source region 31 is reduced, resulting in partial sidewall exposure of the gate structure 20 (e.g., Figure 7 (shown by the dotted circle in the middle).

[0041] Accordingly, in the step of forming the metal silicide layer 45, the metal silicide layer 45 is also easily formed on the sidewall of the gate structure 20 exposed near the source region 31 (eg, Figure 10 As shown by the dotted circle in the middle, the metal silicide layer also extends downward along the sidewall of the gate structure 20 to the position of the offset sidewall 25, which will affect the electric field distribution in the gate structure 20. Moreover, when the loss of the offset sidewall 25 close to the source region 31 is more serious, the metal silicide layer 45 located on the sidewall of the gate structure 20 is also likely to contact the source region 31 and the metal silicide layer 45 on the lightly doped region 40, resulting in a short circuit between the gate structure 20 and the source region 31.

[0042] In particular, in the semiconductor field, the first sidewall 27 and the offset sidewall 25 are usually made of materials with similar etching properties. For example, the first sidewall 27 and the offset sidewall 25 are made of the same material. In the step of removing the first sidewall 27 located on the side of the first device region 10i close to the source region 31, the offset sidewall 25 is more seriously damaged, and the metal silicide layer 45 is more likely to extend downward along the exposed sidewall of the gate structure 20, resulting in the electric field in the gate structure 20 being affected and a higher risk of short-circuiting the gate structure 20 and the source region 31.

[0043] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region for forming a tunneling field effect transistor; forming a gate structure on the substrate, wherein an offset sidewall is formed on the sidewall of the gate structure; forming a sidewall film located on the top surface and sidewalls of the offset sidewall, the top surface of the gate structure and the top surface of the substrate, and a first sidewall located on the sidewall of the sidewall film of the offset sidewall; after forming the first sidewall, forming a source region in the substrate on one side of the gate structure in the first device region, and forming a drain region in the substrate on the other side of the gate structure, wherein the doping type of the drain region is different from that of the source region; forming a protective film conformally covering the top surface and sidewalls of the first sidewall, and the offset sidewall and gate junction. on the sidewall film on the top surface of the substrate; in the first device area, the protective film on the first sidewall close to the source area is removed, and the remaining protective film is used as a protective layer; using the protective layer as a mask, the first sidewall close to the source area is removed; after removing the first sidewall close to the source area, the protective layer and the sidewall film exposed by the first sidewall are removed, and the remaining sidewall film between the offset sidewall and the first sidewall, and between the substrate and the first sidewall is used as a second sidewall; in the first device area, a first lightly doped region is formed in the substrate between the source area and the offset sidewall, and the first lightly doped region has the same doping type as the source area; a metal silicide layer is formed on the source area, the drain area, the first lightly doped region and the top surface of the gate structure.

[0044] In the method for forming a semiconductor structure provided by an embodiment of the present invention, before forming the protective film, the sidewall film located on the top surface of the offset sidewall and the gate structure is retained. Accordingly, in the step of forming the protective film, the protective film can conformally cover the top surface and sidewall of the first sidewall, as well as the sidewall film on the offset sidewall and the gate structure and the top surface of the substrate. Therefore, compared with only the protective film formed on the sidewall of the first sidewall, the film layer on the top surface of the offset sidewall and the gate structure is a stacked structure composed of the sidewall film and the protective film, and the film layer on the top surface of the offset sidewall and the gate structure is thicker. Therefore, in the step of removing the protective film on the sidewall of the first sidewall close to the source region, after removing the protective film on the sidewall of the first sidewall close to the source region, the film layer on the top of the gate structure and the offset sidewall is still The film layer that can retain a certain thickness and is located on the top of the gate structure and the offset side wall can protect the offset side wall during the step of removing the first side wall close to the source region, so as to prevent the offset side wall close to the source region in the first device region from being damaged. This is beneficial to ensuring the integrity of the offset side wall close to the source region, and reducing the risk of partial exposure of the side wall of the gate structure due to the reduction of the offset side wall close to the source region, thereby preventing the metal silicide layer from forming on the exposed side wall of the gate structure, and preventing the metal silicide layer from affecting the electric field distribution inside the gate structure, and preventing the problem of short circuit with the metal silicide layer located on the first lightly doped region and the source region due to the extension of the metal silicide layer along the side wall of the gate structure, thereby optimizing the performance of the semiconductor structure.

[0045] In addition, the embodiment of the present invention retains the sidewall film located on the offset sidewall and the top of the gate structure before forming the protective film, without introducing additional film layers and process steps, thereby avoiding major changes to the process flow, which is correspondingly beneficial to improving process compatibility and saving costs.

[0046] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 11 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0048] refer to Figure 11 , providing a substrate 100 including a first device region 100T for forming a tunneling field-effect transistor (TFET).

[0049] The substrate 100 is used to provide a process platform for subsequent process steps.

[0050] In this embodiment, the substrate 100 is used to form a planar field effect transistor as an example, and the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a three-dimensional substrate according to the type of transistor actually formed.

[0051] The first device region 100T is used to form a tunneling field effect transistor (TFET).

[0052] In this embodiment, the substrate 100 further includes a second device region 100M for forming a Metal Oxide Semiconductor Field-effect Transistor (MOSFET).

[0053] The second device region 100M is used to form a metal oxide semiconductor (MOS) field effect transistor. The first device region 100T and the second device region 100M are isolated from each other.

[0054] In this embodiment, a well region 160 is further formed in the substrate 100 of the second device region 100M.

[0055] The well region 160 has a different doping type from the source and drain doping regions of the MOS transistor. As an example, the second device region 100M is used to form an NMOS transistor, and the well region 160 is a P-type well region.

[0056] To this end, in this embodiment, an isolation structure 110 is further formed in the substrate 100 at the junction of the first device region 100T and the second device region 100M. The isolation structure 110 is used to achieve isolation between the first device region 100T and the second device region 100M.

[0057] In this embodiment, the isolation structure 110 is made of an insulating material. As an example, the isolation structure 110 is a shallow trench isolation (STI) structure, and the isolation structure 110 is made of silicon oxide.

[0058] In this embodiment, a trench (not shown) is formed in the substrate 100 at the junction of the first device region 100T and the second device region 100M, and the isolation structure 110 is formed in the trench.

[0059] In this embodiment, an adhesion layer 120 is formed on the sidewalls and bottom of the trench, and the isolation structure 110 is located on the adhesion layer 120 and fills the trench. The adhesion layer 120 is used to improve the smoothness of the sidewalls and bottom of the trench, thereby providing a good interface state for forming the isolation structure 110. The adhesion layer 120 is also used to improve the adhesion between the isolation structure 110 and the trench.

[0060] In this embodiment, the material of the adhesion layer 120 is silicon oxide.

[0061] Continue to refer Figure 11 A gate structure 200 is formed on the substrate 100 , and an offset spacer 220 is formed on the sidewall of the gate structure 200 .

[0062] In this embodiment, the gate structure 200 includes a gate dielectric layer 230 and a gate layer 210 located on the gate dielectric layer 230 .

[0063] The gate dielectric layer 230 is used to isolate the gate layer 210 from the conductive channel.

[0064] In this embodiment, the gate dielectric layer 230 includes a gate oxide layer, and the material of the gate oxide layer includes silicon oxide or nitrogen-doped silicon oxide.

[0065] When the device is working, the gate layer 210 is used to control the opening or closing of the conductive channel. In this embodiment, the material of the gate layer 210 includes polysilicon or amorphous silicon.

[0066] The offset sidewall 220 is used to protect the sidewall of the gate structure 200; moreover, the offset sidewall 220 of the first device area 100T is used to define the formation position of the subsequent first lightly doped area, and the offset sidewall 220 of the second device area 100M is used to define the formation position of the subsequent second lightly doped area; in addition, after the first sidewall of the first device area 100T close to the source area and the sidewall film exposed by the first sidewall are subsequently removed, in the process of forming the metal silicide layer, the offset sidewall 220 is located on the sidewall of the gate layer 210, and is also used to block the growth of the metal silicide layer on the sidewall of the gate layer 210 in the first device area 100T.

[0067] The material of the offset spacer 220 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the offset spacer 220 is silicon nitride.

[0068] Combined with reference Figure 12 In this embodiment, the method for forming the semiconductor structure further includes: after forming the offset spacer 230 , forming a second lightly doped region 140 in the substrate 100 on both sides of the gate structure 200 and the offset spacer 220 of the second device region 100M.

[0069] The second lightly doped region 140 is used to improve the short channel effect and hot carrier injection effect of the MOS transistor.

[0070] The doping type of the second lightly doped region 140 is the same as the doping type of the source and drain doping regions of the MOS transistor. When forming an NMOS transistor, the doping ions of the second lightly doped region 140 are N-type ions, such as P ions, As ions, or Sb ions. When forming a PMOS transistor, the doping ions of the second lightly doped region 140 are P-type ions, such as B ions, Ga ions, or In ions.

[0071] In this embodiment, the step of forming the second lightly doped region 140 includes: forming a first blocking layer (not shown) covering the first device region 100T and the resistance region 100R, the first blocking layer exposing the second device region 100M; using the first blocking layer as a mask, ion implantation is performed on the substrate 100 on both sides of the gate structure 200 and the offset side wall 220 of the second device region 100M to form the second lightly doped region 140; and removing the first blocking layer.

[0072] The first shielding layer is used as a mask for ion implantation into the substrate 100 on both sides of the gate structure 200 and the offset spacer 220 of the second device region 100M. In this embodiment, the material of the first shielding layer is photoresist.

[0073] In this embodiment, the process of performing ion implantation into the substrate 100 on both sides of the gate structure 200 and the offset spacer 220 of the second device region 100M is a lightly doped drain (LDD) implantation process.

[0074] In this embodiment, the first shielding layer is removed by using an ashing process and a wet resist stripping process performed sequentially.

[0075] refer to Figure 13 , forming a spacer film 130 located on the top surface and sidewall of the offset spacer 220, the top surface of the gate structure 220 and the top surface of the substrate 100, and a first spacer 310 located on the sidewall of the spacer film 130 on the sidewall of the offset spacer 220.

[0076] The spacer film 130 and the first spacer 310 located on the sidewall of the offset spacer 220 constitute a spacer structure, which is used to define the source and drain doping regions of the MOS transistor and the formation positions of the source and drain regions of the TFET device.

[0077] In this embodiment, the material of the first spacer 310 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride.

[0078] As an embodiment, the first sidewall spacer 310 is a single-layer structure. The first sidewall spacer 310 and the offset sidewall spacer 220 are made of the same material, that is, silicon nitride.

[0079] In this embodiment, the material of the spacer film 130 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride.

[0080] As an embodiment, the spacer film 130 is a single-layer structure, and the material of the spacer film 130 is silicon oxide.

[0081] As an example, the steps of forming the spacer film 130 and the first spacer 310 include: forming the spacer film 130 on the top surface and sidewalls of the offset spacer 220, the top surface of the gate structure 220 and the top surface of the substrate 100; forming a conformal spacer material layer (not shown) on the spacer film 130; and etching the spacer material layer using an anisotropic etching process, retaining the spacer material layer on the sidewall of the spacer film 130 to serve as the first spacer 310.

[0082] In this embodiment, only the sidewall material layer located on the sidewall of the sidewall film 130 is retained to serve as the first sidewall 310, thereby preventing the thickness of the film layer located on the top surface of the substrate 100 from being too large, so as to facilitate the subsequent doping of the substrate 100 on both sides of the gate structure 200 of the second device area 100M.

[0083] In this embodiment, an anisotropic etching process is used to etch the spacer material layer. The anisotropic etching process has the characteristic of anisotropic etching, and the etching rate in the direction perpendicular to the surface of the substrate 100 is much greater than the etching rate in the direction parallel to the surface of the substrate 100. Therefore, while the spacer material layer on the top surface of the spacer film 130 is removed, the spacer material layer on the sidewall of the spacer film 130 can be retained to serve as the first spacer 310.

[0084] Specifically, the anisotropic etching process may be an anisotropic dry etching process.

[0085] It should be noted that, in the present embodiment, during the process of etching the sidewall material layer using an anisotropic etching process, the sidewall film 130 located on the gate structure 200, the offset sidewall 220 and the top surface of the substrate 100 is not over-etched, thereby preventing the thickness of the sidewall film 130 located on the top surface of the gate structure 200 and the offset sidewall 220 from being reduced, thereby ensuring that in the subsequent etching process, the sidewall film 130 located on the top surface of the offset sidewall 220 can at least retain a portion of its thickness, so that in the process of removing the first sidewall 310 close to the source region 250 side, the top of the offset sidewall 220 close to the source region 250 side plays a protective role.

[0086] refer to Figure 14 In this embodiment, the method for forming the semiconductor structure further includes: after forming the first sidewall 310 , forming a source-drain doped region 240 in the substrate 100 on both sides of the gate structure 200 and the first sidewall 310 of the second device region 100M.

[0087] The source-drain doped region 240 is used as a source or drain of the MOS transistor, and is used to provide a carrier source when the MOS transistor is working.

[0088] In this embodiment, the doping depth of the source / drain doping region 240 is greater than the doping depth of the second lightly doped region 140 , and the doping type of the source / drain doping region 240 is the same as the doping type of the second lightly doped region 140 , so that the source / drain doping region 240 covers a partial area of the second lightly doped region 140 .

[0089] When forming an NMOS transistor, the doping ions in the source / drain doping region 240 are N-type ions, which include P ions, As ions, or Sb ions. When forming a PMOS transistor, the doping ions in the source / drain doping region 240 are P-type ions, which include B ions, Ga ions, or In ions.

[0090] In this embodiment, the steps of forming the source-drain doped region 240 include: forming a second blocking layer 180 covering the first device region 100T, the second blocking layer 180 exposing the second device region 100M; using the second blocking layer 180 as a mask, ion doping is performed on the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first side wall 310 to form the source-drain doped region 240; and removing the second blocking layer 180.

[0091] The second blocking layer 180 is used as a mask for ion doping the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first spacer 310. In this embodiment, the material of the second blocking layer 180 is photoresist.

[0092] In this embodiment, an ion implantation process is used to perform ion doping on the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first spacer 310 .

[0093] In this embodiment, the second shielding layer 180 is removed by using an ashing process and a wet stripping process performed sequentially.

[0094] refer to Figures 15 and 16 After forming the first sidewall spacer 310, in the first device region 100T, a source region 250 is formed in the substrate 100 on one side of the gate structure 200, and a drain region 260 is formed in the substrate 100 on the other side of the gate structure 200, wherein the drain region 260 has a different doping type from the source region 250.

[0095] The drain region 260 and the source region 250 are used as the drain and source of the TFET device, respectively.

[0096] The drain region 260 and the source region 250 have different doping types, thereby forming a PIN (P-Intrinsic-N) structure, and then using band-to-band tunneling as a conduction mechanism.

[0097] As an example, the TFET device is a P-type TFET device, the doping ions in the drain region 260 are P-type ions, and the doping ions in the source region 250 are N-type ions. In other embodiments, when an N-type TFET device is formed, the doping ions in the drain region are N-type ions, and the doping ions in the source region are P-type ions.

[0098] The drain region 260 and the source region 250 have different doping types. Therefore, the drain region 260 and the source region 250 are formed in different steps.

[0099] As an example, the steps of forming the source region 250 include: Figure 15 As shown, a third blocking layer 190 is formed in the second device area 100M, and the third blocking layer 190 also covers the substrate 100 on the other side of the gate structure 200 of the first device area 100T; using the third blocking layer 190 as a mask, ion implantation is performed on the substrate 100 to form a source area 250 in the substrate 100 on one side of the gate structure 200 of the first device area 100T; and the third blocking layer 190 is removed.

[0100] In this embodiment, the source region 250 and the drain region 260 of the TFET device are formed after the source and drain doping regions 240 of the MOS transistor are formed. However, the order of forming the source and drain doping regions 240 and forming the source region 250 and the drain region 260 is not limited to this.

[0101] refer to Figure 17, forming a protection film 150 conformally covering the top surface and sidewalls of the first spacer 310 , the offset spacer 220 , the gate structure 200 and the spacer film 130 on the top surface of the substrate 100 .

[0102] The protection film 150 is used to form a protection layer through a subsequent etching process, and the protection layer is used as a mask for subsequently removing the first sidewall spacer 310 on a side of the first device region 100T close to the source region 250 .

[0103] In this embodiment, before forming the protection film 150, the spacer film 130 located on the top surface of the offset spacer 220 and the gate structure 200 is retained. Accordingly, the protection film 150 can conformally cover the top surface and sidewall of the first spacer 310, as well as the offset spacer 220, the gate structure 200 and the spacer film 130 on the top surface of the substrate 100. Therefore, compared with the case where only the protection film 150 is formed on the sidewall of the first spacer 310, the offset spacer 220 and the gate structure 200 are more conformally covered. 0 is a stacked structure consisting of the spacer film 130 and the protective film 150. The film layer on the top surface of the offset spacer 220 and the gate structure 200 is thicker. Therefore, in the subsequent step of removing the protective film 150 on the side wall of the first spacer 310 located on the side close to the source region 250, after the protective film 150 on the side wall of the first spacer 310 close to the source region 250 is removed, the film layer on the top of the gate structure 200 and the offset spacer 220 can still retain a certain thickness.

[0104] In this embodiment, the protective film 150 is made of a material having an etching selectivity with the material of the first spacer 310. Specifically, in this embodiment, the material of the protective film 150 is the same as the material of the spacer film 130. Therefore, after the first spacer 310 on the side of the first device region 100T near the source region 250 is subsequently removed, the protective film 150 and the spacer film 130 on the side of the first device region 100T near the source region 250 can be removed in the same step, which is beneficial to simplifying the process steps and improving process compatibility.

[0105] In this embodiment, the material of the protective film 150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride. Specifically, in this embodiment, the material of the protective film 150 is the same as that of the spacer film 130, that is, silicon oxide.

[0106] It should be noted that the thickness of the protective film 150 should not be too small or too large. If the thickness of the protective film 150 is too small, the protective film 150 will be easily etched away during the subsequent removal of the sidewall 150 on the side of the first device region 100T close to the source region 250, which will make it difficult for the protective film 150 to protect the first sidewall 310 on the side of the first device region 100T close to the drain region 250 and the second device region 100M. If the thickness of the protective film 150 is too large, the subsequent removal process of the protective film 150 will be more difficult and the time required to remove the protective film 150 will be too long, which will easily increase the risk of damaging other film structures and easily lead to poor thickness consistency of the protective film 150. In turn, it will easily lead to over-etching of the thinner areas of the protective film 150 during the subsequent removal of the protective layer.

[0107] Therefore, in this embodiment, the thickness of the protection film 150 is slightly different from the thickness of the sidewall film 130 .

[0108] As an example, the thickness of the protective film 150 is the same as the thickness of the sidewall film 130. For example, the thickness of the protective film 150 is The thickness of the protective layer 310 is the same as that of the sidewall film 130, so that in the subsequent process of removing the sidewall film 130 exposed on the first sidewall 310, the protective layer 310 can also be removed at the same time, avoiding the generation of residual protective film 150, further eliminating the impact on the first sidewall 310 of the first device area 100T close to the drain area 260 and the second device area 100M, thereby improving process integration and process compatibility.

[0109] In this embodiment, the process for forming the protective film 150 includes a low-pressure chemical vapor deposition (LPCVD) process. In this embodiment, the material of the protective film 150 is silicon oxide, and the precursor used in the LPCVD process includes TEOS (Tetra-Ethyl-Ortho-Silicate). TEOS is liquid at room temperature. Using TEOS for LPCVD to form silicon oxide is beneficial for improving the thickness uniformity, conformality, and film quality of the protective film 150.

[0110] In other embodiments, the protective film may be formed by other suitable deposition processes, such as a high aspect ratio (HARP) process, a plasma enhanced (PE) deposition process, a high-density plasma (HDP) process, a spin-on coating (SOC) process, and the like.

[0111] refer to Figure 18 In the first device region 100T, the protection film 150 on the first sidewall spacer 310 close to the source region 250 is removed, and the remaining protection film 150 is used as a protection layer 350 .

[0112] The protective layer 350 is used as a mask for the subsequent removal of the sidewall 150 of the first device region 100T near the source region 250, and is used to protect the sidewall 150 of the first device region 100T near the drain region 260, as well as the second device region 100M and the resistance region 100R, so as to reduce the impact on the sidewall 150 of the first device region 100T near the drain region 260, as well as the second device region 100M and the resistance region 100R, thereby improving process compatibility.

[0113] In this embodiment, in the step of forming the protective film 150, the protective film 150 conformally covers the top surface and sidewall of the first spacer 310, as well as the offset spacer 220, the gate structure 200, and the spacer film 130 on the top surface of the substrate 100. Compared with the sidewall of the first spacer 310 where only the protective film 150 is formed, the film layer on the offset spacer 220 and the top surface of the gate structure 200 is a stacked structure consisting of the spacer film 130 and the protective film 150. The film layer on the offset spacer 220 and the top surface of the gate structure 200 is thicker, so that when removing the first spacer located on the side close to the source region 250, the spacer film 130 is formed. In the step of removing the protective film 150 on the side wall of the side wall 310, after removing the protective film 150 on the side wall of the first side wall 310 close to the source area 250, the film layer on the top of the gate structure 200 and the offset side wall 220 can still retain a certain thickness, so that the remaining film layer on the top of the gate structure 200 and the offset side wall 220 can protect the offset side wall 220 in the subsequent step of removing the first side wall 310 close to the source area 250, so as to prevent the offset side wall 220 close to the source area 250 in the first device area 100T from being damaged.

[0114] In this embodiment, in the first device area 100T, the step of removing the protective film 150 on the first side wall 310 close to the source area 250 includes: forming a mask layer 330 on the protective film 150, the mask layer 330 having a mask opening (not marked), and the mask opening is located above the top surface and side wall of the first side wall 310 close to the source area 250 of the first device area 100T; using the mask layer 330 as a mask, removing the protective film 150 exposed by the mask opening; and removing the mask layer 330.

[0115] The mask layer 320 is used as a mask for patterning the protective film 320 to define the shape and position of the protective layer. In this embodiment, the material of the mask layer 320 is photoresist.

[0116] In this embodiment, in order to ensure that the photolithography process for forming the mask layer 330 has a sufficient process window, during the process of forming the mask layer 330, the mask opening is also located at the top portion of the gate structure 200 of the first device region 100T close to the source region 250, and above the top of the offset sidewall 220.

[0117] Accordingly, in the process of removing the protective film 150 exposed by the mask opening using the mask layer 330 as a mask, the etching amount of the protective film 150 is controlled to ensure that while the protective film 150 on the first side wall 310 close to the source region 250 is removed, the side wall film 130 located on the top of the gate structure 200 and the top of the offset side wall 220 close to the source region 250 will not be removed.

[0118] In this embodiment, the process for removing the protective film 150 on the first sidewall spacer 310 near the source region 250 includes a wet etching process. The wet etching process has the characteristic of isotropic etching, so it is easy to remove the protective film 150 on the top surface of the sidewall spacer film 130 and the sidewall of the first sidewall spacer 310 exposed by the mask opening. The wet etching process is simple to operate and low in cost.

[0119] Specifically, the etching solution of the wet etching process may be a hydrofluoric acid solution.

[0120] In other embodiments, an isotropic dry etching process may be used to remove the protection film 150 on the first sidewall spacer 310 close to the source region 250 .

[0121] refer to Figure 19 , using the protection layer 350 as a mask, remove the first sidewall spacer 310 close to the source region 250 .

[0122] In this embodiment, during the process of forming the protective layer 350, the film layer on the top of the gate structure 200 and the offset sidewall 220 can still retain a certain thickness. The remaining film layer on the top of the gate structure 200 and the offset sidewall 220 can protect the top of the offset sidewall 220 during the step of removing the first sidewall 310 close to the source region 250, so as to prevent the offset sidewall 220 close to the source region 250 in the first device region 100T from being damaged. This is beneficial to ensuring the integrity of the offset sidewall 220 close to the source region 250, and reducing the risk of partial sidewall exposure of the gate structure 200 due to the reduction in the height of the offset sidewall 220 close to the source region 250, thereby preventing the subsequent metal silicide layer from being formed on the exposed sidewall of the gate structure 200.

[0123] In this embodiment, the process of removing the first spacer 310 on the side of the first device region 100T close to the source region 250 includes a wet etching process. In this embodiment, the material of the first spacer 310 is silicon nitride, and the etching solution of the wet etching process can be a phosphoric acid solution.

[0124] refer to Figure 20 After removing the first side wall 310 close to the source region 250, the side wall film 130 and the protective layer 350 exposed by the first side wall 310 are removed, and the remaining side wall film 130 located between the offset side wall 220 and the first side wall 310, and between the substrate 100 and the first side wall 310 is used as the second side wall 320.

[0125] After removing the first side wall 310 close to the source region 250, the side wall film 130 exposed by the first side wall 310, and the protective layer 350, the substrate 100 between the source region 250 of the first device region 100T and the offset side wall 220 is exposed, so as to facilitate the subsequent doping of the substrate 100 between the source region 250 of the first device region 100T and the offset side wall 220 to form a first lightly doped region. Accordingly, in the subsequent process of forming a metal silicide layer, a metal silicide layer can also be formed on the top surface of the first lightly doped region.

[0126] In this embodiment, the material of the protective layer 350 is the same as the material of the sidewall film 130; in the same step, the sidewall film 130 and the protective layer 350 exposed by the first sidewall 310 are removed, thereby eliminating the need for an additional step of removing the protective layer 350, simplifying the process flow and improving process integration and compatibility.

[0127] In this embodiment, a wet etching process is used to remove the spacer film 130 and the protective layer 350 exposed by the first spacer 310. The wet etching process has the characteristic of isotropic etching, which easily etches away the film layer on the structure with a stepped morphology, thereby reducing the probability of residual protective layer 350 and the spacer film 130 on the side of the first device region 100T near the source region 250. In this embodiment, the material of the spacer film 130 and the protective layer 350 is silicon oxide, and the etching solution of the wet etching process is a hydrofluoric acid solution.

[0128] refer to Figure 21 In the first device region 100T, a first lightly doped region 270 is formed in the substrate 100 between the source region 250 and the offset spacer 220 . The first lightly doped region 270 has the same doping type as the source region 250 .

[0129] The first lightly doped region 270 is used to form a junction interface with a steeper concentration gradient between the source region and the channel of the TFET device, so as to improve the performance of the TFET by utilizing the band-to-band tunneling effect.

[0130] In this embodiment, the doping depth of the first lightly doped region 270 is less than the doping depth of the source region 250 , the doping type of the first lightly doped region 270 is the same as the doping type of the TFET source region 250 , and the doping concentration of the first lightly doped region 270 is lower than the doping concentration of the source region 250 .

[0131] When forming an N-type TFET, the doping ions of the first lightly doped region 270 are P-type ions, such as B ions, Ga ions or In ions; when forming a P-type TFET, the doping ions of the first lightly doped region 270 are correspondingly N-type ions, such as P ions, As ions or Sb ions.

[0132] In this embodiment, the step of forming the first lightly doped region 270 includes: forming a fourth blocking layer (not shown) covering the drain region 260 and the second device region 100M, the fourth blocking layer exposing the substrate 100 on the side of the gate structure 200 of the first device region 100T close to the source region 250; using the fourth blocking layer as a mask, ion implantation is performed on the substrate 100 on the side of the gate structure 200 of the first device region 100T close to the source region 250 to form the first lightly doped region 270; and removing the fourth blocking layer.

[0133] The fourth shielding layer is used as a mask for ion implantation into the substrate 100 on the side of the gate structure 200 of the first device region 100T close to the source region 250. In this embodiment, the material of the fourth shielding layer is photoresist.

[0134] In this embodiment, the process of performing ion implantation on the substrate 100 on the side of the gate structure 200 of the first device region 100T close to the source region 250 is a lightly doped drain (LDD) implantation process.

[0135] In this embodiment, the fourth shielding layer is removed by using an ashing process and a wet stripping process performed sequentially.

[0136] refer to Figure 22 A metal silicide layer 340 is formed on the top surfaces of the source region 250 , the drain region 260 , the first lightly doped region 270 and the gate structure 200 .

[0137] As can be seen from the above description, the remaining film layer located on the top of the gate structure 200 and the offset sidewall 220 can protect the top of the offset sidewall 220 during the step of removing the first sidewall 310 near the source region 250, so as to prevent the offset sidewall 220 near the source region 250 in the first device region 100T from being damaged, which is beneficial to ensuring the integrity of the offset sidewall 220 near the source region 250, and reducing the risk of partial exposure of the sidewall of the gate structure 200 due to the reduction in the height of the offset sidewall 220 near the source region 250, thereby preventing the metal silicide layer 340 from forming on the exposed sidewall of the gate structure 200, and preventing the metal silicide layer 340 from affecting the electric field distribution inside the gate structure 200, and preventing the problem of short-circuiting with the metal silicide layer located on the first lightly doped region and the source region due to the metal silicide layer 340 extending along the sidewall of the gate structure 200, thereby optimizing the performance of the semiconductor structure.

[0138] In this embodiment, the metal silicide layer 340 is also formed on the top surface of the source-drain doped region 240 of the second device region 100M, thereby forming the metal silicide layer 340 on the first device region 100T and the second device region 100M in the same step, thereby improving the process integration and compatibility of forming TFET devices and MOS devices.

[0139] The metal silicide layer 340 is located on the top surface of the source region 250, the drain region 260, the gate structure 200 and the source-drain doped region 240, and is used to reduce the contact resistance between the source region 250, the drain region 260, the gate structure 200 and the source-drain doped region 240 and the corresponding contact plugs (CT).

[0140] In this embodiment, the metal silicide layer 340 is also located on the top surface of the first lightly doped region 270, and the metal silicide layer 340 is also in contact with the first lightly doped region 270, so that through the impurity segregation effect of the metal silicide and silicon, the junction interface of the first lightly doped region 270 of the TFET device is pushed toward the bottom of the gate structure 200, thereby improving the tunneling efficiency of the TFET device.

[0141] In this embodiment, the material of the metal silicide layer 340 can be nickel silicon compound, cobalt silicon compound or titanium silicon compound.

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate including a first device region for forming a tunneling field effect transistor; forming a gate structure on the substrate, wherein an offset sidewall is formed on a sidewall of the gate structure; forming a spacer film located on the top surface and sidewalls of the offset spacer, the top surface of the gate structure, and the top surface of the substrate, and forming a first spacer on the sidewall of the spacer film on the sidewall of the offset spacer; After forming the first spacer, in the first device region, a source region is formed in the substrate on one side of the gate structure, and a drain region is formed in the substrate on the other side of the gate structure, wherein the drain region and the source region have different doping types; forming a protective film conformally covering the top surface and sidewalls of the first spacer, the offset spacer, the gate structure, and the spacer film on the top surface of the substrate; In the first device region, the protective film on the first sidewall adjacent to the source region is removed, and the remaining protective film is used as a protective layer; Using the protective layer as a mask, removing the first sidewall spacer close to the source region; After removing the first sidewall spacer close to the source region, removing the sidewall spacer film and the protective layer exposed by the first sidewall spacer, and the remaining sidewall spacer film between the offset sidewall spacer and the first sidewall spacer and between the substrate and the first sidewall spacer is used as a second sidewall spacer; In the first device region, a first lightly doped region is formed in the substrate between the source region and the offset spacer, wherein the first lightly doped region has the same doping type as the source region; A metal silicide layer is formed on the source region, the drain region, the first lightly doped region and the top surface of the gate structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the substrate further includes a second device region for forming a metal oxide semiconductor field effect transistor; The method for forming the semiconductor structure further includes: forming source-drain doped regions in the substrate on both sides of the gate structure and the first spacer in the second device region after forming the first spacer and before forming the protective film; In the step of forming the metal silicide layer, the metal silicide layer is also formed on the top surface of the source and drain doped regions.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming a semiconductor structure further includes: after forming the offset spacer and before forming the spacer film, forming a second lightly doped region in the substrate on both sides of the gate structure and the offset spacer of the second device region.

4. The method for forming a semiconductor structure according to claim 2, wherein: After forming the first sidewall spacer and before forming the source region and the drain region, source and drain doped regions are formed in the substrate on both sides of the gate structure and the first sidewall spacer of the second device region.

5. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protective film is the same as that of the sidewall film; In the same step, the spacer film and the protective layer exposed by the first spacer are removed.

6. The method for forming a semiconductor structure according to claim 1 or 4, wherein: In the step of forming the protective film, the material of the protective film includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride or boron carbonitride.

7. The method for forming a semiconductor structure according to claim 1 or 4, wherein: In the step of forming the protection film, the thickness of the protection film is the same as the thickness of the sidewall film.

8. The method for forming a semiconductor structure according to claim 1, wherein: The first sidewall and the offset sidewall are made of the same material.

9. The method for forming a semiconductor structure according to claim 1 or 8, wherein: The material of the first spacer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and silicon oxycarbonitride; The material of the offset spacer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and silicon oxycarbonitride.

10. The method for forming a semiconductor structure according to claim 1, wherein: In the first device area, the step of removing the protective film on the first side wall close to the source area includes: forming a mask layer on the protective film, the mask layer having a mask opening, and the mask opening is located above the top surface and side wall of the first side wall close to the source area of the first device area; using the mask layer as a mask, removing the protective film exposed by the mask opening; and removing the mask layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the protective film on the first sidewall adjacent to the source region includes a wet etching process.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first sidewall spacer on the side of the first device region close to the source region includes a wet etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the spacer film and the protective layer exposed by the first spacer includes a wet etching process.

14. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The gate layer is made of polysilicon or amorphous silicon.

Images