Method for evaluating thermal stability of doped regions in semiconductor devices

Abstract

The present invention discloses a method for evaluating the thermal stability of a doped region of a semiconductor device, comprising: Step 1, providing a chip sample on which the fabrication of a first doped region that needs to be analyzed for thermal stability is completed. Step 2, forming a first protective layer by an electron beam assisted deposition process, and setting the material of the first protective layer and the electron beam energy parameters of the electron beam assisted deposition process to ensure that electrons can enter the surface of the semiconductor substrate and generate a thermal effect on the first doped region to form a first defect. Step 3, using FIB to perform ion beam milling to form a TEM sample. Step 4, analyzing the TEM results of the TEM sample to obtain the morphology of the first defect and evaluating it. The present invention does not need to evaluate the thermal stability of the doped region through electrical aging tests, but can directly evaluate the thermal stability of the doped region by observing the defects formed by thermal damage in the doped region.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for evaluating the thermal stability of a doped region of a semiconductor device. Background Art

[0002] As the size of semiconductor devices becomes smaller and smaller, the thermal stability of semiconductor devices has important reference significance for the failure analysis of semiconductor devices. Generally, the industry evaluates the thermal stability of semiconductor devices by means of electrical aging tests on finished devices. Rarely is it judged through the morphological analysis of semiconductor devices during the processing.

[0003] The Transmission Electron Microscope (TEM) plays an increasingly important role in the morphological analysis of semiconductor devices due to its high resolution and high precision characteristics. The preparation of TEM samples is generally carried out using a Focused Ion Beam (FIB).

[0004] The focus of the existing TEM sample preparation technology is to try to avoid the influence of the condition parameters during the preparation of TEM samples on the samples, so as to avoid artificial defects (artifacts) confusing the influence of the sample preparation conditions and the process itself on the observation results. In addition to FIB cutting, the FIB equipment can also implement a deposition process, and the deposition process includes electron beam (E-Beam) assisted deposition and ion beam (I-Beam) deposition. The electron beam assisted deposition is realized in the E-Beam mode, and the ion beam deposition is realized in the I-Beam mode. The FIB sample preparation process for a conventional TEM sample is to first perform an electron beam assisted deposition process in the electron beam mode to deposit a protective layer in the target area, and then deposit a thin film protective layer in the ion beam mode. The size of the protective layer is determined according to the actual size of the sample. However, the TEM results obtained under the conventional sample preparation conditions generally cannot show some potential weak points in the lightly doped drain (LDD) region of the device, and it is difficult to evaluate the thermal stability problem of the semiconductor device through TEM morphological analysis. For example, Figure 1 shown is a TEM photo of a TEM sample formed by the existing TEM sample preparation method; Figure 1 The area corresponding to the dotted circle 101 in is the formation area of the LDD region. It can be seen that there are no obvious defects in the dotted circle 101. Therefore, it is difficult to evaluate the thermal stability problem of the LDD region of the semiconductor device through the surface morphological analysis of the semiconductor device during the processing. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for evaluating the thermal stability of a doped region of a semiconductor device, which can directly evaluate the thermal stability of the doped region by observing the defects formed by the thermal stability of the doped region, rather than evaluating the thermal stability of the semiconductor device through an electrical aging test.

[0006] To solve the above technical problem, the method for evaluating the thermal stability of a doped region of a semiconductor device provided by the present invention includes the following steps:

[0007] Step 1: Provide a chip sample, on which the first doped region that needs to be analyzed for thermal stability of the semiconductor device is fabricated on a semiconductor substrate; the first doped region is located in the surface region of the semiconductor substrate, and a target region for forming a TEM sample is selected on the chip sample according to the first doped region.

[0008] Step 2: Form a first protective layer by an electron beam assisted deposition process, and the first protective layer covers at least the surface of the target region; the material of the first protective layer and the electron beam energy parameters of the electron beam assisted deposition process are set to ensure that the electrons of the electron beam assisted deposition process can enter the surface of the semiconductor substrate, and the energy of the electrons entering the surface of the semiconductor substrate is used to generate a thermal effect on the first doped region and generate defects that can evaluate the thermal stability of the first doped region.

[0009] Step 3: Use FIB to perform ion beam milling on the target region in the chip sample to form a TEM sample with a required thickness.

[0010] Step 4: Analyze the TEM results of the TEM sample to obtain the morphology of the first defect, and evaluate the thermal stability of the first doped region according to the morphology of the first defect.

[0011] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0012] A further improvement is that the semiconductor device includes a MOS transistor.

[0013] A further improvement is that the first doped region includes the lightly doped drain region of the MOS transistor.

[0014] A further improvement is that the MOS transistor includes NMOS and PMOS.

[0015] A further improvement is that the structure of the MOS transistor includes: a gate structure, a source region, and a drain region.

[0016] A further improvement is that the lightly doped drain region is self-aligned with the side of the gate structure.

[0017] A spacer is also formed on the side surface of the gate structure, and the source region and the drain region are located on both sides of the gate structure and are self-aligned with the corresponding spacer.

[0018] A further improvement is that in step one, the gate structure, the source region, and the drain region are fabricated on the semiconductor substrate.

[0019] A further improvement is that an interlayer film is also fabricated on the semiconductor substrate, and the interlayer film covers the surfaces of the gate structure, the source region, and the drain region.

[0020] A further improvement is that the material of the first protective layer includes C.

[0021] A further improvement is that the electron beam energy parameters of the electron beam assisted deposition process include: an acceleration voltage greater than 2 kV and a current higher than 3.2 nA.

[0022] A further improvement is that in step two, after forming the first protective layer, forming a second protective layer by an ion beam deposition process is further included.

[0023] The second protective layer covers the first protective layer and extends to the surface of the chip sample outside the first protective layer.

[0024] A further improvement is that the material of the second protective layer includes C.

[0025] A further improvement is that in step one, the thickness of the chip sample is 500 nm or more.

[0026] A further improvement is that in step three, the minimum thickness of the formed TEM sample reaches 100 nm or less.

[0027] A further improvement is that in step two, the thickness of the first protective layer is several hundred nm to several microns.

[0028] A further improvement is that in step two, the electron beam assisted deposition is realized in a FIB device.

[0029] The present invention utilizes the means that when forming the first protective layer on the surface of the chip sample during the preparation of the TEM sample, the electron beam relies on the conversion of electrical energy into heat energy for processing to achieve that when the high-energy electron beam penetrates the protective layer and interacts with the semiconductor substrate, an energy exchange thermal effect is generated between the electron beam and the sample atoms, so as to heat the first doping region that needs to be evaluated for thermal stability and make the first defects in the first doping region appear. After completing the preparation of the TEM sample, analyzing the TEM results can directly observe the defect morphology formed by thermal damage in the first doping region, and thus the thermal stability of the first doping region can be directly evaluated through the defect morphology.

[0030] By setting the electron beam energy parameters of the first protective layer and the electron beam assisted deposition process, the present invention can inject electrons with sufficient energy into the surface of the semiconductor substrate, thereby realizing the heating of the first doped region. Therefore, the present invention can well achieve and adjust the energy of the high-energy electron beam processing of the first doped region, thereby adjusting the size of the first defect in the first doped region, which is further beneficial to the evaluation of the thermal stability of the first doped region.

[0031] Since the present invention does not require electrical aging testing, it does not need to analyze the finished semiconductor devices. Instead, it can be analyzed at any time after the formation of the first doped region until the completion of the production of the semiconductor device. Therefore, the present invention can realize the evaluation of the thermal stability of the first doped region during the processing of the semiconductor device, which is beneficial to the early discovery of problems related to the thermal stability of the first doped region.

[0032] The first doped region of the present invention is particularly suitable for the lightly doped drain region of MOS transistors. Brief Description of the Drawings

[0033] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0034] Figure 1 is a TEM photograph of a TEM sample formed by the existing TEM sample preparation method;

[0035] Figure 2 is a flowchart of the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0036] Figures 3A - 3C is a structural diagram of a chip sample in each step of the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0037] Figure 4 is a TEM photograph of a TEM sample prepared by the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0038] Figure 5A is a first TEM photograph of a TEM sample formed by the existing TEM sample preparation method under the first electron beam assisted deposition parameter conditions;

[0039] Figure 5B is a second TEM photograph of a TEM sample formed by the existing TEM sample preparation method under the first electron beam assisted deposition parameter conditions;

[0040] Figure 6A is a first TEM photograph of a TEM sample formed by the existing TEM sample preparation method under the second electron beam assisted deposition parameter conditions;

[0041] Figure 6B It is the second TEM photo of the TEM sample formed under the conditions of the second electron beam assisted deposition parameters adopted by the existing TEM sample preparation method;

[0042] Figure 7A It is the first TEM photo of the TEM sample formed under the conditions of the first electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0043] Figure 7B It is the second TEM photo of the TEM sample formed under the conditions of the first electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0044] Figure 8A It is the first TEM photo of the TEM sample formed under the conditions of the second electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0045] Figure 8B It is the second TEM photo of the TEM sample formed under the conditions of the second electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0046] Figure 9A It is the first TEM photo of the TEM sample formed under the conditions of the third electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0047] Figure 9B It is the second TEM photo of the TEM sample formed under the conditions of the third electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0048] Figure 10A It is the first TEM photo of the TEM sample formed under the conditions of the fourth electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention;

[0049] Figure 10B It is the second TEM photo of the TEM sample formed under the conditions of the fourth electron beam assisted deposition parameters in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention. Detailed implementation manners

[0050] As Figure 2 shown, it is the flowchart of the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention; As Figures 3A to 3CAs shown, it is the structural diagram of the chip sample 201 in each step of the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention; the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention includes the following steps:

[0051] Step 1: As Figure 3A shown, provide a chip sample 201, on which the fabrication of the first doped region that needs to be analyzed for thermal stability of the semiconductor device is completed on the semiconductor substrate of the chip sample 201; the first doped region is located in the surface region of the semiconductor substrate, and a target region for forming a TEM sample is selected on the chip sample 201 according to the first doped region.

[0052] In an embodiment of the present invention, the semiconductor substrate includes a silicon substrate.

[0053] The semiconductor device includes a MOS transistor.

[0054] The first doped region includes the lightly doped drain region of the MOS transistor.

[0055] The MOS transistor includes NMOS and PMOS.

[0056] The structure of the MOS transistor includes: a gate structure, a source region, and a drain region.

[0057] The lightly doped drain region is self-aligned with the side of the gate structure.

[0058] A spacer is further formed on the side of the gate structure, and the source region and the drain region are located on both sides of the gate structure and are self-aligned with the corresponding spacers.

[0059] In some embodiments, after the formation process of the lightly doped drain region is completed, the fabrication of the gate structure, the source region, and the drain region is also completed on the semiconductor substrate.

[0060] The fabrication of an interlayer dielectric is also completed on the semiconductor substrate, and the interlayer dielectric covers the surfaces of the gate structure, the source region, and the drain region.

[0061] In some embodiments, the thickness of the chip sample 201 is 500 nm or more.

[0062] The chip sample 201 is obtained by performing an ion beam milling and thinning process on a wafer composed of the semiconductor substrate.

[0063] Step 2: As Figure 3AAs shown, a first protective layer 202 is formed by an electron beam assisted deposition process, and the first protective layer 202 covers at least the surface of the target area; the material of the first protective layer 202 and the electron beam energy parameters of the electron beam assisted deposition process are set to ensure that the electrons of the electron beam assisted deposition process can enter the surface of the semiconductor substrate, and the energy of the electrons entering the surface of the semiconductor substrate is used to thermally act on the first doped region and generate defects capable of evaluating the thermal stability of the first doped region.

[0064] In an embodiment of the present invention, the material of the first protective layer 202 includes C.

[0065] The electron beam assisted deposition is implemented in a FIB device.

[0066] The electron beam energy parameters of the electron beam assisted deposition process include: the acceleration voltage is greater than 2 kV, and the current is higher than 3.2 nA.

[0067] In some embodiments, the thickness of the first protective layer 202 is several hundred nm to several microns.

[0068] In some embodiments, as Figure 3B shown, after forming the first protective layer 202, a second protective layer 203 is further formed by an ion beam deposition process.

[0069] The second protective layer 203 covers the first protective layer 202 and extends to the surface of the chip sample 201 outside the first protective layer 202.

[0070] The material of the second protective layer 203 includes C.

[0071] Figure 3C also shows the cross-sectional structure after forming the second protective layer 203.

[0072] Step 3: Use FIB to perform ion beam cutting on the target area in the chip sample 201 to form a TEM sample with a required thickness.

[0073] In some embodiments, the minimum thickness of the formed TEM sample reaches below 100 nm.

[0074] Step 4: Perform TEM result analysis on the prepared TEM sample to obtain the morphology of the first defect, and evaluate the thermal stability of the first doped region according to the morphology of the first defect. That is: In Step 4 of the embodiments of the present invention, TEM result analysis is performed on the prepared TEM sample. During the electron beam processing, high-energy electron beams are likely to penetrate the first protective layer 202 and cause thermal effects at the semiconductor substrate such as a silicon substrate, thereby increasing the generation of defects. The thermal stability of the first doped region is evaluated according to the morphology of the defects caused by the electron thermal effects.

[0075] As Figure 4 shown, it is a TEM photo of the TEM sample prepared in the method for evaluating the thermal stability of the doped region of a semiconductor device according to the embodiments of the present invention; Figure 4 The area corresponding to the virtual dotted circle 103 in the figure is the formation area of the LDD region. It can be seen that there are defect morphologies in the virtual dotted circle 103. Therefore, the thermal stability problem of the semiconductor device can be evaluated by analyzing the defect morphologies.

[0076] In the embodiments of the present invention, during the preparation of the TEM sample, when forming the first protective layer 202 on the surface of the chip sample 201, the electron beam relies on the conversion of electrical energy into heat energy for processing to achieve the penetration of the high-energy electron beam through the protective layer and the interaction with the semiconductor substrate, resulting in an energy exchange thermal effect with the sample atoms, thereby heating the first doped region that needs to be evaluated for thermal stability and making the first defect in the first doped region appear. After completing the preparation of the TEM sample, performing TEM result analysis can directly observe the defect morphology formed by thermal damage in the first doped region, and thus the thermal stability of the first doped region can be directly evaluated through the defect morphology.

[0077] By setting the electron beam energy parameters of the first protective layer 202 and the electron beam assisted deposition process in the present invention, sufficient energy electrons can be injected into the surface of the semiconductor substrate, thereby achieving the heating of the first doped region. Therefore, the present invention can well achieve and well adjust the energy of the high-energy electron beam processing of the first doped region, thereby adjusting the size of the first defect in the first doped region, which is further beneficial to the evaluation of the thermal stability of the first doped region.

[0078] Since the embodiments of the present invention do not require electrical aging tests, the present invention does not need to analyze the finished semiconductor device, but can be analyzed at any time after the formation of the first doped region until the completion of the production of the semiconductor device. Therefore, the embodiments of the present invention can evaluate the thermal stability of the first doped region during the processing of the semiconductor device, which is beneficial to early discovery of problems related to the thermal stability of the first doped region.

[0079] The first doped region of the embodiments of the present invention is particularly suitable for the lightly doped drain region of a MOS transistor.

[0080] To further illustrate the differences between the TEM samples formed by the method of the embodiments of the present invention and those formed by the existing method, the following is a comparative description through the photos of TEM samples prepared under various TEM sample preparation parameters:

[0081] As Figure 5A shown, it is the first TEM photo of the TEM sample formed by the existing TEM sample preparation method under the first electron beam assisted deposition parameter conditions; as Figure 5B shown, it is the second TEM photo of the TEM sample formed by the existing TEM sample preparation method under the first electron beam assisted deposition parameter conditions; the existing first electron beam assisted deposition parameter conditions are:

[0082] The material of the protective layer formed by electron beam assisted deposition is Pt;

[0083] The electron beam energy parameters of electron beam assisted deposition are: the acceleration voltage is greater than 2 kV and the current is higher than 3.2 nA.

[0084] Figure 5A The areas shown by the dashed boxes 101a on both sides of the gate structure 301 in

[0085] Figure 5B are the formation areas of the LDD regions. It can be seen that there are no obvious defects in the LDD regions.

[0086] As Figure 6A shown, it is the first TEM photo of the TEM sample formed by the existing TEM sample preparation method under the second electron beam assisted deposition parameter conditions; as Figure 6B shown, it is the second TEM photo of the TEM sample formed by the existing TEM sample preparation method under the second electron beam assisted deposition parameter conditions; the existing second electron beam assisted deposition parameter conditions are:

[0087] The material of the protective layer formed by electron beam assisted deposition is Pt;

[0088] The electron beam energy parameters of electron beam assisted deposition are: the acceleration voltage is greater than 5 kV and the current is higher than 3.2 nA.

[0089] Figure 6A The areas shown by the dashed box 101b in

[0090] Figure 6B are the formation areas of the LDD regions. It can be seen that there are no obvious defects in the LDD regions.

[0091] As shown in Figure 7A FIG. 1 is TEM photo 1 of the TEM sample formed under the first electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention; as shown in Figure 7B FIG. 2 is TEM photo 2 of the TEM sample formed under the first electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention; the first electron beam assisted deposition parameter conditions of the method according to the embodiment of the present invention are as follows:

[0092] The material of the first protective layer formed by electron beam assisted deposition is C;

[0093] The electron beam energy parameters of the electron beam assisted deposition are: the acceleration voltage is greater than 2 kV and the current is higher than 3.2 nA.

[0094] Figure 7A The area shown by the dashed box 102a on both sides of the gate structure 301 in FIG. 1 is the formation area of the LDD region. It can be seen that the LDD region has potential defects.

[0095] Figure 7B It also shows the film layer 302 formed on the gate structure 301 and the first protective layer 304a formed by the C layer.

[0096] As shown in Figure 8A FIG. 3 is TEM photo 1 of the TEM sample formed under the second electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention; as shown in Figure 8B FIG. 4 is TEM photo 2 of the TEM sample formed under the second electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device according to an embodiment of the present invention; the second electron beam assisted deposition parameter conditions of the method according to the embodiment of the present invention are as follows:

[0097] The material of the first protective layer formed by electron beam assisted deposition is C;

[0098] The electron beam energy parameters of the electron beam assisted deposition are: the acceleration voltage is greater than 5 kV and the current is higher than 3.2 nA.

[0099] Figure 8A The area shown by the dashed box 102b on both sides of the gate structure 301 in FIG. 3 is the formation area of the LDD region. It can be seen that obvious defects appear in the LDD region.

[0100] Figure 8B It also shows the film layer 302 formed on the gate structure 301 and the first protective layer 304b formed by the C layer.

[0101] As shown in Figure 9AAs shown, it is TEM Photo 1 of the TEM photo of the TEM sample formed under the third electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device in an embodiment of the present invention; as Figure 9B As shown, it is TEM Photo 2 of the TEM photo of the TEM sample formed under the third electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device in an embodiment of the present invention; the third electron beam assisted deposition parameter conditions of the method in the embodiment of the present invention are:

[0102] The material of the first protective layer formed by electron beam assisted deposition is C;

[0103] The electron beam energy parameters of the electron beam assisted deposition are: the acceleration voltage is greater than 2 kV and the current is higher than 13 nA.

[0104] Figure 9A The area shown by the dashed box 102c on both sides of the gate structure 301 in [the figure] is the formation area of the LDD region. It can be seen that obvious defects appear in the LDD region.

[0105] Figure 9B It also shows the film layer 302 formed on the gate structure 301 and the first protective layer 304c formed by the C layer.

[0106] As Figure 10A As shown, it is TEM Photo 1 of the TEM photo of the TEM sample formed under the fourth electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device in an embodiment of the present invention; as Figure 10B As shown, it is TEM Photo 2 of the TEM photo of the TEM sample formed under the fourth electron beam assisted deposition parameter conditions in the method for evaluating the thermal stability of the doped region of a semiconductor device in an embodiment of the present invention; the fourth electron beam assisted deposition parameter conditions of the method in the embodiment of the present invention are:

[0107] The material of the first protective layer formed by electron beam assisted deposition is C;

[0108] The electron beam energy parameters of the electron beam assisted deposition are: the acceleration voltage is greater than 5 kV and the current is higher than 13 nA.

[0109] Figure 10A The area shown by the dashed box 102a on both sides of the gate structure 301 in [the figure] is the formation area of the LDD region. It can be seen that obvious defects appear in the LDD region.

[0110] Figure 10B It also shows the film layer 302 formed on the gate structure 301 and the first protective layer 304d formed by the C layer.

[0111] As can be seen from the above, the method of the embodiment of the present invention can make the defects in the LDD region appear in the TEM photo. The basic principle is as follows: In the general process of preparing a TEM sample, since electron beam processing relies on the conversion of electrical energy into thermal energy for processing, when a high-energy electron beam penetrates the protective layer and interacts with a semiconductor substrate such as a silicon substrate, an energy exchange will occur between the electron beam and the sample atoms. Most of the energy will be converted into heat and remain in the sample, causing the local temperature of the sample to rise. The higher the temperature, the greater the thermal damage to the target area of the sample. At the same time, as the atomic number of the sample increases, the maximum penetration depth decreases. In the existing conventional TEM sample preparation, plating a Pt protective layer causes most electrons to be rebounded and it is not easy to penetrate to the substrate, resulting in an electron beam thermal effect. However, plating a C thin film protective layer will make the electron beam penetration depth greater, and the electron beam is more likely to penetrate down and cause a thermal effect at the silicon substrate, thereby increasing the generation of defects.

[0112] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for evaluating the thermal stability of a doped region of a semiconductor device, characterized in that, The method includes the following steps: Step 1: Provide a chip sample on which the fabrication of a first doped region of a semiconductor device that needs to be subjected to thermal stability analysis is completed on a semiconductor substrate; the first doped region is located in the surface region of the semiconductor substrate, and a target region for forming a TEM sample is selected on the chip sample according to the first doped region; Step 2: Form a first protective layer by an electron beam assisted deposition process, and the first protective layer covers at least the surface of the target region; the material of the first protective layer and the electron beam energy parameters of the electron beam assisted deposition process are set to ensure that the electrons of the electron beam assisted deposition process can enter the surface of the semiconductor substrate, and the energy of the electrons entering the surface of the semiconductor substrate is used to generate a thermal effect on the first doped region and generate a first defect capable of evaluating the thermal stability of the first doped region; Step 3: Use FIB to perform ion beam milling on the target region in the chip sample to form a TEM sample with a required thickness; Step 4: Perform TEM result analysis on the TEM sample to obtain the morphology of the first defect, and evaluate the thermal stability of the first doped region according to the morphology of the first defect.

2. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.

3. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 2, wherein: The semiconductor device includes a MOS transistor.

4. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 3, wherein: The first doped region includes the lightly doped drain region of the MOS transistor.

5. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 3, characterized in that: The MOS transistor includes NMOS and PMOS.

6. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 4, characterized in that: The structure of the MOS transistor includes: a gate structure, a source region, and a drain region.

7. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 6, wherein: The lightly doped drain region is self-aligned with the side of the gate structure; A spacer is further formed on the side of the gate structure, and the source region and the drain region are located on both sides of the gate structure and are self-aligned with the corresponding spacers.

8. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 6, characterized in that: In Step 1, the fabrication of the gate structure, the source region, and the drain region is completed on the semiconductor substrate.

9. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 8, wherein: The fabrication of an interlayer dielectric film is also completed on the semiconductor substrate, and the interlayer dielectric film covers the surfaces of the gate structure, the source region, and the drain region.

10. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 1, wherein: The material of the first protective layer includes C.

11. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 10, characterized in that: The electron beam energy parameters of the electron beam assisted deposition process include: an acceleration voltage greater than 2 kV and a current higher than 3.2 nA.

12. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 1, characterized in that: In Step 2, after forming the first protective layer, it further includes forming a second protective layer by an ion beam deposition process; The second protective layer covers the first protective layer and extends to the surface of the chip sample outside the first protective layer.

13. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 12, characterized in that: The material of the second protective layer includes C.

14. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 1, wherein: In Step 1, the thickness of the chip sample is 500 nm or more.

15. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 1, characterized in that: In Step 3, the minimum thickness of the formed TEM sample reaches 100 nm or less.

16. The method for evaluating the thermal stability of a doped region of a semiconductor device according to claim 1, characterized in that: In Step 2, the electron beam assisted deposition is implemented in an FIB device.

Images