A radiation-resistant power semiconductor device with a voltage-dividing layer

Abstract

The present invention discloses a semiconductor device, wherein the semiconductor device comprises an intermediate layer and a voltage-dividing layer between a voltage-resistant layer and a bottom region, wherein the intermediate layer plays a role of cutting off the electric field, and the voltage-dividing layer plays a role of bearing an external voltage when the semiconductor device is in a cut-off state and is irradiated by high-energy particles, thereby avoiding dynamic avalanche breakdown of the voltage-resistant layer. The semiconductor device has radiation resistance and high reliability.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, in particular to power semiconductor devices. Background Art

[0002] Power semiconductor devices are widely used in power conversion. When used in space and high-altitude environments, power semiconductor devices will be exposed to cosmic rays. For power semiconductor devices, single-particle failure is an important radiation failure mechanism. Silicon power semiconductor devices have been used in space and high-altitude environments, and their radiation-resistant design has a certain degree of maturity, but there is still room for improvement. The single-particle failure problem of wide-bandgap power semiconductor devices is more serious. For example, under a reverse bias voltage higher than 30% of the rated breakdown voltage, silicon carbide power semiconductor devices will degrade or even fail when hit by particles. Power semiconductor devices generally need to improve their radiation resistance to meet the needs of applications in irradiated environments. Summary of the invention

[0003] The object of the present invention is to provide a radiation-resistant power semiconductor device. Compared with ordinary power semiconductor devices, the radiation-resistant power semiconductor device provided by the present invention can very effectively suppress single particle failure.

[0004] refer to Figure 1-7 The present invention provides a semiconductor device, whose cell structure includes: at least one top region 30, at least one voltage-resistant layer (20, or 21 and 22), at least one middle layer 12 and at least one bottom region 40, characterized in that:

[0005] The bottom plane of the top area 30 is in direct contact with the top plane of the voltage-resistant layer (20, or 21 and 22), the bottom plane of the voltage-resistant layer (20, or 21 and 22) is in direct contact with the top plane of the intermediate layer 12, and at least one voltage-dividing layer 11 is contained between the intermediate layer 12 and the bottom area 40; at least a portion of the bottom plane of the bottom area 40 is in direct contact with the first conductor 1, and at least a portion of the top plane of the top area 30 is in direct contact with the second conductor 2;

[0006] The voltage-resistant layer (20, or 21 and 22) is composed of a drift region 20 of the first conductivity type or a super junction region (21 and 22), and the super junction region (21 and 22) is composed of a columnar region 21 of the first conductivity type and a columnar region 22 of the second conductivity type alternately arranged in a horizontal direction; the doping type of the intermediate layer 12 and the voltage-dividing layer 11 are both the first conductivity type; the top region 30 is composed of a semiconductor material of the first conductivity type and / or a semiconductor material of the second conductivity type; the bottom region 40 is composed of a semiconductor material of the first conductivity type and / or a semiconductor material of the second conductivity type;

[0007] The voltage-dividing layer 11 is in direct contact with the middle layer 12 or is in indirect contact with the middle layer 12 through a first connection area 13, and the voltage-dividing layer 11 is in direct contact with the bottom area 40 or is in indirect contact with the bottom area 40 through a second connection area 14; when there are two or more voltage-dividing layers 11 in the cell structure, two adjacent voltage-dividing layers 11 are in indirect contact with each other through a third connection area 15; the doping types of the first connection area 13, the second connection area 14 and the third connection area 15 are all the first conductive type; the average doping concentrations of the first connection area 13, the second connection area 14 and the third connection area 15 are higher than the average doping concentration of the voltage-dividing layer 11;

[0008] The cellular structure contains at least one deep trench dielectric region 50 extending from the top plane of the semiconductor device to the inside, or does not contain the deep trench dielectric region 50; the depth of the deep trench dielectric region 50 is within the range from the top plane of the voltage-resistant layer (20, or 21 and 22) to the bottom plane of the bottom region 40.

[0009] refer to Figure 6 The second conductor 2 extends from the top plane of the deep trench dielectric region 50 downward into the deep trench dielectric region 50 to form a field plate structure.

[0010] Reference Figure 7 The voltage-dividing layer (11 and 16) contains at least one fourth connection area 16, the top plane of the fourth connection area 16 is flush with the top plane of the voltage-dividing layer (11 and 16), and the bottom plane of the fourth connection area 16 is flush with the bottom plane of the voltage-dividing layer (11 and 16); the doping type of the fourth connection area 16 is the first conductive type, and the average doping concentration of the fourth connection area 16 is higher than the average doping concentration of the voltage-dividing layer (11 and 16).

[0011] refer to Figure 8 The intermediate layer 12 is composed of a layer of uniformly doped semiconductor material or multiple layers of uniformly doped semiconductor material; the first connection area 13, the second connection area 14 and the third connection area 15 are composed of a layer of uniformly doped semiconductor material or multiple layers of uniformly doped semiconductor material.

[0012] refer to Figure 9-13 , the semiconductor device contains PiN diode cells and / or Schottky diode cells and / or junction barrier Schottky diode cells and / or hybrid PiN Schottky diode cells;

[0013] The bottom region 40 is composed of a first heavily doped semiconductor region 41 of the first conductivity type, and the first conductor 1 is in direct contact with the first heavily doped semiconductor region 41 of the first conductivity type to form an ohmic contact and is connected to the cathode K;

[0014] In the PiN diode cell, the top region 30 is composed of a first heavily doped semiconductor region 31 of the second conductivity type, and the second conductor 2 is in direct contact with the first heavily doped semiconductor region 31 of the second conductivity type to form an ohmic contact and is connected to the anode A;

[0015] In the Schottky diode cell, the top region 30 has the same doping type and doping concentration as the drift region 20 of the first conductivity type or the column region 21 of the first conductivity type, so as to be connected to the drift region 20 of the first conductivity type or the column region 21 of the first conductivity type to form the same region; the second conductor 2 is in direct contact with the drift region 20 of the first conductivity type or the column region 21 of the first conductivity type to form a Schottky contact and is connected to the anode A;

[0016] In the junction barrier Schottky diode cell and the hybrid PiN Schottky barrier diode cell, the top region 30 is composed of a first heavily doped second conductivity type semiconductor region 31, the first heavily doped second conductivity type semiconductor region 31 is isolated into multiple regions by the first conductivity type drift region 20 or the first conductivity type column region 21, the second conductor 2 is in direct contact with the first conductivity type drift region 20 or the first conductivity type column region 21 to form a Schottky contact and is connected to the anode A, and the second conductor 2 is in direct contact with the first heavily doped second conductivity type semiconductor region 31 to form an ohmic contact and is connected to the anode A.

[0017] refer to Fig.14 , the semiconductor device contains bipolar junction transistor cells and / or thyristor cells;

[0018] The top region 30 is composed of a first second conductivity type base region 32, wherein the first second conductivity type base region 32 contains at least one second heavily doped second conductivity type semiconductor region 33, the first second conductivity type base region 32 is in direct contact with at least one second heavily doped first conductivity type semiconductor region 34, the second conductor 2 is in direct contact with the second heavily doped second conductivity type semiconductor region 33 to form an ohmic contact and is connected to the base B, and the top plane of the second heavily doped first conductivity type semiconductor region 34 is covered with a third conductor 3 to form an ohmic contact and is connected to the low potential electrode E.

[0019] In the bipolar junction transistor cell, the bottom region 40 is composed of a first heavily doped semiconductor region 41 of the first conductivity type, and the first conductor 1 is in direct contact with the first heavily doped semiconductor region 41 of the first conductivity type to form an ohmic contact and is connected to a high potential electrode C;

[0020] In the thyristor cell, the bottom region 40 is composed of a collector region 42 of a second conductivity type and a buffer region 43 of a first conductivity type, the bottom plane of the buffer region 43 of the first conductivity type is in direct contact with the top plane of the collector region 42 of the second conductivity type, and the bottom plane of the collector region 42 of the second conductivity type is in direct contact with the first conductor 1 to form an ohmic contact and is connected to the high potential electrode C.

[0021] refer to Figure 15-18 , the semiconductor device contains metal-oxide-semiconductor field effect transistor cells and / or insulated gate bipolar transistor cells;

[0022] The top region 30 is composed of a second base region 35 of the second conductivity type, wherein the second base region 35 of the second conductivity type contains at least one semiconductor region 37 of the third heavily doped second conductivity type, the second base region 35 of the second conductivity type is in direct contact with at least one semiconductor region 36 of the third heavily doped first conductivity type, and the second conductor 2 is in direct contact with the third heavily doped semiconductor region 37 of the second conductivity type and the third heavily doped semiconductor region 36 of the first conductivity type to form an ohmic contact and be connected to a low potential electrode (S or E);

[0023] The cell structure contains at least one gate structure (51 and 4), the gate structure (51 and 4) is composed of a gate insulating dielectric layer 51 and a gate conductor region 4, and the gate structure (51 and 4) is a planar gate structure or a trench gate structure; the gate insulating dielectric layer 51 is in direct contact with the drift region 20 of the first conductivity type or the columnar region 21 of the first conductivity type, and is in direct contact with the base region 35 of the second conductivity type and the semiconductor region 37 of the third heavily doped first conductivity type; the gate conductor region 4 is in direct contact with the gate insulating dielectric layer 51, and is separated from the drift region 20 of the first conductivity type, the columnar region 21 of the first conductivity type, the base region 35 of the second conductivity type and the semiconductor region 36 of the third heavily doped first conductivity type by the gate insulating dielectric layer 51; the gate conductor region 4 is composed of heavily doped polycrystalline semiconductor material and / or metal conductor material, and the gate conductor region 4 is connected to the gate G;

[0024] In the metal-oxide-semiconductor field effect transistor cell, the bottom region 40 is composed of a first heavily doped semiconductor region 41 of the first conductivity type, and the first conductor 1 is in direct contact with the first heavily doped semiconductor region 41 of the first conductivity type to form an ohmic contact and is connected to a high potential electrode D;

[0025] In the insulated gate bipolar transistor cell, the bottom region 40 is composed of a collector region 42 of a second conductivity type and a buffer region 43 of a first conductivity type, the bottom plane of the buffer region 43 of the first conductivity type is in direct contact with the top plane of the collector region 42 of the second conductivity type, and the bottom plane of the collector region 42 of the second conductivity type is in direct contact with the first conductor 1 to form an ohmic contact and is connected to the high potential electrode C.

[0026] refer to Figure 1-18 The semiconductor material used in the semiconductor device is silicon or silicon carbide or gallium nitride or gallium oxide or diamond or gallium arsenide. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 (a): A semiconductor device of the present invention comprises a voltage-dividing layer, wherein the voltage-withstanding layer is composed of a drift region;

[0028] Figure 1 (b): Another semiconductor device of the present invention comprises a voltage-dividing layer, wherein the voltage-withstanding layer is formed by a super junction region;

[0029] Figure 2 (a): Another semiconductor device of the present invention, wherein a first connection region is provided between the intermediate layer and the voltage dividing layer;

[0030] Figure 2 (b): Another semiconductor device of the present invention has a second connection region between the bottom region and the voltage dividing layer;

[0031] Figure 3 (a): Another semiconductor device of the present invention comprises two voltage-dividing layers, and a third connection region is provided between the two voltage-dividing layers;

[0032] Figure 3 (b): Another semiconductor device of the present invention comprises three voltage-dividing layers, and a third connection region is provided between two adjacent voltage-dividing layers;

[0033] Figure 4 (a): Another semiconductor device of the present invention comprises a deep trench dielectric region, the deep trench dielectric region extending deep into the drift region;

[0034] Figure 4 (b): Another semiconductor device of the present invention comprises a deep trench dielectric region, the deep trench dielectric region extends deep into the middle layer;

[0035] Figure 5 (a): Another semiconductor device of the present invention comprises a deep trench dielectric region, the deep trench dielectric region extends deep into the voltage dividing layer;

[0036] Figure 5(b): Another semiconductor device of the present invention comprises a deep trench dielectric region, the deep trench dielectric region extending deep into the bottom region;

[0037] Figure 6 (a): According to Figure 5 (a) In another semiconductor device of the present invention, the second conductor extends deep into the deep trench dielectric region and extends deep into the drift region;

[0038] Figure 6 (b): According to Figure 5 (b) In another semiconductor device of the present invention, the second conductor extends deep into the deep trench dielectric region and extends as deep as the voltage dividing layer;

[0039] Figure 7 : according to Figure 3 (a), another semiconductor device of the present invention, wherein the voltage dividing layer has a fourth connection region;

[0040] Figure 8 (a): According to Figure 1 (a), Schematic diagram of the doping distribution of the middle layer, which has three uniformly doped regions;

[0041] Figure 8 (b): According to Figure 2 (b) Schematic diagram of doping distribution of the second connection region, where the second connection region has two layers of uniformly doped regions;

[0042] Fig. 9 (a): According to Figure 1 (a) A further semiconductor device of the present invention comprises a PiN diode cell;

[0043] Fig. 9 (b): According to Figure 5 (a) A semiconductor device according to the present invention comprises a PiN diode cell and a deep trench dielectric region;

[0044] Fig.10 (a): According to Figure 1 (a) A semiconductor device according to the present invention, comprising a Schottky diode cell;

[0045] Fig.10 (b): According to Figure 5 (a) A semiconductor device according to the present invention comprises a Schottky diode cell and a deep trench dielectric region;

[0046] Fig.11 (a): According to Figure 1 (a) A semiconductor device according to the present invention comprises a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell;

[0047] Fig.11 (b): According to Figure 1 (b) A semiconductor device according to the present invention comprises a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell;

[0048] Fig.12 (a): According to Figure 5 (a) Another semiconductor device of the present invention comprises a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell, wherein the deep trench dielectric region passes through the first heavily doped second conductivity type semiconductor region;

[0049] Fig.12 (b): According to Figure 5 (a) Another semiconductor device of the present invention comprises a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell, wherein the deep trench dielectric region does not pass through the first heavily doped second conductivity type semiconductor region;

[0050] Fig.13 (a): According to Figure 1 (b) Another semiconductor device of the present invention comprises a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell, and comprises a deep trench dielectric region passing through a columnar region of the second conductivity type;

[0051] Fig.13 (b): According to Figure 1 (b) Another semiconductor device of the present invention comprises a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell, and comprises a deep trench dielectric region passing through a columnar region of the first conductivity type;

[0052] Fig.14 (a): According to Figure 1 (a) A semiconductor device according to the present invention comprises a bipolar junction transistor cell;

[0053] Fig.14 (b): According to Figure 5 (a) A further semiconductor device of the present invention comprises a thyristor cell;

[0054] Fig.15 (a): According to Figure 1 (a) Another semiconductor device of the present invention comprises a metal-oxide-semiconductor field effect transistor cell and adopts a planar gate structure;

[0055] Fig.15 (b): According to Figure 5(a) Another semiconductor device of the present invention comprises a metal-oxide-semiconductor field effect transistor cell, adopts a planar gate structure, and the deep trench dielectric region does not pass through the second second conductivity type base region;

[0056] Fig.16 (a): According to Figure 1 (a) Another semiconductor device of the present invention comprises a metal-oxide-semiconductor field effect transistor cell and adopts a trench gate structure;

[0057] Fig.16 (b): According to Figure 5 (a) Another semiconductor device of the present invention comprises a metal-oxide-semiconductor field effect transistor cell, adopts a trench gate structure, and a deep trench dielectric region passes through a second base region of a second conductivity type;

[0058] Fig.17 (a): According to Figure 1 (b) A semiconductor device according to the present invention comprises a metal-oxide-semiconductor field effect transistor cell and adopts a planar gate structure;

[0059] Fig.17 (b): According to Figure 1 (b) Another semiconductor device of the present invention comprises a metal-oxide-semiconductor field effect transistor cell and adopts a trench gate structure;

[0060] Fig.18 (a): According to Figure 1 (a) A semiconductor device according to the present invention comprises an insulated gate bipolar transistor cell;

[0061] Fig.18 (b): According to Figure 1 (a) Another semiconductor device of the present invention comprises both a metal-oxide-semiconductor field effect transistor cell and an insulated gate bipolar transistor cell;

[0062] Fig.19 : Fig.11 (a) Transient current of the junction barrier Schottky diode of the present invention and the ordinary junction barrier Schottky diode during single particle incidence I R Compare waveforms;

[0063] Fig. 20 : Fig.11 (a) The maximum internal temperature of the junction barrier Schottky diode of the present invention and the ordinary junction barrier Schottky diode during the single particle incident process T Compare waveforms. DETAILED DESCRIPTION

[0064] The present invention is described in detail below with reference to the accompanying drawings.

[0065] Generally, single-particle failures of power semiconductor devices are mainly single-particle burnout and single-particle gate punchout. Both single-particle burnout and single-particle gate punchout usually occur when the device is in a blocking state (or cut-off state) and is hit by high-energy particles. Single-particle burnout is caused by the generation of a large number of electrons and holes by high-energy particles, which triggers a dynamic avalanche effect in the voltage-withstand layer and ultimately leads to thermal failure. It can occur in any type of power semiconductor device. Single-particle gate punchout is caused by the generation of a large number of electrons and holes by high-energy particles, which causes carrier accumulation at the interface between the gate oxide dielectric layer and the semiconductor, raises the potential, and causes the breakdown failure of the gate oxide dielectric layer. It occurs in power semiconductor devices with an insulated gate, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

[0066] Figure 1 (a) is a typical structure of the power semiconductor device of the present invention, wherein the voltage-resistant layer adopts the drift region (n-drift region 20) of the first conductivity type (n-type). The top region (top region 30) is composed of the semiconductor material of the first conductivity type (n-type) and / or the semiconductor material of the second conductivity type (p-type), which is used to ensure that the device can be normally blocked. The possible composition is Figure 9-18 The bottom region (bottom region 40) is composed of a semiconductor material of the first conductivity type (n-type) and / or a semiconductor material of the second conductivity type (p-type), and its possible composition is given in Figure 9-18 Different combinations of the top region (top region 30) and the bottom region (bottom region 40) can present different types of power semiconductor devices. However, different power semiconductor devices will use the same withstand voltage structure. Figure 1 Taking (a) as an example, the withstand voltage structure is the drift region (n-drift region 20) of the first conductivity type (n-type), the middle layer (middle layer 12) of the first conductivity type (n-type) and the voltage divider layer (n-divider layer 11) of the first conductivity type (n-type). Therefore, Figure 1 (a) covers various types of power semiconductor devices including a drift region (n-drift region 20), an intermediate layer (middle layer 12) and a voltage divider layer (n-divider layer 11). Figure 1 (b) and Figure 2-5 It also covers various types of power semiconductor devices.

[0067] Compared with ordinary power semiconductor devices, Figure 1The notable feature of (a) is the presence of a voltage divider layer (n-divider layer 11), which is used to improve the single-particle failure resistance of power semiconductor devices. In the static blocking state, the drift region (n-drift region 20) is depleted by the external bias, and the middle layer (n-middle region 12) acts as a cutoff electric field, so the voltage divider layer (n-divider layer 11) is not voltage-resistant. When high-energy particles are incident from the top plane of the device to the inside, the depth of most high-energy particles will be lower than the depth of the drift region (n-drift region 20). Therefore, high-energy particles will generate a large number of electrons and holes inside the drift region (n-drift region 20), where electrons will move downward and holes will move upward.

[0068] For ordinary power semiconductor devices (without a voltage divider layer (n-divider layer 11)), the positive charge concentration at the top of the drift region (n-drift region 20) will increase, thereby increasing the electric field at the top of the drift region (n-drift region 20) to induce dynamic avalanche breakdown, and when the negative charge concentration at the bottom of the drift region (n-drift region 20) increases to exceed its doping concentration, a high electric field will also be formed in the bottom region of the drift region (n-drift region 20) to induce dynamic avalanche breakdown. In fact, the dynamic avalanche breakdown in the top region of the drift region (n-drift region 20) has a self-recovery effect, because the holes generated by the dynamic avalanche will be quickly pumped upward, and the dynamically generated electrons can help reduce the concentration of positive charges and thus weaken the electric field. However, when dynamic avalanche breakdown also occurs at the bottom of the drift region (n-drift region 20), electrons generated from the dynamic avalanche at the top of the drift region (n-drift region 20) will increase the electric field at the bottom of the drift region (n-drift region 20), while holes generated by the dynamic avalanche at the bottom of the drift region (n-drift region 20) will increase the electric field at the top of the drift region (n-drift region 20), which leads to the continued maintenance of dynamic avalanche breakdown, thereby triggering thermal failure, that is, single particle burning.

[0069] for Figure 1(a), the doping concentration and thickness of the voltage divider layer (n-divider layer 11) can be the same as or close to the doping concentration and thickness of the drift region (n-drift region 20). When high-energy particles are incident on the drift region (n-drift region 20) to generate a large number of electrons and holes, the resistance of the drift region (n-drift region 20) will be instantly reduced, and its resistance will be much lower than the resistance of the voltage divider layer (n-divider layer 11). Therefore, the voltage divider layer (n-divider layer 11) will also be instantly subjected to the effect of the applied voltage, thereby directly reducing the electric field of the drift region (n-drift region 20), avoiding the occurrence of dynamic avalanche breakdown in the drift region (n-drift region 20), thereby avoiding single-particle burnout, and also avoiding single-particle gate penetration (because the drift region (n-drift region 20) is almost not subjected to an applied voltage). Furthermore, in the most extreme case (high-energy particles penetrate the entire device), although a large number of electrons and holes will be generated in the voltage divider layer (n-divider layer 11), at the moment of high-energy particle incidence, the voltage divider layer (n-divider layer 11) does not bear voltage, there is no high electric field inside, and the voltage divider layer (n-divider layer 11) will not experience dynamic avalanche, while the drift region (n-drift region 20) will experience dynamic avalanche, which means that the resistance of the drift region (n-drift region 20) will still be lower than the resistance of the voltage divider layer (n-divider layer 11), and the voltage divider layer can still play a role in sharing most of the external voltage. In addition, if the thickness of the middle layer (n-middle region 12) is increased, it can effectively prevent high-energy particles from entering the voltage divider layer (n-divider layer 11), eliminating the impact of high-energy particles on the voltage divider layer (n-divider layer 11).

[0070] exist Figure 1 (b) and Figure 1 The main difference between (a) and (b) is that the voltage-resistant layer uses a super junction region (n-pillar region 21 and p-pillar region 22). Under the same thickness, if the doping concentrations of the first conductive type columnar region (n-pillar region 21) and the drift region (n-drift region 20) are equal, the voltage-resistant layer using the super junction region (n-pillar region 21 and p-pillar region 22) can have a higher breakdown voltage than the drift region (n-drift region 20), so the former can obtain a better compromise relationship between the on-state voltage drop and the breakdown voltage than the latter.

[0071] exist Figure 2 (a), with Figure 1The main difference of (a) is that there is a first connection region (n-con1 region 13) of the first conductivity type (n-type) between the middle layer (n-middle region 12) and the voltage divider layer (n-divider layer 11). The functions of the first connection region (n-con1 region 13) are: first, to reduce the lattice and stress mismatch between the middle layer (n-middle region 12) and the voltage divider layer (n-divider layer 11), and the means can be that the doping concentration of the first connection region (n-con1 region 13) is between the doping concentrations of the middle layer (n-middle region 12) and the voltage divider layer (n-divider layer 11); second, to increase the distance between the voltage divider layer (n-divider layer 11) and the top plane of the device to prevent the high-energy particles incident from the top of the device from affecting the voltage divider layer (n-divider layer 11); third, to play the role of conducting current with low resistance.

[0072] exist Figure 2 (b) and Figure 1 The main difference of (a) is that there is a second connection area (n-con2 area 14) of the first conductivity type (n-type) between the bottom area (bottom area 40) and the voltage dividing layer (n-divider layer 11). The functions of the second connection area (n-con2 area 14) are: first, to reduce the lattice and stress mismatch between the bottom area (bottom area 40) and the voltage dividing layer (n-divider layer 11), and the means can be that the doping concentration of the second connection area (n-con2 area 14) is between the doping concentrations of the bottom area (bottom area 40) and the voltage dividing layer (n-divider layer 11); second, to increase the distance between the voltage dividing layer (n-divider layer 11) and the bottom plane of the device to prevent the high-energy particles incident from the bottom of the device from affecting the voltage dividing layer (n-divider layer 11); third, to play the role of conducting current with low resistance.

[0073] exist Figure 3 (a), with Figure 1 The main difference of (a) is that there are two voltage divider layers (n-divider layer 11), and there is a third connection area (n-con3 area 15) of the first conductivity type (n type) between the two voltage divider layers. Figure 1 The explanation of (a) is easy to understand. Multiple voltage divider layers (n-divider layer 11) are beneficial to improving the ability to resist single particle failure. The functions of the third connection area (n-con3 area 15) are: first, to increase the distance between a certain voltage divider layer (n-divider layer 11) and the top plane or bottom plane of the device to prevent high-energy particles incident from the top or bottom of the device from affecting the voltage divider layer (n-divider layer 11); second, to play the role of conducting current with low resistance.

[0074] exist Figure 3 (b) and Figure 1 The main difference of (a) is that there are three voltage divider layers (n-divider layer 11).

[0075] exist Figure 4 (a), with Figure 1 The main difference between (a) and (b) is that there is a deep trench dielectric region (50), and the deep trench dielectric region (50) extends deep into the drift region (n-drift region 20). When the deep trench dielectric region (50) extends deep into the interior, the electrons generated in the drift region (n-drift region 20) will flow relatively concentratedly toward the voltage divider layer (n-divider layer 11) during the downward movement, so that the cross-sectional area of ​​the electrons flowing through the voltage divider layer can be reduced, the resistance of the voltage divider layer (n-divider layer 11) through which the electron current flows increases, the voltage drop (i.e., the applied voltage) of the voltage divider layer (n-divider layer 11) will be greater, and the voltage divider effect will be more obvious.

[0076] exist Figure 4 (b) and Figure 4 The main difference between (a) and (b) is that the deep trench dielectric region (50) extends deep into the middle layer (n-middle layer 12). Figure 4 (a) Similar.

[0077] exist Figure 5 (a), with Figure 4 The main difference between (a) and (b) is that the deep trench dielectric region (50) extends deep into the voltage divider layer (n-divider layer 11). Figure 4 (a) Similar.

[0078] exist Figure 5 (b) and Figure 4 The main difference between (a) and (b) is that the deep trench dielectric region (50) extends deep into the bottom region (bottom region 40). Figure 4 (a) Similar.

[0079] exist Figure 6 (a), with Figure 5 The main difference between (a) and (b) is that the second conductor (2) penetrates deep into the deep trench dielectric region (50), and the depth of the second conductor (2) is between the top plane and the bottom plane of the drift region (n-drift region 50). The second conductor (2) acts as a field plate, which can effectively modulate the electric field of the drift region (n-drift region 50) and improve the dynamic avalanche breakdown voltage.

[0080] exist Figure 6 (b) and Figure 5The main difference between (b) and (c) is that the second conductor (2) penetrates into the deep trench dielectric region (50), and the depth of the second conductor (2) is between the top plane and the bottom plane of the voltage divider layer (n-divider layer 11). The second conductor (2) plays the role of a field plate, and can effectively modulate the electric field of the voltage divider layer (n-divider layer 11), thereby improving the dynamic avalanche breakdown voltage.

[0081] exist Figure 7 In, with Figure 3 The main difference of (a) is that there is a fourth connection region (n-con4 region 16) of the first conductivity type (n-type) in the voltage divider layer (n-divider layer 11). The fourth connection region (n-con4 region 16) plays the role of conducting current with low resistance. Figure 7 In the embodiment, the fourth connection areas (n-con4 area 16) in the two voltage-dividing layers (n-divider layer 11) are staggered in the vertical direction, that is, there is only one fourth connection area (n-con4 area 16) on the same vertical line. The advantage of this is that when conducting current normally, most of the current is conducted from the low-resistance fourth connection area (n-con4 area 16), which is conducive to reducing the on-state resistance; in the blocking state, if high-energy particles penetrate the entire device along a vertical line passing through a fourth connection area (n-con4 area 16), at least one voltage-dividing layer (n-divider layer 11) can be guaranteed to bear the external voltage.

[0082] exist Figure 8 In (a), the middle layer (n-middle layer 12) has three uniformly doped regions, wherein the doping concentration of the two regions where the middle layer (n-middle layer 12) contacts the drift region (n-drift region 20) and the voltage divider layer (n-divider layer 11) is lower than the middle region of the middle layer (n-middle layer 12), but higher than the doping concentration of the drift region (n-drift region 20) and the voltage divider layer (n-divider layer 11). The purpose is to reduce the lattice and stress mismatch between the middle layer (n-middle layer 12) and the drift region (n-drift region 20) and the voltage divider layer (n-divider layer 11) caused by the doping concentration difference while ensuring low resistance.

[0083] exist Figure 8In (b), the second connection region (n-con2 region 14) has two uniformly doped regions, wherein the doping concentration of the region in contact with the voltage divider layer (n-divider layer 11) is lower than that of the region in contact with the bottom region (bottom region 40). The purpose is to reduce the lattice and stress mismatch between the second connection region (n-con2 region 14) and the voltage divider layer (n-divider layer 11) and the bottom region (bottom region 40) caused by the doping concentration difference while ensuring low resistance.

[0084] Figure 9-18 Given Figure 1-8 The semiconductor device of the present invention may contain Figure 9-18 Any one or more of the cellular structures shown.

[0085] exist Fig. 9 (a), with Figure 1 (a) In comparison, the top region (top region 30) is composed of a semiconductor region (1p + The bottom region (bottom region 40) is composed of a first heavily doped semiconductor region (1n+ region 41) of the first conductivity type (n-type), forming a PiN diode cell.

[0086] exist Fig. 9 (b) and Figure 8 The main difference of (a) is that it contains a deep groove dielectric region (50).

[0087] exist Fig.10 (a), with Figure 1 Compared with (a), the top region (top region 30) has the same doping as the drift region (n-drift region 20), so it is connected to the drift region (n-drift region 20) as the same region, the bottom region (bottom region 40) is composed of a first heavily doped first conductivity type (n-type) semiconductor region (1n+ region 41), and the second conductor (2) forms a Schottky contact with the drift region (n-drift region 20) to form a Schottky diode cell.

[0088] exist Fig.10 (b) and Fig.10 The main difference of (a) is that it contains a deep groove dielectric region (50).

[0089] exist Fig.11 (a), with Figure 1 (a) Compared with the top region (top region 30), the top region (top region 30) is composed of a plurality of semiconductor regions (1p +The bottom region (bottom region 40) is composed of a semiconductor region (1n+ region 41) of the first heavily doped first conductivity type (n-type), and the second conductor (2) forms a Schottky contact with the drift region (n-drift region 20) to form a junction barrier Schottky diode cell or a hybrid PiN Schottky diode cell. It should be noted that when the two semiconductor regions (1p + When the distance between the first and second conductive types (p-type) semiconductor regions (1p + The PN junction formed by the first heavily doped semiconductor region (1p 31) and the drift region (n-drift region 20) is called a hybrid PiN Schottky diode; on the contrary, when the two semiconductor regions (1p + When the distance between the first heavily doped semiconductor region (1p + The conduction of the PN junction formed by the n-drift region (region 31) and the drift region (n-drift region 20) is called a junction barrier Schottky diode.

[0090] exist Fig.11 (b) and Fig.11 The main difference of (a) is that its voltage-resistant layer uses a super junction region (n-pillar region 21 and p-pillar region 22).

[0091] exist Fig.12 (a) and Fig.12 (b) and Fig.11 The main difference of (a) is that it contains a deep groove dielectric region (50). Fig.12 The deep trench dielectric region (50) of (a) passes through the first heavily doped second conductivity type (p-type) semiconductor region (1p + 31 District), and Fig.12 The deep trench dielectric region (50) of (b) does not pass through the first heavily doped second conductivity type (p-type) semiconductor region (1p + Area 31).

[0092] exist Fig.13 (a) and Fig.13 (b) and Fig.11 The main difference of (b) is that it contains a deep groove dielectric region (50). Fig.13 The deep trench dielectric region (50) of (a) passes through the first heavily doped second conductivity type (p-type) semiconductor region (1p + 31 District), and Fig.13The deep trench dielectric region (50) of (b) does not pass through the first heavily doped second conductivity type (p-type) semiconductor region (1p + Area 31).

[0093] exist Fig.14 (a), with Figure 1 (a) Compared with the above, the top region (top region 30) is composed of a first base region (p-b1 region 32) of the second conductivity type (p-type), a second heavily doped semiconductor region (2p+ region 33) of the second conductivity type (p-type) and a second heavily doped semiconductor region (2n+ region 34) of the first conductivity type (n-type), and the bottom region (bottom region 40) is composed of a first heavily doped semiconductor region (1n+ region 41) of the first conductivity type (n-type), forming a bipolar transistor cell.

[0094] exist Fig.14 (b) and Fig.14 The main difference of (a) is that the bottom region (bottom region 40) is composed of a collector region (p-collector region 42) of the second conductivity type (p-type) and a buffer region (n-buffer region 43) of the first conductivity type (n-type), and contains a deep trench dielectric region (50).

[0095] In 15(a), Figure 1 (a) Compared with the top region (top region 30), the top region (top region 30) is composed of a second base region (p-b2 region 35) of the second second conductivity type (p type), and there is also a third heavily doped semiconductor region of the second conductivity type (p type) (3p+ region 37) and a third heavily doped semiconductor region of the first conductivity type (n type) (3n+ region 36), and the bottom region (bottom region 40) is composed of a first heavily doped semiconductor region of the first conductivity type (n type) (1n+ region 41), contains a planar gate structure (51 and 4), and forms a metal-oxide-semiconductor field effect transistor cell.

[0096] exist Fig.15 (b) and Fig.15 The main difference of (a) is that it contains a deep groove dielectric region (50).

[0097] exist Fig.16 (a), with Fig.15 The main difference of (a) is that a trench gate structure (51 and 4) is used.

[0098] exist Fig.16 (b) and Fig.16 The main difference of (a) is that it contains a deep groove dielectric region (50).

[0099] exist Fig.17 (a), with Fig.15The main difference of (a) is that its voltage-resistant layer uses a super junction region (n-pillar region 21 and p-pillar region 22).

[0100] exist Fig.17 (b) and Fig.16 The main difference of (a) is that its voltage-resistant layer uses a super junction region (n-pillar region 21 and p-pillar region 22).

[0101] exist Fig.18 (a), with Fig.16 The main difference of (a) is that its bottom region (bottom region 40) is composed of a collector region (p-collector region 42) of the second conductivity type (p-type) and a buffer region (n-buffer region 43) of the first conductivity type (n-type), forming an insulated gate bipolar transistor cell.

[0102] exist Fig.18 (b) and Fig.18 The main difference between (a) and (b) is that it also contains Fig.16 (b) shows a metal-oxide-semiconductor field-effect transistor cell. Fig.18 (b), it is also easy for technicians familiar with the art to obtain Figure 9-18 A semiconductor device with two or more cell structures as shown. For example, Fig. 9 (a) and Fig.15 (a) shows two kinds of semiconductor devices with cell structures, including 14 (a) and Fig.15 (a) shows two types of semiconductor devices with cellular structures, etc.

[0103] Figure 1-18 The device of the present invention shown can use different types of semiconductor materials, not only the most commonly used silicon, but also silicon carbide (4H-SiC, 6H-SiC, 3C-SiC), gallium nitride, gallium oxide, diamond, gallium arsenide, etc.

[0104] In order to illustrate the advantages of the present invention, the present invention utilizes Fig.11 (a) The structure is simulated and compared with the common structure, where the common structure refers to the Figure 1 (a) The structure without the voltage divider layer (n-divider layer 11) is used in the simulation. Fig.11 (a) Multiple cells of the structure (width 328.3 μm); 4H-SiC material is used; the first heavily doped semiconductor region of the second conductivity type (1p + The junction depth and doping concentration of region 31 are 0.68 μm and 1×10 19 cm -3The thickness and doping concentration of the drift region (n-drift region 20) are 8.8 μm and 9.1×10 15 cm -3 The thickness and doping concentration of the middle layer (n-middle layer 12) are 50 μm and 1×10 19 cm -3 The thickness and doping concentration of the voltage divider layer (n-divider layer 11) are 20 μm and 9.1×10 15 cm -3 The thickness and doping concentration of the first heavily doped semiconductor region of the first conductivity type (1n+ region 41) are 130 μm and 1×10 19 cm -3 ; The barrier height of the Schottky contact is set to 1.27 eV; The incident heavy ion used in the single particle incident simulation is 70 MeV irradiation energy, and the linear energy transfer value (LET value) is 37.2 MeV cm 2 / mg Ge particles, the incident depth is 12.98 μm and the track width is 0.48 μm. Fig.11 (a) The voltage divider layer (n-divider layer 11) is eliminated from the structural basis, and the other parameters (including single particle incident simulation parameters) remain unchanged.

[0105] Fig.19 and Fig. 20 The given ones are Fig.11 (a) Transient current of the junction barrier Schottky diode of the present invention and the ordinary junction barrier Schottky diode during single particle incidence I R and maximum body temperature T Compare the waveforms. It can be seen from the figure that the current peak value of the junction barrier Schottky diode of the present invention after single particle incident is 0.048 A, which is 63% lower than that of the ordinary junction barrier Schottky diode. The maximum temperature peak value of the junction barrier Schottky diode of the present invention after single particle incident is 549 K, which is 68% lower than that of the ordinary junction barrier Schottky diode. It can be seen that the present invention has a significant advantage of radiation resistance.

[0106] In fact, the fundamental reason for the radiation-resistant property of the present invention is that it has excellent dynamic avalanche resistance. Therefore, the semiconductor device of the present invention not only has radiation-resistant properties, but also has excellent high-voltage shutdown capability and high-current shutdown capability. Therefore, the semiconductor device of the present invention cannot be classified only as a radiation-resistant semiconductor device, but should also be classified as a high-reliability semiconductor device.

[0107] The present invention has been described in many embodiments above, wherein the n-type semiconductor material described therein can be regarded as a semiconductor material of the first conductivity type, and the p-type semiconductor material can be regarded as a semiconductor material of the second conductivity type. Obviously, according to the principle of the present invention, the n-type and p-type in the embodiments can be interchanged with each other without affecting the content of the present invention. For those skilled in the art, many other embodiments can also be obtained under the concept of the present invention without exceeding the claims of the present invention.

Claims

1. A semiconductor device, the cell structure of which comprises: at least one top zone, a pressure-resistant layer, an intermediate layer and a bottom zone, characterized in that The bottom plane of the top region is in direct contact with the top plane of the voltage-resistant layer, the bottom plane of the voltage-resistant layer is in direct contact with the top plane of the middle layer, and at least one voltage-dividing layer is included between the middle layer and the bottom region; at least a portion of the bottom plane of the bottom region is in direct contact with the first conductor, and at least a portion of the top plane of the top region is in direct contact with the second conductor; The voltage-resistant layer is composed of a drift region of the first conductivity type or a super junction region, and the super junction region is composed of columnar regions of the first conductivity type and columnar regions of the second conductivity type arranged alternately in the horizontal direction; the doping types of the middle layer and the voltage-dividing layer are both the first conductivity type; the top region is composed of a semiconductor material of the first conductivity type and / or a semiconductor material of the second conductivity type; the bottom region is composed of a semiconductor material of the first conductivity type and / or a semiconductor material of the second conductivity type; The voltage-dividing layer is in direct contact with the middle layer or is in indirect contact with the middle layer through a first connection area, and the voltage-dividing layer is in direct contact with the bottom area or is in indirect contact with the bottom area through a second connection area; when there are two or more voltage-dividing layers in the cell structure, two adjacent voltage-dividing layers are in indirect contact with each other through a third connection area; the doping types of the first connection area, the second connection area and the third connection area are all of the first conductive type; the average doping concentrations of the first connection area, the second connection area and the third connection area are higher than the average doping concentration of the voltage-dividing layer; The cell structure contains at least one deep trench dielectric region extending from the top plane of the semiconductor device to the inside or does not contain the deep trench dielectric region; the depth of the deep trench dielectric region is within the range from the top plane of the voltage-resistant layer to the bottom plane of the bottom region.

2. The semiconductor device according to claim 1, wherein The second conductor extends from the top plane of the deep trench dielectric region downward into the deep trench dielectric region to form a field plate structure.

3. The semiconductor device according to claim 1, wherein The voltage-dividing layer contains at least one fourth connection area, the top plane of the fourth connection area is flush with the top plane of the voltage-dividing layer, and the bottom plane of the fourth connection area is flush with the bottom plane of the voltage-dividing layer; the doping type of the fourth connection area is the first conductive type, and the average doping concentration of the fourth connection area is higher than the average doping concentration of the voltage-dividing layer.

4. The semiconductor device according to claim 1, wherein The intermediate layer is composed of a layer of uniformly doped semiconductor material or multiple layers of uniformly doped semiconductor material; the first connection region, the second connection region and the third connection region are composed of a layer of uniformly doped semiconductor material or multiple layers of uniformly doped semiconductor material.

5. The semiconductor device according to claim 1, wherein: The semiconductor device contains PiN diode cells and / or Schottky diode cells and / or junction barrier Schottky diode cells and / or mixed PiN Schottky diode cells; The bottom region is composed of a first heavily doped semiconductor region of the first conductivity type, and the first conductor is in direct contact with the first heavily doped semiconductor region of the first conductivity type to form an ohmic contact and is connected to the cathode; In the PiN diode cell, the top region is composed of a first heavily doped semiconductor region of the second conductivity type, and the second conductor is in direct contact with the first heavily doped semiconductor region of the second conductivity type to form an ohmic contact and is connected to an anode; In the Schottky diode cell, the top region has the same doping type and doping concentration as the drift region of the first conductivity type or the column region of the first conductivity type, so as to be connected with the drift region of the first conductivity type or the column region of the first conductivity type to form the same region; the second conductor directly contacts the drift region of the first conductivity type or the column region of the first conductivity type to form a Schottky contact and is connected to the anode; In the junction barrier Schottky diode cell and the hybrid PiN Schottky barrier diode cell, the top region is composed of a first heavily doped second conductivity type semiconductor region, the first heavily doped second conductivity type semiconductor region is isolated into multiple regions by the first conductivity type drift region or the first conductivity type column region, the second conductor is in direct contact with the first conductivity type drift region or the first conductivity type column region to form a Schottky contact and is connected to the anode, and the second conductor is in direct contact with the first heavily doped second conductivity type semiconductor region to form an ohmic contact and is connected to the anode.

6. The semiconductor device according to claim 1, wherein: The semiconductor device contains bipolar junction transistor cells and / or thyristor cells; The top region is composed of a first base region of the second conductivity type, the first base region of the second conductivity type contains at least one second heavily doped semiconductor region of the second conductivity type, the first base region of the second conductivity type is in direct contact with at least one second heavily doped semiconductor region of the first conductivity type, the second conductor is in direct contact with the second heavily doped semiconductor region of the second conductivity type to form an ohmic contact and is connected to the base, and the top plane of the second heavily doped semiconductor region of the first conductivity type is covered with a third conductor to form an ohmic contact and is connected to a low potential electrode; In the bipolar junction transistor cell, the bottom region is composed of a first heavily doped semiconductor region of the first conductivity type, and the first conductor is in direct contact with the first heavily doped semiconductor region of the first conductivity type to form an ohmic contact and is connected to a high potential electrode; In the thyristor cell, the bottom region is composed of a collector region of a second conductivity type and a buffer region of a first conductivity type, the bottom plane of the buffer region of the first conductivity type is in direct contact with the top plane of the collector region of the second conductivity type, and the bottom plane of the collector region of the second conductivity type is in direct contact with the first conductor to form an ohmic contact and is connected to the high potential electrode.

7. The semiconductor device according to claim 1, wherein: The semiconductor device contains metal-oxide-semiconductor field effect transistor cells and / or insulated gate bipolar transistor cells; The top region is composed of a second base region of the second conductivity type, the second base region of the second conductivity type contains at least one semiconductor region of the second conductivity type that is heavily doped with a third type, the second base region of the second conductivity type is in direct contact with at least one semiconductor region of the first conductivity type that is heavily doped with a third type, and the second conductor is in direct contact with both the third semiconductor region of the second conductivity type and the third semiconductor region of the first conductivity type to form an ohmic contact and is connected to a low potential electrode; The cell structure contains at least one gate structure, the gate structure is composed of a gate insulating dielectric layer and a gate conductor region, and the gate structure is a planar gate structure or a trench gate structure; the gate insulating dielectric layer is in direct contact with the drift region of the first conductivity type or the columnar region of the first conductivity type, and is in direct contact with the base region of the second conductivity type and the semiconductor region of the third heavily doped first conductivity type; the gate conductor region is in direct contact with the gate insulating dielectric layer, and is separated from the drift region of the first conductivity type, the columnar region of the first conductivity type, the base region of the second conductivity type and the semiconductor region of the third heavily doped first conductivity type by the gate insulating dielectric layer; the gate conductor region is composed of heavily doped polycrystalline semiconductor material and / or metal conductor material, and the gate conductor region is connected to the gate; In the metal-oxide-semiconductor field effect transistor cell, the bottom region is composed of a first heavily doped semiconductor region of the first conductivity type, and the first conductor is in direct contact with the first heavily doped semiconductor region of the first conductivity type to form an ohmic contact and is connected to a high potential electrode; In the insulated gate bipolar transistor cell, the bottom region is composed of a collector region of a second conductivity type and a buffer region of a first conductivity type, the bottom plane of the buffer region of the first conductivity type is in direct contact with the top plane of the collector region of the second conductivity type, and the bottom plane of the collector region of the second conductivity type is in direct contact with the first conductor to form an ohmic contact and is connected to the high potential electrode.

8. The semiconductor device according to claim 1, wherein The semiconductor material used in the semiconductor device is silicon or silicon carbide or gallium nitride or gallium oxide or diamond or gallium arsenide.

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