A low-capacitance array transient voltage suppressor and a method of manufacturing the same

Abstract

This invention provides a low-capacitance array transient voltage suppressor and its manufacturing method. Multiple preset regions, from left to right, are: a first preset region, a second preset region, a third preset region, a fourth preset region, and a fifth preset region. The third preset region includes a first P-type well region formed on an epitaxial layer, and two segmented doped regions formed within the first P-type well region. Each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region. The fifth N+ regions and the fourth P+ regions are arranged along the depth direction. The dielectric layer includes contact holes corresponding to each segmented doped region and the fourth N+ region within the third preset region. The coverage area of ​​the contact holes above the segmented doped regions involves each fifth N+ region and the fourth P+ region within the segmented doped region. This provides a TVS device with small or no quick-return, lower on-resistance, and lower clamping voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor protection devices, and more particularly to a low-capacitance array TVS device and its manufacturing method. Background Technology

[0002] A transient voltage suppressor (TVS) is a diode that uses the reverse breakdown characteristic of a PN junction to clamp and shunt inrush current, thereby suppressing and eliminating instantaneous voltage in a circuit system to achieve a protective function. It features fast response and high instantaneous overcurrent capability. In engineering, TVS diodes are commonly used in signal ports, switching power supplies, and other fields to effectively reduce high-voltage pulses generated by lightning strikes or inductive components during circuit switching, preventing damage to equipment and ensuring the safety of people and property.

[0003] With the rapid development of technology, integrated circuits are constantly evolving towards lower voltage, lower power consumption, and higher speed transmission, placing higher performance demands on corresponding TVS protection devices. The first requirement is low capacitance, because a capacitor acts as a filter during signal transmission. Excessive capacitance can cause signal attenuation, leading to data loss. For high-speed signal ports such as USB 3.0 and HDMI 2.0, the current capacitance requirement is less than 0.5pF. Another requirement is a low clamping voltage. A lower clamping voltage effectively protects subsequent ICs from electrostatic discharge (ESD) damage. The industry generally uses the snapback characteristic of NPN transistors to reduce the clamping voltage. However, if the snapback voltage is lower than the operating voltage, it will damage the subsequent IC system.

[0004] In the product family of low-capacitance ESD protection devices, there are both unidirectional or bidirectional discrete ESD devices based on a single device structure, as well as multi-line protection low-capacitance ESD array chips based on a device network. These products are commonly used for high-speed ESD protection for ports with many pins, and are a general-purpose product widely used for multi-pin protection of USB and HDMI interfaces. Because these ports have many pins, using unidirectional or bidirectional ESD devices would occupy a large board area; therefore, low-capacitance array chips are a good ESD solution. Thus, for TVS products at signal ports, a low-capacitance, low-quick-back or non-quick-back array TVS product needs to be designed for electrostatic discharge protection. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a low-capacitance array transient voltage suppressor and its manufacturing method, aiming to provide a TVS device with small or even no transient return to provide electrostatic discharge (ESD) protection for semiconductor chips, especially suitable for ESD protection chips for high-speed signal ports.

[0006] A low-capacitance array transient voltage suppressor, comprising:

[0007] Substrate;

[0008] The epitaxial layer is formed on the substrate, and the conductivity type of the epitaxial layer is different from that of the substrate.

[0009] Multiple preset regions are isolated by isolation structures. The multiple preset regions are arranged from left to right as follows: first preset region, second preset region, third preset region, fourth preset region and fifth preset region.

[0010] An isolation structure, which extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer and into the substrate;

[0011] The first preset region and the fifth preset region respectively include a first P+ region, a first N+ region and a second P+ region formed in the epitaxial layer;

[0012] The second and fourth preset regions sequentially include a second N+ region, a third P+ region, and a third N+ region formed within the epitaxial layer, respectively.

[0013] The third preset region includes: a first P-type well region formed on the epitaxial layer, a second P-type well region formed within the first P-type well region, a fourth N+ region formed within the second P-type well region, and two segmented doped regions formed within the first P-type well region; the two segmented doped regions are located on the left and right sides of the second P-type well region, respectively.

[0014] Each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region, with the fifth N+ region and the fourth P+ region arranged along the depth direction.

[0015] A dielectric layer is formed on the upper surface of the epitaxial layer. The dielectric layer includes contact holes for each P+ region and N+ region corresponding to the first preset region, the second preset region, the fourth preset region, and the fifth preset region, as well as contact holes for each segmented doped region and the fourth N+ region corresponding to the third preset region.

[0016] The coverage of the contact holes above the segmented doped regions extends to each of the fifth N+ region and the fourth P+ region within the segmented doped regions.

[0017] Multiple metal layers are formed in each contact hole.

[0018] Furthermore, it also includes a buried layer formed on the upper surface of the substrate, with the isolation structure extending longitudinally from the upper surface of the epitaxial layer through the epitaxial layer, the buried layer, and into the substrate.

[0019] Further, it further includes: a third P-type well region, which is respectively formed in the epitaxial layers within the first preset region and the fifth preset region, and the first P+ region, the first N+ region, and the second P+ region are formed within the third P-type well region.

[0020] Further, the area ratio of the P+ region and the N+ region contained in the segmented doping region is 1:1;

[0021] Among them, there are four fourth P+ regions and three fifth N+ regions in the segmented doping region, and the four fourth P+ regions and the three fifth N+ regions are arranged alternately in the transverse direction and the depth direction.

[0022] Further, the area ratio of the P+ region and the N+ region contained in the segmented doping region is 3:1;

[0023] Among them, there are two fourth P+ regions and one fifth N+ region in the segmented doping region, and the two fourth P+ regions and the one fifth N+ region are arranged alternately in the transverse direction and the depth direction; the width of each fourth P+ region in the depth direction is greater than the width of the fifth N+ region in the depth direction.

[0024] Further, the area ratio of the P+ region and the N+ region contained in the segmented doping region is 10:1;

[0025] Among them, there are two fourth P+ regions and one fifth N+ region in the segmented doping region, and the two fourth P+ regions and the one fifth N+ region are arranged alternately in the transverse direction and the depth direction; the width of each fourth P+ region in the depth direction is greater than the width of the fifth N+ region in the depth direction; or,

[0026] Among them, there are eight fourth P+ regions and one fifth N+ region in the segmented doping region, and the fifth N+ region presents a font of "abundant", separating the eight fourth P+ regions one by one.

[0027] Further, the multiple metal layers are divided into:

[0028] A ground terminal metal layer, connecting the first P+ region and the second P+ region in the first preset region and the fifth preset region, and the segmented doping region in the third preset region;

[0029] A power supply terminal metal layer, connecting the second N+ region and the third N+ region in the second preset region and the fourth preset region, and the fourth N+ region in the third preset region;

[0030] A first metal layer, connecting the first port and connecting the third P+ region in the second preset region;

[0031] A second metal layer, connecting the second port and connecting the third P+ region in the fourth preset region.

[0032] Furthermore, the first P-type well region completely surrounds the second P-type well region, and the impurity concentration of the second P-type well region is jointly determined by the doping concentration of the first P-type well region and the doping concentration of the second P-type well region.

[0033] Furthermore, the first P-type well region is implanted with boron at a dose of 5E11–9E12 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0034] The second P-type well region was implanted with boron at a dose of 1E14–8E14 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0035] A method for manufacturing a low-capacitance array transient voltage suppressor, for preparing the aforementioned low-capacitance array transient voltage suppressor, includes the following steps:

[0036] Step S1: Provide a silicon wafer substrate;

[0037] Step S2: An epitaxial layer is grown on the upper surface of the silicon wafer. The conductivity type of the epitaxial layer is different from that of the substrate.

[0038] Step S3: On the epitaxial layer of the silicon wafer, a first P-type well region is formed by photolithography and ion implantation, followed by high-temperature propagation.

[0039] Step S4: A second P-type well region is formed by photolithography and ion implantation. The second P-type well region is formed within the first P-type well region, followed by high-temperature propagation.

[0040] Step S5: On the upper surface of the silicon wafer, N+ regions are implanted through photolithography and ion implantation to form the first N+ region, the second N+ region, the third N+ region, the fourth N+ region and the fifth N+ region;

[0041] Step S6: On the upper surface of the silicon wafer, P+ regions are implanted by photolithography and ion implantation to form the first P+ region, the second P+ region, the third P+ region and the fourth P+ region. Then, annealing is performed to repair implantation damage.

[0042] Step S7: Apply adhesive, perform photolithography on the upper surface of the silicon wafer, define the silicon etching area window, etch deep trenches using dry etching, and fill the deep trenches with silicon dioxide or undoped polysilicon to form an isolation structure.

[0043] Step S8: Dielectric deposition is performed on the upper surface of the silicon wafer to form a dielectric layer, and contact holes are formed in the dielectric layer through photolithography and etching processes;

[0044] Step S9: Metal deposition is performed on the upper surface of the silicon wafer, forming multiple metal layers through photolithography and etching processes.

[0045] The beneficial technical effects of this invention are as follows: by segmenting the N+ / P+ regions within the third preset region, the sudden return of the TVS device is reduced, providing a TVS device with small or even no sudden return. The TVS device of this invention not only has the advantages of low breakdown voltage and trigger voltage and faster protection response, but also features lower on-resistance and clamping voltage, resulting in stronger protection for subsequent integrated circuits. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of one embodiment of a low-capacitance array transient voltage suppressor according to the present invention;

[0047] Figure 2 This is a schematic diagram of step S1 of one embodiment of the manufacturing method of a low-capacitance array transient voltage suppressor of the present invention;

[0048] Figure 3 This is a schematic diagram of step S2 of one embodiment of the manufacturing method of a low-capacitance array transient voltage suppressor of the present invention;

[0049] Figure 4 This is a schematic diagram of step S3 of one embodiment of the manufacturing method of a low-capacitance array transient voltage suppressor of the present invention;

[0050] Figure 5 This is a schematic diagram of step S4 of one embodiment of the manufacturing method of a low-capacitance array transient voltage suppressor of the present invention;

[0051] Figure 6 This is a flowchart illustrating one embodiment of a method for manufacturing a low-capacitance array transient voltage suppressor according to the present invention.

[0052] Figure 7 The layout structure of the N+ and P+ regions of one embodiment of a low-capacitance array transient voltage suppressor according to the present invention;

[0053] Figure 8 This is a schematic diagram of another embodiment of the low-capacitance array transient voltage suppressor of the present invention;

[0054] Figure 9 This is a schematic diagram of another embodiment of the low-capacitance array transient voltage suppressor of the present invention;

[0055] Figure 10 This invention provides a layout structure of N+ and P+ regions with different area ratios for a low-capacitance array transient voltage suppressor.

[0056] Figure 11This is a schematic diagram of the equivalent circuit principle of a low-capacitance array transient voltage suppressor according to the present invention;

[0057] Figure 12 This is a schematic diagram of the current-voltage curve of a low-capacitance array transient voltage suppressor according to the present invention.

[0058] in,

[0059] 1-Substrate;

[0060] 2-Buried layer;

[0061] 3-Epipolar layer;

[0062] 4-Third P-type well region;

[0063] 5-First P-type well region;

[0064] 6-Second P-type well region;

[0065] 7-P+ area;

[0066] 8-N+ region;

[0067] 9-Dielectric layer;

[0068] 10-Isolation structure;

[0069] 11-Grounding terminal metal layer;

[0070] 12 - First metal layer;

[0071] 13-Power supply terminal metal layer;

[0072] 14 - Second metal layer; Detailed Implementation

[0073] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0075] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0076] Example 1

[0077] See Figure 1 The present invention provides a low-capacitance array transient voltage suppressor, comprising:

[0078] Substrate 1;

[0079] A buried layer 2 is formed on the upper surface of the substrate 1; the conductivity type of the buried layer 2 is different from that of the substrate.

[0080] An epitaxial layer 3 is formed on the upper surface of the buried layer 2. The conductivity type of the epitaxial layer 3 is different from that of the substrate 1. That is, the conductivity type of the epitaxial layer 3 is the same as that of the buried layer 2. If the substrate 1 is an N-type substrate Nsub, then the epitaxial layer 3 is a P-type epitaxial layer P-epi and the buried layer 2 is a P-type buried layer PBL. If the substrate 1 is a P-type substrate Psub, then the epitaxial layer 3 is an N-type epitaxial layer N-epi and the buried layer 2 is an N-type buried layer NBL. In this first embodiment, a P-type substrate Psub, an N-type epitaxial layer N-epi, and an N-type buried layer NBL are taken as an example.

[0081] Multiple preset regions are formed in the epitaxial layer 3, and the multiple preset regions are isolated by the isolation structure 10. The isolation structure 10 extends longitudinally from the upper surface of the epitaxial layer 3, through the epitaxial layer 3 and the buried layer 2, and into the substrate 1. The preset regions in the epitaxial layer 3 from left to right are: a first preset region, a second preset region, a third preset region, a fourth preset region, and a fifth preset region. The low capacitance array transient voltage suppressor of the present invention is a left-right symmetrical structure with the third preset region as the axis of symmetry.

[0082] The first and fifth preset regions respectively include: a third P-type well region (PW3)4 formed in the epitaxial layer, and a first P+ region, a first N+ region and a second P+ region formed sequentially in the third P-type well region 4.

[0083] The second and fourth preset regions respectively include: a second N+ region, a third P+ region, and a third N+ region formed sequentially within the epitaxial layer;

[0084] The third preset region includes: a first P-type well region (PW1) 5, a second P-type well region (PW2) formed within the first P-type well region PW1 6, and a fourth N+ region formed within the second P-type well region PW2; the second P-type well region PW2 is formed within the first P-type well region PW1, and the first P-type well region PW1 completely surrounds the second P-type well region PW2, that is, the junction depth of the second P-type well region PW2 is less than the junction depth of the first P-type well region PW1, and the impurity concentration of the second P-type well region PW2 is jointly determined by the doping concentration of the first P-type well region PW1 and the doping concentration of the second P-type well region PW2. The second P-type well region PW2 is a heavily doped region, and the first P-type well region PW1 is a lightly doped region.

[0085] The third preset region further includes: two segmented doped regions formed within the first P-type well region PW1, one segmented doped region being located to the left of the second P-type well region PW2, and the other segmented doped region being located to the right of the second P-type well region PW2; each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region; each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region, the fifth N+ region and the fourth P+ region being arranged along the depth direction; as a preferred embodiment, the fifth N+ region and the fourth P+ region are arranged alternately along the depth direction; the lateral direction refers to the direction from left to right, the depth direction refers to the direction from front to back, and the longitudinal direction refers to the direction from top to bottom;

[0086] A dielectric layer 9 is formed on the upper surface of the epitaxial layer. The dielectric layer 9 includes contact holes corresponding to each P+ region and N+ region in the first preset region, the second preset region, the fourth preset region, and the fifth preset region. The dielectric layer 9 also includes contact holes corresponding to the fourth N+ region in the third preset region and contact holes corresponding to each segmented doped region in the third preset region. The range of the contact holes in the segmented doped regions involves each fifth N+ region and the fourth P+ region within the segmented doped region.

[0087] Multiple metal layers are respectively filled in each contact hole, and the metal layers include:

[0088] The grounding metal layer (Gnd) 11, the first P+ region and the second P+ region in the first preset region and the fifth preset region, and the segmented doped region in the third preset region are connected to the grounding metal layer (Gnd) 11.

[0089] The power supply metal layer (VCC) 13, the second N+ region and the third N+ region in the second preset region and the fourth preset region, and the fourth N+ region in the third preset region are connected to the power supply metal layer (VCC) 13.

[0090] The first metal layer 12 is connected to the first port IO1, and the third P+ area in the second preset area is connected to the first metal layer 12;

[0091] The second metal layer 14 is connected to the second port IO2, and the third P+ area in the fourth preset area is connected to the first metal layer 12.

[0092] Specifically, N+ zone 8 includes the first N+ zone, the second N+ zone, the third N+ zone, the fourth N+ zone, and the fifth N+ zone.

[0093] Specifically, P+ area 7 includes the first P+ area, the second P+ area, the third P+ area, and the fourth P+ area.

[0094] In a preferred embodiment, substrate 1 is a P-type substrate (Psub), using a heavily doped P-type silicon wafer with a resistivity of 0.01–0.1 Ω*cm. Antimony or arsenic is implanted as ions at an implantation energy of 60–100 keV and an implantation dose of 5E14–8E15cm. -2 The injection angle is 7 degrees.

[0095] In a preferred embodiment, the epitaxial layer 3 is an N-type epitaxial layer N-epi, which is grown with phosphorus or arsenic impurities, has a resistivity of 50 to 300 Ω*cm, and an epitaxial thickness of 6 to 15 μm.

[0096] In a preferred embodiment, the third P-type well region PW3 is implanted with boron at a dose of 1E12–8E13 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0097] In a preferred embodiment, the first P-type well region PW1 is implanted with boron at a dose of 5E11–9E12 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0098] In a preferred embodiment, the second P-type well region PW2 is implanted with boron at a dose of 1E14–8E14 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0099] In a preferred embodiment, all N+ regions, namely N+ regions 8 (i.e., the first N+ region, the second N+ region, the third N+ region, the fourth N+ region, and the fifth N+ region), are implanted with phosphorus or arsenic, and the implantation dose is 2E15~1E16cm. -2 The injected energy is 80–120 keV.

[0100] In a preferred embodiment, all P+ regions, namely P+ regions 7 (i.e., the first P+ region, the second P+ region, the third P+ region, and the fourth P+ region), are implanted with boron or boron difluoride, and the implantation dose is 1E15~8E15cm. -2 The injected energy is 40–80 keV.

[0101] In a preferred embodiment, the isolation structure 10 is formed by filling a deep trench with silicon dioxide or undoped polysilicon. The depth of the isolation structure 10 ranges from 9 to 20 μm, and the width of the isolation structure 10 is 1 to 2 μm.

[0102] In a preferred embodiment, the dielectric layer 9 can be an oxide layer, a borosilicate glass, or a composite layer formed by multiple insulating films.

[0103] In a preferred embodiment, the metal layer can be pure aluminum or an aluminum-silicon compound; more preferably, the metal has a three-layer composite structure, consisting of titanium, titanium nitride, and aluminum-silicon-copper layers from bottom to top; preferably, the titanium thickness is [missing information]. Titanium nitride thickness is The thickness of aluminum-silicon-copper alloy is 2–4 μm.

[0104] join Figure 7 , Figure 7 The layout structure of N+ and P+ regions fabricated by the process is shown. The main improvement is in the segmented doping region. In the first, second, fourth and fifth preset regions, the N+ and P+ regions extend in the depth direction and are arranged laterally in the corresponding regions. In the third preset region, the fourth N+ region extends in the depth direction. In each segmented doping region in the third preset region, the fifth N+ region and the fourth P+ region extend laterally and are arranged alternately in the depth direction.

[0105] In this embodiment, the above-mentioned low-capacitance array transient voltage suppressor is prepared by the following steps.

[0106] See Figure 2 Step S1: Provide a substrate 1, preferably a P-type substrate Pub, where the P-type substrate Psub is a heavily doped silicon wafer. Grow a thin oxide layer on its surface, and then perform N-type ion implantation to form an N-type buried layer NBL to prevent boron impurities in the substrate 1 from diffusing upward into the epitaxial layer 3 during subsequent thermal processes. Then remove the thin oxide layer on the surface using a wet etching process.

[0107] Preferably, the resistivity of the P-type substrate (Pub) is 0.01–0.1 Ω*cm, and the thickness of the thin oxide layer is [missing value]. N-type ion implantation is performed with antimony or arsenic, with an implantation energy of 60–100 keV and an implantation dose of 5E14–8E15 cm⁻¹. -2 The injection angle is 7 degrees. After N-type ion implantation, a thermal process is carried out to form an N-type buried layer (NBL). The thermal process is carried out in a furnace tube at a temperature of 1050℃~1200℃ for 60~120 minutes.

[0108] See Figure 3 Step S2: On the upper surface of the silicon wafer, an epitaxial layer 3 is grown, specifically, an N-type epitaxial layer N-epi is grown.

[0109] Preferably, the doping element of the N-type epitaxial layer N-epi is phosphorus or arsenic, the resistivity of the epitaxial layer 3 is 50 to 300 Ω*cm, and the thickness of the epitaxial layer 3 is 6 to 15 μm.

[0110] See Figure 4Step S3: On the surface of the epitaxial layer 3 of the silicon wafer, the third P-type well region PW3 is formed by photolithography and ion implantation, and the first P-type well region PW1 is formed by photolithography and ion implantation. After ion implantation, high-temperature propagation is performed.

[0111] Preferably, the ion implantation element in the third P-type trap region PW3 is boron, and the implantation dose is 1E12~8E13cm. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0112] Preferably, the ion implantation element in the first P-type well region PW1 is boron, and the implantation dose is 5E11 to 9E12 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0113] Preferably, the high-temperature propulsion in step S3 is carried out in a furnace tube, with a propulsion temperature of 1000-1150°C and a propulsion time of 60-360 minutes.

[0114] See Figure 5 Step S4: Perform photolithography and ion implantation to form the second P-type well region PW2. The second P-type well region PW2 is formed within the first P-type well region PW1 and is advanced at high temperature after ion implantation.

[0115] Specifically, the second P-type well region PW2 is formed within the first P-type well region PW1, and the first P-type well region PW1 completely surrounds the third P-type well region PW3. That is, the junction depth of the second P-type well region PW2 is less than the junction depth of the first P-type well region PW1, and the impurity concentration of the second P-type well region PW2 is jointly determined by the doping concentration of the first P-type well region PW1 and the doping concentration of the second P-type well region PW2.

[0116] Preferably, the ion implantation element in the second P-type well region PW2 is boron, and the implantation dose is 1E14 to 8E14 cm⁻¹. -2 The injection energy is 60–100 keV, and the injection angle is 7 degrees.

[0117] Preferably, the high-temperature propulsion in step S4 is carried out in a furnace tube, with a propulsion temperature of 1000-1150°C and a propulsion time of 60-360 minutes.

[0118] Step S5: Selective implantation of N+ regions is performed on the upper surface of the silicon wafer using photolithography and ion implantation processes.

[0119] Specifically, N+ zone 8 includes the first N+ zone, the second N+ zone, the third N+ zone, the fourth N+ zone, and the fifth N+ zone mentioned above.

[0120] Preferably, the injected element in each N+ region is phosphorus or arsenic, and the injection dose is 2E15 to 1E16 cm⁻¹. -2 The injected energy is 80–120 keV.

[0121] Step S6: Selectively implant P+ regions onto the upper surface of the silicon wafer using photolithography and ion implantation processes, followed by annealing to repair implantation damage.

[0122] Specifically, P+ area 7 includes the first P+ area, the second P+ area, the third P+ area, and the fourth P+ area mentioned above.

[0123] Preferably, the implantation dose of boron or boron difluoride in each P+ region is 1E15 to 8E15 cm⁻¹. -2 The injected energy is 40–80 keV.

[0124] The annealing process in step S6 can use a furnace tube process, with a preferred annealing temperature of 850℃~950℃ and an annealing time of 30~60 minutes. Alternatively, the annealing process in step S6 can also use a rapid thermal annealing process, with a preferred rapid thermal annealing temperature of 950~1050℃ and a preferred rapid thermal annealing time of 10~30 seconds.

[0125] Step S7: Apply adhesive, perform photolithography, and define the silicon etching area window on the upper surface of the silicon wafer. Then, use dry etching to etch deep trenches and fill the deep trenches with silicon dioxide or undoped polysilicon to form an isolation structure 10. Then, remove the excess oxide layer on the front side.

[0126] The isolation structure 10 extends longitudinally from the upper surface of the epitaxial layer 3, through the epitaxial layer 3 and the buried layer 2, into the substrate 1. That is, the depth of the isolation structure 10 is greater than the sum of the depths of the epitaxial layer 3 and the buried layer 2.

[0127] The depth of the isolation structure 10 ranges from 9 to 20 μm, and the width of the isolation structure 10 ranges from 1 to 2 μm.

[0128] Step S8: Dielectric deposition is performed on the upper surface of the silicon wafer to form dielectric layer 9, and contact holes are formed in dielectric layer 9 through photolithography and etching processes.

[0129] Preferably, the dielectric layer (9) can be an oxide layer, a borosilicate glass, or a composite layer formed by multiple insulating films.

[0130] Step S9: Metal deposition is performed on the upper surface of the silicon wafer, forming multiple corresponding metal layers through photolithography and etching processes.

[0131] Specifically, the metal layer includes:

[0132] The grounding metal layer (Gnd) 11, the first P+ region and the second P+ region in the first preset region and the fifth preset region, and the segmented doped region in the third preset region are connected to the grounding metal layer (Gnd) 11.

[0133] The power supply metal layer (VCC) 13, the second N+ region and the third N+ region in the second preset region and the fourth preset region, and the fourth N+ region in the third preset region are connected to the power supply metal layer (VCC) 13.

[0134] The first metal layer 12 is connected to the first port IO1, and the third P+ area in the second preset area is connected to the first metal layer 12;

[0135] The second metal layer 14 is connected to the second port IO2, and the third P+ area in the fourth preset area is connected to the second metal layer 14.

[0136] Preferably, the metal layer can be pure aluminum or an aluminum-silicon compound; more preferably, the metal has a three-layer composite structure, consisting of titanium, titanium nitride, and aluminum-silicon-copper layers from bottom to top, wherein the titanium layer has a thickness of [missing information]. Titanium nitride thickness is The thickness of aluminum-silicon-copper alloy is 2–4 μm.

[0137] Example 2

[0138] This embodiment is similar to the structure and preparation method of Embodiment 1, but the following differences exist between this embodiment and Embodiment 1:

[0139] See Figure 8 The third P-type well region PW3 of the first and fifth preset regions is removed. The function of the device remains almost unchanged, thus obtaining this embodiment. In this embodiment, a photolithography plate can be saved, thereby reducing production costs.

[0140] This embodiment of a low-capacitance array transient voltage suppressor includes:

[0141] Substrate 1;

[0142] A buried layer 2 is formed on the upper surface of the substrate 1; the conductivity type of the buried layer 2 is different from that of the substrate.

[0143] An epitaxial layer 3 is formed on the upper surface of the buried layer 2; the conductivity type of the epitaxial layer 3 is different from that of the substrate 1; that is, the conductivity type of the epitaxial layer 3 is the same as that of the buried layer 2. If the substrate 1 is an N-type substrate Nsub, then the epitaxial layer 3 is a P-type epitaxial layer P-epi and the buried layer 2 is a P-type buried layer PBL; if the substrate 1 is a P-type substrate Psub, then the epitaxial layer 3 is an N-type epitaxial layer N-epi and the buried layer 2 is an N-type buried layer NBL.

[0144] Multiple preset regions are formed in the epitaxial layer 3, and the multiple preset regions are isolated by the isolation structure 10. The isolation structure 10 extends longitudinally from the upper surface of the epitaxial layer 3, through the epitaxial layer 3 and the buried layer 2, and into the substrate 1. The preset regions in the epitaxial layer 3 from left to right are: a first preset region, a second preset region, a third preset region, a fourth preset region, and a fifth preset region. The low capacitance array transient voltage suppressor of the present invention is a left-right symmetrical structure with the third preset region as the axis of symmetry.

[0145] The first and fifth preset regions each include: a first P+ region, a first N+ region, and a second P+ region formed sequentially within the epitaxial layer;

[0146] The second and fourth preset regions respectively include: a second N+ region, a third P+ region, and a third N+ region formed sequentially within the epitaxial layer;

[0147] The third preset region includes: a first P-type well region PW1, a second P-type well region PW2 formed within the first P-type well region PW1, and a fourth N+ region formed within the second P-type well region PW2; the second P-type well region PW2 is formed within the first P-type well region PW1, and the first P-type well region PW1 completely surrounds the second P-type well region PW2, that is, the junction depth of the second P-type well region PW2 is less than the junction depth of the first P-type well region PW1, and the impurity concentration of the second P-type well region PW2 is jointly determined by the doping concentration of the first P-type well region PW1 and the doping concentration of the second P-type well region PW2. The second P-type well region PW2 is a heavily doped region, and the first P-type well region PW1 is a lightly doped region.

[0148] The third preset region further includes: two segmented doped regions formed within the first P-type well region PW1, one segmented doped region being located to the left of the second P-type well region PW2, and the other segmented doped region being located to the right of the second P-type well region PW2; each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region; each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region, the fifth N+ region and the fourth P+ region being arranged along the depth direction; as a preferred embodiment, the fifth N+ region and the fourth P+ region are arranged alternately along the depth direction; the lateral direction refers to the direction from left to right, the longitudinal direction refers to the direction from top to bottom, and the depth direction refers to the direction from front to back;

[0149] A dielectric layer 9 is formed on the upper surface of the epitaxial layer. The dielectric layer 9 includes contact holes corresponding to each P+ region and N+ region within the first preset region, the second preset region, the fourth preset region, and the fifth preset region. The dielectric layer 9 also includes contact holes corresponding to the fourth N+ region within the third preset region and contact holes corresponding to the two segmented doped regions within the third preset region. The range of the contact holes in the segmented doped regions covers each fifth N+ region and the fourth P+ region within the segmented doped region.

[0150] Multiple metal layers are respectively filled in each contact hole, and the metal layers include:

[0151] The grounding metal layer (Gnd) 11, the first P+ region and the second P+ region in the first preset region and the fifth preset region, and the segmented doped region in the third preset region are connected to the grounding metal layer (Gnd) 11.

[0152] The power supply metal layer (VCC) 13, the second N+ region and the third N+ region in the second preset region and the fourth preset region, and the fourth N+ region in the third preset region are connected to the power supply metal layer (VCC) 13.

[0153] The first metal layer 12 is connected to the first port IO1, and the third P+ area in the second preset area is connected to the first metal layer 12;

[0154] The second metal layer 14 is connected to the second port IO2, and the third P+ area in the fourth preset area is connected to the first metal layer 12.

[0155] In the preparation method, the third P-type well region PW3 photolithography and ion implantation to form the third P-type well region PW3 are no longer performed in step S3.

[0156] Other structures and method steps are the same as or similar to those in each of the above embodiments 1, and will not be repeated here.

[0157] Example 3

[0158] This embodiment differs from the above embodiments in the following ways:

[0159] See Figure 9 The third P-type well region PW3 in the first and fifth preset regions is removed, along with the buried layer 2. The device function remains almost unchanged, thus obtaining this embodiment. In this embodiment, the thickness of the epitaxial layer 3 needs to be increased.

[0160] This embodiment of a low-capacitance array transient voltage suppressor includes:

[0161] Substrate 1;

[0162] An epitaxial layer 3 is formed on the upper surface of the substrate 1; the conductivity type of the epitaxial layer 3 is different from that of the substrate 1; if the substrate 1 is an N-type substrate Nsub, then the epitaxial layer 3 is a P-type epitaxial layer P-epi; if the substrate 1 is a P-type substrate Psub, then the epitaxial layer 3 is an N-type epitaxial layer N-epi.

[0163] Multiple preset regions are formed in the epitaxial layer 3, and the multiple preset regions are isolated by the isolation structure 10. The isolation structure 10 extends longitudinally from the upper surface of the epitaxial layer 3, through the epitaxial layer 3 and the buried layer 2, and into the substrate 1. The preset regions in the epitaxial layer 3 from left to right are: a first preset region, a second preset region, a third preset region, a fourth preset region, and a fifth preset region. The low capacitance array transient voltage suppressor of the present invention is a left-right symmetrical structure with the third preset region as the axis of symmetry.

[0164] The first and fifth preset regions each include: a first P+ region, a first N+ region, and a second P+ region formed sequentially within the epitaxial layer;

[0165] The second and fourth preset regions respectively include: a second N+ region, a third P+ region, and a third N+ region formed sequentially within the epitaxial layer;

[0166] The third preset region includes: a first P-type well region PW1, a second P-type well region PW2 formed within the first P-type well region PW1, and a fourth N+ region formed within the second P-type well region PW2; the second P-type well region PW2 is formed within the first P-type well region PW1, and the first P-type well region PW1 completely surrounds the second P-type well region PW2, that is, the junction depth of the second P-type well region PW2 is less than the junction depth of the first P-type well region PW1, and the impurity concentration of the second P-type well region PW2 is jointly determined by the doping concentration of the first P-type well region PW1 and the doping concentration of the second P-type well region PW2. The second P-type well region PW2 is a heavily doped region, and the first P-type well region PW1 is a lightly doped region.

[0167] The third preset region further includes: two segmented implantation regions formed within the first P-type well region PW1, one segmented doping region being located to the left of the second P-type well region PW2, and the other segmented doping region being located to the right of the second P-type well region PW2; each segmented doping region includes at least one fifth N+ region and at least one fourth P+ region; each segmented doping region includes at least one fifth N+ region and at least one fourth P+ region, the fifth N+ region and the fourth P+ region being arranged along the depth direction; as a preferred embodiment, the fifth N+ region and the fourth P+ region are arranged alternately along the depth direction; the lateral direction refers to the direction from left to right, therefore the longitudinal direction refers to the direction from top to bottom, and the depth direction refers to the direction from front to back;

[0168] A dielectric layer 9 is formed on the upper surface of the epitaxial layer. The dielectric layer 9 includes contact holes corresponding to each P+ region and N+ region within the first preset region, the second preset region, the fourth preset region, and the fifth preset region. The dielectric layer 9 also includes contact holes corresponding to the fourth N+ region within the third preset region, and contact holes corresponding to the two segmented doped regions within the third preset region. The range of the contact holes in the segmented doped regions covers each fifth N+ region and the fourth P+ region within the segmented doped region.

[0169] Multiple metal layers are respectively filled in each contact hole, and the metal layers include:

[0170] The grounding metal layer (Gnd) 11, the first P+ region and the second P+ region in the first preset region and the fifth preset region, and the segmented doped region in the third preset region are connected to the grounding metal layer (Gnd) 11.

[0171] The power supply metal layer (VCC) 13, the second N+ region and the third N+ region in the second preset region and the fourth preset region, and the fourth N+ region in the third preset region are connected to the power supply metal layer (VCC) 13.

[0172] The first metal layer 12 is connected to the first port IO1, and the third P+ area in the second preset area is connected to the first metal layer 12;

[0173] The second metal layer 14 is connected to the second port IO2, and the third P+ area in the fourth preset area is connected to the first metal layer 12.

[0174] In the fabrication method, step S1 no longer involves N-type ion implantation to form the N-type buried layer NBL. Similarly, in the fabrication method, step S3 no longer involves photolithography and ion implantation to form the third P-type well region PW3.

[0175] Other structures and preparation methods are the same as or similar to those in each of the above Examples 1, and will not be repeated here.

[0176] Example 4

[0177] This embodiment differs from the above embodiments in the following ways:

[0178] Substrate 1 is changed to an N-type substrate Nsub, buried layer 2 is changed to a P-type buried layer PBL, and epitaxial layer 3 is changed to a P-type epitaxial layer P-epi to obtain this embodiment.

[0179] Other structures and preparation methods are the same as or similar to those in the above embodiments, and will not be repeated here.

[0180] Example 5

[0181] This embodiment differs from the above embodiments in the following ways:

[0182] See Figure 10 Different quick-return voltage values ​​can be obtained by changing the area ratio of the P+ and N+ regions in the segmented doped region.

[0183] Preferably, the change in the area ratio of the P+ region and the N+ region is achieved by changing the layout of the segmented doped regions formed by the fourth P+ region and the fifth N+ region.

[0184] Preferably, the area ratio of the P+ region to the N+ region is 1:1, 3:1 or 10:1.

[0185] Preferably, when the area ratio of the P+ region to the N+ region is 1:1, as a preferred embodiment, each segmented doping region has four fourth P+ regions and three fifth N+ regions. The four fourth P+ regions and the three fifth N+ regions extend horizontally and are arranged alternately vertically.

[0186] Preferably, when the area ratio of the P+ region to the N+ region is 3:1, as a preferred embodiment, each segmented doping region has two fourth P+ regions and one fifth N+ region. The two fourth P+ regions and the one fifth N+ region extend horizontally and are arranged alternately vertically, and the area of each fourth P+ region is larger than that of the fifth N+ region.

[0187] Preferably, when the area ratio of the P+ region to the N+ region is 10:1, as a preferred embodiment, each segmented doping region has two fourth P+ regions and one fifth N+ region. The two fourth P+ regions and the one fifth N+ region extend horizontally and are arranged alternately vertically, and the area of each fourth P+ region is larger than that of the fifth N+ region.

[0188] Preferably, when the area ratio of the P+ region to the N+ region is 10:1, as another preferred embodiment, each segmented doping region has one fifth N+ region, presenting a Chinese character '丰' shape and separating the eight fourth P+ regions one by one.

[0189] In addition to the above preferred methods, other area ratios of the P+ region to the N+ region can be set, and other forms of the layout of the segmented doping region can be designed to achieve the purpose.

[0190] Other structures are the same as those in the above embodiments, and the manufacturing methods are also the same.

[0191] Circuit principle

[0192] See Figure 11 , and each embodiment of the present invention has a similar or identical circuit schematic diagram, including:

[0193] The first diode D1 is located in the second preset region. The forward electrode of the first diode D1 is connected to the first port IO1, and the negative electrode of the first diode D1 is connected to the power terminal metal layer 13;

[0194] The second diode D2 is located in the fourth preset region. The forward electrode of the second diode D2 is connected to the second port IO2, and the negative electrode of the second diode D2 is connected to the power terminal metal layer 13;

[0195] The third diode D3 is located in the first preset area. The negative electrode of the third diode D3 is connected to the first port IO1, and the positive electrode of the third diode D3 is connected to the ground metal layer 11.

[0196] The fourth diode D4 is located in the fifth preset region. The negative electrode of the fourth diode D4 is connected to the second port IO2, and the positive electrode of the fourth diode D4 is connected to the ground metal layer 11.

[0197] A bipolar transistor (TVS) is located in the third preset region. The base of the TVS is connected to a resistor R. PW1 The collector of the bipolar transistor TVS is connected to the ground metal layer 11, and the emitter of the bipolar transistor TVS is connected to the power supply metal layer 13.

[0198] See Figure 11 The bipolar transistor TVS is of the NPN type.

[0199] See Figure 12 Conventional TVS devices with small quick-return characteristics often experience a clamping voltage that quickly returns to around 5V during application. When used for 5V port protection, this clamping voltage may fall below the operating voltage Vcc, posing a risk. The embodiment of this invention, during transmission line pulse (TLP) testing, exhibits a typical IO-IO curve as shown below, demonstrating a small quick-return (or no quick-return) characteristic. This prevents the clamping voltage from falling below Vcc, effectively improving the reliability of electrostatic discharge (ESD) protection. Furthermore, under high current conditions, the clamping voltage of this embodiment is lower than that of conventional NPN devices.

[0200] The technical features and advantages of the present invention are described in detail below:

[0201] (1) The TVS transistor in this structure is a bipolar transistor composed of the N+ region of the Vcc terminal / PW2 / PW1 / ground terminal N+. The base region of the TVS, namely the second P-type well region PW2 and the first P-type well region PW1, is led to ground through the ground terminal P+ region (7). The part below the ground terminal metal layer 11 adopts the N+ / P+ segmented design and is led out by the ground terminal metal layer 11. Among them, the doping concentration of the second P-type well region PW2 is relatively high, and the breakdown voltage of the corresponding PN junction can be controlled to be very low. When the voltage of the power supply is greater than the junction breakdown voltage of the N+ region and the second P-type well region PW2, the PN junction is broken down. By adopting the N+ / P+ segmented structure design, the hole current generated by the collision ionization of the PN junction can be drawn away by the P+ region (7) of the ground terminal along the first P-type well region PW1 and the second P-type well region PW2, so that no voltage drop is generated on the PN junction of the N+ region of the ground terminal and the first P-type well region PW1. The NPN conductance modulation effect caused by electron injection from the N+ region of the ground terminal into the first P-type well region PW1 is suppressed, thus achieving the design requirement of smaller or even no quick-turnback. In summary, the TVS device of this invention not only has the advantages of low breakdown voltage and trigger voltage and faster protection response, but also has the characteristics of lower on-resistance and clamping voltage, and stronger protection capability for subsequent integrated circuits.

[0202] (2) The N+ / P+ segmented arrangement scheme adopted in this invention will cause the sudden return amplitude of the device to decrease as the proportion of the P+ region increases. Therefore, the desired characteristics can be obtained by controlling the N+ / P+ ratio.

[0203] (3) The doping type of the substrate used in this invention is opposite to that of the epitaxial layer. At the same time, the isolation trench is added to ensure that the ports IO (IO1-IO2 or IO2-IO1) are isolated. Even when the ground terminal is floating, the device can still work normally, with a wider protection range and more flexible application in circuits.

[0204] (4) This invention includes two types of diodes: The first type is a diode from the IO terminal to the VCC terminal, which is formed by the P+ region, the epitaxial layer N-epi, and the N+ region. Since the epitaxial layer 3 is a high-resistivity epitaxial layer, the space charge region formed by P+ is relatively wide, thus reducing the capacitance of this type of diode. The second type is a diode from the ground terminal (GND) to the IO terminal, which is formed by the P+ region, the third P-type well region PW1, and the N+ region. The third P-type well region PW1 is lightly doped, thus the space charge region formed by N+ is relatively wide, further reducing the capacitance of this type of diode, and consequently reducing the overall capacitance of the device.

[0205] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-capacitance array transient voltage suppressor, characterized in that, include: Substrate; An epitaxial layer is formed on the substrate, wherein the conductivity type of the epitaxial layer is different from that of the substrate; Multiple preset regions are isolated by an isolation structure. The multiple preset regions are, from left to right, the first preset region, the second preset region, the third preset region, the fourth preset region, and the fifth preset region. An isolation structure, wherein the isolation structure extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer and into the substrate; The first preset region and the fifth preset region sequentially include a first P+ region, a first N+ region and a second P+ region formed in the epitaxial layer, respectively. The second preset region and the fourth preset region sequentially include a second N+ region, a third P+ region, and a third N+ region formed within the epitaxial layer, respectively; The third preset region includes: a first P-type well region formed on the epitaxial layer, a second P-type well region formed within the first P-type well region, a fourth N+ region formed within the second P-type well region, and two segmented doped regions formed within the first P-type well region; the two segmented doped regions are respectively located on the left and right sides of the second P-type well region. Each segmented doped region includes at least one fifth N+ region and at least one fourth P+ region, wherein the fifth N+ region and the fourth P+ region are arranged along the depth direction; A dielectric layer is formed on the upper surface of the epitaxial layer. The dielectric layer includes contact holes corresponding to each P+ region and N+ region in the first preset region, the second preset region, the fourth preset region, and the fifth preset region, as well as contact holes corresponding to each segmented doped region and the fourth N+ region in the third preset region. The coverage area of ​​the contact holes above the segmented doped regions involves each of the fifth N+ region and the fourth P+ region within the segmented doped regions; Multiple metal layers are formed in each contact hole; Different quick-return voltage values ​​can be obtained by changing the area ratio of the P+ and N+ regions in the segmented doped region.

2. The low-capacitance array transient voltage suppressor as described in claim 1, characterized in that, It also includes a buried layer formed on the upper surface of the substrate, and the isolation structure extends longitudinally from the upper surface of the epitaxial layer through the epitaxial layer, the buried layer and into the substrate.

3. A low-capacitance array transient voltage suppressor as described in claim 1, characterized in that, Also includes: The third P-type well region is formed in the epitaxial layer in the first preset region and the fifth preset region, respectively, and the first P+ region, the first N+ region and the second P+ region are formed in the third P-type well region.

4. A low-capacitance array transient voltage suppressor as described in claim 1, characterized in that, When the area ratio of the P+ region and the N+ region contained in the segmented doped region is 1:1, the segmented doped region has four fourth P+ regions and three fifth N+ regions, and the four fourth P+ regions and the three fifth N+ regions extend in the lateral direction and are arranged alternately in the depth direction.

5. A low-capacitance array transient voltage suppressor as described in claim 4, characterized in that, When the area ratio of P+ regions to N+ regions in the segmented doped region is 3:1, the segmented doped region has two fourth P+ regions and one fifth N+ region. The two fourth P+ regions and one fifth N+ region extend in the lateral direction and are arranged alternately in the depth direction. The width of each fourth P+ region in the depth direction is greater than the width of the fifth N+ region in the depth direction.

6. A low-capacitance array transient voltage suppressor as described in claim 4, characterized in that, When the area ratio of the P+ region and the N+ region in the segmented doping region is 10:1, there are two of the fourth P+ regions in the segmented doping region, one fifth N+ region, and the two fourth P+ regions and the one fifth N+ region are arranged alternately in the transverse direction and the depth direction; the width of each fourth P+ region in the depth direction is greater than the width of the fifth N+ region in the depth direction; Or, wherein, there are eight of the fourth P+ regions in the segmented doping region, one fifth N+ region, and the fifth N+ region is in a shape like the Chinese character "feng", separating the eight fourth P+ regions one by one.

7. A low-capacitance array transient voltage suppressor as described in claim 1, characterized in that, The multiple metal layers are divided into: The ground terminal metal layer, connecting the first P+ region and the second P+ region in the first preset region and the fifth preset region, and the segmented doping region in the third preset region; The power terminal metal layer, connecting the second N+ region and the third N+ region in the second preset region and the fourth preset region, and the fourth N+ region in the third preset region; The first metal layer, connecting the first port and connecting the third P+ region in the second preset region; 8. A low-capacitance array transient voltage suppressor as described in claim 1, characterized in that, The second metal layer, connecting the second port and connecting the third P+ region in the fourth preset region. The first P-type well region completely surrounds the second P-type well region, and the impurity concentration of the second P-type well region is jointly determined by the doping concentration of the first P-type well region and the doping concentration of the second P-type well region. The first P-type well region is implanted with boron at a dose of 5E11~9E12 cm⁻¹. -2 The injection energy is 60~100 keV, and the injection angle is 7 degrees; The second P-type well region was implanted with boron at a dose of 1E14~8E14 cm⁻¹. -2 The injection energy is 60~100 keV, and the injection angle is 7 degrees.

10. A method for manufacturing a low-capacitance array transient voltage suppressor, characterized in that, 9. A low-capacitance array transient voltage suppressor according to claim 1, wherein: For preparing a low-capacitance array transient voltage suppressor according to claim 1, the following steps are included: Step S1, providing a silicon wafer substrate; Step S2, growing an epitaxial layer on the upper surface of the silicon wafer, and the conductivity type of the epitaxial layer is different from that of the substrate; Step S3, forming the first P-type well region on the upper surface of the epitaxial layer of the silicon wafer by photolithography and ion implantation, and then performing high-temperature drive-in; Step S4, forming the second P-type well region by photolithography and ion implantation, and the second P-type well region is formed within the first P-type well region, and then performing high-temperature drive-in; Step S5: Injecting N+ regions by photolithography and ion implantation on the upper surface of the silicon wafer to form the first N+ region, the second N+ region, the third N+ region, the fourth N+ region and the fifth N+ region; Step S6: Injecting P+ regions by photolithography and ion implantation on the upper surface of the silicon wafer to form the first P+ region, the second P+ region, the third P+ region and the fourth P+ region, and then performing annealing treatment to repair the implantation damage; Step S7: Coating glue, performing photolithography on the upper surface of the silicon wafer, defining a silicon etching region window, etching a deep groove by dry etching, and filling the deep groove with silicon dioxide or undoped polysilicon to form the isolation structure; Step S8: Depositing a dielectric on the upper surface of the silicon wafer to form the dielectric layer, and forming the contact holes in the dielectric layer by photolithography and etching processes; Step S9: Depositing metal on the upper surface of the silicon wafer, and forming multiple metal layers by photolithography and etching processes; Different quick-return voltage values ​​can be obtained by changing the area ratio of the P+ and N+ regions in the segmented doped region.

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