Semiconductor switching device, manufacturing method, and semiconductor device
By forming obtuse-angled grooves and filling them with an insulating layer in semiconductor switching devices, the problem of tip discharge caused by groove etching is solved, thereby improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SIRIUS CORE SEMICON (CHENGDU) CO LTD
- Filing Date
- 2022-07-19
- Publication Date
- 2026-05-22
AI Technical Summary
In traditional semiconductor device and equipment manufacturing processes, tip discharge defects caused by groove etching can damage devices and affect performance.
By forming a groove on the source layer that extends to the side surface of the electron migration layer away from the drain layer, with at least a portion of the inner sidewall of the groove forming an obtuse angle with the surface of the electron migration layer near the source layer, and filling it with an insulating layer to isolate the gate and source layers, the problem of tip discharge is improved.
It effectively improves the defects of tip discharge, avoids internal damage to semiconductor devices, and improves the performance of devices and equipment.
Smart Images
Figure CN115274829B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor devices, and particularly relates to a semiconductor switching device, a manufacturing method, and a semiconductor apparatus. Background Technology
[0002] In traditional semiconductor device and equipment manufacturing processes, etching trenches is a common technique. During trench etching, due to the typically hard physical properties of semiconductor materials, the surface smoothness at deeper etching points is often poor, resulting in defects such as particles, peeling, and breakage. These uneven defects are prone to causing point discharges. Furthermore, excessively sharp corners in the trench can further exacerbate point discharge phenomena. Point discharges in certain areas can damage semiconductor device regions, thereby affecting the performance of the semiconductor device.
[0003] Therefore, in traditional semiconductor device and apparatus manufacturing processes, there is a problem of easy generation of tip discharge defects. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor switching device, manufacturing method, and semiconductor device, which aims to improve the problem of easy generation of tip discharge defects in the traditional semiconductor device and device manufacturing process.
[0005] A first aspect of this application provides a semiconductor switching device, comprising:
[0006] Drain layer;
[0007] An electron migration layer is formed on one side surface of the drain layer;
[0008] A source layer is formed on the surface of the electron migration layer away from the drain layer, and includes a groove extending through the surface of the electron migration layer away from the drain layer; and
[0009] A gate electrode is formed within the recess and is insulated from the source layer; wherein,
[0010] The angle between the plane containing at least a portion of the sidewalls of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle.
[0011] In an optional embodiment, the semiconductor switching device further includes:
[0012] An insulating layer is filled within the groove to isolate the gate and the source layers.
[0013] In an optional embodiment, the included angle is any value between 120° and 150°.
[0014] In an optional embodiment, the drain layer, the electron migration layer, the source layer, and the gate are made of silicon carbide.
[0015] A second aspect of this application provides a method for manufacturing a semiconductor switching device, the method comprising:
[0016] Forming a drain layer;
[0017] An electron migration layer is formed on one side surface of the drain layer;
[0018] A source layer is formed on the surface of the electron migration layer away from the drain layer;
[0019] A groove is formed on the source layer that extends to the side surface of the electron migration layer away from the drain layer, and the angle formed between the plane containing at least a portion of the sidewall of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle.
[0020] A gate is formed within the groove, and the gate is insulated from the source layer.
[0021] In an optional embodiment, the method for forming the source layer includes:
[0022] A first limiting block is formed on the surface of the electron migration layer away from the drain layer;
[0023] A source material layer located outside the first limiting block is formed on one side surface of the electron migration layer;
[0024] Remove the first limiting block to expose the space occupied by the first limiting block;
[0025] The sidewall of the source material layer facing the space occupied by the first limiting block is smoothed to form the source layer and the groove.
[0026] In an optional embodiment, the method for forming the source layer includes:
[0027] A first limiting block is formed on the surface of the electron migration layer away from the drain layer;
[0028] A first sub-source layer is formed on one side surface of the electron migration layer, located outside the first limiting block;
[0029] Remove the first limiting block to expose the space occupied by the first limiting block;
[0030] The sidewall of the space occupied by the first sub-source electrode layer facing the first limiting block is smoothed to form an empty space;
[0031] A second limiting block is formed within the empty space, and the second limiting block is flush with the first sub-source electrode layer;
[0032] A third limiting block is formed on the side surface of the second limiting block away from the electron migration layer, and a second sub-source layer located outside the third limiting block is formed on the side surface of the first sub-source layer away from the electron migration layer.
[0033] Remove the third limiting block and the second limiting block so that the space occupied by the third limiting block and the second limiting block forms the groove.
[0034] In an optional embodiment, the source layer includes a plurality of first sub-source layers stacked sequentially along a direction away from the electron migration layer, and the method for forming the source layer includes:
[0035] A first sub-limiting block is formed on the surface of the electron migration layer away from the drain layer;
[0036] A first sub-source layer is formed on one side surface of the electron migration layer, located outside the first sub-limiting block;
[0037] Each non-first first sub-source layer is formed sequentially, wherein the step of forming each non-first first sub-source layer includes: forming a first sub-limiting block corresponding to the non-first first sub-source layer on the surface jointly formed by the adjacent previous first sub-source layer and the first sub-limiting block corresponding to the adjacent previous first sub-source layer, wherein the orthographic projection edge of each first sub-limiting block is outside the orthographic projection of the adjacent previous first sub-limiting block;
[0038] Remove all first sub-limiting blocks to expose the space occupied by all the first sub-limiting blocks;
[0039] The sidewalls of each first sub-source layer facing the space occupied by all first sub-limiting blocks are smoothed to form the source layer and the groove.
[0040] In an optional embodiment, the source layer includes a plurality of first sub-source layers and second sub-source layers stacked sequentially along a direction away from the electron migration layer, and the method for forming the source layer includes:
[0041] A first sub-limiting block is formed on the surface of the electron migration layer away from the drain layer;
[0042] A first sub-source layer is formed on one side surface of the electron migration layer, located outside the first first sub-limiting block;
[0043] Each non-first first sub-source layer is formed sequentially, wherein the step of forming each non-first first sub-source layer includes: forming a first sub-limiting block corresponding to the non-first first sub-source layer on the surface jointly formed by the adjacent previous first sub-source layer and the first sub-limiting block corresponding to the adjacent previous first sub-source layer, wherein the orthographic projection edge of each first sub-limiting block is outside the orthographic projection of the adjacent previous first sub-limiting block;
[0044] Remove all first sub-limiting blocks to expose the space occupied by all first sub-limiting blocks, and smooth the sidewalls of each first sub-source layer facing the space occupied by all first sub-limiting blocks to form empty spaces;
[0045] A second sub-limiting block is formed within the empty space, and the second sub-limiting block is flush with the structural layer formed by stacking all the first sub-source layers;
[0046] A first third sub-limiting block is formed on the surface of the second sub-limiting block away from the electron migration layer, and a first second sub-source layer located outside the first third sub-limiting block is formed on the surface of the structural layer away from the electron migration layer.
[0047] Each non-first second sub-source layer is formed sequentially, wherein the step of forming each non-first second sub-source layer includes: forming a third sub-limiting block corresponding to the non-first second sub-source layer on the surface jointly formed by the adjacent previous second sub-source layer and the third sub-limiting block corresponding to the adjacent previous second sub-source layer, wherein the orthographic projection edge of each third sub-limiting block is outside the orthographic projection of the adjacent previous third sub-limiting block;
[0048] Remove the second limiting block and all third sub-limiting blocks so that the space occupied by the second limiting block and all the third sub-limiting blocks forms the groove.
[0049] A third aspect of this embodiment provides a semiconductor device, the semiconductor device comprising a semiconductor switching device as described in any one of claims 1-4.
[0050] The beneficial effects of the embodiments of this application compared with the prior art are as follows: By using the semiconductor device manufacturing method provided in this application, a groove is formed on the source layer by forming a filling block and a plurality of limiting blocks, extending to the side surface of the electron migration layer away from the drain layer. Furthermore, the angle formed between the plane containing at least a portion of the inner sidewall of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle, which improves the problem of tip discharge defects at the bottom of the groove, avoids damage to the inside of the semiconductor device, and thereby improves the performance of the semiconductor device and apparatus. Attached Figure Description
[0051] Figure 1 This is a schematic diagram of the structure of a semiconductor switching device provided in an embodiment of this application;
[0052] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor switching device, as provided in this application embodiment;
[0053] Figure 3a A schematic diagram illustrating the manufacturing process of a drain layer and an electron migration layer provided in an embodiment of this application;
[0054] Figure 3b One of the schematic diagrams illustrating the manufacturing process of a single first sub-source layer and a single second sub-source layer;
[0055] Figure 3c Schematic diagram of the manufacturing process of a single first sub-source layer and a single second sub-source layer (Part 2);
[0056] Figure 3d Schematic diagram three of the manufacturing process for a single first sub-source layer and a single second sub-source layer;
[0057] Figure 3e Schematic diagram four of the manufacturing process for a single first sub-source layer and a single second sub-source layer;
[0058] Figure 3f Fifth schematic diagram of the manufacturing process of a single first sub-source layer and a single second sub-source layer;
[0059] Figure 3g Schematic diagram of the manufacturing process of a single first sub-source layer and a single second sub-source layer (Part 6);
[0060] Figure 3h Schematic diagram seven of the manufacturing process for a single first sub-source layer and a single second sub-source layer;
[0061] Figure 3i Schematic diagram of the manufacturing process of a single first sub-source layer and a single second sub-source layer (Part 8);
[0062] Figure 3j Schematic diagram nine of the manufacturing process for a single first sub-source layer and a single second sub-source layer;
[0063] Figure 3k Schematic diagram ten of the manufacturing process for a single first sub-source layer and a single second sub-source layer;
[0064] Figure 4 A schematic diagram illustrating the manufacturing process of a semiconductor switching device provided in an embodiment of this application;
[0065] Figure 5a One of the schematic diagrams illustrating the manufacturing process of multiple first sub-source layers and multiple second sub-source layers;
[0066] Figure 5b Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers (Part 2);
[0067] Figure 5c Schematic diagram three of the manufacturing process for multiple first sub-source layers and multiple second sub-source layers;
[0068] Figure 5d Schematic diagram four of the manufacturing process for multiple first sub-source pole layers and multiple second sub-source pole layers;
[0069] Figure 5e Fifth schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers;
[0070] Figure 5f Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers (Part 6);
[0071] Figure 5g Schematic diagram seven of the manufacturing process for multiple first sub-source layers and multiple second sub-source layers;
[0072] Figure 5h Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers (Part 8);
[0073] Figure 5i Schematic diagram nine of the manufacturing process for multiple first sub-source layers and multiple second sub-source layers;
[0074] Figure 5j Schematic diagram ten of the manufacturing process for multiple first sub-source layers and multiple second sub-source layers;
[0075] Figure 5k 11. Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers;
[0076] Figure 5l 12. Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers;
[0077] Figure 5m Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers (Figure 13);
[0078] Figure 5n Fourteenth schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers;
[0079] Figure 5o Schematic diagram of the manufacturing process of multiple first sub-source layers and multiple second sub-source layers, number 15;
[0080] Figure 6This is a schematic diagram illustrating the manufacturing process of another semiconductor switching device provided in an embodiment of this application. Detailed Implementation
[0081] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0082] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0083] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0085] In traditional semiconductor device manufacturing processes, semiconductor materials typically possess rigid physical properties, resulting in poor flatness at deeper etched surfaces. This unevenness easily leads to point discharge. Furthermore, excessively sharp corners in the grooves within the device can further contribute to point discharge, causing damage to the semiconductor device and affecting its performance. Therefore, this application provides a semiconductor switching device, a manufacturing method, and a semiconductor apparatus.
[0086] Figure 1 A schematic diagram of the structure of a semiconductor switching device provided in an embodiment of this application is shown. Figure 1As shown, the semiconductor switching device includes a drain layer 100, an electron migration layer 101, a source layer 102, and a gate 103. The electron migration layer 101 is formed on one side surface of the drain layer 100; the source layer 102 is formed on the side surface of the electron migration layer 101 away from the drain layer 100, and includes a groove 104 extending to the side surface of the electron migration layer 101 away from the drain layer 100; the gate 103 is formed in the groove 104 and is insulated from the source layer 102; wherein, the angle formed between the plane containing at least a portion of the inner sidewall of the groove 104 and the plane containing the surface of the electron migration layer 101 near the source layer 102 is an obtuse angle.
[0087] Furthermore, the semiconductor switching device also includes an insulating layer 105 filled in the groove 104 to isolate the gate 103 and the source layer 102. When the gate 103 forms a conductive channel between the source layer 102 and the drain layer 100 under appropriate voltage control, the current can be turned on.
[0088] For example, the material of the insulating layer 105 may include one or more layers of insulating material, such as silicon oxide, silicon nitride, low dielectric constant material, and combinations thereof.
[0089] In this embodiment, the angle between the plane containing part of the inner sidewall of the groove 104 and the plane containing the surface of the electron migration layer 101 near the source layer 102 is any value between 120° and 150°. Setting the angle to an obtuse angle can improve the tip discharge problem of semiconductor devices to a certain extent.
[0090] In this embodiment, the drain layer 100, electron migration layer 101, source layer 102, and gate 103 are made of epitaxially grown semiconductor materials. The epitaxially grown semiconductor materials may include silicon, silicon nitride, silicon carbide, gallium nitride, and gallium arsenide, etc. The epitaxially grown semiconductor materials of the drain layer 100 and source layer 102 may be doped with p-type dopants or n-type dopants. The drain layer 100, electron migration layer 101, source layer 102, and gate 103 may use different materials and doping methods from each other.
[0091] Furthermore, embodiments of this application also provide a semiconductor device, which includes, as shown in the example below. Figure 1 The semiconductor switching device shown.
[0092] Figure 2 A flowchart illustrating a semiconductor switching device manufacturing method according to an embodiment of this application is shown below. Figure 2 In this embodiment of the application, the method for manufacturing a semiconductor switching device includes:
[0093] Step 200: Form the drain layer.
[0094] Step 201: Form an electron migration layer on one side surface of the drain layer.
[0095] For example, such as Figure 3a As shown, Figure 3a A drain layer 300 is formed in the middle, and an electron migration layer 301 is formed on one side surface of the drain layer 300. The drain layer 300 and the electron migration layer 301 are made of semiconductor materials, such as silicon nitride, silicon carbide, gallium nitride and other semiconductor materials. The formation method can be chemical vapor deposition, which uses gaseous or vapor-state reactants to react at the gas phase or gas-solid interface to generate solid semiconductor materials.
[0096] Step 202: Form a source layer on the side surface of the electron migration layer away from the drain layer; form a groove on the source layer that extends to the side surface of the electron migration layer away from the drain layer, wherein the angle between the plane containing at least a portion of the inner sidewall of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle.
[0097] like Figures 3b to 3g As shown, the method for forming the source layer 311 includes:
[0098] A first limiting block 304 is formed on the surface of the electron migration layer 301 away from the drain layer 300;
[0099] For example, the specific formation process of the first limiting block 304 is as follows: a limiting block is deposited on the surface of the electron migration layer 301 away from the drain layer 300; photoresist is coated on the limiting block; a mask 302 is formed on the area of the electron migration layer 301 where the source layer 311 is to be formed; after exposure, the unexposed portion of the limiting block is removed to form the limiting block 303. Figure 3b As shown. Etching and removing the photoresist from the limiting block 303 will form... Figure 3c The first limit block 304 in the middle.
[0100] It should be noted that the photoresist in this embodiment is only a negative photoresist as an example to explain the formation process of the first limiting block. In actual applications, the photoresist can also be a positive photoresist. In this case, the hollow area and the non-hollow area in the mask need to be interchanged, which will not be elaborated on here.
[0101] Furthermore, the limiting block 303 and the first limiting block 304 can be made of glass or silicon dioxide, etc., and a limiting block can be deposited on the surface of the electron migration layer 301 away from the drain layer 300 by chemical vapor deposition. When the material of each limiting block is glass, the etching of the corresponding limiting block 301 can be carried out by wet etching, that is, the limiting block 303 made of glass can be etched by using highly corrosive hydrofluoric acid to form the first limiting block 304.
[0102] See Figure 3d A source material layer 305 is formed on one side surface of the electron migration layer 301, located outside the first limiting block 304. The source material layer 305 can be formed outside the first limiting block 304 by epitaxial growth technology, and the source material layer 305 is at the same height as the first limiting block 304.
[0103] Furthermore, removing the first limiting block 304 exposes the space occupied by the first limiting block 304, forming a shape as shown in the image. Figure 3e The structure shown allows for the removal of the first limiting block 304 using highly corrosive hydrofluoric acid.
[0104] Furthermore, such as Figure 3f As shown, the sidewalls of the source material layer 305 facing the space occupied by the first limiting block 304 are smoothed to form a shape as shown. Figure 3g The first sub-source pole layer 307 and the empty space 306 are shown.
[0105] For example, a method for smoothing the sidewall of the space occupied by the source material layer 305 toward the first limiting block 304 can be performed using an etchant formed by a combination of HCl, CF4 and HBr.
[0106] Furthermore, a second limiting block 308 is formed within the empty space 306. The second limiting block is flush with the first sub-source electrode layer 307, forming a shape as shown below. Figure 3h The structure shown. The second limiting block 308 can be formed within the empty space 306 by chemical vapor deposition.
[0107] For example, see Figure 3i and Figure 3j A third limiting block 309 is formed on the surface of the second limiting block 308 away from the electron migration layer 301, and a second sub-source layer 310 located outside the third limiting block 309 is formed on the surface of the first sub-source layer 307 away from the electron migration layer 301. The third limiting block 309 can be formed by chemical vapor deposition, and the second sub-source layer 310 can be formed by epitaxial growth technology.
[0108] Furthermore, remove Figure 3j The third limiting block 309 and the second limiting block 308 in the middle, so that the space occupied by the third limiting block 309 and the second limiting block 308 forms a groove 312, such as Figure 3k As shown, the first sub-source layer 307 and the second sub-source layer 310 are stacked to form the source layer 311.
[0109] It should be noted that the surface of the second limiting block 308 away from the electron migration layer 301 has the same shape and size as the surface of the third limiting block 308 close to the electron migration layer 301. The orthographic projection edge of the third limiting block 308 is outside the orthographic projection of the first limiting block 304. Furthermore, each limiting block is made of the same material, which can be glass or silicon dioxide.
[0110] In other embodiments of this application, see [reference]. Figure 4 The method for forming the source layer 402 includes: forming a first limiting block on the side surface of the electron migration layer 400 away from the drain layer 401; forming a source material layer located outside the first limiting block on the side surface of the electron migration layer; removing the first limiting block to expose the space occupied by the first limiting block; and smoothing the sidewall of the source material layer facing the space occupied by the first limiting block to form the source layer 402 and the groove 403.
[0111] For example, in the embodiments of this application, the material of each limiting block can be glass or silicon dioxide, the forming method can be chemical vapor deposition, and the removal method can be hydrofluoric acid reaction with strong corrosiveness.
[0112] For example, a method for smoothing the sidewall of the source material layer facing the space occupied by the first limiting block can be performed using an etchant formed by a combination of HCl, CF4 and HBr.
[0113] In another embodiment of this application, see [reference] Figure 5o The source layer 520 includes a plurality of first sub-source layers and second sub-source layers stacked sequentially along a direction away from the electron migration layer 501. The method for forming the source layer 520 is as follows:
[0114] The first sub-limiting block 504 is formed on the surface of the electron migration layer 501 away from the drain layer 500, as follows: Figure 5b As shown. Exemplarily, the formation process of the first sub-limiting block 504 is as follows: a sub-limiting block is deposited on the surface of the electron migration layer 501 away from the drain layer 500; photoresist is coated on the sub-limiting block; a mask 502 is formed on the area of the electron migration layer 501 where the source layer 520 is to be formed; after exposure, the unexposed portion of the sub-limiting block is removed, forming the sub-limiting block 503 as shown. Figure 5a As shown, further etching of the sub-limiting block 503 and removal of the photoresist will form... Figure 5b The first sub-limiting block 504 in the middle.
[0115] For further details, please refer to [link / reference]. Figure 5c A first sub-source layer 505 is formed on one side surface of the electron migration layer 501, located outside the first sub-limiting block 504.
[0116] Repeat the above steps, see below. Figures 5d to 5f On the surface jointly formed by the first sub-source layer 505 and the first sub-limiting block 504, a sub-limiting block 506 is formed as follows: Figure 5d As shown in the diagram; the sub-limiting block 506 is etched to form a second first sub-limiting block 507, and a second first sub-source layer 508 is formed on the surface jointly formed by the first first sub-source layer 505 and the first first sub-limiting block 504, located on the second first sub-limiting block 507, forming as shown in the diagram. Figure 5e The structure in the middle; furthermore, on the surface jointly formed by the second first sub-limiting block 507 and the second first sub-source layer 508, a third first sub-limiting block 509 and a third first sub-source layer 510 are formed, as shown. Figure 5f As shown.
[0117] It should be noted that the orthographic projection edge of the second first sub-limiting block 507 is outside the orthographic projection of the first first sub-limiting block 504, and the orthographic projection edge of the third first sub-limiting block 509 is outside the orthographic projection of the second first sub-limiting block 507.
[0118] Furthermore, by removing the first first sub-limiting block 504, the second first sub-limiting block 507, and the third first sub-limiting block 509, the space 511 occupied by all the first sub-limiting blocks is exposed, forming a structure as follows: Figure 5g The structure shown; as Figure 5h As shown, the sidewalls of each first sub-source layer facing the space 511 occupied by all first sub-limiting blocks are smoothed to form a shape as shown. Figure 5i The empty space shown is 512; see reference. Figure 5j A second sub-limiting block 513 is formed in the empty space 512, and the second sub-limiting block 513 is flush with the structure formed by stacking all the first sub-source layers.
[0119] For example, the method of smoothing the sidewalls of each first sub-source layer toward the space 511 occupied by all first sub-limiting blocks can be performed using an etchant formed by a combination of HCl, CF4 and HBr.
[0120] See Figure 5k A first third sub-limiting block 514 is formed on the surface of the second sub-limiting block 513 away from the electron migration layer 501, and as follows: Figure 5l As shown, a first second sub-source layer 515 is formed on the surface of the structural layer formed by stacking all the first sub-source layers away from the electron migration layer 501, located outside the first third sub-constraint block.
[0121] Furthermore, each non-first second sub-source pole layer is formed sequentially, such as... Figures 5m to 5n As shown, Figure 5mIn the middle, on the surface formed by the first second sub-source layer 515 and the first third sub-limiting block 514, a second second sub-source layer 517 and a second third sub-limiting block 516 are formed. Figure 5n In the middle, on the surface jointly formed by the second second sub-source layer 517 and the second third sub-limiting block 516, a third second sub-source layer 519 and a third third sub-limiting block 518 are formed.
[0122] It should be noted that the orthographic projection edges of the first third sub-limiting block 514, the second third sub-limiting block 516, and the third third sub-limiting block 518 coincide.
[0123] For further details, please refer to [link / reference]. Figure 5o Remove the second limiting block 513 and all the third sub-limiting blocks so that the space occupied by the second limiting block 513 and all the third sub-limiting blocks forms a groove 521, and the sub-source layers are stacked to form a source layer 520.
[0124] In the embodiments of this application, see Figure 5o The angle θ formed by the plane of the inner sidewall of the groove 521 and the plane of the electron migration layer near the source layer can be any value between 120° and 150°.
[0125] It should be noted that, in this embodiment, only the formation process of three first sub-source layers and three second sub-source layers is taken as an example. In other embodiments of this application, the source layer includes multiple first sub-source layers and multiple second sub-source layers, which are stacked sequentially to form the source layer. This will not be elaborated further here.
[0126] Furthermore, in the embodiments of this application, the material of each limiting block can be glass or silicon dioxide, the forming method can be chemical vapor deposition, the removal method can be hydrofluoric acid reaction with strong corrosiveness, and the forming method of each sub-source electrode layer can be epitaxial growth technology.
[0127] In another embodiment of this application, such as Figure 6As shown, the source layer 603 includes a plurality of first sub-source layers stacked sequentially along a direction away from the electron migration layer 601. The method of forming the source layer 603 includes: forming a first sub-limiting block on the side surface of the electron migration layer 601 away from the drain layer 600; forming a first first sub-source layer located outside the first sub-limiting block on the side surface of the electron migration layer 601; and sequentially forming each non-first first sub-source layer, wherein the step of forming each non-first first sub-source layer includes: forming a first sub-source layer on the adjacent previous first sub-source layer... On the surface formed together with the first sub-limiting block corresponding to the adjacent previous first sub-source layer, a first sub-limiting block corresponding to the non-first first sub-source layer is formed, wherein the orthographic projection edge of each first sub-limiting block is outside the orthographic projection of the adjacent previous first sub-limiting block; all first sub-limiting blocks are removed to expose the space occupied by all first sub-limiting blocks; the sidewalls of each first sub-source layer facing the space occupied by all first sub-limiting blocks are smoothed to form the source layer 603 and the groove 604.
[0128] It should be noted that the material of each limiting block can be glass or silicon dioxide, and the formation method can be chemical vapor deposition. The formation method of each sub-source electrode layer can be epitaxial growth technology. The method for smoothing the sidewalls of each first sub-source electrode layer facing the space occupied by all first sub-limiting blocks can be etched by an etchant composed of HCl, CF4 and HBr.
[0129] In this embodiment, step 204 involves forming a gate within the recess and insulating it from the source layer. For example... Figure 1 As shown, specifically, an insulating layer 105 can be formed in the groove 104 first, and then a gate 103 can be formed and housed in the insulating layer 105. Alternatively, the gate 103 can be formed in the groove 104 first, and then insulating material can be injected into the groove 104 to form an insulating layer 105 and wrap the gate 103.
[0130] This application provides a semiconductor switching device, wherein the source layer of the semiconductor switching device can be as follows: Figure 3k , Figure 4 , Figure 5o and Figure 6 As shown, it should be noted that the source layer in the above figure is related to... Figure 1 The source layer 102 in the original text has the same essence and function, and the only difference lies in the manufacturing process. Figure 5o Source layer 520 and Figure 6 Source layer 603 in the middle, Figure 3k Source layer 311 and Figure 4 The source layer 402 in the middle may require more sophisticated instruments to achieve the desired fabrication effect.
[0131] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0132] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0133] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0134] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for manufacturing a semiconductor switching device, characterized in that, The manufacturing method includes: Forming a drain layer; An electron migration layer is formed on one side surface of the drain layer; A source layer is formed on the surface of the electron migration layer away from the drain layer; A groove is formed on the source layer that extends to the side surface of the electron migration layer away from the drain layer, and the angle formed between the plane containing at least a portion of the sidewall of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle. A gate electrode is formed within the groove, and the gate electrode is insulated from the source layer; wherein, the method for forming the source layer includes: A first limiting block is formed on the surface of the electron migration layer away from the drain layer; A first sub-source layer is formed on one side surface of the electron migration layer, located outside the first limiting block; Remove the first limiting block to expose the space occupied by the first limiting block; The sidewall of the space occupied by the first sub-source electrode layer facing the first limiting block is smoothed to form an empty space; A second limiting block is formed within the empty space, and the second limiting block is flush with the first sub-source electrode layer; A third limiting block is formed on the side surface of the second limiting block away from the electron migration layer, and a second sub-source layer located outside the third limiting block is formed on the side surface of the first sub-source layer away from the electron migration layer. Remove the third limiting block and the second limiting block so that the space occupied by the third limiting block and the second limiting block forms the groove.
2. A method for manufacturing a semiconductor switching device, characterized in that, The manufacturing method includes: Forming a drain layer; An electron migration layer is formed on one side surface of the drain layer; A source layer is formed on the surface of the electron migration layer away from the drain layer; A groove is formed on the source layer that extends to the side surface of the electron migration layer away from the drain layer, and the angle formed between the plane containing at least a portion of the sidewall of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle. A gate is formed within the recess, the gate being insulated from the source layer; wherein the source layer comprises a plurality of first sub-source layers stacked sequentially along a direction away from the electron migration layer, and the method for forming the source layer includes: A first sub-limiting block is formed on the surface of the electron migration layer away from the drain layer; A first sub-source layer is formed on one side surface of the electron migration layer, located outside the first sub-limiting block; Each non-first first sub-source layer is formed sequentially, wherein the step of forming each non-first first sub-source layer includes: forming a first sub-limiting block corresponding to the non-first first sub-source layer on the surface jointly formed by the adjacent previous first sub-source layer and the first sub-limiting block corresponding to the adjacent previous first sub-source layer, wherein the orthographic projection edge of each first sub-limiting block is outside the orthographic projection of the adjacent previous first sub-limiting block; Remove all first sub-limiting blocks to expose the space occupied by all the first sub-limiting blocks; The sidewalls of each first sub-source layer facing the space occupied by all first sub-limiting blocks are smoothed to form the source layer and the groove.
3. A method for manufacturing a semiconductor switching device, characterized in that, The manufacturing method includes: Forming a drain layer; An electron migration layer is formed on one side surface of the drain layer; A source layer is formed on the surface of the electron migration layer away from the drain layer; A groove is formed on the source layer that extends to the side surface of the electron migration layer away from the drain layer, and the angle formed between the plane containing at least a portion of the sidewall of the groove and the plane containing the surface of the electron migration layer near the source layer is an obtuse angle. A gate is formed within the groove, the gate being insulated from the source layer; the source layer includes a plurality of first sub-source layers and second sub-source layers stacked sequentially along a direction away from the electron migration layer, the method for forming the source layer comprising: A first sub-limiting block is formed on the surface of the electron migration layer away from the drain layer; A first sub-source layer is formed on one side surface of the electron migration layer, located outside the first first sub-limiting block; Each non-first first sub-source layer is formed sequentially, wherein the step of forming each non-first first sub-source layer includes: forming a first sub-limiting block corresponding to the non-first first sub-source layer on the surface jointly formed by the adjacent previous first sub-source layer and the first sub-limiting block corresponding to the adjacent previous first sub-source layer, wherein the orthographic projection edge of each first sub-limiting block is outside the orthographic projection of the adjacent previous first sub-limiting block; Remove all first sub-limiting blocks to expose the space occupied by all first sub-limiting blocks, and smooth the sidewalls of each first sub-source layer facing the space occupied by all first sub-limiting blocks to form empty spaces; A second sub-limiting block is formed within the empty space, and the second sub-limiting block is flush with the structural layer formed by stacking all the first sub-source layers; A first third sub-limiting block is formed on the surface of the second sub-limiting block away from the electron migration layer, and a first second sub-source layer located outside the first third sub-limiting block is formed on the surface of the structural layer away from the electron migration layer. Each non-first second sub-source layer is formed sequentially, wherein the step of forming each non-first second sub-source layer includes: forming a third sub-limiting block corresponding to the non-first second sub-source layer on the surface jointly formed by the adjacent previous second sub-source layer and the third sub-limiting block corresponding to the adjacent previous second sub-source layer, wherein the orthographic projection edge of each third sub-limiting block is outside the orthographic projection of the adjacent previous third sub-limiting block; Remove the second sub-limiting block and all third sub-limiting blocks so that the space occupied by the second sub-limiting block and all the third sub-limiting blocks forms the groove.
4. The manufacturing method according to any one of claims 1-3, characterized in that, The manufacturing method further includes: An insulating layer is formed within the groove to isolate the gate and the source layer.
5. The manufacturing method according to any one of claims 1-3, characterized in that, The included angle is any value between 120° and 150°.
6. The manufacturing method according to any one of claims 1-3, characterized in that, The drain layer, the electron migration layer, the source layer, and the gate are made of silicon carbide.