A protection circuit for driving a switching device

Abstract

The application is a kind of switch device drive protection circuit, including drive signal and switch state detection circuit and envelope circuit. Drive signal and switch state detection circuit can send fault signal in the state that drive signal is true and MOS switch tube is not turned on, envelope circuit can lock PWM wave in time in fault state, and slowly release the lock after fault removal, to give a delay buffer time to the system. The protection circuit is completed by pure hardware, the protection function is more rapid and reliable, and the fault signal can be used as digital input of control chip to help the host computer to complete algorithm decision, so that the system is safer and more humanized.

Description

Technical Field

[0001] This invention relates to the field of electronic device protection technology, and more specifically to a switching device drive protection circuit. Background Technology

[0002] Switching devices are mostly used in bridge structures, including both rectification and inversion. Regardless of whether it's a three-phase bridge, H-bridge, or half-bridge structure, each bridge arm consists of two (or groups of) switching devices, serving as the upper and lower arms respectively. The upper and lower arms achieve complementary conduction through a PWM signal with a dead time. Due to the nature of the operation, the upper and lower arms cannot be turned on simultaneously, regardless of the bridge type. Otherwise, a DC bus voltage shoot-through will occur, causing a short circuit. This can trigger protection mechanisms or even burn out the circuit. Traditional hardware drive circuits only amplify the digital signals generated by the control system to meet the on / off conditions of the power switching devices. Traditional drive schemes achieve drive protection by adding a dead time, without detecting the actual on / off state of the power switching devices. This fails to form a closed loop. Even if the actual switching device is damaged, switching commands continue to be issued, which can lead to the system failing to perform normal control or even causing a short circuit on the bus and burning out the equipment. In terms of safety, timely hardware protection is not achieved. Summary of the Invention

[0003] To solve the above problems, a switching device drive protection circuit is provided.

[0004] The object of this invention is achieved in the following manner:

[0005] A switching device drive protection circuit, applicable to MOSFET and IGBT switching devices, further includes a switching device fault monitoring circuit and a blocking circuit. The switching device fault monitoring circuit includes operational amplifier A and operational amplifier B. The non-inverting input terminal of operational amplifier A is connected to the gate (G) of the MOSFET switching device, and the inverting input terminal of operational amplifier A is connected to the power supply Vcc through resistor R79. The non-inverting input terminal of operational amplifier B is connected to the drain (D) of the MOSFET switching device through diode D16, and the non-inverting input terminal of operational amplifier B is connected to the power supply Vee through resistor R76 and resistor R70. The inverting input terminal of operational amplifier B is connected to the power supply Vee through resistor R82. The output terminals of operational amplifier A and operational amplifier B are connected to the negative terminal of the emitter of an optocoupler. The positive terminal of the emitter of the optocoupler is connected to the power supply Vcc through pull-up resistor R61. The collector (C) of the optocoupler receiver is connected to the input terminal of the blocking circuit, and the emitter (E) of the optocoupler receiver is grounded.

[0006] The output terminals of operational amplifier A and operational amplifier B are connected to Vcc via resistor R67, and the positive and negative terminals of the optocoupler emitter are connected via resistor R64.

[0007] The collector (C) of the optocoupler receiver is connected to the power supply Vdd via resistor R58.

[0008] The input terminal of the wave-blocking circuit is connected to the positive terminal of diode D22, and the negative terminal of diode D22 is connected to the input terminal of the tri-state buffer of the tri-state output buffer chip. The input terminal of the wave-blocking circuit is connected to the power supply Vdd through resistor R89. The input terminal of the wave-blocking circuit is connected to the positive terminal of diode D23 through resistor R96. The negative terminal of D23 is connected to the positive terminal of capacitor C36. The negative terminal of capacitor C36 is connected to the negative terminal of diode D22 through resistor R98. The negative terminal of diode D23 is connected to the positive terminal of diode D24. The negative terminal of diode D24 is connected to the negative terminal of diode D22.

[0009] The tri-state output buffer chip is either ALS244C or 54LS244.

[0010] The operational amplifiers A and B mentioned above use the LM393 chip.

[0011] The voltage of the power supply Vee is -12V, the voltage of the power supply Vcc is +12V, and the voltage of the power supply Vdd is +5V.

[0012] Compared with the prior art, the present invention provides a hardware protection scheme for driving switching devices. This scheme can simultaneously detect the driving signal and the actual conduction state of the MOS switch, and report a driving fault when the switching signal is high but the MOS switch is not conducting. Hardware protection is completed instantly, blocking the PWM signal, and after the driving fault is recovered, the signal blocking is slowly released, giving the system a delayed response time. Attached Figure Description

[0013] Figure 1 This is the schematic diagram of a fault monitoring circuit.

[0014] Figure 2 This is the actual circuit diagram of the fault monitoring circuit.

[0015] Figure 3 This is the schematic diagram of the S2 switch fault monitoring circuit.

[0016] Figure 4 It is the connection method of the three bridge arms of a three-phase circuit.

[0017] Figure 5 This is a schematic diagram of the wave-blocking circuit for rapid wave blocking.

[0018] Figure 6This is a schematic diagram of the principle of slowly releasing the blockade circuit.

[0019] Figure 7 This is the actual circuit diagram of the wave blocking circuit. Detailed Implementation

[0020] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] A switching device drive protection circuit includes a front-end driving signal for a MOS switching transistor and a switching device fault monitoring circuit, and a back-end blocking circuit. The monitoring circuit is responsible for reporting a fault when the switching signal is true and the switching device is not conducting. The blocking circuit is responsible for quickly blocking the signal under fault conditions and slowly releasing the blocking after the fault is cleared.

[0024] like Figure 1-2 The diagram shows the schematic and actual circuit diagram of the switching device fault monitoring circuit. The drive signal for the front-end switching device MOS transistor is driven by an N-channel enhancement-mode MOS transistor. The switching device fault monitoring circuit includes operational amplifier A and operational amplifier B. Operational amplifier A and operational amplifier B can be LM393 chips or F158 chips from the domestic Aerospace 771 Research Institute. Operational amplifier A operates in comparator mode. The non-inverting input of operational amplifier A is connected to the gate (G) of the MOS transistor as the drive signal. The negative input of operational amplifier A is connected to the threshold voltage of the switching device (this voltage can be generated by voltage division through resistors from an independent power supply, generally around 8V). The inverting input of operational amplifier A is connected to the power supply Vcc through resistor R79. The voltage of Vcc is +12V. At the same time, the inverting input of operational amplifier A is connected to the power supply Vee through resistor R73. The voltage of Vee is -12V, so that the voltage of the inverting input of operational amplifier A is maintained at around +8V.

[0025] The operational amplifier B operates in the comparator mode. The non-inverting input terminal of the operational amplifier B is connected to the D pole of the MOS switch of the switching device through diodes D16 and D17. The D pole of the MOS switch is connected to Bat+. At the same time, the non-inverting input terminal of the operational amplifier B is connected to the power supply Vee through a resistor R76, and the non-inverting input terminal of the operational amplifier B is connected to Vcc through a resistor R70.

[0026] The inverting input terminal of the operational amplifier B is connected to the power supply Vee through a resistor R82, and the inverting input terminal of the operational amplifier B is connected to the power supply Vcc through a resistor R83, so that the voltage at the inverting input terminal of the operational amplifier B is maintained at about +4V. This voltage is the on-voltage drop of the MOS switch.

[0027] The output terminals of the operational amplifier A and the operational amplifier B are connected to the negative pole of the emitter of the optocoupler. The output terminals of the operational amplifier A and the operational amplifier B are connected to Vcc through a resistor R67. The positive pole of the emitter of the optocoupler is connected to the power supply Vcc through a pull-up resistor R61. A resistor R64 is connected between the positive pole and the negative pole of the emitter of the optocoupler. The C pole of the receiving end of the optocoupler is connected to the input terminal of the wave-blocking circuit through a resistor R58. The voltage of Vdd is +5V. The C pole of the receiving end of the optocoupler is connected to the input terminal of the wave-blocking circuit, and the E pole of the receiving end of the optocoupler is grounded.

[0028] Pin 1 of the optocoupler represents the positive pole of the emitter, pin 2 of the optocoupler represents the negative pole of the emitter, pin 3 of the optocoupler represents the E pole of the receiving end, and pin 4 of the optocoupler represents the C pole of the receiving end, as Figure 2 described.

[0029] After the above connections, there are a total of 4 output states for the two operational amplifier arrangements. Taking the MOS switch of S1 in Figure 1 as an example, the 4 output states are analyzed as follows:

[0030] (1) The MOS switch does not receive a switching signal, Vg1 < VA1- (where Vg1 is the voltage at the non-inverting input terminal of the operational amplifier A, that is, the voltage at the G pole of the MOS switch, and VA1- is the voltage at the inverting input terminal of the operational amplifier A. Here, the voltage of the electric eye is about +8V, and the same applies hereinafter). The output of the operational amplifier A is low level, the MOS switch is not turned on, Vd1 > VB1- (the voltage of Vd1 is the voltage at the D pole of the MOS switch, and the voltage of VB1- is the voltage at the inverting input terminal of the operational amplifier B. Here, the voltage is about +4V). The output of the operational amplifier B is in a high-impedance state, the overall output is low level, the optocoupler is turned on, and the fault signal is low level;

[0031] (2) The MOS switch tube does not receive the switching signal, Vg1 < VA1-, the output of operational amplifier A is low level, the MOS switch tube conducts (even if the switch tube does not receive the conduction signal, it may be mis-conducted by the voltage of stray inductance and capacitance, etc.), Vd1 < VB1-, the output of operational amplifier B is low level, the overall output is low level, the optocoupler conducts, and the fault signal is low level;

[0032] (3) The MOS switch tube receives the switching signal, Vg1 > VA1-, the output of operational amplifier A is in high impedance state, the MOS switch tube does not conduct, Vd1 > VB1-, the output of operational amplifier B is in high impedance state, the overall output is affected by the pull-up level and outputs high level, the optocoupler does not conduct, and the fault signal is high level;

[0033] (4) The MOS switch tube receives the switching signal, Vg1 > VA1-, the output of operational amplifier A is in high impedance state, the MOS switch tube conducts, Vd1 < VB1-, the output of operational amplifier B is low level, the overall output is low level, the optocoupler conducts, and the fault signal is low level.

[0034] In summary, only when the G-pole signal is high (greater than VT), and the voltage between the D and S poles of the MOS switch tube is greater than VDS (the MOS switch tube does not conduct), that is, when the switching signal is true but the switching device does not conduct, the optocoupler conducts and the fault signal outputs high level, it can be determined that the switching device has an open-circuit fault, and the output is low level at other times, and the switching device is in normal working condition. Thus, the effect of detecting the working state of the MOS switch tube device is achieved.

[0035] A three-phase circuit has three bridge arms, and one bridge arm has two switch tubes (such as Figure 1 the s1 MOS switch tube and the s2 MOS switch tube in the figure), and each MOS switch tube is equipped with 1 monitoring circuit, so a total of 6 monitoring circuits are required. In the above text, only the s1 MOS switch tube of the upper bridge arm is taken as an example to elaborate on the working principle of the monitoring circuit. For the lower bridge arm, the working principle is the same. For example, for the connection method of the s2 MOS switch tube, a monitoring circuit on the right side of the figure is required. As Figure 3 shown, then connect the G pole of the switch tube S2 MOS switch tube to the S2 MOS switch tube and the D pole d2, and lead it to the principle of the corresponding switch tube. The principle here is the same as that of the MOS switch tube of S1 MOS switch tube, and it will not be introduced here.

[0036] The above is the principle introduction of a three-phase circuit with one bridge arm. The connection methods of the other two bridge arms are the same as those of the above bridge arm. As Figure 4 shown is the connection method of the MOS switch tubes of the three bridge arms of the three-phase circuit. The switching device fault monitoring circuit is the same as that of the S1 MOS tube and the S2 MOS tube, and it will not be repeated here.

[0037] Such as Figure 5-7 The diagram shows the schematic and actual circuit diagram of the wave blocking circuit. The input terminal of the wave blocking circuit is connected to the positive terminal of diode D22, and the negative terminal of diode D22 is connected to the input terminal of the tri-state buffer of the tri-state output buffer chip. The input terminal of the wave blocking circuit is connected to the power supply Vdd through resistor R89. The input terminal of the wave blocking circuit is connected to the positive terminal of diode D23 through resistor R96. The negative terminal of D23 is connected to the positive terminal of capacitor C36. The negative terminal of capacitor C36 is connected to the negative terminal of diode D22 through resistor R98. The negative terminal of diode D23 is connected to the positive terminal of diode D24, and the negative terminal of diode D24 is connected to the negative terminal of diode D22.

[0038] Figure 1 The high or low level of the fault output signal Err1 (the signal output from the collector terminal of the optocoupler) represents the state of the switching device. For a three-phase inverter circuit, there are six such switching devices. Each circuit has a fault monitoring circuit, whose output signals (Err1-Err6) are ORed by a gate to output the total fault signal Err. This signal is transmitted to the software control center and also connected to... Figure 3 The STOP pin (input terminal of the ripple circuit). Figure 5-6 This is a schematic diagram of the hardware wave blocking circuit. Figure 7 This is the actual circuit diagram of the hardware blocking circuit (all the chips used in the diagram can be replaced with domestic alternatives; the tri-state output buffer chip can be the ALS244C, or the domestically produced 54LS244 chip from Tianshui Tianguang Semiconductor can be used instead). Compared with software blocking, hardware blocking has higher response efficiency, greater reliability, and greater security.

[0039] like Figure 5-6 As shown, the STOP pin is the fault signal input terminal, connected to the tri-state output buffer via a delay circuit. The STOP pin is pulled up to Vdd through resistor R89, and connected to the positive terminal of capacitor C36 through resistor R96 and diode D23. Both the STOP pin and the positive terminal of capacitor C36 are connected to the input of the tri-state buffer through diode D22. Capacitor C36 forms a discharge circuit through diode D24 and resistor R98. As can be seen from the diagram, when the STOP signal changes from low to high, the input of the tri-state buffer immediately rises to a high level, while the voltage Vdd slowly charges capacitor C36 to the same voltage value as Vdd through resistor R96. When the STOP signal changes from high to low, the input of the tri-state buffer remains at Vdd (powered by the positive terminal of the capacitor), while the capacitor discharges through resistor R98. Only when the capacitor discharges to 0V does the input of the tri-state buffer drop to a low level. This achieves rapid circuit blocking when STOP is high and slow unlocking when STOP is low, giving the hardware a safe response time.

[0040] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered to be within the scope of this specification. When the combination of technical solutions contradicts each other or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the protection scope claimed by this invention. Moreover, for those skilled in the art, various changes, modifications, substitutions, and variations of these embodiments without departing from the spirit of the principles of this invention are all within the scope of this specification.

[0041] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several changes and improvements without departing from the overall concept of the present invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A switching device drive protection circuit, applicable to MOSFET and IGBT switching devices, characterized in that: It also includes a switching device fault monitoring circuit and a wave blocking circuit. The switching device fault monitoring circuit includes operational amplifier A and operational amplifier B. The non-inverting input terminal of operational amplifier A is connected to the gate (G) of the MOS switching transistor. The inverting input terminal of operational amplifier A is connected to the power supply Vcc through resistor R79. The inverting input terminal of operational amplifier A is connected to the power supply Vee through resistor R73. The non-inverting input terminal of operational amplifier B is connected to the drain (D) of the MOS switching transistor through diode D16. The non-inverting input terminal of operational amplifier B is connected to the power supply Vee through resistor R76. The non-inverting input terminal of operational amplifier B is connected to the power supply Vcc through resistor R70. The inverting input terminal of operational amplifier B is connected to the power supply Vee through resistor R82. The output terminals of operational amplifier A and operational amplifier B are connected to the negative terminal of the optocoupler emitter. The positive terminal of the optocoupler emitter is connected to the power supply Vcc through pull-up resistor R61. The collector (C) of the optocoupler receiver is connected to the input terminal of the wave blocking circuit. The emitter (E) of the optocoupler receiver is grounded.

2. The switching device drive protection circuit as described in claim 1, characterized in that: The output terminals of operational amplifier A and operational amplifier B are connected to Vcc via resistor R67, and the positive and negative terminals of the optocoupler emitter are connected via resistor R64.

3. The switching device drive protection circuit as described in claim 1, characterized in that: The collector (C) of the optocoupler receiver is connected to the power supply Vdd via resistor R58.

4. The switching device drive protection circuit as described in claim 1, characterized in that: The input terminal of the wave-blocking circuit is connected to the positive terminal of diode D22, and the negative terminal of diode D22 is connected to the input terminal of the tri-state buffer of the tri-state output buffer chip. The input terminal of the wave-blocking circuit is connected to the power supply Vdd through resistor R89. The input terminal of the wave-blocking circuit is connected to the positive terminal of diode D23 through resistor R96. The negative terminal of D23 is connected to the positive terminal of capacitor C36. The negative terminal of capacitor C36 is connected to the negative terminal of diode D22 through resistor R98. The negative terminal of diode D23 is connected to the positive terminal of diode D24. The negative terminal of diode D24 is connected to the negative terminal of diode D22.

5. The switching device drive protection circuit as described in claim 4, characterized in that: The tri-state output buffer chip is either ALS244C or 54LS244.

6. The switching device drive protection circuit as described in claim 1, characterized in that: The operational amplifiers A and B mentioned above use the LM393 chip.

7. The switching device drive protection circuit as described in claim 1, characterized in that: The voltage of the power supply Vee is -12V, the voltage of the power supply Vcc is +12V, and the voltage of the power supply Vdd is +5V.

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