A high-performance hybrid dither-type DPWM circuit structure

Abstract

The present invention discloses a high-performance hybrid dither-type DPWM circuit structure, which includes a dither module, an adder, a delay chain with controllable delay, a counter 1, a counter 2, a comparator, and an RS flip-flop. The delay chain with controllable delay includes a multiplexer and multiple delay units. The high-performance hybrid DPWM circuit structure proposed by the present invention can achieve high-frequency, high-linearity, high-resolution, and high-precision DPWM.

Description

Technical Field

[0001] The invention relates to the field of mixed signal integrated circuits, in particular to a digital switching power supply, realizing precise control of output voltage, and specifically to a high-performance mixed jitter type DPWM circuit structure. Background Art

[0002] In recent years, as people's requirements for the performance of consumer electronic products have been increasing, power management chips have gradually become a hot topic of research. As the energy center of electronic products, the output of the power supply must be efficient and stable. When the load changes suddenly, it can recover to the voltage and current required for normal operation in a very short time and maintain stable output.

[0003] Nowadays, DC-DC switching power supplies can be divided into two categories according to the implementation method of feedback control, namely analog control method (analog power supply) and digital control method (digital power supply). The analog switching power supply uses the error amplifier to calculate the difference and amplify the sampled signal, and generates a control signal through the feedback loop of the analog circuit to send it to the pulse width modulator (Pulse Width Modulation, PWM), modulating a specific duty cycle signal to control the on and off time of the power tube, thereby achieving the purpose of adjusting the output voltage. The digital switching power supply uses the analog-to-digital converter (Analog-to-Digital Converter, ADC) to sample and quantize the output voltage or current in real time, feeds back the control signal through a series of control algorithms, and uses the digital pulse width modulator (Digital Pulse Width Modulation, DPWM) to generate a specific duty cycle signal to control the on and off time of the power tube.

[0004] Compared with analog switching power supplies, digital switching power supplies have the advantages of good stability, strong anti-interference ability, flexible design, strong portability, low power consumption, and high system efficiency, so they have received widespread attention. The high-resolution DPWM module is an important component for realizing a fully digital, high-precision, and high-switching frequency digital switching power supply. Its resolution is directly related to the steady-state accuracy of the output voltage. High-precision DPWM has become a current research hotspot and is also a problem that needs to be solved urgently in digital control switching power supplies. Summary of the invention

[0005] In order to overcome the shortcomings of the prior art and achieve high frequency, high linearity, high resolution and high precision digital pulse width modulation (DPWM), the present invention aims to propose a high performance hybrid jitter type DPWM circuit structure, which is mainly used in the fields of digital switching power supplies.

[0006] To achieve the object of the present invention, a high-performance hybrid dither type DPWM circuit structure provided by the present invention includes a dither module, an adder, a delay chain with controllable delay, a counter 1, a counter 2, a comparator, and an RS flip-flop. The delay chain with controllable delay includes a multiplexer and a plurality of delay units.

[0007] The dither module is used to generate a corresponding dither sequence according to the externally input P-bit dither bits.

[0008] The adder is used to add the dither sequence to the externally input N-bit duty cycle to obtain an N-bit control word. At the same time, the N-bit control word is split into a high M-bit and a low N-M-bit.

[0009] The counter is used to count the externally input clock CLK and output a count value cnt[M-1:0].

[0010] The comparator 1 is used to compare the count value cnt[M-1:0] with the high M-bit. When the two are equal, a high-level signal A is output.

[0011] The comparator 2 is used to compare the count value cnt[M-1:0] with M’b0. When cnt[M-1:0] is all 0, a set signal Set is output.

[0012] The RS flip-flop is set according to the set signal Set, and the DPWM signal is set to a high level.

[0013] The A signal enters the delay chain with controllable delay to generate a delay signal as the input end of the multiplexer. The low N-M-bit is used as the selection end of the multiplexer, and the corresponding delay signal is output as a reset signal Reset. The Reset triggers the RS flip-flop to be reset, and the DPWM signal is reset to a low level.

[0014] Among them, there are N-M delay units in the delay chain with controllable delay. The delay time of each delay unit is controllable and can be controlled by the externally input D-bit delay selection SE[D-1:0].

[0015] Among them, the A signal enters the delay chain with controllable delay to generate a delay signal. Specifically:

[0016] The A signal enters the N-M-bit delay chain, and 2N-M delay signals Q0, Q1, Q2... Q2N-M-1 are sequentially generated as the input ends of the 2N-M:1 selector.

[0017] Among them, the digital "dither" of the dither module is achieved by the method of taking the average value in multiple switching cycles.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows.

[0019] A high-performance hybrid DPWM circuit structure proposed by the present invention can achieve high-frequency, high-linearity, high-resolution, and high-precision DPWM.

[0020] The structure proposed by the present invention overcomes the disadvantages of traditional counting-type DPWM and delay-type DPWM. When the counting-type DPWM has high precision, its operating frequency will increase exponentially, accompanied by large area and power consumption losses. Due to temperature or process deviations, the delay-type DPWM will cause unequal delay times in the delay chain, and the delay-type DPWM occupies a large area. However, the hybrid dither-type DPWM proposed by the present invention combines the structural characteristics of both, combines the advantages of high linearity and high precision of the counting-type DPWM, and the advantage of being able to operate at high-frequency clocks of the delay-type DPWM, and combines the principle of digital "dithering" to improve the resolution of the DPWM.

[0021] In addition, the present invention also proposes a delay chain structure with controllable delay.

[0022] In addition, the hybrid dither-type DPWM structure proposed by the present invention can make a compromise between the contradiction of high precision and high frequency, and at the same time uses the principle of digital "dithering" to improve the resolution of the DPWM. Brief Description of the Drawings

[0023] Figure 1 Overall structure diagram of the hybrid dither-type DPWM in the embodiment of the present application

[0024] Figure 2 Schematic diagram of 2-bit digital "dithering" in the embodiment of the present application;

[0025] Figure 3 Structure diagram of the 8-way selection delay module in the embodiment of the present application;

[0026] Figure 4 Structure diagram of the hybrid dither-type DPWM with 4-bit duty cycle + 2-bit dither bits in the embodiment of the present application;

[0027] Figure 5 Operating timing diagram in the embodiment of the present application. Detailed Description of the Embodiment

[0028] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0029] The following further describes the present invention in detail with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0030] For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] The present invention proposes a high-performance hybrid dither-type DPWM circuit structure, which is composed of modules such as a dither module, an adder, a delay chain with controllable delay, a multiplexer, a counter, a comparator, and an RS flip-flop. Its structure is as Figure 1 shown.

[0032] Among them, an external input of N-bit duty cycle and P-bit dither bits are input simultaneously. The dither module generates a corresponding dither sequence according to the P-bit dither bits. The digital "dither" realizes the conversion from low precision to high precision by taking the average value in multiple switching cycles. The specific principle will be described in detail below.

[0033] The adder adds the dither sequence to the N-bit duty cycle to obtain an N-bit control word. The N-bit control word is split into a high M-bit and a low N-M-bit, and the high and low bits are processed separately. The high M-bit is coarsely adjusted, and the low N-M-bit is finely adjusted, thereby improving the resolution.

[0034] The external input clock CLK triggers the M-bit counter to count, and outputs a count value cnt[M-1:0]. Comparator 1 compares the count value cnt[M-1:0] with the high M-bit, and outputs a high-level signal A when the two are equal. Comparator 2 compares the count value cnt[M-1:0] with M'b0, and outputs a set signal Set when cnt[M-1:0] is all 0. Set triggers the RS flip-flop to be set, and sets the DPWM signal to a high level.

[0035] There are N-M delay units in the delay chain with controllable delay. The delay time of each delay unit is controllable and can be controlled by the external D-bit delay selection SE[D-1:0]. The specific principle will be described in detail below. The A signal enters the N-M-bit delay chain and sequentially generates 2 N-M delay signals Q0, Q1, Q2... Q2 N-M-1 as the input terminals of the 2 N-M :1 selector. The low N-M bits are used as the selection terminals of the multiplexer, and the corresponding delay signals are output as the reset signal Reset. Reset triggers the RS flip-flop to be reset, and resets the DPWM signal to a low level. Thus, a DPWM signal with a duty cycle corresponding to the N-bit control word is generated.

[0036] First, the principle of digital "dithering" is explained. Taking 2 dithering bits as an example for illustration, that is, P = 2. The DPWM controls the on / off of the main circuit power transistor, thereby affecting the magnitude of the output voltage. Digital "dithering" is based on the principle of the average value of the output voltage. Assuming that among every 4 output DPWM waveforms, one pulse increases by the width corresponding to 1 LSB, then the average value of the output voltage will increase by the output voltage value corresponding to 1 / 4 LSB, and the resolution of the corresponding DPWM will also increase by 1 / 4 LSB, that is Similarly, 1 / 2 LSB and 3 / 4 LSB can be achieved, as Figure 2 shown. The 2-bit digital dithering lookup table is shown in Table 1. It is selected according to 2 dithering bits to generate the corresponding dithering sequence. In turn, within every 4 switching cycles, the N-bit duty cycle is added to the dithering sequence to obtain a new N-bit control word. Here, taking 2 dithering bits 2’b01 and 4-bit duty cycle 4’b0110 as an example for illustration, according to the lookup table, the generated dithering sequence is 0 0 0 1, which is added to the 4-bit duty cycle within 4 switching cycles in turn, obtaining 4’b0110, 4’b0110, 4’b0110, 4’b0111. The output DPWM duty cycles are Then, the DPWM duty cycle after being processed using the averaging principle is Thus, it can be seen that using 2-bit digital dithering, a DPWM equivalent to 6 bits is achieved based on 4-bit DPWM, improving the resolution by 2 bits. Similarly, using 3-bit digital dithering, a group of dithering sequences is generated every 8 switching cycles. The digital dithering lookup table is shown in

[0037] Table 2, and finally the resolution is improved by 3 bits.

[0038] 2-bit dither bit Digital dither sequence 00 0 0 0 0 01 0 0 0 1 10 0 1 0 1 11 0 1 1 1

[0039] Table 1

[0040] 3-bit dither bit Digital dither sequence 000 0 0 0 0 0 0 0 0 001 0 0 0 0 0 0 0 1 010 0 0 0 1 0 0 0 1 011 0 0 1 0 0 1 0 1 100 0 1 0 1 0 1 0 1 101 0 1 0 1 1 0 1 1 110 0 1 1 1 0 1 1 1 111 0 1 1 1 1 1 1 1

[0041] Table 2

[0042] Then, the principle of the delay chain with controllable delay is explained. The delay chain with controllable delay consists of a multiplexer and multiple delay units.

[0043] Here, taking the 8-way selectable delay module as an example for illustration, it consists of 28 delay units and an 8-to-1 selector, as Figure 3As shown. Each rectangular module is a standard delay cell in a standard process library. SE[2:0] represents a 3-bit selection code, and it adopts a structure of 8 delay paths and a 1-of-8 selector. There are 8 paths with different delays from IN to OUT. Each path includes the number of delay cells shown in the figure. SE[2:0] controls the selected path to achieve the purpose of adjusting the total delay of the delay cells. This module selects the corresponding transmission path from the 8 delay paths composed of standard cell blocks through a 1-of-8 selector, thereby obtaining the corresponding delay. If the delay of each delay cell is t0 and the delay of the multiplexer is td, the 8 delay paths can generate 8 different delays: td, td + t0, td + 2t0, td + 3t0, td + 4t0, td + 5t0, td + 6t0, td + 7t0. By selecting the required delay path through SE[2:0], a delay chain with controllable delay is realized.

[0044] The following takes 4-bit duty cycle, 2 high bits, 2 low bits, 2-bit dither, and 8-way delay controllability as an example for illustration, that is, N = 4, M = 2, P = 2, D = 3, and its structure diagram is as Figure 4 shown. Assume that the external input is a 4-bit duty cycle 4’b1010 and 2-bit digital “dither” 2’b01. The dither module generates the corresponding dither sequence 0 0 0 1 according to the 2-bit dither 2’b01. Each 4 switch cycles is a cycle, and the 2-bit duty cycle is added to the dither sequence in turn. In the first switch cycle, the 4-bit duty cycle is added to the dither sequence 0. In the second switch cycle, the 4-bit duty cycle is added to the dither sequence 0. In the third switch cycle, the 4-bit duty cycle is added to the dither sequence 0. In the fourth switch cycle, the 4-bit duty cycle is added to the dither sequence 1, thereby obtaining a 4-bit new duty cycle control word duty[3:0], that is, 4’b1010, 4’b1010, 4’b1010, 4’b1011. The 2-bit digital “dither” realizes the conversion from low precision to high precision by taking the average value in 4 switch cycles, improving the 2-bit resolution.

[0045] When the control word duty[3:0] = 4'b1010, the 4-bit control word is split into the high 2 bits 2'b10 and the low 2 bits 2'b10, which are processed separately. The high 2 bits are for coarse adjustment and the low 2 bits are for fine adjustment. The external clock CLK triggers the counter to count, and the count value cnt[1:0] is output. The comparator 2 compares the count value cnt[1:0] with all 0s. When cnt[1:0] = 2'b00, the set signal Set is output. Set triggers the RS flip-flop to be set, and the DPWM signal is set to high level. The comparator 1 compares the count value cnt[1:0] with the high 2 bits 2'b10. When cnt[1:0] = 2'b10, the high-level signal A is output. The signal A is used as the input signal of the delay chain, and is delayed by 3 delay units internally to generate delay signals Q0, Q1, Q2, and Q3 respectively, which are used as the input terminals of the 4-to-1 selector. The low 2 bits 2'b10 are used as the selection terminals of the selector, and the corresponding delay signal Q2 is output as the reset signal Reset. Reset triggers the RS flip-flop to be reset, and the DPWM signal is reset to low level. Thus, a DPWM signal with a duty cycle corresponding to the 4-bit control word is generated, and its working timing diagram is as shown in Figure 5 shown.

[0046] The delay of each delay unit in the delay chain is △t, and the period of the clock CLK needs to be exactly 4 times that of △t, that is, Tclk = 4△t. To meet this relationship, the above-mentioned delay unit with controllable delay can be used for delay control. Through the 3-bit delay control bit SE[2:0], a suitable delay path is selected, and then a suitable delay time is obtained. It can be seen from the timing diagram that since the input 4-bit duty cycle is 4'b1010 and the 2-bit jitter bits 2'b01 correspond to the jitter sequence 0 0 0 1, new duty cycle control words duty1[3:0] = 4'b1010, duty2[3:0] = 4'b1010, duty3[3:0] = 4'b1010, and duty4[3:0] = 4'b1011 are generated in turn within 4 switching cycles. Finally, the corresponding 10△t (coarse adjustment 8△t + fine adjustment 2△t), 10△t (coarse adjustment 8△t + fine adjustment 2△t), 10△t (coarse adjustment 8△t + fine adjustment 2△t), and 11△t (coarse adjustment 8△t + fine adjustment 3△t) are output. At the same time, using the principle of digital "jitter" averaging, the DPWM is improved by 1 / 4 LSB, which is equivalent to improving the resolution by 2 bits, and finally the resolution of 6 bits is achieved, realizing high-precision and high-resolution DPWM output.

[0047] The above is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A high-performance hybrid dither-type DPWM circuit structure, characterized in that, It includes a dithering module, an adder, a delay chain with controllable delay, a counter 1, a counter 2, a comparator, and an RS flip-flop. The delay chain with controllable delay includes a multiplexer and multiple delay units. The dithering module is used to generate a corresponding dithering sequence according to the externally input P-bit dithering bits. The adder is used to add the dithering sequence to the externally input N-bit duty cycle to obtain an N-bit control word. At the same time, the N-bit control word is split into a high M-bit and a low N-M-bit. The counter is used to count the externally input clock CLK and output a count value cnt[M-1:0]. The comparator 1 is used to compare the count value cnt[M-1:0] with the high M-bit. When they are equal, it outputs a high-level signal A. The comparator 2 is used to compare the count value cnt[M-1:0] with M’b0. When cnt[M-1:0] is all 0, it outputs a set signal Set. The RS flip-flop is set according to the set signal Set to set the DPWM signal to a high level. The A signal enters the delay chain with controllable delay to generate a delayed signal as the input end of the multiplexer. The low N-M-bit serves as the selection end of the multiplexer, and the corresponding delayed signal is output as a reset signal Reset. The Reset triggers the RS flip-flop to be reset, and the DPWM signal is reset to a low level.

2. The high-performance hybrid dither type DPWM circuit structure according to claim 1, wherein There are N-M delay units in the delay chain with controllable delay. The delay time of each delay unit is controllable and can be controlled by the externally input D-bit delay selection SE[D-1:0].

3. A high-performance hybrid dither-type DPWM circuit structure according to claim 2, characterized in that, The A signal enters the delay chain with controllable delay to generate a delayed signal. Specifically: The A signal enters an N-M bit delay chain, successively generating 2 N-M delayed signals Q0, Q1, Q2... Q2 N-M-1 , which serve as the input terminals of a 2 N-M :1 selector.

4. A high-performance hybrid dither-type DPWM circuit structure according to claim 1, characterized in that, The digital "dithering" of the dithering module is achieved by taking the average value over multiple switching cycles.

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