A comparator circuit and electronic device

Abstract

The application relates to a comparator circuit and electronic equipment in the technical field of integrated circuit design, which comprises a first high-voltage input stage circuit, a second high-voltage input stage circuit, a first low-voltage output stage circuit and a second low-voltage output stage circuit, the output end of the first high-voltage input stage circuit is connected with the input end of the first low-voltage output stage circuit, the output end of the second high-voltage input stage circuit is connected with the input end of the second low-voltage output stage circuit, the output end of the first low-voltage output stage circuit is connected with the output end of the second low-voltage output stage circuit, and the first high-voltage input stage circuit and the second high-voltage input stage circuit are complementary differential input stages, which have the advantages of wide common-mode input range, and break through the bottleneck of large parasitic capacitance of traditional comparator circuits.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a comparator circuit and an electronic device. Background Technology

[0002] Using existing comparators as receivers requires the transmitting device to increase power consumption and amplify the received signal amplitude to achieve gigabit-frequency signal reception. However, for transmitting devices that cannot increase power consumption, the signal received by conventional comparators will be distorted.

[0003] The traditional approach uses a rail-to-rail structure for the input stage, which has a wide common-mode input range. The second stage is a level conversion circuit implemented by an inverter. However, because the NMOS and PMPOS transistors in the traditional approach are high-voltage transistors, the transistor area is large, resulting in large parasitic capacitance and limited bandwidth. Summary of the Invention

[0004] This invention addresses the shortcomings of existing technologies by providing a comparator circuit and electronic device that has the advantage of a wide common-mode input range and overcomes the bottleneck of large parasitic capacitance in traditional comparator circuits.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A comparator circuit includes a first high-voltage input stage circuit, a second high-voltage input stage circuit, a first low-voltage output stage circuit, and a second low-voltage output stage circuit. The output terminal of the first high-voltage input stage circuit is connected to the input terminal of the first low-voltage output stage circuit, the output terminal of the second high-voltage input stage circuit is connected to the input terminal of the second low-voltage output stage circuit, and the output terminal of the first low-voltage output stage circuit is connected to the output terminal of the second low-voltage output stage circuit. The first high-voltage input stage circuit and the second high-voltage input stage circuit are complementary differential input stages.

[0007] Optionally, the first high-voltage input stage circuit receives a first differential voltage signal and outputs a first differential current signal. The first high-voltage input stage circuit includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor is connected to the first input terminal, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the second NMOS transistor is connected to the second input terminal, and the drains of both the first and second NMOS transistors are connected to the first low-voltage output stage circuit. The substrates of the first and second NMOS transistors are connected to ground and then grounded. Both the first and second NMOS transistors are high-voltage transistors.

[0008] Optionally, the first low-voltage output stage circuit includes an output circuit one and an output circuit two, the first differential voltage signal includes a differential voltage sub-signal one and a differential voltage sub-signal two, the first differential current signal includes a differential current sub-signal one and a differential current sub-signal two, the output circuit one receives the differential current sub-signal one, and the output circuit two receives the differential current sub-signal two.

[0009] Optionally, the output circuit includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The drain and gate of the third PMOS transistor are connected to the gate of the fourth PMOS transistor. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor and then connected to a low-voltage power supply. The drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor. The drain and gate of the third NMOS transistor are connected to the gate of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor and then grounded. The drain of the fourth NMOS transistor is the output. All three PMOS transistors are low-voltage transistors.

[0010] Optionally, the second output circuit includes a fifth PMOS transistor and a sixth PMOS transistor. The drain of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, and the source of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and then connected to a low-voltage power supply. The drain of the sixth PMOS transistor is the output, and both the fifth and sixth PMOS transistors are low-voltage transistors.

[0011] Optionally, the second high-voltage input stage circuit receives a second differential voltage signal and outputs a second differential current signal. The second high-voltage input stage circuit includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to a third input terminal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is connected to a fourth input terminal, and the drains of both the first and second PMOS transistors are connected to a second low-voltage output stage circuit. The substrates of the first and second PMOS transistors are connected to a high-voltage power supply, and both the first and second PMOS transistors are high-voltage transistors.

[0012] Optionally, the second low-voltage output stage circuit includes output circuit three and output circuit four, the second differential voltage signal includes differential voltage sub-signal three and differential voltage sub-signal four, the second differential current signal includes differential current sub-signal three and differential current sub-signal four, the output circuit three receives differential current sub-signal three, and the output circuit three receives differential current sub-signal four.

[0013] Optionally, the output circuit three includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The drain and gate of the fifth NMOS transistor are connected to the gate of the sixth NMOS transistor. The source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor and then grounded. The drain of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor. The drain and gate of the seventh PMOS transistor are connected to the gate of the eighth PMOS transistor. The source of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor and then connected to a low-voltage power supply. The drain of the eighth PMOS transistor is the output. All five NMOS transistors (fifth, sixth, seventh, and eighth) are low-voltage transistors.

[0014] Optionally, the output circuit four includes a seventh NMOS transistor and an eighth NMOS transistor. The drain and gate of the seventh NMOS transistor are connected to the gate of the eighth NMOS transistor. The source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor and then grounded. The drain of the eighth NMOS transistor is the output. Both the seventh and eighth NMOS transistors are low-voltage transistors.

[0015] An electronic device comprising a comparator circuit as described in any of the preceding claims.

[0016] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0017] By complementing the differential input stages of the first and second high-voltage input stages, the input stages have a common-mode input range from power supply to ground. Regardless of the size of the input signal, the comparator circuit can receive and process it. At the same time, by using high-voltage input at the input stage and low-voltage output at the output stage, the output signal is low-level, eliminating the need for a high-voltage to low-voltage level conversion circuit, thus saving circuit area. Furthermore, by using a combination of high-voltage and low-voltage transistors, the generation of parasitic capacitance is minimized. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a circuit diagram of a comparator circuit proposed in Embodiment 1. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0021] Example 1

[0022] like Figure 1 As shown, it should first be noted that in this embodiment, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are... Figure 1 The transistors are denoted as AN1, AN2, AN3, AN4, AN5, AN6, AN7, AN8, and AN9 respectively; the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are... Figure 1 The numbers are AP1, AP2, AP3, AP4, AP5, AP6, AP7, AP8, and AP9, respectively.

[0023] like Figure 1 As shown, a comparator circuit includes a first high-voltage input stage circuit, a second high-voltage input stage circuit, a first low-voltage output stage circuit, and a second low-voltage output stage circuit. The output terminal of the first high-voltage input stage circuit is connected to the input terminal of the first low-voltage output stage circuit, the output terminal of the second high-voltage input stage circuit is connected to the input terminal of the second low-voltage output stage circuit, and the output terminal of the first low-voltage output stage circuit is connected to the output terminal of the second low-voltage output stage circuit. The first high-voltage input stage circuit and the second high-voltage input stage circuit are complementary differential input stages. Because the outputs are in the same direction, the first low-voltage output stage circuit and the second low-voltage output stage circuit are directly connected to drive the next stage. This input stage structure has a common-mode input range from power supply to ground.

[0024] The first high-voltage input stage circuit receives a first differential voltage signal and outputs a first differential current signal. The first high-voltage input stage circuit includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor is connected to the first input terminal, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the second NMOS transistor is connected to the second input terminal, and the drains of both the first and second NMOS transistors are connected to the first low-voltage output stage circuit. The substrates of the first and second NMOS transistors are connected to the ground and then grounded. Both the first and second NMOS transistors are high-voltage transistors.

[0025] Furthermore, the first input terminal is the reference voltage VREF, the second input terminal is the comparison voltage VIN, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, and then connected to the drain of the ninth NMOS transistor. The gate of the ninth NMOS transistor is connected to the high-voltage power supply VDDQ, and the source of the ninth NMOS transistor is grounded. The ninth NMOS transistor is also a high-voltage transistor. Thus, the first differential voltage signal is converted into a first differential current signal through the first NMOS transistor and the second NMOS transistor, and then output to the next stage.

[0026] The second high-voltage input stage circuit receives the second differential voltage signal and outputs the second differential current signal. The second high-voltage input stage circuit includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to the third input terminal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is connected to the fourth input terminal, and the drains of both the first and second PMOS transistors are connected to the second low-voltage output stage circuit. The substrates of the first and second PMOS transistors are connected to a high-voltage power supply, and both the first and second PMOS transistors are high-voltage transistors.

[0027] Furthermore, the third input terminal is also the reference voltage VREF, and the fourth input terminal is also the comparison voltage VIN. The sources of the first PMOS transistor and the second PMOS transistor are connected to a ninth PMOS transistor, which is connected to the drain of the ninth PMOS transistor. The source of the ninth PMOS transistor is connected to the high-voltage power supply VDDQ, and the gate of the ninth PMOS transistor is grounded. The ninth PMOS transistor is also a high-voltage transistor. Thus, the second differential voltage signal is converted into a second differential current signal through the first PMOS transistor and the second PMOS transistor, and then output to the next stage.

[0028] Specifically, the first NMOS transistor and the second NMOS transistor form an NMOS differential pair, and the first PMOS transistor and the second PMOS transistor form a PMOS differential pair. Thus, the NMOS differential pair and the PMOS differential pair together form a complementary differential input stage. Since the outputs are in the same direction, they can be directly connected to drive the next stage. Furthermore, this input stage circuit structure enables the circuit to have a common-mode input range from power supply to ground, making the common-mode input range wider.

[0029] On the other hand, the first low-voltage output stage circuit includes output circuit one and output circuit two, the first differential voltage signal includes differential voltage sub-signal one and differential voltage sub-signal two, the first differential current signal includes differential current sub-signal one and differential current sub-signal two, output circuit one receives differential current sub-signal one, and output circuit two receives differential current sub-signal two. The second low-voltage output stage circuit includes output circuit three and output circuit four, the second differential voltage signal includes differential voltage sub-signal three and differential voltage sub-signal four, the second differential current signal includes differential current sub-signal three and differential current sub-signal four, output circuit three receives differential current sub-signal three, and output circuit three receives differential current sub-signal four.

[0030] Specifically, before the comparison, the circuit converts the differential voltage sub-signal one into a differential current sub-signal one and transmits it to the output circuit one, which receives the differential current sub-signal one; the second NMOS transistor converts the differential voltage sub-signal two into a differential current sub-signal two and transmits it to the output circuit two, which receives the differential current sub-signal two; the first PMOS transistor converts the differential voltage sub-signal three into a differential current sub-signal three and transmits it to the output circuit three, which receives the differential current sub-signal three; the second PMOS transistor converts the differential voltage sub-signal four into a differential current sub-signal four and transmits it to the output circuit four, which receives the differential current sub-signal four.

[0031] The output circuit includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The drain of the first NMOS transistor is connected to the source of the third PMOS transistor. The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor and then connected to a low-voltage power supply. The drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and then connected to the gate of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor and then grounded. The drain of the fourth NMOS transistor outputs OUT. All three PMOS transistors are low-voltage transistors. The third PMOS transistor and the fourth PMOS transistor form a current mirror.

[0032] Output circuit two includes a fifth PMOS transistor and a sixth PMOS transistor. The drain of the second NMOS transistor is connected to the source of the fifth PMOS transistor. The drain of the fifth PMOS transistor is connected to the gate and then to the gate of the sixth PMOS transistor. The source of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and then to a low-voltage power supply. The drain of the sixth PMOS transistor is the output, that is, the drain of the sixth PMOS transistor is connected to the source of the fourth NMOS transistor and then outputs OUT. Both the fifth and sixth PMOS transistors are low-voltage transistors. The fifth and sixth PMOS transistors form a current mirror.

[0033] Furthermore, by using a hybrid approach of high-voltage transistors as inputs and low-voltage transistors as outputs, the input signal voltage range is high, while the output signal voltage range is low. For example, the high-voltage range can be 0–1.8V, and the low-voltage range can be 0–1.1V, i.e., VDDQ = 1.8V and VDD = 1.1V. Thus, the circuit can perform signal comparison with the same amplitude input signal without requiring higher gain. Moreover, since the low-voltage transistor is smaller than the high-voltage transistor, its parasitic parameters are smaller, thereby minimizing the generation of parasitic capacitance and achieving high bandwidth.

[0034] Output circuit three includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The source of the first PMOS transistor is connected to the drain of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor. The source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor and then grounded. The drain of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor. The drain of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor. The source of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor and then connected to the low-voltage power supply VDD. The drain of the eighth PMOS transistor outputs OUT. All five NMOS transistors (the fifth, sixth, seventh, and eighth) are low-voltage transistors. The fifth and sixth NMOS transistors form a current mirror.

[0035] The output circuit four includes a seventh NMOS transistor and an eighth NMOS transistor. The source of the second PMOS transistor is connected to the drain of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the gate and then to the gate of the eighth NMOS transistor. The source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor and then grounded. The drain of the eighth NMOS transistor is the output, that is, the source of the eighth NMOS transistor is connected to the drain of the eighth PMOS transistor and then outputs OUT. Both the seventh and eighth NMOS transistors are low-voltage transistors. The seventh and eighth NMOS transistors form a current mirror.

[0036] Since the input signal of the first and second PMOS transistors is at most 1.8V, they are high-voltage transistors. The power supply voltage is VDDQ = 1.8V. Because the fifth and seventh NMOS transistors are connected in a diode manner, their gate and drain voltages are clamped to about 0.7V, which will not cause overvoltage and ensure the safe use of the circuit.

[0037] Furthermore, VREF is connected to the reference potential VDDQ / 2 = 0.9V, and VIN is connected to the input signal. For the first high-voltage input stage circuit, when the input signal is high, the current of the second NMOS transistor increases, and the currents of the fifth and sixth PMOS transistors also increase. Since the gate of the first NMOS transistor is connected to the reference potential VREF, the currents of the first, third, and fourth PMOS transistors remain unchanged, resulting in an increase in the output OUT voltage. In other words, when VIN is high, the OUT output is high. For the second high-voltage input stage circuit, when the input signal is high, the current of the second PMOS transistor decreases, and the currents of the seventh and eighth NMOS transistors also decrease. Since the gate of the first PMOS transistor is connected to the reference potential VREF, the currents of the first, fifth, sixth, seventh, and eighth PMOS transistors remain unchanged, resulting in an increase in the output OUT voltage. In other words, when VIN is high, the OUT output is high.

[0038] On the other hand, for the first high-voltage input stage circuit, when the input signal is low, the current of the second NMOS transistor decreases, and the currents of the fifth and sixth PMOS transistors also decrease. Since the gate of the first NMOS transistor is connected to the reference potential VREF, the currents of the first NMOS transistor, third PMOS transistor, fourth PMOS transistor, third NMOS transistor, and fourth NMOS transistor remain unchanged, thus reducing the output OUT voltage. In other words, when VIN is low, the OUT output is low. For the second high-voltage input stage circuit, when the input signal is low, the current of the second PMOS transistor increases, and the currents of the seventh and eighth NMOS transistors also increase. Since the gate of the first PMOS transistor is connected to the reference potential VREF, the currents of the first PMOS transistor, fifth NMOS transistor, sixth NMOS transistor, seventh PMOS transistor, and eighth PMOS transistor remain unchanged, thus reducing the output OUT voltage. In other words, when VIN is low, the OUT output is low. This achieves the voltage comparison while ensuring that the circuit has a small parasitic capacitance and high bandwidth.

[0039] Example 2

[0040] An electronic device is provided, comprising a comparator circuit as described in Embodiment 1. The electronic device described in this embodiment may be a DDR memory. The comparator circuit comprises a first high-voltage input stage circuit, a second high-voltage input stage circuit, a first low-voltage output stage circuit, and a second low-voltage output stage circuit. The output terminal of the first high-voltage input stage circuit is connected to the input terminal of the first low-voltage output stage circuit, the output terminal of the second high-voltage input stage circuit is connected to the input terminal of the second low-voltage output stage circuit, and the output terminal of the first low-voltage output stage circuit is connected to the output terminal of the second low-voltage output stage circuit. The first high-voltage input stage circuit and the second high-voltage input stage circuit are complementary differential input stages.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any form or substance. It should be noted that those skilled in the art can make various improvements and additions without departing from the method of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention. Any modifications, alterations, and equivalent changes made by those skilled in the art based on the above-disclosed technical content without departing from the spirit and scope of the present invention are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, and evolutions made to the above embodiments based on the essential technology of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A comparator circuit, characterized in that, The circuit includes a first high-voltage input stage circuit, a second high-voltage input stage circuit, a first low-voltage output stage circuit, and a second low-voltage output stage circuit. The output terminal of the first high-voltage input stage circuit is connected to the input terminal of the first low-voltage output stage circuit. The output terminal of the second high-voltage input stage circuit is connected to the input terminal of the second low-voltage output stage circuit. The output terminals of the first and second low-voltage output stages are also connected, and they are complementary differential input stages. The first high-voltage input stage circuit receives a first differential voltage signal and outputs a first differential current signal. The first high-voltage input stage circuit includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor is connected to the first input terminal, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the second input terminal. The drains of both the first and second NMOS transistors are connected to the first low-voltage output stage circuit. The substrates of the first and second NMOS transistors are connected to each other and then grounded. Both the first and second NMOS transistors are high-voltage transistors. The voltage output stage circuit includes output circuit one and output circuit two. The first differential voltage signal includes differential voltage sub-signal one and differential voltage sub-signal two. The first differential current signal includes differential current sub-signal one and differential current sub-signal two. Output circuit one receives differential current sub-signal one, and output circuit two receives differential current sub-signal two. Output circuit one includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The drain and gate of the third PMOS transistor are connected and then connected to the gate of the fourth PMOS transistor. The source of the third PMOS transistor... The third NMOS transistor's drain is connected to the gate of the fourth NMOS transistor, and the third NMOS transistor's source is connected to the source of the fourth NMOS transistor. The third NMOS transistor's source is connected to the source of the fourth NMOS transistor and then grounded. The fourth NMOS transistor's drain is the output. All three transistors (the third, fourth, and third NMOS transistors) are low-voltage transistors. The output circuit two includes a fifth PMOS transistor and a sixth PMOS transistor. The fifth PMOS transistor's drain is connected to the gate of the sixth PMOS transistor, and the fifth PMOS transistor's source is connected to the source of the sixth PMOS transistor. The fifth PMOS transistor's source is connected to the source of the sixth PMOS transistor, and the third NMOS transistor's source is connected to the source of the fourth NMOS transistor and then connected to a low-voltage power supply. The sixth PMOS transistor's drain is the output. Both the fifth and sixth PMOS transistors are low-voltage transistors, and they form a current mirror.

2. The comparator circuit according to claim 1, characterized in that, The second high-voltage input stage circuit receives the second differential voltage signal and outputs the second differential current signal. The second high-voltage input stage circuit includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to the third input terminal. The source of the first PMOS transistor is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor is connected to the fourth input terminal. The drains of the first PMOS transistor and the second PMOS transistor are both connected to the second low-voltage output stage circuit. The substrates of the first PMOS transistor and the second PMOS transistor are connected to a high-voltage power supply. Both the first PMOS transistor and the second PMOS transistor are high-voltage transistors.

3. A comparator circuit according to claim 2, characterized in that, The second low-voltage output stage circuit includes output circuit three and output circuit four. The second differential voltage signal includes differential voltage sub-signal three and differential voltage sub-signal four. The second differential current signal includes differential current sub-signal three and differential current sub-signal four. Output circuit three receives differential current sub-signal three and differential current sub-signal four.

4. A comparator circuit according to claim 3, characterized in that, The output circuit three includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The drain and gate of the fifth NMOS transistor are connected to the gate of the sixth NMOS transistor. The source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor and then grounded. The drain of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor. The drain and gate of the seventh PMOS transistor are connected to the gate of the eighth PMOS transistor. The source of the seventh PMOS transistor and the source of the eighth PMOS transistor are connected to VDD. The drain of the eighth PMOS transistor is the output. All five NMOS transistors are low-voltage transistors.

5. A comparator circuit according to claim 3, characterized in that, The output circuit four includes a seventh NMOS transistor and an eighth NMOS transistor. The drain and gate of the seventh NMOS transistor are connected to the gate of the eighth NMOS transistor. The source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor and then grounded. The drain of the eighth NMOS transistor is the output. Both the seventh and eighth NMOS transistors are low-voltage transistors.

6. An electronic device, characterized in that, The electronic device includes a comparator circuit as described in any one of claims 1 to 5.

Images