Analog switch with improved channel isolation

Abstract

The application discloses an analog switch for improving channel isolation, and relates to the field of switch circuits.The application comprises N ports and N T-type switches, wherein one end of a first T-type switch is connected with a first port analog signal input end; the other end of the first T-type switch is connected with an analog-to-digital converter; one end of an Nth T-type switch is connected with an Nth port analog signal input end; and the other end of the Nth T-type switch is connected with the analog-to-digital converter.The application adopts complementary T-type NMOS and T-type PMOS parallel transmission, so that full-amplitude transmission of signals can be obtained, level loss is avoided, and on-resistance is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of switching circuit, more particularly to an analog switch with improved channel isolation. BACKGROUND

[0002] Analog switches play an extremely important role in various fields, and high-performance analog switches are often required in many large-scale integrated circuit systems and electronic systems. The switches can be used to complete specific functions such as signal switching, control, and gating. The main requirements for the performance of the switches are: high isolation, good frequency response characteristics, wide dynamic range, and small nonlinear distortion. In recent years, analog switches have been increasingly widely used in data acquisition systems.

[0003] With the continuous increase in frequency, traditional switches cannot meet the application requirements in some aspects (low isolation and serious crosstalk), so it has become a development trend to design a new type of analog switch with higher frequency characteristics. SUMMARY

[0004] Therefore, the present application provides an analog switch with improved channel isolation to solve the problem of low channel isolation of existing analog switches.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] An analog switch with improved channel isolation includes N ports and N T-type switches, wherein one end of a first T-type switch is connected with a first port analog signal input end; the other end of the first T-type switch is connected with an analog-to-digital converter; one end of an Nth T-type switch is connected with an Nth port analog signal input end; the other end of the Nth T-type switch is connected with the analog-to-digital converter.

[0007] Optionally, the T-type switch includes two CMOS switches, which are composed of an NMOS tube and a PMOS tube. The on-resistance of the CMOS switch presents a complementary phenomenon with the change of the input voltage.

[0008] Optionally, the T-type switch includes: the source of a PMOS tube M1 is connected with the drain of an NMOS tube M3, and the drain of the PMOS tube M1 is connected with the source of the NMOS tube M3 to jointly constitute a CMOS switch; the output end of the CMOS tube is connected with the source of a PMOS tube M2 and an NMOS tube M4, and is connected with the drain of an NMOS tube M5; the drain of the PMOS tube M2 is connected with the drain of the NMOS tube M4, and is connected with a total output end.

[0009] Optionally, the T-type switch further comprises: the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are connected to the enable end; the source of the PMOS tube M1, the gate of the NMOS tube M3 and the output end of the bootstrap circuit are connected, the gate of the NMOS tube M3 is also connected to the source of the PMOS tube M6 and the drain of the NMOS tube M7; the source of the PMOS tube M6 is connected to the drain of the NMOS tube M7, the drain of the PMOS tube M6 is connected to the source of the NMOS tube M7, and after being connected, the gate of the NMOS tube M4 and the drain of the NMOS tube M8 are connected; the gate of the PMOS tube M11, the gate of the NMOS tube M12 and the gate of the PMOS tube M5 are connected to the enable end, the gate of the NMOS tube M7 is connected to the enable end, and the gate of the PMOS tube M6 is connected to the input end.

[0010] Optionally, the source of the NMOS tube M5 is connected to the ground, and the gate is connected to the enable end.

[0011] Optionally, the NMOS tube M8, the PMOS tube M9, the NMOS tube M10, the PMOS tube M11 and the NMOS tube M12 jointly constitute a pull-down circuit.

[0012] Compared with the prior art, the technical scheme provided by the present application can improve the channel isolation of the analog switch. Figure 1 As shown in the figure, the transmission gates M6 and M7 are added between the A point and the B point, when the enable end EN is high, the transmission gate is closed, and A and B are normally bootstrapped; when the EN is low, the A point is pulled down to the ground by the bootstrap circuit, and at the same time, the transmission gate is disconnected, so that the noise coupled from the A point to the B point is blocked by the transmission gate, and the circuit composed of M8-M12 pulls down the B point to the ground, thus greatly reducing the noise coupled from the B point to OUT. When the frequency is 100MHz, the channel isolation of the prior T-type switch is 70dB, and the channel isolation of the improved switch is 82dB, which significantly improves the channel isolation. By using the complementary T-type NMOS and T-type PMOS in parallel transmission, the signal can be transmitted with full amplitude without loss of level, and the on-resistance is also reduced. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 The T-type switch of the present application is shown in the figure;

[0015] Figure 2It is a schematic diagram of a T-type switch in the prior art;

[0016] Figure 3 This is the block diagram of the ADC circuit principle. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] In the existing technology, SW usually adopts Figure 2 The circuit shown in Figure 1 is shown. M3 and M4 have large W / L ratios to reduce their on-resistance. As IN changes, the on-resistance of M3 and M4 also changes. We want the on-resistance of SW to remain constant during the ADC sampling process, so a bootstrap circuit is used. This circuit sets VA = IN + AVDD during ADC sampling and VA = AVDD during ADC conversion, where AVDD is the analog circuit supply voltage. M1 and M2 have small W / L ratios, primarily to compensate for the change in on-resistance of M3 and M4 caused by changes in IN.

[0019] When EN is low, SW is closed. M5 is now conducting, pulling point C down to ground. Without M5, the signal fed from IN to point C is fed back to OUT via the parasitic capacitance between point C and OUT. M5 discharges the signal fed from IN to point C to ground, effectively reducing the signal fed from IN to OUT.

[0020] Because M3 and M4 have large W / L values, large parasitic capacitances exist between IN and point C, between C and OUT, between IN and point A, and between A and OUT. Due to these parasitic capacitances, the input signal of the disconnected channel is coupled to the output terminal OUT through these parasitic capacitances. The larger the parasitic capacitance, the greater the noise energy coupled to OUT. The larger the number of channels, the greater the parasitic capacitance. Increasing the W / L value of M5 in the circuit above can effectively suppress the coupling between IN and point C and point C and OUT, but it cannot suppress the coupling between IN and point A or point A and OUT. The existing design does not take this feedthrough branch into account.

[0021] To solve the above problems, an embodiment of the present invention discloses an analog switch that improves channel isolation. Figure 3As shown, the T-shaped switch includes two CMOS switches, and the CMOS switch is composed of an NMOS tube and a PMOS tube.

[0022] As shown, the T-shaped switch includes two CMOS switches, and the CMOS switch is composed of an NMOS tube and a PMOS tube. Figure 1 As shown, the T-shaped switch includes two CMOS switches, and the CMOS switch is composed of an NMOS tube and a PMOS tube.

[0023] The T-shaped switch includes: the source of the PMOS tube M1 is connected with the drain of the NMOS tube M3, and the drain of the PMOS tube M1 is connected with the source of the NMOS tube M3 to jointly constitute a CMOS switch; the output end of the CMOS tube is connected with the source of the PMOS tube M2 and the drain of the NMOS tube M5; the drain of the PMOS tube M2 is connected with the drain of the NMOS tube M4 and is connected with a total output end; the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are both connected with an enable end; the gate of the PMOS tube M1, the gate of the NMOS tube M3 and the output end of a bootstrap circuit are connected, and the gate of the NMOS tube M3 is also connected with the source of the PMOS tube M6 and the drain of the NMOS tube M7; the source of the PMOS tube M6 is connected with the drain of the NMOS tube M7, and the drain of the PMOS tube M6 is connected with the source of the NMOS tube M7, wherein the source of the NMOS tube M5 is grounded, and the gate is connected with the enable end.

[0024] The NMOS tube M8, the PMOS tube M9, the NMOS tube M10, the PMOS tube M11 and the NMOS tube M12 jointly constitute a pull-down circuit. The gate of the NMOS tube M4, the drain of the PMOS tube M6, the source of the NMOS tube M7 and the drain of the NMOS tube M8 are connected; the gate of the PMOS tube M11, the NMOS tube M12 and the PMOS tube M5 is connected with the enable end, the gate of the NMOS tube M7 is connected with the enable end, and the gate of the PMOS tube M6 is connected with an input end.

[0025] In the application of an analog-to-digital converter (ADC), there is such a scenario: in Figure 3In the figure, AIN0~AIN9 are connected to different analog input signals, and SW0~SW9 are used to select AIN0~AIN9, wherein SW0~SW9 are the same T-type switch, which controls a signal channel (hereinafter referred to as channel) respectively. Usually, the number of signal sources is equal to the number of channels, when a channel collects the signal of a signal source, the channel is closed, and other channels are turned off to prevent other signal sources from interfering with the signal. C0~C9 are parasitic capacitances. If SW0 is turned on, the ADC converts AIN0, due to the existence of C0~C9, AOUT will have part of the information of AIN1~AIN9, thereby affecting the conversion of AIN0. The present application can effectively suppress the size of the above-mentioned AIN1~AIN9 signal feedthrough to AOUT. The technology belongs to the analog circuit design in integrated circuit design.

[0026] The analog switches SW0~SW9 are as follows Figure 1 The working principle is as follows: M3, M4, M5, M7, M8, M10, M12 are NMDS tubes, M1, M2, M6, M9, M11 are PMOS tubes, and EN and ENN are two complementary switch logic control signals. When the input signal frequency is high, under the parasitic capacitance of the MOS tube itself, the signal is coupled through the capacitor, at this time M5 is turned on, the coupled signal is discharged to the ground through the conduction resistance of M5, and the transmission gate M6, M7 is increased between A point and B point, when the enable end EN is high, the transmission gate is closed, A and B are normally self-boosted; when EN is low, A point will be pulled down to the ground by the self-boosting circuit, at the same time, the transmission gate will be disconnected, so that the noise coupled from A point to B point is blocked by the transmission gate, at the same time, the circuit composed of M8~M12 pulls down B point to "ground", thus greatly reducing the noise coupled from B point to OUT, and significantly improving the channel isolation. By using complementary T-type NMOS and T-type PMOS tubes in parallel transmission, the signal can obtain full amplitude transmission without level loss, and the on-resistance is also reduced.

[0027] In Figure 1 In the figure, M6, M7 and M8 should be particularly noted for their voltage resistance. The self-boosting circuit will make VA=IN+AVDD during the ADC sampling process, if the gate of M6 is connected to ENN, M6 will have voltage resistance problem, which will cause M6 to be burned out. At the same time, the existence of M8 avoids the voltage resistance problem of M12.

[0028] In another embodiment, a kind of analog switch for improving channel isolation is disclosed, which realizes the basic function of one out of ten multiplexing, SW0~SW9 are the same T switch, which controls a signal channel respectively, AIN0~AIN9 are the input of T switch, which connects a different analog input signal respectively, each T switch connects an input respectively, AOUT is the output of T switch, which connects T switch at one end and connects analog-to-digital conversion at the other end.T switches are the same structure, each analog switch unit is composed of a T switch by two CMOS switches, one of which is composed of an NMOS and a PMOS, whose on-resistance changes with input voltage and presents complementary phenomenon, so that the two are used in parallel to improve the linearity of on-resistance.The source and drain of M1, M3 are connected together to form a CMOS switch.IN is its input, its output is connected with the source of M2 and M4 and the drain of M5, the drain of M2 and M4 is connected together and connected with the total output OUT.The gate of M3 is connected with the output of bootstrap circuit and the source of M6 and the drain of M7 (M6 and M7 also form a CMOS switch).The drain of M6 is connected with the source of M7 and the gate of M4 and the drain of M8, the gate of M11, M12 and M5 is connected with ENN, the gate of M7 is connected with EN, and the gate of M6 is connected with input (this is to prevent VGS of M6 from appearing voltage resistance problem)

[0029] M8, M9, M10, M11, M12 together form a pull-down circuit, which functions to pull down B point to ground when EN is "0", and can avoid VDS of M8 from appearing voltage resistance problem when EN is "1". The existence of M9 and M10 reduces the glitch on the gate of M8, the gate of M8 is connected with the drain of M9, and the source of M8 is connected with the drain of M11 and M12. The source of M9 and M11 is connected with positive power supply voltage AVDD. The drain and gate of M10 are connected with the gate of M9, and the source of M10 and M12 is connected with ground.

[0030] The manufacturing process of the embodiment is SMIC180nm process. The basic parameters of PMOS and NMOS in the circuit of the application are as follows: threshold voltage VT of enhancement mode NMOS: 0.6-1V, voltage between source and drain VDS≤3.63V;

[0031] threshold voltage VT of enhancement mode PMOS:-0.7--1.1V, voltage between source and drain VDS≤3.63V

[0032] width-length ratio of M1: 8*2um / 300nm; width-length ratio of M2: 8*2um / 300nm

[0033] Aspect ratio of M3: 8*20um / 350nm; Aspect ratio of M4: 8*20um / 350nm

[0034] Aspect ratio of M5: 2*10um / 350nm; Aspect ratio of M6: 2um / 300nm

[0035] Aspect ratio of M7: 4um / 350nm;

[0036] The various embodiments described in this specification are presented by way of example, and each embodiment describes a specific feature of the application that is independently useful. The various embodiments described in this specification can be combined in any way. Each embodiment can be combined with any other embodiment, unless the combination is clearly mutually exclusive. The various embodiments described in this specification can be combined in any way. Each embodiment can be combined with any other embodiment, unless the combination is clearly mutually exclusive.

[0037] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and are within the scope of this application, while remaining within the scope of this application as defined by the appended claims. The application is not limited to the embodiments described herein, but the general principles described herein can be implemented in various embodiments. The present application is thus to be interpreted as not being limited or confined to the details given herein, but as including all embodiments which are deemed to fall within the principles and novel features disclosed herein.

Claims

1. An analog switch for improving channel isolation, characterized in that: The device comprises N ports and N T-type switches, wherein one end of a first T-type switch is connected to a first port; the other end of the first T-type switch is connected to an analog-to-digital converter; one end of an Nth T-type switch is connected to an Nth port; the other end of the Nth T-type switch is connected to the analog-to-digital converter; The T-type switch includes two CMOS switches, each consisting of an NMOS transistor and a PMOS transistor, and the on-resistance of the CMOS switches exhibits a complementary phenomenon as the input voltage changes; The T-type switch includes: the source of the PMOS tube M1 is connected to the drain of the NMOS tube M3, and the drain of the PMOS tube M1 is connected to the source of the NMOS tube M3 to form a CMOS switch; the output end of the CMOS tube is connected to the source of the PMOS tube M2 and the NMOS tube M4 and to the drain of the NMOS tube M5; the drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4 and to the total output end; The T-type switch further includes: the gate of the PMOS transistor M1 and the gate of the PMOS transistor M2 are both connected to the enable terminal; the source of the PMOS transistor M1 and the gate of the NMOS transistor M3 are connected to the output terminal of the bootstrap circuit, and the gate of the NMOS transistor M3 is also connected to the source of the PMOS transistor M6 and the drain of the NMOS transistor M7; the source of the PMOS transistor M6 is connected to the drain of the NMOS transistor M7, and the drain of the PMOS transistor M6 is connected to the source of the NMOS transistor M7, and after being connected, is also connected to the gate of the NMOS transistor M4 and the drain of the NMOS transistor M8; the gates of the PMOS transistors M11, M12, and M5 are connected to the enable terminal, the gate of the NMOS transistor M7 is connected to the enable terminal, and the gate of the PMOS transistor M6 is connected to the input terminal.

2. The analog switch for improving channel isolation according to claim 1, wherein: The source of the NMOS transistor M5 is grounded, and the gate is connected to the enable terminal.

3. The analog switch for improving channel isolation according to claim 1, wherein: The NMOS transistor M8 , the PMOS transistor M9 , the NMOS transistor M10 , the PMOS transistor M11 , and the NMOS transistor M12 together form a pull-down circuit.

Images