Low-power DDR counter with correlated multi-sampling

Abstract

The present invention relates to the field of readout circuit design in CMOS image sensors. The present invention proposes a design that uses a latch as a first-stage counter and performs automatic correction after the entire counting cycle ends. While improving the quantization speed of the SSADC, the overall power consumption can be reduced, and a correlated multi-sampling function is realized based on a bitwise inversion circuit. The present invention can realize a low-power DDR counter for correlated multi-sampling, including a 1st bit circuit, a 2nd bit circuit, an (N‑2) bit multiplexed circuit, and a correction circuit, where N is a positive integer. The present invention is mainly used in the design and manufacturing of readout circuits in CMOS image sensors.

Description

Technical Field

[0001] The present invention relates to the field of readout circuit design in CMOS image sensors, and in particular to the field of low power design in analog-to-digital converter design, and in particular to a low power DDR counter capable of realizing correlated multi-sampling. Background Art

[0002] As an analog-to-digital conversion circuit with simple structure, small layout area and low circuit power consumption, the single slope analog-to-digital converter (SSADC) is widely used in the readout circuit of CMOS image sensors. The structure of SSADC includes a ramp generator, a comparator, a counter and a latch. The working mode of SSADC is as follows: the ramp generator generates a linearly rising ramp. When the ramp voltage is equal to the input voltage, the comparator flips, and the counter stops counting at this time. The latch latches the current counter count result as the final output of SSADC.

[0003] In order to suppress the noise in CMOS image sensors, SSADC usually works in correlated multi-sampling mode. Correlated multi-sampling mode requires that the pixels in the CMOS image sensor be sampled multiple times at different stages. When the pixel outputs a reset signal, SSADC will quantize the pixel output voltage N times, and the quantized result will be inverted in the counter; when the pixel outputs a photo-generated voltage, SSADC will quantize the pixel output voltage N times based on the counting result obtained by the previous quantization of the reset signal. After the above operations, SSADC not only eliminates the fixed pattern noise caused by process deviations in pixels and SSADC, but also effectively suppresses the random noise in the readout circuit.

[0004] However, the time required for SSADC to quantize the signal is longer than that of other ADC structures. The introduction of correlated multi-sampling technology further prolongs the quantization cycle of SSADC. Therefore, in order to speed up the quantization speed of SSADC, a common and effective method is to introduce a double data rate (DDR) counter as the first stage of the SSADC counter. However, whether it is a DDR structure composed of two D flip-flops or a DDR structure composed of latches, they both have two problems: (1) Since the first stage of the counter structure introduces the DDR structure, the complexity of the first stage design is greatly increased, resulting in a significant increase in the power consumption of the first stage of the counter compared to the traditional ripple counter, which is not conducive to the design of column-parallel SSADC; (2) Due to the particularity of the DDR mechanism, the traditional circuit based on the bitwise inversion mode cannot adapt to the correlated multi-sampling operation. Summary of the invention

[0005] In order to overcome the shortcomings of the prior art and address the shortcomings of DDR SSADC, such as high power consumption and difficulty in realizing correlated multi-sampling, the present invention aims to propose a design that uses a latch as the first-level counter and performs automatic correction after the entire counting cycle. While improving the quantization speed of the SSADC, it can reduce its overall power consumption and realize the correlated multi-sampling function based on a bitwise inversion circuit. To this end, the technical solution adopted by the present invention is to realize a low-power DDR counter with correlated multi-sampling, including a 1st bit circuit, a 2nd bit circuit, an (N-2) bit multiplexed circuit and a correction circuit, where N is a positive integer; the input signal of the counter includes a clock MCLK, a comparator output COMPOUT, a control signal BWI_CK1, a control signal BWI|_CK2, a control signal LSB_RN_CAL, a control signal BWI_CK1_CAL, a control signal BWI_CK2_SLSB, a control signal LLAT, a control signal LLATB, and a control signal S_LSB; the output signal of the counter is D<1:N>; the 1st bit circuit is composed of a latch LATCH1, an input D terminal of the LATCH1 is connected to the clock MCLK, an input G terminal of the LATCH1 is connected to the comparator output COMPOUT, a reset terminal R of the LATCH1 is connected to the output RN_LSB of the correction circuit, a set terminal S of the LATCH1 is connected to the set signal S_LSB, and an output terminal Q of the LATCH1 is the lowest bit output D of the counter. <1> , the D <1> The input IN end of the bitwise inversion module BWI1 of the second bit circuit and the input of the correction circuit transmission gate TG1 are connected; the correction circuit is composed of a transmission gate TG1, a transmission gate TG2, a D flip-flop DFF1, a D flip-flop DFF2, a multiplexer, a latch LATCH3, an inverter IV1, an inverter IV2, an OR gate OR1, and an AND gate AN1; the input of the TG1 in the correction circuit is connected to the output D of the first bit circuit <1> The output of TG1 is connected to the input of TG2 and the input of DFF1, the forward control terminal of TG1 is connected to LLAT, and the reverse control terminal is connected to LLATB; the input of TG2 is connected to the output of TG1, the output of TG2 is grounded, the forward control terminal of TG2 is connected to LLATB, and the reverse control terminal is connected to LLAT; the reverse output terminal of DFF1 The output terminal Q of DFF2 is connected to the input terminal 1 of the multiplexer, the output terminal Q of DFF2 is connected to the input terminal D of DFF1, the input terminal CLK of DFF2 and the input terminal D of LATCH3; the output terminal Q of DFF2 is connected to the input terminal 1 of the multiplexer, the output terminal Q of DFF2 is connected to the input terminal CLK of DFF2 and the input terminal D of LATCH3; The output of the multiplexer is connected to the input terminal D of the DFF2; the output of the LATCH3 is BWI_CK2_CTL; the input terminal of the OR1 is the output terminal of the DFF1 The signal after IV1 has the other end LSB_RN_CAL, and the output signal of OR1 is RN_LSB; the input end of AN1 is the output of DFF1 The second terminal is the output of DFF2 The third end of the signal after passing through IV2 is BWI_CK1_CTL, and the output of AN1 is BWI_CK1_CTL; the second bit circuit is composed of an OR gate OR2, an OR gate OR3, an AND gate AN2, a bitwise inversion module BWI1, and a D flip-flop DFF3; the input of OR2 is connected to BWI_CK2_SLSB and BWI_CK2_CTL, and the output is connected to one end of the input of AN2; the input end of AN2 is respectively connected to the outputs of BWI_CK2 and OR2, and the output of AN2 is connected to the input of BWI1; the input of OR3 is respectively connected to BWI_CK1 and BWI_CK1_CTL, and the output of OR3 is connected to the input of BWI1; the output of BWI1 is connected to the input CLK of DFF3; the output of DFF3 Segment D is the output of the second bit of the counter <2> , the D <2> The D input terminal of the DFF3 is connected to the BWI module IN terminal of the (N-2)-bit multiplexed circuit; the (N-2)-bit multiplexed circuit is composed of (N--2) identical circuit structures connected in the first place, each circuit includes a bitwise inversion module BWIR and a D flip-flop DFFR; the input terminal IN of the BWIR is connected to the output D of the previous 1-bit circuit <n>The other two input terminals of the BWIR are connected to BWI_CK1 and BWI_CK2, and the output BWI_OUT of the BWIR is connected to the input terminal CLK of the DFFR; the output of the DFFR The output D of the bit counter <n> ，D <n>Connect the input D end of the DFFR and the bitwise inversion module IN end of the next bit circuit of the (N-2) bit multiplexed circuit.

[0006] The specific process for 2-time correlated multi-sampling is as follows: after COUNTER_EN is set to 1, MCLK starts to beat, at which time the LATCH1 is turned on, and the counter starts counting until COMPOUT flips at t1, and LATCH1 is turned off. At this time, the first count is completed, and D<1:N> outputs the count result; between t1-t2, the count correction is completed. Since TG2 is turned on and TG1 is turned off before t1, the output node of TG1 is always 0 before t1. After t1, LLAT is set to 1, TG1 is turned on, and TG2 is turned off. The output of the first bit is transmitted to the CLK end of the DFF1 through the TG1; if the output of the first bit is 0 at this time, the state of the correction circuit does not change. If the output of the first bit is 1 at this time, the CLK end level of the DFF1 will change from 0 to 1, and the output of the DFF1 will change from 0 to 1, the output of DFF2 will change from 0 to 1, the output of the multiplexer will be converted from the 0 end to the 1 end, the G end of the LATCH3 will change from 0 to 1, and the LATCH3 will be turned on; then LLAT is set to 0, S_LSB is set to 1, and the output of the 1st bit is set to 1, ensuring that LATCH1, as the first-level counter, has the same initial state in each counting cycle; then S_LSB is set to 0, and BWI_CK2_SLSB is sent to a reverse pulse. If the output BWI_CK2_CTL of the LATCH3 is 1, then BWI_CK2_SLSB will not change after passing through the OR2, so the 1st bit circuit will not change. If the output BWI_CK2_CTL of the LATCH3 is 0, the reverse pulse of BWI_CK2_SLWB will be sent to the BWI1 through the OR2 and the AN2, so that the output OUT of the BWI1 is flipped, thereby making the output of the DFF3 Flip, making the counter count +2, that is, D <1> Flip once; between t2 and t3, the counter repeats the operation before t1 based on the correction result to complete the second count, and D<1:N> outputs the count result; between t3 and t4, first repeat the operation between t1 and t2 to complete the count correction. At this time, the count result output by D<1:N> is the first stage quantization result, recorded as DRST:

[0007] D<1:N> t4 =DRST (1)

[0008] Then, the operations of setting BWI_CK2 to 1, BWI_CK1 to 0, BWI_CK2 to 0, and BWI_CK1 to 1 are completed in sequence, so that the outputs of the BWI1 and BWIR modules change from 0 to 1 and then to 0, and the DFF3 And all DFFRs in the (N-2) bit multiplexed circuit At the same time, the counter is flipped and inverted, so that the output of the counter completes the bitwise inversion operation. At this time, the output counting result of D<1:N> is the reverse of the quantization result of the first stage:

[0009] D<1:N> t5 =-DRST (2)

[0010] Between t4 and t8, the counter repeats the operation between t1 and t4 based on -DRST, completing the third quantization and correction, the fourth quantization and correction, and the correlated double sampling operation. The output result D<1:N> of the counter has three possibilities:

[0011] D<1:N> t8 =-DRST+DSIG+1 (3)

[0012] D<1:N> t8 =-DRST+DSIG-1 (4)

[0013] D<1:N> t8 =-DRST+DSIG (5)

[0014] DSIG is the result of the new measurement of the counter between t4 and t8. After t8, BWI_CK1_CAL generates a positive pulse and LSB_RN_CAL generates a negative pulse. If the output of DFF1 is 1, LSB_RN_CAL will set the output of LATCH1 to 0. If the output of DFF1 is 0, the output of LATCH1 is still 1; if the output of DFF1 is 1 and the output of DFF2 is 0, the BWI_CK1_CAL will set BWI_CK1_CTL to 1. At this time, the change of the output of LATCH1 from 1 to 0 caused by the LSB_RN_CAL will be sent to the 2nd bit circuit, causing the 2nd bit circuit to flip, which is equivalent to the overall count result +1; if the output of the DFF1 0 or the output of DFF2 If LSB_RN_CAL is 1, BWI_CK1_CAL will set BWI_CK1_CTL to 0. At this time, the change of the output of LATCH1 from 1 to 0 caused by LSB_RN_CAL cannot cause changes in subsequent circuits, which is equivalent to the overall count result -1:

[0015] D<1:N> f =-DRST+DISG+2 (6)

[0016] Formula (6) is the final output result of the counter.

[0017] The characteristics and beneficial effects of the present invention are:

[0018] The present invention reduces the power consumption of DDR SSADC when it is working by introducing a correction circuit, and makes DDR SSADC suitable for a related multi-sampling working mode, and can be used in the design of an image sensor readout circuit to reduce the random noise of the image sensor and improve the working speed of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A low-power DDR counter structure design that can implement correlated multi-sampling.

[0020] Figure 2 A low-power DDR counter operating mode that can implement correlated multi-sampling.

[0021] Figure 3 Design scheme of Bit Wise Inverter (BWI) module. DETAILED DESCRIPTION

[0022] The present invention discloses a low-power counter design for realizing correlated multi-sampling applied to SSADC, and its connection method is as follows: Figure 1 As shown, it is composed of a 1st bit circuit, a 2nd bit circuit, an (N-2) bit multiplexed circuit (N is a positive integer) and a correction circuit; the input signal of the counter includes a clock MCLK, a comparator output COMPOUT, a control signal BWI_CK1, a control signal BWI|_CK2, a control signal LSB_RN_CAL, a control signal BWI_CK1_CAL, a control signal BWI_CK2_SLSB, a control signal LLAT, a control signal LLATB, and a control signal S_LSB; the output signal of the counter is D<1:N>; the 1st bit circuit is composed of a latch LATCH1, an input D terminal of the LATCH1 is connected to the clock MCLK, an input G terminal of the LATCH1 is connected to the comparator output COMPOUT, a reset terminal R of the LATCH1 is connected to the output RN_LSB of the correction circuit, a set terminal S of the LATCH1 is connected to the set signal S_LSB, and an output terminal Q of the LATCH1 is the lowest bit output D of the counter. <1> , the D <1> The input IN end of the bitwise inversion module BWI1 of the second bit circuit and the input of the correction circuit transmission gate TG1 are connected; the correction circuit is composed of a transmission gate TG1, a transmission gate TG2, a D flip-flop DFF1, a D flip-flop DFF2, a multiplexer, a latch LATCH3, an inverter IV1, an inverter IV2, an OR gate OR1, and an AND gate AN1; the input of the TG1 in the correction circuit is connected to the output D of the first bit circuit <1> The output of TG1 is connected to the input of TG2 and the input of DFF1, the forward control terminal of TG1 is connected to LLAT, and the reverse control terminal is connected to LLATB; the input of TG2 is connected to the output of TG1, the output of TG2 is grounded, the forward control terminal of TG2 is connected to LLATB, and the reverse control terminal is connected to LLAT; the reverse output terminal of DFF1 The output terminal Q of DFF2 is connected to the input terminal 1 of the multiplexer, the output terminal Q of DFF2 is connected to the input terminal D of DFF1, the input terminal CLK of DFF2 and the input terminal D of LATCH3; the output terminal Q of DFF2 is connected to the input terminal 1 of the multiplexer, the output terminal Q of DFF2 is connected to the input terminal CLK of DFF2 and the input terminal D of LATCH3; The output of the multiplexer is connected to the input terminal D of the DFF2; the output of the LATCH3 is BWI_CK2_CTL; the input terminal of the OR1 is the output terminal of the DFF1 The signal after IV1 has the other end LSB_RN_CAL, and the output signal of OR1 is RN_LSB; the input end of AN1 is the output of DFF1 The second terminal is the output of DFF2 The third end of the signal after passing through IV2 is BWI_CK1_CTL, and the output of AN1 is BWI_CK1_CTL; the second bit circuit is composed of an OR gate OR2, an OR gate OR3, an AND gate AN2, a bitwise inversion module BWI1, and a D flip-flop DFF3; the input of OR2 is connected to BWI_CK2_SLSB and BWI_CK2_CTL, and the output is connected to one end of the input of AN2; the input end of AN2 is respectively connected to the outputs of BWI_CK2 and OR2, and the output of AN2 is connected to the input of BWI1; the input of OR3 is respectively connected to BWI_CK1 and BWI_CK1_CTL, and the output of OR3 is connected to the input of BWI1; the output of BWI1 is connected to the input CLK of DFF3; the output of DFF3 Segment D is the output of the second bit of the counter <2> , the D <2> The D input terminal of the DFF3 is connected to the BWI module IN terminal of the (N-2)-bit multiplexed circuit; the (N-2)-bit multiplexed circuit is composed of N-2 identical circuit structures connected in the first place, each circuit includes a bitwise inversion module BWIR and a D flip-flop DFFR; the input terminal IN of the BWIR is connected to the output D of the previous 1-bit circuit <n>The other two input terminals of the BWIR are connected to BWI_CK1 and BWI_CK2, and the output BWI_OUT of the BWIR is connected to the input terminal CLK of the DFFR; the output of the DFFR The output D of the bit counter <n> ，D <n>Connect the input D end of the DFFR and the bitwise inversion module IN end of the next bit circuit of the (N-2) bit multiplexed circuit.

[0023] The present invention discloses a low-power counter design for realizing correlated multi-sampling applied to SSADC. Taking 2-time correlated multi-sampling as an example, its working principle is as follows: Figure 2 As shown, the specific process is as follows: after COUNTER_EN is set to 1, MCLK starts to beat, at this time the LATCH1 is turned on, and the counter starts counting until COMPOUT flips at t1, LATCH1 is turned off, at this time the first count is completed, and D<1:N> outputs the count result; between t1-t2, the count correction is completed. Since TG2 is turned on and TG1 is turned off before t1, the output node of TG1 is always 0 before t1. After t1, LLAT is set to 1, TG1 is turned on, TG2 is turned off, and the output of the first bit is transmitted to the CLK end of the DFF1 through the TG1; if the output of the first bit is 0 at this time, the state of the correction circuit does not change. If the output of the first bit is 1 at this time, the CLK end level of the DFF1 will change from 0 to 1, and the output of the DFF1 will change from 0 to 1, the output of DFF2 will change from 0 to 1, the output of the multiplexer will be converted from the 0 end to the 1 end, the G end of the LATCH3 will change from 0 to 1, and the LATCH3 will be turned on; then LLAT is set to 0, S_LSB is set to 1, and the output of the 1st bit is set to 1, ensuring that LATCH1, as the first-level counter, has the same initial state in each counting cycle; then S_LSB is set to 0, and BWI_CK2_SLSB is sent to a reverse pulse. If the output BWI_CK2_CTL of the LATCH3 is 1, then BWI_CK2_SLSB will not change after passing through the OR2, so the 1st bit circuit will not change. If the output BWI_CK2_CTL of the LATCH3 is 0, the reverse pulse of BWI_CK2_SLWB will be sent to the BWI1 through the OR2 and the AN2, so that the output OUT of the BWI1 is flipped, thereby making the output of the DFF3 Flip, making the counter count +2, that is, D <1> Flip once; between t2 and t3, the counter repeats the operation before t1 based on the correction result to complete the second count, and D<1:N> outputs the count result; between t3 and t4, first repeat the operation between t1 and t2 to complete the count correction. At this time, the count result output by D<1:N> is the first stage quantization result, recorded as DRST:

[0024] D<1:N> t4 =DRST (1)

[0025] Then, the operations of setting BWI_CK2 to 1, BWI_CK1 to 0, BWI_CK2 to 0, and BWI_CK1 to 1 are completed in sequence, so that the outputs of the BWI1 and BWIR modules change from 0 to 1 and then to 0, and the DFF3 And all DFFRs in the (N-2) bit multiplexed circuit At the same time, the counter is flipped and inverted, so that the output of the counter completes the bitwise inversion operation. At this time, the output counting result of D<1:N> is the reverse of the quantization result of the first stage:

[0026] D<1:N> t5 =-DRST (2)

[0027] Between t4 and t8, the counter repeats the operation between t1 and t4 based on -DRST, completing the third quantization and correction, the fourth quantization and correction, and the correlated double sampling operation. The output result D<1:N> of the counter has three possibilities:

[0028] D<1:N> t8 =-DRST+DSIG+1 (3)

[0029] D<1:N> t8 =-DRST+DSIG-1 (4)

[0030] D<1:N> t8 =-DRST+DSIG (5)

[0031] DSIG is the result of the new measurement of the counter between t4 and t8. After t8, BWI_CK1_CAL generates a positive pulse and LSB_RN_CAL generates a negative pulse. If the output of DFF1 is 1, LSB_RN_CAL will set the output of LATCH1 to 0. If the output of DFF1 is 0, the output of LATCH1 is still 1; if the output of DFF1 is 1 and the output of DFF2 is 0, the BWI_CK1_CAL will set BWI_CK1_CTL to 1. At this time, the change of the output of LATCH1 from 1 to 0 caused by the LSB_RN_CAL will be sent to the 2nd bit circuit, causing the 2nd bit circuit to flip, which is equivalent to the overall count result +1; if the output of the DFF1 0 or the output of DFF2 If BWI_CK1_CAL is 1, BWI_CK1_CAL will set BWI_CK1_CTL to 0. At this time, the change of the output of LATCH1 from 1 to 0 caused by LSB_RN_CAL cannot cause the change of the subsequent circuit, which is equivalent to the overall counting result -1. The final output result of the counter

[0032] D<1:N> f =-DRST+DISG+2 (6)

[0033] The BWI module structure of the present invention is as follows Figure 3 As shown, VDD is 1.5 V. The pulse widths of the LLAT, S_LSB, and BWI_CK2_SLSB are 200 ns, the pulse widths of the BWI_CK1_CTL and LSB_RN_CAL are 400 ns, the pulse widths of the BWI_CK2 and the BWI_CK1 are 400 ns, the falling edge of the BWI_CK1 between t3 and t4 is 100 ns later than the rising edge of the BWI_CK2 between t3 and t4, and the rising edge of the BWI_CK1 between t3 and t4 is 100 ns later than the falling edge of the BWI_CK2 between t3 and t4.

[0034] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A low-power DDR counter capable of implementing correlated multi-sampling, characterized in that: The invention comprises a 1st bit circuit, a 2nd bit circuit, an (N-2) bit multiplexed circuit and a correction circuit, wherein N is a positive integer; the input signal of the counter comprises a clock MCLK, a comparator output COMPOUT, a control signal BWI_CK1, a control signal BWI|_CK2, a control signal LSB_RN_CAL, a control signal BWI_CK1_CAL, a control signal BWI_CK2_SLSB, a control signal LLAT, a control signal LLATB and a control signal S_LSB; the output signal of the counter is D<1:N>; the 1st bit circuit is composed of a latch LATCH1, an input D terminal of the LATCH1 is connected to the clock MCLK, an input G terminal of the LATCH1 is connected to the comparator output COMPOUT, a reset terminal R of the LATCH1 is connected to the output RN_LSB of the correction circuit, a set terminal S of the LATCH1 is connected to the set signal S_LSB, and an output terminal Q of the LATCH1 is the lowest bit output D of the counter. <1> , the D <1> The input IN end of the bitwise inversion module BWI1 of the second bit circuit and the input of the correction circuit transmission gate TG1 are connected; the correction circuit is composed of a transmission gate TG1, a transmission gate TG2, a D flip-flop DFF1, a D flip-flop DFF2, a multiplexer, a latch LATCH3, an inverter IV1, an inverter IV2, an OR gate OR1, and an AND gate AN1; the input of the TG1 in the correction circuit is connected to the output D of the first bit circuit <1> The output of TG1 is connected to the input of TG2 and the input of DFF1, the forward control terminal of TG1 is connected to LLAT, and the reverse control terminal is connected to LLATB; the input of TG2 is connected to the output of TG1, the output of TG2 is grounded, the forward control terminal of TG2 is connected to LLATB, and the reverse control terminal is connected to LLAT; the reverse output terminal of DFF1 The output terminal Q of DFF2 is connected to the input terminal 1 of the multiplexer, the output terminal Q of DFF2 is connected to the input terminal D of DFF1, the input terminal CLK of DFF2 and the input terminal D of LATCH3; the output terminal Q of DFF2 is connected to the input terminal 1 of the multiplexer, the output terminal Q of DFF2 is connected to the input terminal CLK of DFF2 and the input terminal D of LATCH3; The output of the multiplexer is connected to the input terminal D of the DFF2; the output of the LATCH3 is BWI_CK2_CTL; the input terminal of the OR1 is the output terminal of the DFF1 The signal after IV1 has the other end LSB_RN_CAL, and the output signal of OR1 is RN_LSB; the input end of AN1 is the output of DFF1 The second terminal is the output of DFF2 The third end of the signal after passing through IV2 is BWI_CK1_CTL, and the output of AN1 is BWI_CK1_CTL; the second bit circuit is composed of an OR gate OR2, an OR gate OR3, an AND gate AN2, a bitwise inversion module BWI1, and a D flip-flop DFF3; the input of OR2 is connected to BWI_CK2_SLSB and BWI_CK2_CTL, and the output is connected to one end of the input of AN2; the input end of AN2 is respectively connected to the outputs of BWI_CK2 and OR2, and the output of AN2 is connected to the input of BWI1; the input of OR3 is respectively connected to BWI_CK1 and BWI_CK1_CTL, and the output of OR3 is connected to the input of BWI1; the output of BWI1 is connected to the input CLK of DFF3; the output of DFF3 Segment D is the output of the second bit of the counter <2> , the D <2> The D input terminal of the DFF3 is connected to the BWI module IN terminal of the (N--2)-bit multiplexed circuit; the (N-2)-bit multiplexed circuit is composed of (N-2) identical circuit structures connected in the first place, each circuit includes a bitwise inversion module BWIR and a D flip-flop DFFR; the input terminal IN of the BWIR is connected to the output D of the previous 1-bit circuit <n>The other two input terminals of the BWIR are connected to BWI_CK1 and BWI_CK2, and the output BWI_OUT of the BWIR is connected to the input terminal CLK of the DFFR; the output of the DFFR The output D of the bit counter <n> ，D <n>Connect the input D end of the DFFR and the bitwise inversion module IN end of the next bit circuit of the (N-2) bit multiplexed circuit.< / n> < / n> < / n> 2. The low-power DDR counter capable of implementing correlated multi-sampling as claimed in claim 1, characterized in that The specific process of 2 times correlated multi-sampling is as follows: after COUNTER_EN is set to 1, MCLK starts to beat, at this time the LATCH1 is turned on, and the counter starts counting until COMPOUT flips at t1, LATCH1 is turned off, at this time the first count is completed, and D<1:N> outputs the count result; between t1-t2, the count correction is completed. Since TG2 is turned on and TG1 is turned off before t1, the output node of TG1 is always 0 before t1. After t1, LLAT is set to 1, TG1 is turned on, TG2 is turned off, and the output of the 1st bit is transmitted to the CLK end of the DFF1 through the TG1; if the output of the 1st bit is 0 at this time, the state of the correction circuit does not change. If the output of the 1st bit is 1 at this time, the CLK end level of the DFF1 will change from 0 to 1, and the output of the DFF1 will change from 0 to 1, the output of DFF2 will change from 0 to 1, the output of the multiplexer will be converted from the 0 end to the 1 end, the G end of the LATCH3 will change from 0 to 1, and the LATCH3 will be turned on; then LLAT is set to 0, S_LSB is set to 1, and the output of the 1st bit is set to 1, ensuring that LATCH1, as the first-level counter, has the same initial state in each counting cycle; then S_LSB is set to 0, and BWI_CK2_SLSB is sent to a reverse pulse. If the output BWI_CK2_CTL of the LATCH3 is 1, then BWI_CK2_SLSB will not change after passing through the OR2, so the 1st bit circuit will not change. If the output BWI_CK2_CTL of the LATCH3 is 0, the reverse pulse of BWI_CK2_SLWB will be sent to the BWI1 through the OR2 and the AN2, so that the output OUT of the BWI1 is flipped, thereby making the output of the DFF3 Flip, making the counter count +2, that is, D <1> Flip once; between t2 and t3, the counter repeats the operation before t1 based on the correction result to complete the second count, and D<1:N> outputs the count result; between t3 and t4, first repeat the operation between t1 and t2 to complete the count correction. At this time, the count result output by D<1:N> is the first stage quantization result, recorded as DRST: D<1:N> t4 =DRST (1) Then, the operations of setting BWI_CK2 to 1, BWI_CK1 to 0, BWI_CK2 to 0, and BWI_CK1 to 1 are completed in sequence, so that the outputs of the BWI1 and BWIR modules change from 0 to 1 and then to 0, and the DFF3 And all DFFRs in the (N-2) bit multiplexed circuit At the same time, the counter is flipped and inverted, so that the output of the counter completes the bitwise inversion operation. At this time, the output counting result of D<1:N> is the reverse of the quantization result of the first stage: D<1:N> t5 =-DRST (2) Between t4 and t8, the counter repeats the operation between t1 and t4 based on -DRST, completing the third quantization and correction, the fourth quantization and correction, and the correlated double sampling operation. The output result D<1:N> of the counter has three possibilities: D<1:N> t8 =-DRST+DSIG+1 (3) D<1:N> t8 =-DRST+DSIG-1 (4) D<1:N> t8 =-DRST+DSIG (5) DSIG is the result of the new measurement of the counter between t4 and t8. After t8, BWI_CK1_CAL generates a positive pulse and LSB_RN_CAL generates a negative pulse. If the output of DFF1 is 1, LSB_RN_CAL will set the output of LATCH1 to 0. If the output of DFF1 is 0, the output of LATCH1 is still 1; if the output of DFF1 is 1 and the output of DFF2 is 0, the BWI_CK1_CAL will set BWI_CK1_CTL to 1. At this time, the change of the output of LATCH1 from 1 to 0 caused by the LSB_RN_CAL will be sent to the 2nd bit circuit, causing the 2nd bit circuit to flip, which is equivalent to the overall count result +1; if the output of the DFF1 0 or the output of DFF2 If LSB_RN_CAL is 1, BWI_CK1_CAL will set BWI_CK1_CTL to 0. At this time, the change of the output of LATCH1 from 1 to 0 caused by LSB_RN_CAL cannot cause changes in subsequent circuits, which is equivalent to the overall count result -1: D<1:N> f =-DRST+DISG+2 (6) Formula (6) is the final output result of the counter.

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