Shift register unit and driving method thereof, gate driving circuit, and display panel

Abstract

The present disclosure relates to the field of display technology and proposes a shift register unit and its driving method, gate drive circuit, and display panel. The shift register unit includes: a first input circuit, a second input circuit, a first storage circuit, a second storage circuit, a first pull-down circuit, a second pull-down circuit, a first output circuit, a second output circuit, and a third storage circuit. The first input circuit is used to input a valid level to the second node; the second input circuit is used to input a valid level to the third node; the first storage circuit is used to store the voltage between the first node and the first clock signal terminal; the second storage circuit is used to store the voltage between the second node and the second clock signal terminal; the first pull-down circuit is used to pull down the first node; the second pull-down circuit is used to pull down the second node; the first output circuit and the second output circuit are used to output signals; and the third storage circuit is used to store the voltage of the third node. The shift register unit has a simple structure.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. Background Art

[0002] The display panel usually provides an enable signal to the pixel driving circuit through a gate driving circuit. In the related art, the gate driving circuit has a complex structure and high cost.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] According to one aspect of the present disclosure, a shift register unit is provided, which includes: a first input circuit, a second input circuit, a first storage circuit, a second storage circuit, a first pull-down circuit, a second pull-down circuit, a first output circuit, a second output circuit, and a third storage circuit. The first input circuit is connected to the first clock signal terminal, the first node, and the second node, and is used to transmit the signal of the first clock signal terminal to the second node in response to the signal of the first node; the second input circuit is connected to the signal input terminal, the third node, and the first clock signal terminal, and is used to transmit the signal of the signal input terminal to the third node in response to the signal of the first clock signal terminal; the first storage circuit is connected between the first clock signal terminal and the first node, and is used to store the voltage between the first node and the first clock signal terminal; the second storage circuit is connected between the second clock signal terminal and the second node, and is used to store the voltage between the second node and the second clock signal terminal; the first pull-down circuit is connected to the signal input terminal, the first power supply terminal, The first node is used to transmit the signal of the first power supply end to the first node in response to the signal of the signal input end; the second pull-down circuit is connected to the first power supply end, the third node, and the second node, and is used to transmit the signal of the first power supply end to the second node in response to the signal of the third node; the first output circuit is connected to the second node, the first power supply end, and the signal output end, and is used to transmit the signal of the first power supply end to the signal output end in response to the signal of the second node; the second output circuit is connected to the third node, the second power supply end, and the signal output end, and is used to transmit the signal of the second power supply end to the signal output end in response to the signal of the third node; the third storage circuit is connected to the third node, and is used to store the voltage of the third node.

[0005] In an exemplary embodiment of the present disclosure, the shift register unit further includes: a third pull-down circuit, which is connected to the second node, the third node, the first power supply terminal, and the second clock signal terminal, and is used to transmit the signal of the first power supply terminal to the third node in response to the signal of the second node and the second clock signal terminal.

[0006] In an exemplary embodiment of the present disclosure, the first input circuit includes: a first transistor, wherein the first electrode of the first transistor is connected to the first clock signal terminal, the second electrode is connected to the second node, and the gate is connected to the first node; the second input circuit includes: a third transistor, wherein the first electrode of the third transistor is connected to the signal input terminal, the second electrode is connected to the third node, and the gate is connected to the first clock signal terminal.

[0007] In an exemplary embodiment of the present disclosure, the first storage circuit includes: a first capacitor, a first electrode of which is connected to the first clock signal terminal, and a second electrode of which is connected to the first node; the second storage circuit includes: a second capacitor, a first electrode of which is connected to the second clock signal terminal, and a second electrode of which is connected to the second node; and the third storage circuit includes: a third capacitor, a first electrode of which is connected to the third node, and a second electrode of which is connected to the second power supply terminal.

[0008] In an exemplary embodiment of the present disclosure, the first pull-down circuit includes: a second transistor, a first electrode of the second transistor is connected to the first node, a second electrode is connected to the first power supply terminal, and a gate is connected to the signal input terminal; the second pull-down circuit includes: a fourth transistor, a first electrode of the fourth transistor is connected to the second node, a second electrode is connected to the first power supply terminal, and a gate is connected to the third node.

[0009] In an exemplary embodiment of the present disclosure, the first output circuit includes: a fifth transistor, the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode is connected to the signal output terminal, and the gate is connected to the second node; the second output circuit includes: a sixth transistor, the first electrode of the sixth transistor is connected to the second power supply terminal, the second electrode is connected to the signal output terminal, and the gate is connected to the third node.

[0010] In an exemplary embodiment of the present disclosure, the third pull-down circuit includes: a seventh transistor and an eighth transistor, wherein the first electrode of the seventh transistor is connected to the first power supply terminal, and the gate is connected to the second node; the first electrode of the eighth transistor is connected to the second electrode of the seventh transistor, the second electrode is connected to the third node, and the gate is connected to the second clock signal terminal.

[0011] According to one aspect of the present disclosure, a shift register unit driving method is provided, the driving method comprising:

[0012] In the first stage: an invalid level signal is input to the signal input terminal and the first clock signal terminal, and a valid level signal is input to the second clock signal terminal;

[0013] In the second stage: inputting an invalid level signal to the signal input terminal and the second clock signal terminal, and inputting a valid level signal to the first clock signal terminal;

[0014] In the third stage: inputting an invalid level signal to the first clock signal terminal, and inputting a valid level signal to the signal input terminal and the second clock signal terminal;

[0015] In the fourth stage: an invalid level signal is input to the second clock signal terminal, and a valid level signal is input to the signal input terminal and the first clock signal terminal.

[0016] According to one aspect of the present disclosure, a gate driving circuit is provided, which includes the above-mentioned shift register unit.

[0017] According to one aspect of the present disclosure, a display panel is provided, comprising the above-mentioned gate driving circuit.

[0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 Schematic diagram of the structure of an exemplary embodiment of the shift register unit disclosed in the present invention;

[0021] Figure 2 for Figure 1 A timing diagram of various control signals in an exemplary embodiment of the shift register unit shown;

[0022] Figure 3 for Figure 1 The state diagram of the shift register unit shown is in the first buffer stage;

[0023] Figure 4 for Figure 1 The state diagram of the shift register unit shown in the first stage;

[0024] Figure 5 for Figure 1The state diagram of the shift register unit shown is in the second stage;

[0025] Figure 6 for Figure 1 The state diagram of the shift register unit shown in the second buffer stage;

[0026] Figure 7 for Figure 1 The state diagram of the shift register unit shown in the third stage;

[0027] Figure 8 for Figure 1 The state diagram of the shift register unit shown in the fourth stage;

[0028] Figure 9 Schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed in the present invention;

[0029] Figure 10 for Figure 9 The state diagram of the shift register unit shown is in the first buffer stage;

[0030] Figure 11 for Figure 9 The state diagram of the shift register unit shown in the first stage;

[0031] Figure 12 for Figure 9 The state diagram of the shift register unit shown is in the second stage;

[0032] Figure 13 for Figure 9 The state diagram of the shift register unit shown in the second buffer stage;

[0033] Figure 14 for Figure 9 The state diagram of the shift register unit shown in the third stage;

[0034] Figure 15 for Figure 9 The state diagram of the shift register unit shown in the fourth stage. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0036] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0037] This exemplary embodiment first provides a shift register unit, such as Figure 1 FIG2 is a schematic diagram of the structure of an exemplary embodiment of a shift register unit of the present disclosure. The shift register unit may include: a first input circuit 11, a second input circuit 12, a first storage circuit 21, a second storage circuit 22, a first pull-down circuit 31, a second pull-down circuit 32, a first output circuit 41, a second output circuit 42, and a third storage circuit 23. The first input circuit 11 is connected to the first clock signal terminal CK, the first node N1, and the second node N2, and is used to transmit the signal of the first clock signal terminal CK to the second node N2 in response to the signal of the first node N1; the second input circuit 12 is connected to the signal input terminal IN, the third node N3, and the first clock signal terminal CK, and is used to transmit the signal of the signal input terminal IN to the third node N3 in response to the signal of the first clock signal terminal CK; the first storage circuit 21 is connected between the first clock signal terminal CK and the first node N1, and is used to store the voltage between the first node N1 and the first clock signal terminal CK; the second storage circuit 22 is connected between the second clock signal terminal CB and the second node N2, and is used to store the voltage between the second node N2 and the second clock signal terminal CB; the first pull-down circuit 31 is connected to the signal input terminal IN, the first power supply terminal VGL, the first node N1 , which is used to transmit the signal of the first power supply terminal VGL to the first node N1 in response to the signal of the signal input terminal IN; the second pull-down circuit 32 is connected to the first power supply terminal VGL, the third node N3, and the second node N2, and is used to transmit the signal of the first power supply terminal VGL to the second node N2 in response to the signal of the third node N3; the first output circuit 41 is connected to the second node N2, the first power supply terminal VGL, and the signal output terminal OUT, and is used to transmit the signal of the first power supply terminal VGL to the signal output terminal OUT in response to the signal of the second node N2; the second output circuit 42 is connected to the third node N3, the second power supply terminal VGH, and the signal output terminal OUT, and is used to transmit the signal of the second power supply terminal VGH to the signal output terminal OUT in response to the signal of the third node N3; the third storage circuit 23 is connected to the third node N3, and is used to store the voltage of the third node N3.

[0038] In this exemplary embodiment, the first power supply terminal VGL can output an inactive level, and the second power supply terminal VGH can output an active level. The active level is a level that can drive the target circuit to operate normally, and the inactive level is a level that shuts down the target circuit. For example, when the target circuit is an N-type transistor, the active level is a high level, and the inactive level is a low level.

[0039] The driving method of the shift register unit may include: a first buffer stage, a first stage, a second stage, a second buffer stage, a third stage, and a fourth stage. In the first buffer stage, an inactive level may be input to the first clock signal terminal CK, and an active level may be input to the signal input terminal IN and the second clock signal terminal CB. The third node N3 maintains the active level of the previous stage (the fourth stage). The second pull-down circuit 32 transmits the inactive level of the first power supply terminal VGL to the second node N2. The first output circuit 41 is turned off under the action of the inactive level of the second node N2. The second output circuit 42 transmits the active level of the second power supply terminal VGH to the signal output terminal OUT under the action of the active level of the third node N3. At the same time, the first pull-down circuit 31 is turned on under the action of the signal input terminal IN to transmit the inactive level of the first power supply terminal VGL to the first node N1. The first input circuit 11 and the second input circuit 12 are turned off. In the first phase, an inactive signal can be input to the signal input terminal IN and the first clock signal terminal CK, and an active signal can be input to the second clock signal terminal CB. The third node N3 maintains the active level of the previous phase (the first buffer phase). The second pull-down circuit 32 transmits the inactive level of the first power supply terminal VGL to the second node N2. The first output circuit 41 is turned off by the inactive level of the second node N2. The second output circuit 42 transmits the active level of the second power supply terminal VGH to the signal output terminal OUT by the active level of the third node N3. Simultaneously, the second input circuit 12 is turned off, the first node N1 maintains the inactive level of the previous phase (the first buffer phase), and the first input circuit 11 is turned off. In the second stage: an invalid level signal can be input to the signal input terminal IN and the second clock signal terminal CB, and a valid level signal can be input to the first clock signal terminal CK. The first storage circuit 21 couples the valid level of the first clock signal terminal CK to the first node N1, and the first input circuit 11 transmits the valid level of the first clock signal terminal CK to the second node N2. The first output circuit 41 transmits the invalid level of the first power supply terminal VGL to the signal output terminal OUT under the action of the second node N2. At the same time, the second input circuit 12 transmits the invalid level of the signal input terminal IN to the third node N3, and the second output circuit 42 and the second pull-down circuit 32 are turned off. In the second buffering stage, an invalid level can be input to the signal input terminal IN and the first clock signal terminal CK, and a valid level can be input to the second clock signal terminal CB. The first storage circuit 21 couples the invalid level of the first clock signal terminal CK to the first node N1, the first input circuit 11 and the second input circuit 12 are turned off, and the second storage circuit 22 couples the valid level of the second clock signal terminal CB to the second node N2. The first output circuit 41 transmits the invalid level of the first power supply terminal VGL to the signal output terminal OUT under the action of the second node N2. The third node N3 maintains the invalid level of the previous stage (second stage), and the second output circuit 42 is turned off.In the third stage: an invalid level signal is input to the first clock signal terminal CK, and a valid level signal is input to the signal input terminal IN and the second clock signal terminal CB. The first pull-down circuit 31 transmits the invalid level of the first power supply terminal to the first node N1 under the action of the signal input terminal IN, the first input circuit 11 is turned off, and the second node N2 maintains the valid level of the previous stage (in the second buffer stage). The first output circuit 41 continues to transmit the invalid level of the first power supply terminal VGL to the signal output terminal OUT under the action of the second node N2. At the same time, the third node N3 maintains the invalid level of the previous stage (in the second buffer stage), and the second output circuit 42 is turned off. In the fourth phase, an inactive level signal is input to the second clock signal terminal CB, and active level signals are input to the signal input terminal IN and the first clock signal terminal CK. The first pull-down circuit 31 transmits the inactive level of the first power supply terminal VGL to the first node N1, the first input circuit 11 is turned off, the second input circuit 12 transmits the active level of the signal input terminal IN to the third node N3, and the second output circuit 42 transmits the active level of the second power supply terminal VGH to the signal output terminal OUT under the action of the third node N3. At the same time, the second pull-down circuit 32 transmits the inactive level of the first power supply terminal VGL to the second node N2, and the first output circuit 41 is turned off. This shift register unit can output the enable signal required by the pixel driving circuit.

[0040] It should be understood that, in other exemplary embodiments, the driving method of the shift register unit may not include the first buffer stage and the second buffer stage.

[0041] In this exemplary embodiment, the first input circuit 11 may include: a first transistor T1, a first electrode of the first transistor T1 is connected to the first clock signal terminal CK, a second electrode is connected to the second node N2, and a gate is connected to the first node N1; the second input circuit 12 may include: a third transistor T3, a first electrode of the third transistor T3 is connected to the signal input terminal IN, a second electrode is connected to the third node N3, and a gate is connected to the first clock signal terminal CK.

[0042] In this exemplary embodiment, the first storage circuit 21 may include: a first capacitor C1, a first electrode of the first capacitor C1 is connected to the first clock signal terminal CK, and a second electrode of the first capacitor C1 is connected to the first node N1; the second storage circuit 22 may include: a second capacitor C2, a first electrode of the second capacitor C2 is connected to the second clock signal terminal CB, and a second electrode of the second capacitor C2 is connected to the second node N2; the third storage circuit 23 may include: a third capacitor C3, a first electrode of the third capacitor C3 is connected to the third node N3, and a second electrode of the third capacitor C3 is connected to the second power supply terminal VGH.

[0043] In this exemplary embodiment, the first pull-down circuit 31 may include: a second transistor T2, a first electrode of the second transistor T2 is connected to the first node N1, a second electrode is connected to the first power supply terminal VGL, and a gate is connected to the signal input terminal IN; the second pull-down circuit 32 may include: a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the second node N2, a second electrode is connected to the first power supply terminal VGL, and a gate is connected to the third node N3.

[0044] In this exemplary embodiment, the first output circuit 41 may include: a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the first power supply terminal VGL, a second electrode is connected to the signal output terminal OUT, and a gate is connected to the second node N2; the second output circuit 42 may include: a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the second power supply terminal VGH, a second electrode is connected to the signal output terminal OUT, and a gate is connected to the third node N3.

[0045] In this exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may all be N-type transistors. It should be understood that in other exemplary embodiments, the above transistors may also be P-type transistors.

[0046] like Figure 2 As shown, Figure 1 The timing diagram of each control signal in an exemplary embodiment of the shift register unit shown in the figure, wherein CK represents the timing diagram of the first clock signal terminal, CB represents the timing diagram of the second clock signal terminal, IN represents the timing diagram of the signal input terminal, and OUT represents the timing diagram of the signal output terminal.

[0047] like Figure 2 As shown, the driving method of the shift register unit may include: a first buffer stage t11, a first stage t1, a second stage t2, a second buffer stage t31, a third stage t3, and a fourth stage t4.

[0048] In the first buffering stage t11, a low level signal can be input to the first clock signal terminal CK, and a high level signal can be input to the signal input terminal IN and the second clock signal terminal CB. Figure 3 As shown, Figure 1 The state diagram of the shift register unit in the first buffer stage is shown in FIG. 1 , wherein, in this exemplary embodiment, the transistors with diagonal lines are off transistors, and the transistors without diagonal lines are on transistors. Figure 3As shown, the third node N3 maintains the high level of the previous stage (the fourth stage), the fourth transistor T4 is turned on, and the fourth transistor T4 transmits the low level signal of the first power supply terminal VGL to the second node N2. The fifth transistor T5 is turned off under the action of the low level signal of the second node N2, and the sixth transistor T6 is turned on under the action of the high level signal of the third node N3 to transmit the high level signal of the second power supply terminal VGH to the signal output terminal OUT. At the same time, the second transistor T2 is turned on under the action of the signal input terminal IN to transmit the low level signal of the first power supply terminal VGL to the first node N1, and the first transistor T1 and the third transistor T3 are turned off.

[0049] In the first stage t1: a low level signal can be input to the signal input terminal IN and the first clock signal terminal CK, and a high level signal can be input to the second clock signal terminal CB, such as Figure 4 As shown, Figure 1 The state diagram of the shift register unit shown in the first stage. The third node N3 maintains the high level of the previous stage (the first buffer stage), the fourth transistor T4 is turned on to transmit the low-level signal of the first power supply terminal VGL to the second node N2, the fifth transistor T5 is turned off in response to the low-level signal of the second node N2, and the sixth transistor T6 transmits the high-level signal of the second power supply terminal VGH to the signal output terminal OUT in response to the high-level signal of the third node N3. The first node N1 maintains the low level of the previous stage (the first buffer stage), and the first transistor T1 and the third transistor T3 are turned off.

[0050] In the second phase t2: a low level signal may be input to the signal input terminal IN and the second clock signal terminal CB, and a high level signal may be input to the first clock signal terminal CK. Figure 5 As shown, Figure 1 The shift register unit is shown in the state diagram of the second stage. The first capacitor C1 couples the high-level signal of the first clock signal terminal CK to the first node N1. The first transistor T1 is turned on to transmit the high-level signal of the first clock signal terminal CK to the second node N2. The fifth transistor T5 is turned on by the second node N2 to transmit the low-level signal of the first power supply terminal VGL to the signal output terminal OUT. At the same time, the third transistor T3 is turned on to transmit the low-level signal of the signal input terminal IN to the third node N3. The sixth transistor T6 and the fourth transistor T4 are turned off.

[0051] In the second buffering stage t31, a low level signal may be input to the signal input terminal IN and the first clock signal terminal CK, and a high level signal may be input to the second clock signal terminal CB. Figure 6 As shown, Figure 1The state diagram of the shift register unit shown is in the second buffer stage. In this diagram, the first capacitor C1 couples the low-level signal of the first clock signal terminal CK to the first node N1, the first transistor T1 and the third transistor T3 are turned off, the second capacitor C2 couples the high-level signal of the second clock signal terminal CB to the second node N2, the fifth transistor T5 is turned on by the second node N2 to transmit the low-level signal of the first power supply terminal VGL to the signal output terminal OUT, the third node N3 maintains the low level of the previous stage (second stage), and the sixth transistor T6 is turned off.

[0052] In the third stage: a low level signal is input to the first clock signal terminal CK, and a high level signal is input to the signal input terminal IN and the second clock signal terminal CB. Figure 7 As shown, Figure 1 FIG2 is a state diagram of the shift register unit in the third stage. In the state diagram, the second transistor T2 is turned on by the signal input terminal IN to transmit the low-level signal of the first power supply terminal to the first node N1. The first transistor T1 is turned off, and the second node N2 maintains the high level of the previous stage (the second buffer stage). The fifth transistor T5 is continuously turned on by the second node N2 to transmit the low-level signal of the first power supply terminal VGL to the signal output terminal OUT. At the same time, the third node N3 maintains the low level of the previous stage (the second buffer stage), and the sixth transistor T6 is turned off.

[0053] In the fourth stage: a low level signal is input to the second clock signal terminal CB, and a high level signal is input to the signal input terminal IN and the first clock signal terminal CK. Figure 8 As shown, Figure 1 The state diagram of the shift register unit shown in the fourth stage. The second transistor T2 is turned on to transmit the low-level signal of the first power supply terminal VGL to the first node N1. The first transistor T1 is turned off. The third transistor T3 is turned on to transmit the high-level signal of the signal input terminal IN to the third node N3. The sixth transistor T6 is turned on by the third node N3 to transmit the high-level signal of the second power supply terminal VGH to the signal output terminal OUT. The fourth transistor T4 is turned on to transmit the low-level signal of the first power supply terminal to the second node N2. The fifth transistor T5 is turned off.

[0054] like Figure 9 FIG2 is a schematic diagram of another exemplary embodiment of a shift register unit according to the present disclosure. The shift register unit may further include a third pull-down circuit 33, which may be connected to the second node N2, the third node N3, the first power supply terminal VGL, and the second clock signal terminal CB, and configured to transmit a signal from the first power supply terminal VGL to the third node N3 in response to a signal from the second node N2 and the second clock signal terminal CB.

[0055] In this exemplary embodiment, the third pull-down circuit 33 includes a seventh transistor T7 and an eighth transistor T8. The first electrode of the seventh transistor T7 is connected to the first power supply terminal VGL, and the gate is connected to the second node N2. The first electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, the second electrode is connected to the third node N3, and the gate is connected to the second clock signal terminal CB. The seventh transistor T7 and the eighth transistor T8 may be N-type transistors.

[0056] The timing diagram of each control signal in an exemplary embodiment of the shift register unit can be as follows: Figure 2 The driving method of the shift register unit may also include: a first buffer stage t11, a first stage t1, a second stage t2, a second buffer stage t31, a third stage t3, and a fourth stage t4.

[0057] In the first buffering stage t11, a low level signal can be input to the first clock signal terminal CK, and a high level signal can be input to the signal input terminal IN and the second clock signal terminal CB. Figure 10 As shown, Figure 9 The state diagram of the shift register unit in the first buffer stage is shown in FIG. 1 , wherein, in this exemplary embodiment, the transistors with diagonal lines are off transistors, and the transistors without diagonal lines are on transistors. Figure 10 As shown, the third node N3 maintains the high level of the previous stage (the fourth stage), the fourth transistor T4 is turned on, and the fourth transistor T4 transmits the low level signal of the first power supply terminal VGL to the second node N2. The fifth transistor T5 and the seventh transistor T7 are turned off under the action of the low level signal of the second node N2, and the sixth transistor T6 is turned on under the action of the high level signal of the third node N3 to transmit the high level signal of the second power supply terminal VGH to the signal output terminal OUT. At the same time, the second transistor T2 is turned on under the action of the signal input terminal IN to transmit the low level signal of the first power supply terminal VGL to the first node N1, the first transistor T1 and the third transistor T3 are turned off, and the eighth transistor T8 is turned on.

[0058] In the first stage t1: a low level signal can be input to the signal input terminal IN and the first clock signal terminal CK, and a high level signal can be input to the second clock signal terminal CB, such as Figure 11 As shown, Figure 9The state diagram of the shift register unit shown in the first stage. The third node N3 maintains the high level of the previous stage (the first buffer stage), the fourth transistor T4 is turned on to transmit the low-level signal of the first power supply terminal VGL to the second node N2, the fifth transistor T5 and the seventh transistor T7 are turned off in response to the low-level signal at the second node N2, the sixth transistor T6 transmits the high-level signal of the second power supply terminal VGH to the signal output terminal OUT in response to the high-level signal at the third node N3, the first node N1 maintains the low level of the previous stage (the first buffer stage), the first transistor T1 and the third transistor T3 are turned off, and the eighth transistor T8 is turned on.

[0059] In the second phase t2: a low level signal may be input to the signal input terminal IN and the second clock signal terminal CB, and a high level signal may be input to the first clock signal terminal CK. Figure 12 As shown, Figure 9 The shift register unit is shown in the state diagram of the second stage. The first capacitor C1 couples the high-level signal of the first clock signal terminal CK to the first node N1. The first transistor T1 is turned on to transmit the high-level signal of the first clock signal terminal CK to the second node N2. The fifth transistor T5 is turned on by the second node N2 to transmit the low-level signal of the first power supply terminal VGL to the signal output terminal OUT. At the same time, the third transistor T3 is turned on to transmit the low-level signal of the signal input terminal IN to the third node N3. The sixth transistor T6, the fourth transistor T4, and the eighth transistor T8 are turned off, and the seventh transistor is turned on.

[0060] In the second buffering stage t31, a low level signal may be input to the signal input terminal IN and the first clock signal terminal CK, and a high level signal may be input to the second clock signal terminal CB. Figure 13 As shown, Figure 9 The state diagram of the shift register unit shown in the second buffering stage. In this diagram, the first capacitor C1 couples the low-level signal of the first clock signal terminal CK to the first node N1, the first transistor T1 and the third transistor T3 are turned off, the second capacitor C2 couples the high-level signal of the second clock signal terminal CB to the second node N2, the fifth transistor T5 is turned on by the second node N2 to transmit the low-level signal of the first power supply terminal VGL to the signal output terminal OUT, the seventh transistor T7 and the eighth transistor T8 are turned on to transmit the low-level signal of the first power supply terminal VGL to the third node N3, and the sixth transistor T6 is turned off.

[0061] In the third stage: a low level signal is input to the first clock signal terminal CK, and a high level signal is input to the signal input terminal IN and the second clock signal terminal CB. Figure 14 As shown, Figure 9FIG2 is a state diagram of the shift register unit in the third stage. In the state diagram, the second transistor T2 is turned on by the signal input terminal IN to transmit the low-level signal of the first power supply terminal VGL to the first node N1. The first transistor T1 is turned off, and the second node N2 maintains the high level of the previous stage (the second buffer stage). The fifth transistor T5 is continuously turned on by the second node N2 to transmit the low-level signal of the first power supply terminal VGL to the signal output terminal OUT. At the same time, the seventh transistor T7 and the eighth transistor T8 are turned on to transmit the low-level signal of the first power supply terminal VGL to the third node N3. The sixth transistor T6 is turned off.

[0062] In the fourth stage: a low level signal is input to the second clock signal terminal CB, and a high level signal is input to the signal input terminal IN and the first clock signal terminal CK. Figure 15 As shown, Figure 9 The state diagram of the shift register unit shown in the fourth stage. The second transistor T2 is turned on to transmit the low-level signal of the first power supply terminal VGL to the first node N1. The first transistor T1 is turned off. The third transistor T3 is turned on to transmit the high-level signal of the signal input terminal IN to the third node N3. The sixth transistor T6 is turned on by the third node N3 to transmit the high-level signal of the second power supply terminal VGH to the signal output terminal OUT. The fourth transistor T4 is turned on to transmit the low-level signal of the first power supply terminal to the second node N2. The fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0063] This exemplary embodiment further provides a shift register unit driving method, the driving method comprising:

[0064] In the first stage: an invalid level signal is input to the signal input terminal IN and the first clock signal terminal CK, and a valid level signal is input to the second clock signal terminal CB;

[0065] In the second stage: an invalid level signal is input to the signal input terminal IN and the second clock signal terminal CB, and a valid level signal is input to the first clock signal terminal CK;

[0066] In the third stage: an invalid level signal is input to the first clock signal terminal CK, and a valid level signal is input to the signal input terminal IN and the second clock signal terminal CB;

[0067] In the fourth stage: an invalid level signal is input to the second clock signal terminal CB, and a valid level signal is input to the signal input terminal IN and the first clock signal terminal CK.

[0068] This exemplary embodiment also provides a gate drive circuit comprising a plurality of the aforementioned shift register units. The plurality of shift register units can be cascaded, with the signal output of the previous shift register unit connected to the signal input of the next shift register unit. The gate drive circuit can provide a gate drive signal or an enable signal to the pixel drive circuit.

[0069] This exemplary embodiment further provides a display panel, comprising the above-mentioned gate driving circuit, which can be applied to display devices such as mobile phones, tablet computers, and televisions.

[0070] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0071] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register unit, characterized in that: include: a first input circuit connected to the first clock signal terminal, the first node, and the second node, and configured to transmit the signal of the first clock signal terminal to the second node in response to the signal of the first node; a second input circuit connected to the signal input terminal, the third node, and the first clock signal terminal, and configured to transmit the signal from the signal input terminal to the third node in response to the signal from the first clock signal terminal; a first storage circuit, connected between the first clock signal terminal and the first node, and configured to store a voltage between the first node and the first clock signal terminal; a second storage circuit connected between the second clock signal terminal and the second node, and configured to store a voltage between the second node and the second clock signal terminal; a first pull-down circuit connected to the signal input terminal, the first power terminal, and the first node, and configured to transmit the signal of the first power terminal to the first node in response to the signal of the signal input terminal; a second pull-down circuit connected to the first power supply terminal, the third node, and the second node, and configured to transmit the signal of the first power supply terminal to the second node in response to a signal of the third node; a first output circuit connected to the second node, the first power supply terminal, and the signal output terminal, and configured to transmit the signal of the first power supply terminal to the signal output terminal in response to the signal of the second node; a second output circuit connected to the third node, the second power supply terminal, and the signal output terminal, and configured to transmit the signal of the second power supply terminal to the signal output terminal in response to the signal of the third node; The third storage circuit is connected to the third node and is used to store the voltage of the third node.

2. The shift register unit according to claim 1, wherein: The shift register unit further includes: The third pull-down circuit is connected to the second node, the third node, the first power supply terminal, and the second clock signal terminal, and is used to transmit the signal of the first power supply terminal to the third node in response to the signals of the second node and the second clock signal terminal.

3. The shift register unit according to claim 1, wherein: The first input circuit comprises: a first transistor, wherein a first electrode of the first transistor is connected to the first clock signal terminal, a second electrode of the first transistor is connected to the second node, and a gate of the first transistor is connected to the first node; The second input circuit includes: A third transistor, wherein a first electrode of the third transistor is connected to the signal input terminal, a second electrode is connected to the third node, and a gate is connected to the first clock signal terminal.

4. The shift register unit according to claim 1, wherein: The first storage circuit includes: a first capacitor, a first electrode of which is connected to the first clock signal terminal, and a second electrode of which is connected to the first node; The second storage circuit includes: a second capacitor, a first electrode of which is connected to the second clock signal terminal, and a second electrode of which is connected to the second node; The third storage circuit includes: The third capacitor has a first electrode connected to the third node and a second electrode connected to the second power supply terminal.

5. The shift register unit according to claim 1, wherein: The first pull-down circuit comprises: a second transistor, having a first electrode connected to the first node, a second electrode connected to the first power supply terminal, and a gate connected to the signal input terminal; The second pull-down circuit includes: The fourth transistor has a first electrode connected to the second node of the book search, a second electrode connected to the first power supply terminal, and a gate connected to the third node.

6. The shift register unit according to claim 1, wherein: The first output circuit includes: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the signal output terminal, and a gate electrode connected to the second node; The second output circuit includes: A sixth transistor has a first electrode connected to the second power supply end, a second electrode connected to the signal output end, and a gate connected to the third node.

7. The shift register unit according to claim 2, wherein: The third pull-down circuit comprises: a seventh transistor, a first electrode connected to the first power supply terminal, and a gate connected to the second node; An eighth transistor has a first electrode connected to the second electrode of the seventh transistor, a second electrode connected to the third node, and a gate connected to the second clock signal terminal.

8. A shift register unit driving method, characterized in that: The driving method is used to drive the shift register unit according to any one of claims 1 to 7, and the driving method includes: In the first stage: an invalid level signal is input to the signal input terminal and the first clock signal terminal, and a valid level signal is input to the second clock signal terminal; In the second stage: inputting an invalid level signal to the signal input terminal and the second clock signal terminal, and inputting a valid level signal to the first clock signal terminal; In the third stage: inputting an invalid level signal to the first clock signal terminal, and inputting a valid level signal to the signal input terminal and the second clock signal terminal; In the fourth stage: an invalid level signal is input to the second clock signal terminal, and a valid level signal is input to the signal input terminal and the first clock signal terminal.

9. A gate drive circuit, characterized in that: The gate driving circuit includes the shift register unit according to any one of claims 1 to 7.

10. A display panel, characterized in that: The display panel includes the gate driving circuit according to claim 9.

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