Non-volatile memory with optimized read

Abstract

This invention is entitled "Non-volatile memory with optimized reads." A non-volatile storage system that implements a storage region (e.g., a persistent storage region) and a cache of the storage region that are accessible by a host (e.g., via a PCIe connection) shares details of the structure of the storage region and / or cache (e.g., cache segment size). By being aware of the shared details of the structure of the storage region and / or cache, the host arranges and issues requests to read data from the persistent storage region in a manner that takes advantage of parallelism within the non-volatile storage system. For example, the host can initially issue one read request per cache segment to cause the non-volatile storage system to load the cache. Subsequently, additional read requests are made to the non-volatile storage system where data has already been loaded (or started to be loaded) in the cache, thereby improving performance.

Description

Background Technology

[0001] This technology relates to the operation of non-volatile memory devices.

[0002] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile or volatile memories. Non-volatile memories allow information to be stored and retained even when not connected to a power source (e.g., a battery). An example of a non-volatile memory is flash memory (e.g., NAND flash memory and NOR flash memory).

[0003] Many electronic devices utilize embedded or connected storage systems that include non-volatile memory. Electronic devices that include embedded storage systems or are connected to storage systems are generally referred to as host devices. Data stored in embedded or connected storage systems can be transferred to the host device for use by a host with various applications. For example, a storage system can store a database in non-volatile memory, which is used by applications on the host device to perform any number of tasks. The performance of the application, such as the time required to execute tasks, is important to the user of the application. To achieve high performance, applications need to be able to read data from the storage system without latency, so that the application is not slowed down by the delay in reading data from the storage system. Therefore, there is a need to improve the speed at which data is read from the storage system. Attached Figure Description

[0004] Components with similar numbers refer to common parts in different drawings.

[0005] Figure 1A It is a block diagram of one implementation of a storage system connected to the host.

[0006] Figure 1B This is a block diagram of one implementation scheme of the front-end processor circuit.

[0007] Figure 1C This is a block diagram of one implementation scheme for the back-end processor circuit.

[0008] Figure 1D This is a block diagram of one implementation scheme of a memory package.

[0009] Figure 1E This is a block diagram of one implementation of a volatile memory used with a memory controller.

[0010] Figure 1F This is a block diagram of one implementation scheme for PMR cache.

[0011] Figure 2A This is a functional block diagram of one implementation scheme for a memory die.

[0012] Figure 2B This is a functional block diagram of one implementation of an integrated memory component.

[0013] Figure 3 An example of a meta-block is shown.

[0014] Figure 4A This illustrates one implementation of the structure of a TLP read request message.

[0015] Figure 4B This illustrates one implementation of the structure of a TLP read complete message.

[0016] Figure 5A Multiple cache segments are shown, and an exemplary order in which the contents of the cache segments are read is shown.

[0017] Figure 5B Showing targets Figure 5A The implementation scheme specifies the order in which TLP read request messages are sent.

[0018] Figure 6 This is a flowchart describing one implementation of the process for reading data.

[0019] Figure 7 This is a flowchart describing one implementation of the process for reading data.

[0020] Figure 8 It is a flowchart describing one implementation of a process performed by the storage system.

[0021] Figure 9 It is a flowchart describing an implementation of a process performed by the host to read data from the storage system.

[0022] Figure 10 It is a flowchart describing an implementation of the process performed by the storage system when a host requests to read data.

[0023] Figure 11 It is a flowchart describing an implementation of a process performed by the storage system as part of a reading process.

[0024] Figure 12A This illustrates multiple cache segments and an exemplary order for reading the contents of a cache segment.

[0025] Figure 12B Showing targets Figure 12A The implementation scheme specifies the order in which TLP read request messages are sent. Detailed Implementation

[0026] To improve the speed of reading data from a non-volatile storage system, it is recommended that the non-volatile storage system share details of the structure of its storage regions and / or caches with the host. By being aware of the shared details of the structure of the storage regions and / or caches, the host can arrange and issue data read requests in a manner that leverages the parallelism within the non-volatile storage system.

[0027] In one implementation, the non-volatile storage system implements a persistent storage region (“PMR”) accessible to the host. To improve performance, the non-volatile storage system also implements a PMR cache comprising multiple cache segments. During initialization (or at another point in time), the non-volatile storage system informs the host of the size of the cache segments (or other information about the PMR and / or the PMR cache). When the host determines that it needs to read data from the PMR, it uses its knowledge of the cache segment sizes to identify which cache segments in the PMR cache will be used to read the data. The host first sends a single read request to the non-volatile storage system for each of the identified cache segments in the PMR cache to be used for reading data. In response, the non-volatile storage system loads data into the identified cache segment of the PMR cache and returns the requested data to the host. Upon receiving the requested data for the cache segment, the host then sends an additional read request for additional data in the corresponding cache segment. In this way, all or part of the first set of read requests are executed simultaneously with each other and simultaneously with all or part of the read requests for additional data. This concurrency improves the performance of the read process and results in the read data being delivered to the host in a shorter amount of time.

[0028] Figure 1AThis is a block diagram of one embodiment of a storage system 100 connected to a host system 120. The storage system 100 can implement the techniques disclosed herein. Many different types of storage systems can be used with the techniques disclosed herein. An exemplary storage system is a solid-state drive (“SSD”); however, other types of storage systems may also be used. The storage system 100 includes a memory controller 102, one or more memory packages 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. The memory controller 102 includes a front-end processor circuitry (FEP) 110 and one or more back-end processor circuitry (BEP) 112. In one embodiment, the FEP circuitry 110 is implemented on an ASIC. In one embodiment, each BEP circuitry 112 is implemented on a separate ASIC. In one embodiment, the ASIC for each of the BEP circuitry 112 and the FEP circuitry 110 is implemented on the same semiconductor, such that the memory controller 102 is fabricated as a system-on-a-chip (“SoC”). Both the FEP 110 and the BEP 112 include their own processors. In one implementation, FEP 110 and BEP 112 operate in a master-slave configuration, where FEP 110 is the master and each BEP 112 is a slave. For example, FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of SSDs (or other non-volatile memory systems). BEP circuit 112 manages memory operations within memory package 104 based on requests from FEP circuit 110. For example, BEP circuit 112 can implement read, erase, and program processes. Additionally, BEP circuit 112 can perform buffer management, set specific voltage levels required by FEP circuit 110, perform error correction (ECC), control the switching mode interface to the memory package, etc. In one implementation, each BEP circuit 112 is responsible for its own set of memory packages. Memory controller 102 is an example of control circuitry.

[0029] In one embodiment, there are multiple memory packages 104. Each memory package 104 may include one or more memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package 104 may include other types of memory; for example, the memory package may include phase-change memory (PCM) or magnetoresistive random access memory (MRAM).

[0030] In one embodiment, memory controller 102 communicates with host system 120 using interface 130, which implements NVM Express (NVMe) via PCI Express (PCIe). To operate with storage system 100, host system 120 includes a host processor 122, host memory 124, and PCIe interface 126 communicating via bus 128. Host memory 124 is the host's physical memory and may be DRAM, SRAM, non-volatile memory, or another type of storage device. Host 120 may also include a hard disk drive connected to bus 128 and / or a USB drive communicating with bus 128. Software (code) for programming host processor 122 may be stored in host memory 124, the hard disk drive connected to bus 128, or the USB drive. Host memory 124, the hard disk drive connected to bus 128, and the USB drive are examples of non-transitory processor-readable storage media storing processor-readable code that, when executed on host processor 122, causes host processor 122 to perform the methods described below.

[0031] The host system 120 is external to and separate from the storage system 100. In one embodiment, the storage system 100 is embedded within the host system 120. In other embodiments, the memory controller 102 may communicate with the host 120 via other types of communication buses and / or links, including, for example, via NVMe on a constructed architecture, or via a cache / memory coherent architecture based on Accelerator Cache Coherent Interconnect (CCIX), Fast Link Compute (CXL), Open Coherent Accelerator Processor Interface (OpenCAPI), Gen-Z, etc. For simplicity, the following embodiment will be described with reference to a PCIe example.

[0032] Figure 1B This is a block diagram of one implementation scheme of FEP circuit 110. Figure 1BA PCIe interface 150 and a host processor 152 communicating with a host system 120 are shown. The PCIe interface 150 includes a direct memory access (DMA) module to perform DMA transfers to host memory 124. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, typically between cores within a SoC. NOCs can span synchronous and asynchronous clock domains or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and delivers significant improvements compared to conventional bus and cross-switch interconnects. NOCs improve the scalability of SoCs and the power efficiency of complex SoCs compared to other designs. The wires and links of a NOC are shared by many signals. Because all links in a NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 operates and communicates with the DRAM (e.g., DRAM 106, which is volatile memory). The SRAM 160 is a local volatile RAM used by the memory processor 156. The memory processor 156 runs the FEP circuitry and performs various memory operations. Two PCIe interfaces, 164 and 166, also communicate with the NOC. Figure 1B In one embodiment, the memory controller 102 includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface 164 / 166 communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0033] Typically, a persistent memory region (PMR) is a region of persistent memory located within storage device 100 that can be accessed by host 120 using standard PCIe commands / transfers (e.g., reads or writes) without any of the overhead of typical NVMe command queues. Address ranges are assigned to the PMR for use by the host with standard PCIe commands / transfers. In various embodiments, the PMR may reside entirely in non-volatile memory 104, entirely in volatile memory (e.g., DRAM 106 or SRAM 160), or span both non-volatile and volatile memory. In one embodiment, storage device 100 implements the PMR within non-volatile memory 104, as described below. Access to the PMR is controlled by a PMR manager 184 (connected to NOC 154), which may be a separate processor (hardwired or software-programmed). In another embodiment, the PMR manager 184 is software running on memory processor 156 or host processor 152. PMR manager 184 includes PMR host access manager 186 and PMR cache manager 188, both of which can be dedicated circuitry, software, or a combination of both. PMR host access manager 186 manages communication with host 120. To improve PMR performance, memory controller 102 implements a PMR cache to store a subset of PMRs locally at the memory controller for faster access. In some implementations, the PMR cache is implemented in volatile memory such as DRAM 106 or SRAM 160. More details about the PMR cache will be discussed below. PMR cache manager 188 manages the PMR cache, reading from and writing to non-volatile memory 104.

[0034] Figure 1C This is a block diagram of one implementation scheme of BEP circuit 112. Figure 1C This is shown for communicating with FEP circuit 110 (e.g., with...). Figure 1B PCIe interface 200 communicates with one of PCIe interfaces 164 and 166. PCIe interface 200 communicates with two NOCs 202 and 204. In one implementation, the two NOCs may be combined into one large NOC. Each NOC (202 / 204) is connected to SRAM (230 / 260), buffers (232 / 262), processor (220 / 250), and data path controller (222 / 252) via XOR engine (224 / 254) and ECC engine (226 / 256).

[0035] ECC engines 226 / 256 are used to perform error correction, as is known in the art. Hereinafter, ECC engines 226 / 256 may be referred to as the controller ECC engine. XOR engines 224 / 254 are used to perform XOR operations on data, enabling data to be combined and stored in a recoverable manner in the event of programming errors. In one implementation, XOR engines 224 / 254 can recover data that could not be decoded using ECC engines 226 / 256.

[0036] Data path controller 222 is connected to memory interface 228 for communicating with the integrated memory component via four channels. Therefore, top NOC 202 is associated with memory interface 228 for the four channels used to communicate with the memory package, and bottom NOC 204 is associated with memory interface 258 for the four additional channels used to communicate with the memory package. In one embodiment, each memory interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. For each channel, there is one scheduler, one buffer, and one TM interface. The processor can be any standard processor known in the art. Data path controller 222 / 252 can be a processor, an FPGA, a microprocessor, or other type of controller. XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuitry referred to as hardware accelerators. In other embodiments, XOR engines 224 / 254 and ECC engines 226 / 256 can be implemented in software. The scheduler, buffers, and TM interfaces are hardware circuitry. In other embodiments, the memory interface (circuit for communicating with the memory die) can be... Figure 1C The different structures are depicted. Additionally, they have the same... Figure 1B Controllers with structures different from those in Figure 1C can also be used with the techniques described herein.

[0037] Figure 1D This is a block diagram of one embodiment of a memory package 104, which includes multiple memory dies 300 (memory die 0, memory die 1, memory die 2, ... memory die M) connected to a memory bus (data line and chip enable line) 318. The memory bus 318 is connected to a switching mode interface 270 for communication with the TM interface of the BEP circuit 112 (see, for example...). Figure 1CIn some embodiments, the memory package may include a small controller connected to the memory bus 318 and the TM interface 270. In summary, the memory package 104 may have eight or 16 memory dies; however, other numbers of memory dies may also be implemented. The techniques described herein are not limited to any particular number of memory dies. In some embodiments, the memory package may also include a processor, CPU device such as a RISC-V CPU, and a amount of RAM to help achieve some of the capabilities described below. The techniques described herein are not limited to any particular number of memory dies.

[0038] Figure 1E This is a block diagram of one embodiment of a volatile memory used with a memory controller 102. In one embodiment, Figure 1E The volatile memory is DRAM 106.

[0039] In many storage systems, non-volatile memory is addressed inwards to the memory system using physical addresses associated with one or more memory dies. However, the host uses logical addresses to address various memory locations. This allows the host to allocate data to contiguous logical addresses while the memory system remains idle, storing data as desired across the locations of one or more memory dies. To implement such a system, the memory controller typically performs a translation (“address translation”) between logical addresses used by the host and physical addresses used by the memory dies. An exemplary implementation is a data structure that maintains identification of the current translation between logical and physical addresses. An example of such a data structure is called an L2P table. For the purposes of this document, an L2P table is a data structure that identifies the translation between logical and physical addresses. An L2P table does not need to be a table in the literal sense, and many different forms of data structures can be used and referred to as L2P tables, as long as they enable the translation from logical to physical addresses. For the purposes of this document, one or more data structures that enable the translation from logical to physical addresses can be referred to as one L2P table or multiple L2P tables. For example, the data structure can be broken down into blocks or other units.

[0040] In one implementation, host 120 can use logical block addresses to address non-volatile memory. Memory controller 102 can use its L2P table to translate between logical block addresses used by host 120 and physical block addresses used within non-volatile memory 104.

[0041] Typically, memory controller 102 uses DRAM 106 to store all or a portion of the L2P table. In some examples, the memory space of the memory system is large enough that DRAM 106 cannot hold the L2P table or any other information (other than the L2P table) that DRAM 106 is used to store. In this case, the entire set of L2P tables is stored in non-volatile memory 104, and a subset of the L2P tables is cached in local memory (called the L2P cache). Figure 1E The DRAM 106 is shown, which stores L2P cache 282.

[0042] In one set of embodiments, storage system 100 implements PMR. To improve PMR performance, memory controller 102 implements PMR cache 284 to locally store a subset of PMR at the memory controller for faster access. In some embodiments, PMR cache 282 resides in DRAM 106. In another embodiment, L2P table 282 and PMR cache 284 reside in SRAM 160.

[0043] Figure 1F This is a block diagram of one implementation of a PMR cache 284 divided into cache segments. For example, Figure 1F N cache segments are shown: cache segment 0, cache segment 1, cache segment 2, ..., cache segment N-1. Each cache segment represents a portion of the PMR and stores the most recently accessed data in the PMR. When the memory controller 102 reads data from the PMR, it first stores the read data in the PMR cache 284 and then transfers it to the host. If the data is needed again, the memory controller can access the data from the PMR cache 284 instead of reading it from the PMR itself if the data is still in the PMR cache. When the memory controller 102 writes data to the PMR, the data to be written is first stored in the PMR cache 284 and then transferred to the PMR. In one embodiment, each cache segment has the same size, referred to as the cache segment size. In another embodiment, the size of a subset of cache segments is designed to be a common cache segment size, and other cache segments may have different sizes.

[0044] Figure 2A This is a block diagram illustrating an example of a memory die 300 that can implement the technology described herein. Memory die 300 (which may correspond to...) Figure 1COne of the memory dies 300 includes a non-volatile memory array 302. All or part of the memory array 302 serves as a PMR 350. In one embodiment, the PMR 350 resides on one memory die 300. In another embodiment, the PMR 350 resides on multiple memory dies 300. The array terminal lines of the memory array 302 include various word line layers organized in rows and various bit line layers organized in columns. However, other orientations may also be implemented. The memory die 300 includes row control circuitry 320, the output of which is 308 connected to a corresponding word line of the memory array 302. The row control circuitry 320 receives a set of M row address signals and one or more various control signals from system control logic circuitry 360, and typically includes circuitry such as a row decoder 322, an array terminal driver 324, and a block select circuitry 326 for both read and write operations. The row control circuitry 320 may also include read / write circuitry. The memory die 300 also includes column control circuitry 310, which includes a sense amplifier 330. The input / output 306 of this column control circuitry is connected to a corresponding bit line of the memory array 302. Although only a single block is shown for array 302, the memory die may include multiple arrays or multiple planes that can be accessed individually. The column control circuitry system 310 receives a set of N column address signals and one or more various control signals from system control logic unit 360, and typically includes circuitry such as a column decoder 312, an array terminal receiver or driver 314, a block selection circuitry system 316, and read / write circuitry systems and I / O multiplexers.

[0045] System control logic unit 360 receives data and commands from host 120 and provides output data and status to controller 102. In some embodiments, system control logic unit 360 includes a state machine 362 that provides die-level control for memory operations. In one embodiment, state machine 362 is programmable by software. In other embodiments, state machine 362 does not use software and is implemented entirely in hardware (e.g., circuitry). In yet another embodiment, state machine 362 is replaced by a microcontroller or microprocessor, which is located on or outside the memory chip. System control logic unit 360 may also include a power control module 364 that controls the power and voltage supplied to rows and columns of memory array 302 during memory operations, and may include charge pump and regulator circuitry for generating regulated voltages. System control logic unit 360 includes a storage device 366 that can be used to store parameters for operating memory array 302.

[0046] Commands and data are transmitted between memory controller 102 and memory die 300 via memory controller interface 368 (also referred to as the “communication interface”). Memory controller interface 368 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 368 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used. For example, memory controller interface 368 may implement a switching mode interface that connects to the switching mode interface of memory interface 228 / 258 of memory controller 102. In one embodiment, memory controller interface 368 includes a set of input and / or output (I / O) pins connected to memory controller 102.

[0047] In some embodiments, all components of memory die 300 (including system control logic 360) may be formed as part of a single die. In other embodiments, some or all of the system control logic 360 may be formed on different dies.

[0048] For the purposes of this document, the phrase "one or more control circuits" may include all or part of the memory controller 102, state machine 362, microcontroller, microprocessor, system control logic unit 360, row control circuitry 320, column control circuitry 310, and / or any or a combination of other similar circuitry for controlling non-volatile memory. One or more control circuits may consist of hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0049] In one embodiment, memory structure 302 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory, which is integrally formed in one or more physical stages of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0050] In another embodiment, memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0051] The exact type of memory array architecture or memory cell included in memory structure 302 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory array 302. Implementing the claimed new embodiments herein does not require a specific non-volatile memory technology. Other examples of suitable technologies for the memory cells of memory array (or other types of memory structure) 302 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of suitable technologies for memory cell architectures include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0052] One example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0053] Another example is magnetoresistive random access memory (MRAM), which stores data using magnetic storage elements. These elements are formed from two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of these layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the memory by an external magnetic field. The memory device is constructed from a grid of such memory cells. In one implementation for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0054] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by changing the coordination state of germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. Memory cells can be suppressed by preventing them from receiving light. In other PCM embodiments, memory cells are programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves. These memory elements within the individual selectable memory cells or bits may include additional series elements as selectors, such as bidirectional threshold switches or metallic insulator substrates.

[0055] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory configuration, or material composition, but encompass many related memory structures within the technical essence and scope as described herein and as understood by those skilled in the art.

[0056] Figure 2A The components can be grouped into two parts: the structure of the memory array 302 and the peripheral circuitry, which (in some embodiments) includes all the structures other than the memory array 302, namely 310, 320, and 360. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die reserved for the memory structure 302 in the memory system 100; however, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose significant limitations on these peripheral components. For example, the need to mount sense amplifier circuitry within the available area can be a major constraint on sense amplifier design architecture. The reduced available area relative to the system control logic unit 360 may limit the available functionality that can be implemented on the chip. Therefore, a fundamental trade-off must be made in the design of the memory die for the memory system 100 between the amount of dedicated area for the memory structure 302 and the amount of dedicated area for the peripheral circuitry.

[0057] Another area where the memory array 302 and the peripheral circuitry often conflict lies in the processing involved in forming these areas. Because these areas typically involve different processing techniques, trade-offs must be made when implementing different techniques on a single die. For example, when the memory array 302 is NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For instance, components such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in the system control logic unit 360 typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0058] To mitigate these limitations, the implementation scheme described below can... Figure 2A The components are separated onto individually formed dies, and then these dies are bonded together. More specifically, the memory array 302 can be formed on a single die (memory die), and some or all of the peripheral circuitry elements (including one or more control circuits) can be formed on separate dies (control dies). For example, the memory die can be formed solely of memory elements, such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry (even including elements such as decoders and sense amplifiers) can then be moved to separate control dies. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements that are now moved to separate peripheral circuitry system dies that can be optimized for CMOS processing. This provides more space for peripheral elements, and additional capabilities that might not be easily combined can now be incorporated if peripheral elements were confined to the edges of the same die that houses the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with an array on one die connected to peripheral components on the other memory circuit. For example, while the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one peripheral circuit die.

[0059] Figure 2B Show Figure 2A An alternative arrangement can be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 2BA functional block diagram of one embodiment of an integrated memory component 307 is depicted. One or more integrated memory components 307 may be used in a memory package 104 in a memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more simply, "dies"). Memory die 301 includes a memory array 302. Memory array 302 may contain non-volatile memory cells. All or part of memory array 302 serves as a PMR 350. In one embodiment, the PMR 350 resides in the memory array 302 on the memory die 301 of the integrated memory component 307. In one embodiment, the PMR 350 resides within a memory array or within a memory die. In another embodiment, the PMR 350 resides on multiple memory dies 300 and / or multiple integrated memory components 307.

[0060] The control die 311 includes control circuits 310, 320, and 360 (details of which are discussed above). In some embodiments, the control die 311 is configured to be connected to a memory array 302 in a memory die 301. Figure 2B An example of peripheral circuitry is shown, including control circuitry formed in peripheral circuitry or control die 311, which is coupled to a memory array 302 formed in memory die 301. General components are similar to... Figure 2A The system control logic unit 360, row control circuitry 320, and column control circuitry 310 are located in control die 311. In some embodiments, all or part of the column control circuitry 310 and all or part of the row control circuitry 320 are located on memory die 301. In some embodiments, some circuitry in the system control logic unit 360 is located on memory die 301.

[0061] System control logic unit 360, row control circuitry 320, and column control circuitry 310 can be formed using conventional processes (e.g., CMOS processes), making it possible to add components and functions more commonly found on memory controller 102, such as ECC, with few or no additional process steps (i.e., the same process steps used to manufacture controller 102 can also be used to manufacture system control logic unit 360, row control circuitry 320, and column control circuitry 310). Therefore, while removing such circuitry from a die (e.g., memory die 301) reduces the number of steps required to manufacture such a die, adding such circuitry to a die (e.g., control die 311) may not require many additional process steps.

[0062] Figure 2BA column control circuit 310, including a sense amplifier 350, is shown on a control die 311. This column control circuit is coupled to a memory array 302 on a memory die 301 via an electrical path 306. For example, the electrical path 306 can provide electrical connections between the column decoder 312, the driver circuit 314, the block selector 316, and the bit lines of the memory array (or structure) 302. The electrical path can extend from the column control circuit 310 in the control die 311 through pads on the control die 311 that bond to corresponding pads on the memory die 301 that connect to the bit lines of the memory structure 302. Each bit line of the memory structure 302 can have a corresponding electrical path in the electrical path 306, including a pair of bonded pads connected to the column control circuit 310. Similarly, a row control circuit 320 (including a row decoder 322, an array driver 324, and a block selector 326) is coupled to the memory array 302 via an electrical path 308. Each electrical path in electrical path 308 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 311 and the memory structure die 301.

[0063] In some embodiments, the integrated memory assembly 307 contains more than one control die 311 and / or more than one memory die 301. In some embodiments, the integrated memory assembly 307 includes a stack of multiple control dies 311 and multiple memory structure dies 301. In some embodiments, each control die 311 is attached (e.g., bonded) to at least one memory structure die among the memory structure dies 301.

[0064] Figure 3 This shows an example of a meta-block residing on M dies (die 0, die 1, ... die M-1). Figure 3 In one embodiment, each memory die includes two planes (plane 0 and plane 1) for a memory cell. However, in other embodiments, each memory die includes one plane for a memory cell or more than two planes for a memory cell. For the technology described herein, there is no limitation on the exact number of planes. Figure 3 In one implementation, each plane comprises X+1 physical blocks of memory cells (block 0, block 1, ..., block X). In another implementation, the memory controller groups the physical blocks from each plane into meta-blocks. For example, Figure 3Metablock 420 is shown, comprising blocks 4 from each plane; therefore, metablock 420 comprises M*2 physical blocks. In one embodiment, each block includes a set of word lines connected to all the NAND strings in that block. Each block also includes a set of bit lines, such that a bit line is connected to a subset of the NAND strings in that block (e.g., a bit line is connected to one NAND string, four NAND strings, six NAND strings, eight NAND strings, etc., depending on the architecture).

[0065] In one implementation, the erasure unit is a physical block. That is, the entire physical block is erased simultaneously.

[0066] In one implementation, the programming unit and the reading unit are physical pages. That is, a physical page represents the number of data bits that can be programmed or read simultaneously. In one implementation, a physical page includes all data stored in all memory cells connected to the same word line within the same physical block. In other implementations, a physical page includes a subset of the data stored in all memory cells connected to the same word line within the same physical block. For example, a physical page may include data stored in 1 / 4 (or other portion) of the memory cells connected to the same word line within the same physical block. In one exemplary implementation, a physical page is equal to 4KB. In a set of implementations using meta-blocks, the memory controller can write data to and read data from meta-pages, such that a meta-page includes physical pages from each physical block of the meta-block. In the example above where meta-block 420 includes M*2 physical blocks, the meta-page includes pages from M*2 physical blocks and thus stores M*2*4KB of data. As mentioned above regarding Figure 1F The PMR cache 284 discussed includes a set of cache segments. In one embodiment, each cache segment stores data from a single metapage. Therefore, each cache segment has a cache segment size of M*2*4KB. In other embodiments, cache segments may store data from a physical block, multiple metapages, or other amounts of data for a single page.

[0067] As described above, storage system 100 uses standard PCIe commands to implement PMRs that can be accessed (e.g., read or write) by host 120. In PCIe terminology, commands are included in transaction layer packets (“TLPs”), which refer to the transaction layer of the PCIe communication mechanisms (transaction layer, data link layer, and physical layer). A read operation includes two packets: a TLP from host 120 to storage system 100 querying the latter to perform a read operation (e.g., a read request TLP), and a TLP returning data from storage system 100 to host 120 (e.g., a complete TLP). Figure 4AThe diagram shows a TLP (Read Request TLP) from host 120 to storage system 100, which queries the latter to perform a read operation. Figure 4B The diagram illustrates the TLP (Completion TLP) that uses data to return from storage system 100 to host 120.

[0068] Figure 4A The read request TLP shown is generated by host 120 (e.g., host processor 122, host memory controller chipset, or another component of the host), and is sometimes referred to as the root union. The fields of the read request TLP are:

[0069] • Reserve the field marked with R.

[0070] The FMT field, along with the type field, indicates that this is a memory read request.

[0071] • For memory read requests, the TC, EP, and ATTR fields are set to zero.

[0072] • The TD bit indicates whether there is an additional CRC on the TLP data.

[0073] • The length field indicates the number of double words (32-bit words) of data to be read.

[0074] The Requester ID field identifies the sender of this packet. When set to zero, the sender is the root union.

[0075] The tag field functions as a tracking number: when the storage system responds, it must copy this value to the completion TLP. This allows the requester / host to match the completion answer with its request.

[0076] • The 1BE field (enabled by the first double word byte) allows selection of which of the four bytes in the first data double word is valid. (For example, setting it to 0xf indicates that all four bytes are valid).

[0077] • The address field is the address read from the PMR.

[0078] When storage device 100 (e.g., memory controller 102) receives a read request TLP, it responds by completing the TLP. That is, storage device 100 reads data blocks from PMR 350 and returns the results to host 120. The results include... Figure 4B The completed TLP is shown below. The fields of the completed TLP are:

[0079] • Reserve the field marked with R;

[0080] The FMT field, along with the type field, indicates that this is a complete grouping with data.

[0081] • The length field indicates the number of double words of data being transmitted.

[0082] • Byte Count Field: This field indicates the number of bytes remaining to be transmitted, including those in the current packet.

[0083] • The low-order address field consists of the seven least significant bits of the address, from which the first byte of the TLP is read.

[0084] • The Completer ID identifies the sender of this TLP.

[0085] • The requester ID identifies the recipient of this TLP.

[0086] The status field indicates whether the completion was successful.

[0087] • The BCM field is always zero except when the packet originates from a bridge with PCI-X;

[0088] This data field contains the data that is read and returned. This data is a set of two words. Figure 4B It only shows one double word, but can return more than one double word.

[0089] In one implementation, host 120 sends a read request TLP for 256 bytes of data, which is 64 double words; therefore, the length field of the read request TLP is set to 64. In another implementation, host 120 sends a read request TLP for 512 bytes of data, which is 128 double words; therefore, the length field of the read request TLP is set to 128. In other implementations, the host may send read requests for different amounts of data. The amount of data requested by the read request TLP is referred to herein as a TLP data unit.

[0090] As described above, in one embodiment, each cache segment of the PMR cache 284 has a cache segment size of M*2*4KB (where M is the number of dies). In an exemplary embodiment where the metablock spans sixteen dies, the cache segment size is (16*2*4KB) 128KB, which is significantly larger than the amount of data requested in a TLP data unit. In another embodiment, the cache segment size is 64KB. Therefore, in some embodiments, the TLP data unit is smaller than the cache segment size, allowing multiple TLP data units to be accommodated within a single cache segment.

[0091] Because the size of the data unit requested by the read request TLP differs from the size of the cache segment, the host is typically unaware of how the PMR cache is structured and operated. Furthermore, host-side applications using PMR are not optimized for managing non-volatile memory, and may inefficiently access PMR (e.g., failing to utilize parallelism in the storage system, thus degrading performance). For example, a loop iterating over a large buffer in PMR and performing a translation on each double word within the buffer will create a separate memory access for each double word, causing the PCIe link to overflow with tiny requests. Since each request for a page (physical page or metapage) can trigger one or more operations on non-volatile memory 104, a cache layer is needed to align small requests to flash constraints. Similarly, iteration at page boundaries can lead to inefficient load management. Because the PCIe TLP size is significantly smaller than the page size, serial reads or writes can cause queue bursts, and serial reads or writes can cause queue bursts and overflows in the PCIe layer when new pages are swapped in and out by the cache mechanism used for merging reads and writes.

[0092] Figure 5A Multiple cache segments are shown, and examples of hosts that inefficiently access PMR (e.g., without utilizing parallelism in the storage system, thus reducing performance) are provided (i.e., without using the techniques proposed in this paper). Figure 5A Four cache segments are shown: cache segment 0, cache segment 1, cache segment 2, and cache segment 3. These four cache segments are shown for illustrative purposes only. A PMR cache may have more than four cache segments. The exact number of cache segments depends on the specific implementation. Figure 5A In the example, each cache segment stores an equivalent of 128 TLP data units. For this example, Figure 5A Data in the cache segment is labeled based on the order in which the host requests TLP data units. The first TLP data unit requested by the host is labeled dTLP0, the second TLP data unit is labeled dTLP1, the third TLP data unit is labeled dTLP2, ... the 512th TLP data unit requested by the host is labeled dTLP511. The order in which the host requests TLP data units is illustrated by arrows 470, 472, 474, 476, 478, 480, and 482. Figure 5B These read requests are shown in the order they were issued by host 120 according to the read request TLP. Figure 5A The TLP data units are shown in the diagram. For example, TLP0 requests dTLP0, TLP1 requests dTLP1, TLP2 requests dTLP2, and so on.

[0093] When the storage system 100 receives a TLP0 (Read Request TLP), the PMR host access manager 186 translates the address in the TLP0 into an LBA (Logical Block Address) and sends the LBA to the memory processor 156 (see [link]). Figure 1B The controller 120 reads the entire metapage from the non-volatile memory and stores it as dTLP0, dTLP1, ..., dTLP127 in cache segment 0. When storing data in cache segment 0, dTLP0 is returned (from cache segment 0, not from non-volatile memory) in response to TLP0. Before the PMR cache manager 188 completes storing dTLP0, dTLP1, ..., dTLP127 into cache segment 0, the storage system 100 may have already received additional TLPs (e.g., TLP1, TLP2, TLP3, and possibly more). These additional TLPs will not be responded to until dTLP0, dTLP1, ..., dTLP127 are completely stored into cache segment 0. The host 120 will continue sending TLPs. There is a limit to the number of TLPs that may be pending. When TLP128 is received, the data in that TLP (i.e., dTLP128) is not yet in the PMR cache; therefore, storage system 100 will need to read the data from non-volatile memory and load it into the PMR cache. However, as described above, the storage system will not only read the data requested by TLP128. Instead, the storage system will read the metapage of the data and fill cache segment 1 with that metapage, thus storing dTLP128-dTLP255 in cache segment 1. Therefore, the read request embodied in TLP128 will have to wait while cache segment 1 is loaded. TLP256 and TLP384 will experience the same delay as they wait for the next metapage to be loaded into the PMR cache. Therefore, each time a TLP crosses a metapage boundary or cache segment boundary, there is a pause or delay when sending the complete TLP with the requested data. This pause slows down the read process performance.

[0094] To overcome this performance degradation during the read process, it is proposed that storage system 100 share details of the structure of PMR 350 and / or PMR cache 284 with the host. By being aware of the shared details of the structure of PMR 350 and / or PMR cache 284, host 120 can utilize the parallelism within storage system 100 to arrange and send read request TLPs. An example of the details of PMR 350 and / or PMR cache 284 is the cache segment size. If host 120 is aware of the cache segment size, it can optimize the read process compared to the details described above. Figure 5AThe described method of sending read requests is more efficient; for example, host 120 can utilize the parallelism built into storage system 100. The following section discusses... Figure 6 to Figure 12B More details are provided.

[0095] Figure 6 This is a flowchart describing one implementation of the process for reading data. In step 502, a non-volatile storage system 100, which implements a host-accessible storage region (e.g., PMR) and a cache of the storage region (e.g., a PMR cache), shares details of the structure of the storage region and / or cache with the host 120. For example, the storage system 100 informs the host 120 of the cache segment size. Note that although one example of a storage region is a PMR, other types of storage regions can also be used with the techniques described herein. In step 504, by being aware of the shared details of the structure of the storage region and / or cache, the host 120 arranges and issues a request to read data (e.g., a read request TLP) in a manner that utilizes the parallelism within the non-volatile storage system 100. In step 506, due to the arrangement of the host's read data request, data is read from the storage system 100 using the parallelism within the storage system 100. For example, in step 504, the host 120 may send read request TLPs for different cache segments before sending the entire read request TLP. In one implementation, when the host needs to read a large amount of data, the host will initially issue only a single TLP for each cache segment. Once all (or a portion) of the data has been loaded into the cache segment, the host 120 will issue additional read request TLPs. Figure 5AAs an example, host 120 initially sends TLP0, TLP128, TLP256, and TLP384 to storage system 100. Upon receiving TLP0, TLP128, TLP256, and TLP384, storage system 100 reads data from cache segment 0, cache segment 1, cache segment 2, and cache segment 3 and loads the data (dTLP1, dTLP1, ..., dTLP511) into the corresponding cache segments. In response to TLP0, storage system 100 reads the complete metapage including dTLP0, dTLP1, ..., dTLP127 and loads the data into cache segment 0. In response to TLP128, storage system 100 reads the complete metapage including dTLP128, dTLP129, ..., dTLP255 and loads the data into cache segment 1. In response to TLP256, storage system 100 reads the complete metapage including dTLP256, dTLP257, ..., dTLP383 and loads the data into cache segment 2. In response to TLP384, storage system 100 reads the complete metapage including dTLP384, dTLP385, ..., dTLP511 and loads the data into cache segment 3. In one embodiment, storage system 100 performs the process of reading and loading data from cache segments 0, 1, 2, and 3 in parallel (simultaneously). In another embodiment, the process of reading and loading data from cache segments 0, 1, 2, and 3 is performed serially. Even when performed serially, data in cache segment 1 may be loaded into cache segment 1 before storage system 100 receives TLP129.

[0096] Figure 7 This is a flowchart describing one implementation of the process for reading data. Figure 7 The process is Figure 6 An exemplary specific implementation of the process. In one implementation, Figure 7The process is performed by host 120. In step 550, host 120 accesses an indication of the cache segment size of non-volatile storage system 100, which implements storage regions (e.g., PMR 350) and caches of those storage regions (e.g., PMR cache 284). The cache includes multiple cache segments, each designed to have a cache segment size. In one example, storage system 100 sends the cache segment size to host 120 when storage system 100 is powered on and / or initialized. In another embodiment, storage system 100 sends the cache segment size to host 120 periodically or at times other than initialization. In another embodiment, storage system 100 sends the cache segment size to host 120 in response to a request from host 120. In yet another embodiment, host 120 determines what the cache segment size should be and notifies storage system 100 of that cache segment size. In another implementation, storage system 100 stores an indication of the cache segment size in a known location on host 120 for retrieval. Other variations may also be implemented.

[0097] In step 552, based on the cache segment size indication, host 120 determines a set of cache segments from the plurality of cache segments that will be used by storage system 100 to read a set of data. For example, if host 120 needs to read... Figure 5A If data is marked as dTLP256-dTLP390, then host 120 determines that storage system 100 will use cache segment 2 and cache segment 3 to read the requested data. Knowing the cache segment sizes, host 120 can determine which cache segments correspond to which pages or meta pages of data. In one embodiment, storage system 100 may also inform host 120 of the mapping between cache segments and PMR address ranges. In another embodiment, different cache segments may have different sizes, and storage system 100 informs host 120 which cache segments have which sizes.

[0098] In step 554, host 120 sends an initial read request for each cache segment in the group of cache segments corresponding to the data from the group of data. For example, see... Figure 5A In step 554, host 120 initially sends TLP0, TLP128, TLP256, and TLP384 to storage system 100. In the example above, host 120 only needs dTLP256-dTLP390, so host 120 will send TLP256 and TLP384 to storage system 100 in step 554.

[0099] In this example, host 120 will initially send TLP0, TLP128, TLP256, and TLP384 to storage system 100 in step 554. Storage system will respond to these four TLPs by reading data from dTLP0 to dTLP511, loading that data into cache segments 0 through 3, and sending four completion TLPs to host 120 (one completion TLP in response to TLP0, one completion TLP in response to TLP128, one completion TLP in response to TLP256, and one completion TLP in response to TLP384). The completion TLP in response to TLP0 will include dTLP0. The completion TLP in response to TLP128 will include dTLP128. The completion TLP in response to TLP256 will include dTLP256. The completion TLP in response to TLP384 will include dTLP384.

[0100] In step 556, after sending an initial read request for each cache segment in the set of cache segments, host 120 sends additional read requests for additional data in the cache segment corresponding to the set of data. Each read request is for a data unit (e.g., a TLP data unit). In some embodiments, the TLP data unit is smaller than the cache segment size, such that multiple TLP data units are combined within a single cache segment.

[0101] Figures 8 to 11 This is a flowchart describing one implementation of the process for reading data. Figures 8 to 11 The process is Figure 6 An exemplary specific implementation of the process. Figures 8 to 11 The process is also Figure 7 An exemplary specific implementation of the process. Figure 8 , Figure 10 and Figure 11 Describe the operation of storage system 100. Figure 9 Describe the operation of host 120.

[0102] exist Figure 8 In step 602, the storage system 100 is powered on and / or reset. In step 604, the storage system 100 is initialized. In step 606, the storage system shares the cache segment size of the PMR cache 284 with the host 120. This sharing of the cache segment size can be performed using any of the methods described above. In step 608, the storage system is operated using the implemented PMR 350. In one embodiment, the PMR 350 is implemented to allow direct memory-level access, and the PMR 350 is mapped to the host memory 124 so that direct pointer type reads or writes can be performed. Figure 9Steps 704 to 722 Figure 10 The process and Figure 11 The process is all taken as Figure 8 This is part of step 608.

[0103] Figure 9 Describes the operation of host 120 when reading PMR 350. Figure 9 Step 702 includes host 120 receiving the cache segment size of PMR cache 284. This sharing of the cache segment size can be performed using any of the methods described above. As mentioned above, host 120 may also receive other details of PMR 350 and PMR cache 284. As mentioned above, host 120 may receive one cache segment size or multiple cache segment sizes. In response to Figure 8 Step 606, execute Figure 9 Step 720.

[0104] exist Figure 9 In step 704, host 120 determines that a set of data needs to be read from PMR 350 and determines the addresses of this data in the PMR. In one embodiment, those addresses are in the host memory address space. In step 706, based on the cache segment size, host 120 determines the cache segment that storage system 100 will use to read the set of data. Step 706 is similar to step 552.

[0105] In step 708, host 120 generates and sends a first read request TLP (Read Request TLP is an example of a read request) for each cache segment that will be used by the storage system to read the set of data. As described above, the read request TLP requests to read a TLP data unit, which is smaller than the cache segment size, such that multiple TLP data units are combined within one cache segment. Figure 5AIn the example, the host initially sends TLP0, TLP128, TLP256, and TLP384 to storage system 100. However, different TLPs may be sent whenever the host sends at least one TLP for each cache segment that the storage system will use to read the set of data. For example, in step 708, host 120 may also send any one of TLP0-TLP127, any one of TLP128-TLP255, any one of TLP256-TLP383, and any one of TLP384-TLP511. In one example, host 120 sends TLP4, TLP135, TLP300, and TLP414 in step 708. In each of these examples, the host sends one read request for each cache segment in the set of cache segments that the storage system will use to read the set of data. In other embodiments, the host sends more than one read request for each cache segment in the set of cache segments that the storage system will use to read the set of data.

[0106] In step 710, host 120 monitors the reception of completion TLPs sent to host 120 in response to the first read request TLP sent by host 120 in step 708. In one embodiment, host 120 determines whether to receive a completion TLP for the currently operating cache segment. If not, host 120 continues to wait. If host 120 has already received a completion TLP for the current cache segment, host 120 will send additional read request TLPs for the current cache segment in steps 714 through 716. For example, if the host needs to read dTLP0-dTLP511 (step 704) and determines that storage system 100 will use cache segments 0 through 3 to read the data (step 706), then in step 708, host 120 will only send TLP0, TLP128, TLP256, and TLP384 to storage system 100. After host 120 sends a read request TLP for each cache segment in the set of cache segments, host 120 will send additional read requests (e.g., TLP1-TLP127, TLP129-TLP255, TLP257-TLP383, and TLP385-TLP511). In one embodiment, additional read requests TLPs are sent sequentially. Therefore, additional read requests TLPs are sent first for cache segment 0. Thus, a first-time step 714 is performed for this read procedure, where "current cache segment" is cache segment 0, and host 120 determines whether it has received a completion TLP for TLP0 (or which first read request for cache segment 0 was issued in step 708).

[0107] In step 714, host 120 generates and sends an additional read request TLP for the next TLP data unit of the current cache segment. Step 714 is executed for this read process, including generating and sending TLP1. In step 716, the host determines whether there are more TLP data units to request for the current cache segment. If the last TLP sent was TLP1, the answer is yes, and the process loops back to step 714, so TLP2 can be sent. This continues until all read request TLPs for the current cache segment have been sent (e.g., TLP0-TLP127 have been sent). When all read request TLPs for the current cache segment have been sent, the process continues at step 718, where host 120 determines whether there are more cache segments to read from it. If not, the read process is complete, and the read data is stored in host memory 124 (step 722). If more cache segments need to be read from it, host 120 will continue reading additional data starting from the next cache segment (step 720), and the process loops back to step 714 to begin reading additional data from the new current cache segment. For example, after reading all data from cache segment 0, host 120 will continue to request to read data from cache segment 1 (therefore, cache segment 1 becomes the new current cache segment), and the process loops back to step 714 to begin reading additional data from cache segment 1. Steps 714 to 722 include, after receiving at least one completion message for the corresponding cache segment, sending additional read requests for individual cache segments of the group of cache segments in response to a corresponding read request for the initial read request for each cache segment.

[0108] In the example above, the host reads data from cache segments from cache segment 0 to cache segment 3. However, host 120 can read data in a different order.

[0109] In the above implementation, host 120 does not initiate the transmission of additional read request TLPs for cache segments until host 120 receives at least one completion TLP for the cache segment. This is because when host 120 receives at least one completion TLP for the cache segment, host 120 knows that all data in the cache segment has been loaded into the PMR cache. In another implementation, instead of waiting until host 120 receives at least one completion TLP for the cache segment, host 120 can implement a timer that determines the time elapsed since the first read request TLP for each cache segment was transmitted in step 708. When the predetermined time elapsed, the additional read request TLP for step 714 can be transmitted. In one exemplary implementation, the predetermined time period can be the sum of the time required to read from non-volatile memory, the time required to load the read data into the PMR cache, and the time required to transmit the completion TLP. Other predetermined time periods may also be used. For example, step 714 may begin execution for cache segment 0 and dTLP1 after a predetermined time period following the sending of the initial read request (TLP0, TLP128, TLP256, and TLP384) for each cache segment. Alternatively, step 714 may begin execution for cache segment 0 and dTLP1 after a predetermined time period following the sending of the initial read request TLP0 for each cache segment 0.

[0110] Figure 10 Describe the operation of storage system 100. Figure 10 The process is executed multiple times so that the storage system reads the set of data from the PMR and loads the set of data into the set of cache segments. In step 830, the storage system 100 receives a read request TLP from the host 100. In response to Figure 9 Step 708 can be followed by step 830. As described above, in one embodiment, Figure 9 Step 708 may include sending more than one read request TLP. For example, in one embodiment, step 708 may include sending read requests TLP0, TLP128, TLP256, and TLP384. In this case, the storage system can perform simultaneous operations. Figure 10 The process is repeated four times. That is, for each of the read requests TLP0, TLP128, TLP256, and TLP384, the process is executed simultaneously starting from the beginning. Figure 10The process is illustrated with four examples to execute step 830. For the purposes of this document, the term "simultaneously" is used to mean that two or more events / processes / tasks occur during at least one common moment, even if they start and stop at different times. For example, storage system 100 may read a first set of data from PMR and load that first set of data into cache segment 0, while storage system 100 simultaneously reads a second set of data from PMR and loads that second set of data into second cache segment 1, even if the reading of the first set of data starts slightly earlier than the reading of the second set of data, because both processes are running from the start of the reading of the second set of data until the first set of data is loaded into cache segment 0.

[0111] In step 832, storage system 100 determines whether the data requested by the read request received in step 830 is already stored in PMR cache 284. If so, in step 834, the data requested by the read request received in step 830 is transferred from PMR cache 284 to host 120 as part of completing TLP. If the data requested by the read request received in step 830 is not yet stored in PMR cache 284, then (in step 836) storage system 100 determines whether the read request received in step 830 is the first read request for the relevant cache segment in PMR cache 284. If the TLP considered in step 836 is the first read request for the relevant cache segment in PMR 284, the storage system has not yet begun the process of filling the relevant cache segment; therefore, in step 838, the storage system reads the entire cache segment data from PMR 350 (including the data requested in the TLP) and loads that data into the appropriate cache segment. In one implementation, step 838 includes the storage system reading a meta page of data and storing the meta page in a cache segment. In one implementation, reading a meta page includes the memory controller reading physical pages of data from each of a plurality of memory dies and merging the physical pages of data to form a meta page corresponding to the cache segment of data. After loading the data read in step 838 into the cache segment, the data requested in the current read request TLP being processed is transferred to host 120 as part of step 840 in the completion TLP.

[0112] If, in step 836, storage system 100 determines that the TLP considered in step 836 is not the first read request for the relevant cache segment in PMR 284, then the storage system has begun the process of filling the relevant cache segment and does not need to begin another operation of reading from non-volatile memory. Instead, storage system 100 will wait until the data read in step 838 is loaded into the appropriate cache segment, and then transfer the data requested in the current read request TLP being processed to host 120 as part of step 840 upon completion of the TLP.

[0113] use Figure 5A Consider the following example of the components. If step 836 is executed by sending TLP128, then TLP128 is the first read request for the relevant cache segment in PMR cache 284; therefore, the process continues to step 838 to read the metapage including dTLP128-dTLP255 from PMR 350 and store that data in cache segment 1. If step 836 is being executed by TLP129, the storage system can determine that TLP129 is not the first read request for the relevant cache segment in PMR cache 284 because TLP128 has already been received; therefore, the process continues to step 840, allowing the storage system to wait until cache segment 1 is fully loaded in order to send dTLP129 to host 120 in the completed TLP.

[0114] In short, Figure 10 When storage system 100 receives a first read request for a cache segment, it reads the data from the PMR in non-volatile memory, loads the data into the cache segment, and returns the requested data to host 120. Upon receiving an additional read request, following the initial / first read request for the cache segment, storage system 100 responds by reading additional data from the appropriate cache segment and sending the read additional data to host 120, and then returns the additional data to host 120.

[0115] Figure 11 This is a flowchart describing one embodiment of the process for reading a meta page of data from a PMR 350 in non-volatile memory and storing that meta page's data in a cache segment of the PMR cache 284. Therefore, Figure 11 The process is Figure 10 An exemplary specific implementation of step 838. Figure 11In step 902, PMR manager 184 translates the PMR address from the read request TLP into a set of LBAs that include all the data requested in the read request TLP. In step 904, those LBAs are provided to memory processor 156, which implements a flash translation layer that translates the LBAs into physical addresses in non-volatile memory. In another embodiment, PMR 350 may also point to physical addresses in non-volatile memory instead of logical addresses; for example, data may initially be written using sequential modes (such as ZNS), and therefore a separate logical addressing at the PMR level is not required because data is always sequential and parallel within the memory die. In step 906, memory processor 156 (or processor 220 or another processor) will construct one or more read commands to simultaneously read data from one or more planes on one or more memory dies. If the bus between memory controller 102 and non-volatile memory 104 (see for...) Figure 1C If the memory packet communication channel shown is busy and unavailable for transmitting additional data (step 908), the memory controller 102 will wait until the bus becomes available. When the bus between the memory controller 102 and the non-volatile memory 104 becomes available for transmitting additional data, in step 910, the appropriate BEP 112 sends the one or more read commands to one or more memory dies, causing data of a meta page to be read simultaneously from one or more planes on one or more dies, including the PMR. In step 912, the memory controller 102 receives the data of the meta page sensed from one or more planes on one or more dies. In step 914, the data is decoded to remove error correction information (e.g., additional parity bits) and the original data is recovered. In step 916, the data read from the meta page is loaded into the appropriate cache segment.

[0116] Figure 12A It shows multiple cache segments and provides information based on... Figures 8 to 11 An example of a process that effectively reads PMR. Figure 12A Four cache segments are shown: cache segment 0, cache segment 1, cache segment 2, and cache segment 3. These four cache segments are shown for illustrative purposes only. A PMR cache may have more than four cache segments. The exact number of cache segments depends on the specific implementation. Figure 12A In the example, each cache segment stores an equivalent of 128 TLP data units. Note the reference label used for the data in the cache segment and... Figure 5A Matching the reference tags, but in Figure 12A In the example, the reference labels for the data are not based on the order in which the host requests the TLP data units. Host 120 according to Figure 8 The order in which the process requests TLP data units up to Figure 11 is shown in a diagrammatic form by arrows 950, 952, 954, 956, 958, 960, 962, 964, 966, and 968. For this example, Figure 12B shows these read requests in the order in which the host 120 issues the read request TLP.

[0117] exist Figure 12B Before any of the TLPs shown, storage system 100 notifies host 120 of the cache segment size (see [reference]). Figure 9 In step 702), host 120 determines that the set of data dTLP0-dTLP511 needs to be read from PMR 350 (see step 702). Figure 9 Step 704), and host 120 uses the cache segment size to determine a set of cache segments (cache segment 0, cache segment 1, cache segment 2, and cache segment 3) that will be used by storage system 100 to read the set of data (see step 704). Figure 9 Step 706).

[0118] Host 120 first sends at least one read request TLP for each cache segment in the set of cache segments that will be used by the storage system to read the set of data (see...). Figure 9 Step 708). For example, Figure 12B The first four read request TLPs sent by host 120 are shown to be TLP0, TLP128, TLP256, and TLP384. Therefore, this initial set of read request TLPs includes exactly one TLP for each cache segment in the set of cache segments that the storage system will use to read the set of data. In response to the initial set of read request TLPs (TLP0, TLP128, TLP256, and TLP384), storage system 100 reads at least a portion of the set of data from PMR 350 (e.g., all or a subset of the set of data), and in response to at least one read request for each cache segment in the set of cache segments, loads that portion of the set of data into the set of cache segments. For example, in response to receiving TLP0, TLP128, TLP256, and TLP384, storage system 100 simultaneously performs... Figure 10 The process is performed four times (once for each of TLP0, TLP128, TLP256, and TLP384). Figure 10 Each instance of the process results in a read of a meta page and loading that meta page into the corresponding cache segment (see [link]). Figure 10(Step 838). For example, in response to receiving TLP0, the storage system 100 determines that dTLP0 is not in the PMR cache 284 (step 832), and TLP0 is the first read request for PMR cache segment 0 (see step 836); therefore, the storage system 100 reads dTLP0-dTLP127 from PMR 250 (in non-volatile memory) and loads dTLP0-dTLP127 into cache segment 0 (see step 838). In response to receiving TLP128, the storage system 100 determines that dTLP128 is not in the PMR cache 284 (step 832), and that TLP128 is the first read request for PMR cache segment 1 (see step 836); therefore, the storage system 100 reads dTLP128-dTLP255 from PMR 250 (in non-volatile memory) and loads dTLP128-dTLP255 into cache segment 0 (see step 838). In response to receiving TLP256, the storage system 100 determines that dTLP256 is not in the PMR cache 284 (step 832), and that TLP256 is the first read request for PMR cache segment 2 (see step 836); therefore, the storage system 100 reads dTLP256-dTLP383 from PMR 250 (in non-volatile memory) and loads dTLP256-dTLP383 into cache segment 2 (see step 838). In response to receiving TLP384, the storage system 100 determines that dTLP384 is not in the PMR cache 284 (step 832), and that TLP384 is the first read request for PMR cache segment 3 (see step 836); therefore, the storage system 100 reads dTLP384-dTLP511 from PMR 250 (in non-volatile memory) and loads dTLP384-dTLP511 into cache segment 3 (see step 838).

[0119] Note that in other exemplary implementations, the initial set of read request TLPs can be TLPs other than TLP0, TLP128, TLP256, and TLP384. The host needs to send at least one TLP for each relevant cache segment. Therefore, the initial set of read request TLPs can include, for example, TLP5, TLP129, TLP383, and TLP440, because this set includes at least one TLP for each relevant cache segment.

[0120] In response to one or more of at least one read request for each cache segment in the set of cache segments, storage system 100 sends initial data back to host 120 using a completion TLP. This initial data is then sent from PMR cache 284 after the corresponding meta pages are loaded into the corresponding cache segment of PMR cache 284. For example, in response to TLP0, after loading dTLP0-dTLP127 into cache segment 0, the storage system transfers dTLP0 to host 120; in response to TLP128, after loading dTLP128-dTLP255 into cache segment 1, the storage system transfers dTLP128 to host 120; in response to TLP256, after loading dTLP256-dTLP383 into cache segment 2, the storage system transfers dTLP256 to host 120; and in response to TLP384, after loading dTLP384-dTLP511 into cache segment 3, the storage system transfers dTLP384 to host 120 (see [link to TLP128]). Figure 10 Step 840).

[0121] After host 120 sends at least one read request for each cache segment in the set of cache segments, host 120 sends an additional read request (TLP) for additional data in the set of data. In one embodiment, the additional read request (TLP) is sent after a predetermined time period has elapsed since the first read request (TLP) for each cache segment was sent. In one embodiment, the additional read request (TLP) is sent in response to a corresponding completion (TLP) (see [link]). Figure 9 (Steps 712 and 714). For example, in response to receiving a completion TLP of TLP0, host 120 will send TLP1-TLP127; in response to receiving a completion TLP of TLP128, host 120 will send TLP129-TLP255; in response to receiving a completion TLP of TLP256, host 120 will send TLP257-TLP383; and in response to receiving a completion TLP of TLP384, host 120 will send TLP385-TLP511 (see steps 712 and 714). Figure 12B ).

[0122] In response to an additional read request TLP, storage system 100 reads additional data from the corresponding cache segments (e.g., dTLP1-dTLP127, dTLP129-dTLP255, dTLP257-dTLP383, and dTLP385-dTLP511) and transfers this additional data to host 120 (see [link to cache]). Figure 10 Step 834, when executing TLP for each received read request. Figure 10 (This process is executed multiple times).

[0123] A non-volatile storage system has been disclosed, detailing the structure of its shared storage regions and / or caches (e.g., cache segment sizes). By being aware of these shared details of the storage regions and / or cache structures, a host can arrange and issue read requests in a manner that leverages the parallelism within the non-volatile storage system. For example, the host can initially issue one read request per cache segment to load the cache into the non-volatile storage system. Subsequently, additional read requests are made to the non-volatile storage system where data has already been loaded (or is beginning to be loaded) in the cache, thereby improving performance.

[0124] One implementation includes a method comprising: a non-volatile storage system notifying a host connected to the storage system of cache segment sizes, the non-volatile storage system implementing a persistent storage region (“PMR”) and a PMR cache comprising a plurality of cache segments, each of the plurality of cache segments having a cache segment size; the host determining that a set of data needs to be read from the PMR; the host using the cache segment sizes to determine a set of cache segments that will be used by the storage system to read the set of data; and the host sending a request to each cache segment in the set of cache segments that will be used by the storage system to read the set of data. At least one read request; in response to the at least one read request for each cache segment in the set of cache segments, the storage system reads at least a portion of the set of data from the PMR and loads at least said portion of the set of data into the set of cache segments; after the host sends at least one read request for each cache segment in the set of cache segments, the host sends additional read requests for additional data in the set of data; and in response to these additional read requests, the storage system reads the additional data from the set of cache segments and transfers the read additional data to the host.

[0125] One embodiment includes a non-transitory processor-readable storage medium storing processor-readable code, which, when executed on a processor, causes the processor to perform a method comprising the steps of: accessing an indication of the size of a cache segment of a non-volatile storage system implementing a storage region and a cache of the storage region, the cache including a plurality of cache segments, each of the plurality of cache segments having a size set to the cache segment size; determining, based on the cache segment size indication, a set of cache segments among the plurality of cache segments to be used by the storage system to read a set of data; sending an initial read request for each cache segment in the set of cache segments corresponding to data from the set of data; and, after sending the initial read request for each cache segment in the set of cache segments, sending additional read requests for additional data in the cache segments corresponding to the set of data, each of these read requests targeting a data unit smaller than the cache segment size such that multiple data units fit within a single cache segment.

[0126] One embodiment includes an apparatus comprising non-volatile memory configured to implement a host-accessible persistent storage region within the non-volatile memory; a persistent storage region cache including a plurality of cache segments, each the size of a cache segment; and a processor connected to the non-volatile memory and the persistent storage region cache. The processor is configured to communicate with a host. The processor is configured to transfer cache segment sizes to the host. The processor is further configured to receive from the host an initial set of read requests including a read request for each of a set of cache segments in the plurality of cache segments; to read data from persistent storage for each read request in the initial set of read requests; to store the read data in a cache segment in the set of cache segments; to send a completion response with the request data for each read request in the initial set of read requests after receiving the initial set of read requests; and, in response to the initial set of read requests, to receive additional read requests for data already stored in the set of cache segments and to send a completion response with the request data for each additional read request in the additional read requests, such that the sent request data is obtained from one or more cache segments in the set of cache segments.

[0127] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0128] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is mentioned as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between the two elements. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0129] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0130] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0131] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0132] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A method for reading data, comprising: The non-volatile storage system notifies the host connected to the storage system of the cache segment size. The non-volatile storage system implements a persistent storage region, namely "PMR", and a PMR cache including multiple cache segments, each of which has the cache segment size. The host determines that it needs to read a set of data from the PMR; The host uses the cache segment size to determine a set of cache segments that will be used by the storage system to read the set of data; The host sends multiple read requests, the multiple read requests including at least one read request for each of the set of cache segments to be used by the storage system to read the set of data; In response to the plurality of read requests, the storage system reads the dataset from the PMR, loads the dataset into the set of cache segments, and transfers data units from each cache segment in the set of cache segments to the host, such that each dataset is within the size of the cache segment and the data unit is smaller than the size of the cache segment, thereby multiple data units are combined within one cache segment; After the host sends at least one read request for each cache segment in the set of cache segments, the host sends an additional read request for additional data in the set of data; and In response to the additional read request, the storage system transmits the additional data to the host by reading the additional data from the set of cache segments and transmitting the read additional data to the host.

2. The method according to claim 1, further comprising: The storage system sends back first data to the host in response to one or more read requests for at least one read request in each of the set of cache segments, the first data being a data unit from the PMR cache, and the host sends the additional read request in response to receiving the first data.

3. The method according to claim 1, wherein: The plurality of cache segments include a first cache segment and a second cache segment; The at least one read request for each of the set of cache segments to be used by the storage system to read the set of data includes a first read request for a first data unit from the first cache segment and a second read request for a second data unit from the second cache segment; The storage system reads the dataset from the PMR, loads the dataset into the set of cache segments, and transmits data units from each cache segment of the set of cache segments, comprising: the storage system reads a first dataset from the PMR, loads the first dataset into the first cache segment, transmits the first data unit from the first cache segment to the host, reads a second dataset from the PMR, loads the second dataset into the second cache segment, and transmits the second data unit from the second cache segment to the host; The first dataset includes the first data unit, the second dataset includes the second data unit, the first dataset and the second dataset have the cache segment size, and the data unit is smaller than the cache segment size so that multiple data units are combined within one cache segment; and The additional read request includes an additional read request for additional data from the first cache segment and an additional read request for additional data from the second cache segment. The host sends the additional read request for additional data from the first cache segment in response to the storage system transmitting the first data unit from the first cache segment.

4. The method according to claim 3, wherein: The storage system reads the first dataset from the PMR and loads the first dataset into the first cache segment, and the storage system reads the second dataset from the PMR and loads the second dataset into the second cache segment simultaneously.

5. The method according to claim 1, further comprising: After the host sends at least one read request for each of the set of cache segments, the host waits for a predetermined period of time before sending the additional read request.

6. The method of claim 1, wherein the storage system reads a dataset from the PMR, loads the dataset into the set of cache segments, transfers data units from each cache segment, and transfers the read additional data to the host comprises: The storage system receives the TLP from the host; The storage system determines whether the data unit requested by the TLP is in the PMR cache; In response to determining that the data unit is in the PMR cache, the data unit is transmitted to the host; In response to determining that the data unit is not in the PMR cache, determine whether the TLP is a first read request for the PMR cache segment corresponding to the address in the TLP; as well as In response to determining that the TLP is a first read request for the PMR cache segment corresponding to the address in the TLP, PMR data is read from the PMR, the PMR data is loaded into the PMR cache, and the data unit is transferred from the PMR cache segment corresponding to the address in the TLP to the host.

7. The method according to claim 1, wherein: The storage system includes a memory controller connected to volatile memory and non-volatile memory, the PMR residing in the non-volatile memory, the PMR cache residing in the volatile memory, and the non-volatile memory including a plurality of memory dies; The plurality of cache segments include a first cache segment and a second cache segment; The at least one read request for each cache segment in the set of cache segments includes a first read request for a first data unit and a second read request for a second data unit; and The storage system reads a dataset from the PMR and loads the dataset into the set of cache segments, including the memory controller reading pages of data from each of the plurality of memory dies, aggregating the pages of data to form a cache segment of data, and storing the cache segment of data in the first cache segment.

8. The method according to claim 1, wherein: The host is connected to the storage system via a high-speed peripheral interconnect, or "PCIe" connection; and Each read request in the at least one read request for each cache segment in the set of cache segments is a PCIe transaction layer packet, or "TLP", requesting a data unit.

9. A non-transitory processor-readable storage medium storing processor-readable code, wherein the processor-readable code, when executed on a processor, causes the processor to perform the following methods: An indication of the cache segment size of a non-volatile storage system that implements a storage region and a cache of the storage region, the cache comprising multiple cache segments, each of the multiple cache segments having its size set to the cache segment size; Based on the indication of the cache segment size, a set of cache segments among the plurality of cache segments will be used by the storage system to read a set of data; as well as Sending a read request for host data to the non-volatile storage system includes sending an initial read request for each of the set of cache segments, waiting after sending the initial read request for each of the set of cache segments until receiving one or more completion responses for one or more of the initial read requests, and in response to receiving the one or more completion responses, sending an additional read request for data already stored in the set of cache segments, each of the read requests targeting a data unit smaller than the size of the cache segment such that multiple data units fit within one cache segment.

10. The non-transitory processor-readable storage medium according to claim 9, wherein: The storage area is a persistent storage area, or "PMR"; and The cache is a PMR cache.

11. The non-transitory processor-readable storage medium according to claim 9, wherein: The plurality of cache segments include a first cache segment and a second cache segment; The initial read request for each cache segment includes a first read request for a first data unit from the first cache segment and a second read request for a second data unit from the second cache segment; The method further includes receiving the first data unit from the non-volatile storage system; and The additional read request includes an additional read request for additional data from the first cache segment and an additional read request for additional data from the second cache segment. The additional read request for additional data from the first cache segment is sent to the non-volatile storage system in response to receiving the first data unit from the non-volatile storage system.

12. The non-transitory processor-readable storage medium according to claim 9, wherein: The plurality of cache segments include a first cache segment and a second cache segment; The initial read request for each cache segment includes a first read request for a first data unit from the first cache segment and a second read request for a second data unit from the second cache segment; and The additional read requests include additional read requests for additional data from the first cache segment and additional read requests for additional data from the second cache segment.

13. The non-transitory processor-readable storage medium according to claim 9, wherein: The set of data is stored at a set of addresses in the storage area; Determining the set of cache segments that the storage system will use to read the set of data includes determining which subgroup of the multiple cache segments corresponds to the set of addresses.

14. The non-transitory processor-readable storage medium according to claim 9, wherein: The instruction to access the cache segment size includes receiving the instruction to the cache segment size from the non-volatile memory system.

15. The non-transitory processor-readable storage medium according to claim 9, wherein: The storage area is a persistent storage area, or "PMR"; The cache is a PMR cache; The access, determination, and sending of the initial read request and the sending of the additional read request for each cache segment are performed by a host computer connected to the non-volatile storage system via a peripheral interconnect high-speed, i.e., "PCIe" connection. and Each read request for the initial read request for each cache segment is a PCIe transaction layer packet, or "TLP".

16. An apparatus for reading data, comprising: Non-volatile memory, wherein the non-volatile memory is configured to implement a persistent storage region accessible by the host. A persistent storage area cache, wherein the persistent storage area cache comprises multiple cache segments, each of which is the size of a cache segment; and A processor connected to the non-volatile memory and the persistent storage region cache, the processor being configured to communicate with a host, the processor being configured to transfer the cache segment size to the host, and the processor being further configured to: The host receives an initial set of read requests, including a read request for each of a set of cache segments within a plurality of cache segments, wherein the set of cache segments includes a first cache segment, a second cache segment, and a third cache segment. Each read request targets a data request unit smaller than the size of the cache segment, such that multiple data request units are coupled within a single cache segment. The initial set of read requests received includes receiving a read request for the first cache segment, a read request for the second cache segment, and a read request for the third cache segment. For each read request in the initial set of read requests, data is read from the persistent storage area. The read data is stored in the cache segment of the set of cache segments. Send a completion response containing the request data for each of the read requests in the initial set containing the read requests. After receiving the initial set of read requests, in response to the initial set of read requests, additional read requests for data already stored in the set of cache segments are received. Receiving additional read requests for data already stored in the set of cache segments includes receiving multiple read requests for the first cache segment, then receiving multiple read requests for the second cache segment, then receiving multiple read requests for the third cache segment, and so on. Send a completion response with request data for each of the additional read requests, such that the request data sent is obtained from one or more cache segments in the set of cache segments.

17. The apparatus of claim 16, further comprising: The processor includes a memory controller connected to the volatile memory, and the data request unit is smaller than the cache segment size, such that multiple data request units are coordinated within a single cache segment.

18. The apparatus of claim 16, further comprising: A computer external to the non-volatile memory and the processor, the computer implementing the host, the processor including a host interface for communicating with the host, the computer connected to the host interface, and the host configured to: Receive the cache segment size from the processor; Based on the cache segment size and the address of a set of host data, the set of cache segments among the plurality of cache segments is identified, because the set of cache segments will be used by the processor to read the set of host data, which includes the request data of each read request in the initial set of read requests and the request data of each additional read request in the additional read requests. The initial set from which the read request is sent; Wait until one or more completion responses for one or more read requests in the initial set of read requests are received; as well as In response to receiving the one or more completion responses, an additional read request for data already stored in the set of cache segments is sent.

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