Three-dimensional packaging structure and manufacturing method thereof

Abstract

The application discloses a three-dimensional packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate made of an organic resin material, processing a through hole on the substrate, and performing electroplating in the through hole to form an interconnection metal column; processing a through slot at a set position of the substrate, embedding a preset chip in the through slot, and plastic packaging; respectively performing line manufacturing on the pad side and the non-pad side of the substrate embedded with the preset chip to form conductive line layers, mounting a flip chip on one of the conductive line layers and plastic packaging, and ball planting on the other conductive line layer; wherein the conductive line layers are connected with the interconnection metal column, and the conductive line layers comprise a first conductive line layer and a second conductive line layer. The three-dimensional packaging structure has small packaging thickness, high packaging density, high density of three-dimensional interconnection structure, low manufacturing cost, and high precision of chip surface line.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular to a three-dimensional packaging structure and a manufacturing method thereof. BACKGROUND

[0002] In modern chip packaging technology, one widely used chip packaging technology is package on package (PoP), the main idea of which is to stack a memory chip on top of a logic chip (or flip-chip), and of course, further passive components can be mounted on top of the logic chip.

[0003] The biggest technical challenge of chip stacking packaging is the interconnection problem between the bottom package and the top package. Currently, the interconnection between the bottom package and the top package mainly adopts three methods:

[0004] The first method is based on traditional packaging technology, that is, after the chip is molded on the packaging substrate as the bottom package, a hole is drilled in the molding layer of the bottom package, the interconnection is realized by filling conductive paste in the hole, and then the top package is flip-chip mounted on the top of the bottom package.

[0005] The second method is based on advanced packaging technology, first, a seed layer is made on a temporary carrier, then a dry film is pasted to electroplate copper pillars, and the seed layer is etched, thus obtaining a three-dimensional interconnection structure, further mounting chips, and finally molding the chips to grind the copper pillars, thus obtaining a three-dimensional interconnection structure, and obtaining the bottom package, then welding the bottom package on the printed circuit board, and welding the top package on the bottom package.

[0006] The third method is also based on advanced packaging technology, first, a through hole is processed on an organic resin core board for printed circuit board, then electroplating is used to realize the interconnection of both sides of the organic resin core board, then a through slot is processed at the specified position, then the adhesive tape is pasted in sequence, and the chip is attached to the adhesive tape in the through slot, and finally the chip is molded, thus obtaining a three-dimensional interconnection structure. Obtain the bottom package, then weld the bottom package on the printed circuit board, and weld the top package on the bottom package.

[0007] However, in all the above methods, since the top package is generally a packaged chip, due to the thickness of the top package, there are problems such as low packaging density, low density of three-dimensional interconnection structure, high manufacturing cost, and low precision of chip surface circuit. SUMMARY

[0008] Based on this, a three-dimensional packaging structure and a manufacturing method thereof are provided to solve the problems of low packaging density, low density of three-dimensional interconnection structure, high manufacturing cost, and low precision of chip surface circuit in the prior art.

[0009] The embodiment of the present application provides a manufacturing method of a three-dimensional packaging structure, and the manufacturing method comprises the following steps:

[0010] A substrate of organic resin material is provided, a through hole is processed on the substrate, and an interconnection metal column is formed by electroplating in the through hole;

[0011] A through slot is processed at a set position of the substrate, and a preset chip is embedded in the through slot and is plastic encapsulated;

[0012] Conductive circuit layers are formed by respectively processing circuits on the pad side and the non-pad side of the substrate embedded with the preset chip, a flip bare chip is mounted on one of the conductive circuit layers and is plastic encapsulated, and balls are planted on the other conductive circuit layer; wherein the conductive circuit layers are connected with the interconnection metal column, and the conductive circuit layers comprise a first conductive circuit layer and a second conductive circuit layer.

[0013] Optionally, the step of "providing a substrate of organic resin material, processing a through hole on the substrate, and forming an interconnection metal column by electroplating in the through hole" specifically comprises the following steps:

[0014] A through hole is processed on the substrate of organic resin material at a position where the interconnection metal column needs to be formed;

[0015] A seed layer is formed, and the through hole is electroplated to obtain the interconnection metal column, and the surface of the substrate is completely covered with a copper layer.

[0016] Optionally, the step of "embedding a preset chip in the through slot and plastic encapsulating the preset chip" specifically comprises the following steps:

[0017] The one side of the substrate is bonded to a first temporary carrier by using bonding glue; the preset chip is attached to the through slot on the first temporary carrier by using an attaching film, and the pad of the preset chip is away from the first temporary carrier;

[0018] The preset chip in the through slot is plastic encapsulated.

[0019] Optionally, the step of "forming conductive circuit layers by respectively processing circuits on the pad side and the non-pad side of the substrate embedded with the preset chip, mounting a flip bare chip on one of the conductive circuit layers and plastic encapsulating the flip bare chip, and planting balls on the other conductive circuit layer" specifically comprises the following steps:

[0020] The pad side of the substrate is ground to expose the pad of the preset chip; and the first conductive circuit layer is formed by processing circuits on the pad side of the ground substrate;

[0021] mounting the flip-chip on the first conductive circuit layer, filling the flip-chip with a filler, and encapsulating the flip-chip;

[0022] attaching a second temporary carrier to the encapsulation of the flip-chip;

[0023] removing the first temporary carrier, grinding the non-pad side of the substrate after removing the first temporary carrier, and forming a second conductive circuit layer on the non-pad side of the substrate by circuit fabrication;

[0024] removing the second temporary carrier, and mounting balls on the first conductive circuit layer.

[0025] Optionally, the "forming a conductive circuit layer on the pad side and the non-pad side of the substrate with the preset chip embedded therein by circuit fabrication, mounting a flip-chip on one of the conductive circuit layers and encapsulating the flip-chip, and mounting balls on the other conductive circuit layer" specifically comprises:

[0026] grinding the pad side of the substrate to expose the pads of the preset chip, and forming a first conductive circuit layer on the pad side of the substrate after grinding by circuit fabrication;

[0027] attaching a second temporary carrier to the first conductive circuit layer, removing the first temporary carrier, grinding the non-pad side of the substrate after removing the first temporary carrier, and forming a second conductive circuit layer on the non-pad side of the substrate by circuit fabrication;

[0028] mounting the flip-chip on the second conductive circuit layer, filling the flip-chip with a filler, and encapsulating the flip-chip;

[0029] removing the second temporary carrier, and mounting balls on the first conductive circuit layer.

[0030] Optionally, the "forming a conductive circuit layer by circuit fabrication" specifically comprises:

[0031] adopting a build-up method to form a target number of conductive circuit layers by multiple cycles, wherein the conductive circuit layer comprises a conductive circuit and an insulating medium;

[0032] the conductive circuit is formed by a semi-additive method, and the insulating medium is one of photosensitive polyimide, thin composite material, and epoxy resin.

[0033] Optionally, the "mounting a flip-chip on one of the conductive circuit layers and encapsulating the flip-chip before mounting balls on the other conductive circuit layer" further comprises:

[0034] forming a surface treatment layer on the conductive circuit layer on which the flip-chip is mounted.

[0035] Optionally, the ball planting on the other conductive circuit layer specifically comprises:

[0036] A surface treatment layer is made on the conductive circuit layer requiring ball planting, and then a ball is planted on the conductive circuit layer with the surface treatment layer.

[0037] The method for manufacturing the three-dimensional packaging structure provided by the application packages the bare chips together, which can further reduce the thickness of the package and improve the packaging density compared with the stacked packaging. The organic resin substrate is used to assist the chip plastic packaging, which can not only manufacture the interconnection metal column with high density, low cost and high yield, but also improve the mechanical strength of the chip plastic packaging layer, and is especially suitable for large-size advanced packaging. In addition, the amount of plastic packaging material can be reduced, and the material cost of plastic packaging can be reduced. The organic resin substrate is used to assist the chip plastic packaging, which can improve the warpage resistance of the package and is conducive to realizing larger-size packages and improving the integration of the packaging products. The temporary carrier is used to assist the chip plastic packaging, specifically, the temporary carrier with small thermal expansion and isotropy is selected, which can significantly improve the predictability of the chip position deviation during the chip plastic packaging, the position accuracy after the chip plastic packaging, and the alignment accuracy of the conductive circuit on the chip pad side and the chip. The temporary carrier is used to assist the circuit manufacturing for multiple times, specifically, the temporary carrier with high flatness is selected, and the grinding technology is combined to obtain a surface with high flatness, which is conducive to manufacturing the conductive circuit with high precision and improving the packaging density of the chip.

[0038] The three-dimensional packaging structure provided by the embodiment of the application comprises:

[0039] The substrate of the organic resin material has a through hole, and the through hole is plated with an interconnection metal column;

[0040] The substrate is provided with a through slot, and a preset chip is embedded and plastic-packaged in the through slot;

[0041] The substrate is provided with a conductive circuit layer on each side, and the conductive circuit layer is connected with the interconnection metal column; a flip-chip is installed and plastic-packaged on one of the conductive circuit layers, and a ball is planted on the other conductive circuit layer.

[0042] Compared with the conventional stacked packaging technology, the three-dimensional packaging structure provided by the application uses the bare chip stacked packaging in the structure, and has higher packaging density. The three-dimensional packaging structure has the advantages of high density of the conductive circuit, small chip drift, and good predictability. In addition, the three-dimensional packaging structure also has the advantages of low manufacturing cost of the interconnection metal column, short plastic material flow distance, low processing and transportation difficulty, and good warpage resistance.

[0043] Optionally, a first conductive circuit layer is arranged on the pad side of the substrate embedded with the preset chip; and a second conductive circuit layer is arranged on the non-pad side of the substrate embedded with the preset chip.

[0044] The first conductive circuit layer and the second conductive circuit layer are connected with the interconnection metal column;

[0045] The flip-chip is mounted on the second conductive circuit layer and is encapsulated, and the flip-chip bottom is filled with a filling agent; the flip-chip is mounted on the first conductive circuit layer and is encapsulated, and the flip-chip bottom is filled with a filling agent.

[0046] Optionally, a first conductive circuit layer is arranged on the pad side of the substrate in which the preset chip is embedded; and a second conductive circuit layer is arranged on the non-pad side of the substrate in which the preset chip is embedded.

[0047] The first conductive circuit layer and the second conductive circuit layer are connected with the interconnection metal column;

[0048] The flip-chip is mounted on the second conductive circuit layer and is encapsulated, and the flip-chip bottom is filled with a filling agent; the flip-chip is mounted on the first conductive circuit layer and is encapsulated, and the flip-chip bottom is filled with a filling agent. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0050] Figure 1 is a flow chart of a manufacturing method of a three-dimensional packaging structure provided by an embodiment of the present application;

[0051] Figure 2-1 is a schematic diagram of processing a through hole on a substrate provided by an embodiment of the present application;

[0052] Figure 2-2 is a schematic diagram of electroplating a through hole on a substrate provided by an embodiment of the present application;

[0053] Figure 2-3 is a schematic diagram of processing a through slot on a substrate provided by an embodiment of the present application;

[0054] Figure 2-4 is a schematic diagram of pasting adhesive on a substrate provided by an embodiment of the present application;

[0055] Figure 2-5 is a schematic diagram of removing adhesive in a through slot on a substrate provided by an embodiment of the present application;

[0056] Figure 2-6 is a schematic diagram of pasting a first temporary carrier on a substrate by adhesive provided by an embodiment of the present application;

[0057] Figure 2-7is a schematic view of the present application for sticking a preset chip in a through slot on a first temporary carrier;

[0058] Figure 2-8 is a schematic view of the present application for plastic packaging a preset chip in a through slot;

[0059] Figure 2-9 is a schematic view of the present application for grinding a plastic packaging layer of a preset chip;

[0060] Figure 2-10 is a schematic view of the present application for forming a first conductive circuit on a substrate surface;

[0061] Figure 2-11 is a schematic view of the present application for flip-chip a bare chip on a first conductive circuit;

[0062] Figure 2-12 is a schematic view of the present application for filling a filler and plastic packaging at a bottom of a flip-chip on a first conductive circuit;

[0063] Figure 2-13 is a schematic view of the present application for sticking a second temporary carrier on a side of a flip-chip and removing a first temporary carrier;

[0064] Figure 2-14 is a schematic view of the present application for grinding on a side of a substrate where a first temporary carrier is removed;

[0065] Figure 2-15 is a schematic view of the present application for making a second conductive circuit layer on a side of a substrate where a first temporary carrier is removed;

[0066] Figure 2-16 is a schematic view of the present application for ball planting on a second conductive circuit layer on a substrate;

[0067] Figure 3-1 is a schematic view of the present application for grinding a first conductive circuit layer;

[0068] Figure 3-2 is a schematic view of the present application for sticking a second temporary carrier on a first conductive circuit layer and removing a first temporary carrier;

[0069] Figure 3-3 is a schematic view of the present application for sticking a second temporary carrier on a first conductive circuit layer and removing a first temporary carrier;

[0070] Figure 3-4 is a schematic view of the present application for grinding a second conductive circuit layer;

[0071] Figure 3-5 is a schematic diagram of a flip-chip on the second conductive circuit layer according to another embodiment of the present application;

[0072] Figure 3-6 is a schematic diagram of a plastic package on the second conductive circuit layer according to another embodiment of the present application;

[0073] Figure 3-7 is a schematic diagram of a ball-planting on the first conductive circuit according to another embodiment of the present application.

[0074] wherein 1 is an organic resin substrate, 2 is a via, 3 is an interconnection metal pillar, 4 is a through slot, 5 is an adhesive, 6 is a first temporary carrier, 7 is a chip, 8 is an adhesive film, 9 is a plastic package material, 10 is a first conductive circuit layer, 11 is a flip-chip, 12 is a micro-bump, 13 is a filler, 14 is a second conductive circuit, 15 is a second temporary carrier, and 16 is a BGA solder ball. DETAILED DESCRIPTION

[0075] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, technologies, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0076] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", when used in the present specification and in the accompanying claims, means the inclusion of but not limited to, an uncountable number of features, integers, steps, operations, elements, and / or groups thereof, but does not exclude the existence of or the addition of one or more other features, integers, steps, operations, elements, groups and / or their combinations.

[0077] It is also to be understood that the terminology "and / or" when used in the present specification and in the accompanying claims, means the association of one or more of the listed items with the associated item, as well as all possible combinations of the items.

[0078] As used in the present specification and in the accompanying claims, the term "if' can be interpreted as meaning "when", or "once", or "in response to a determination", or "in response to a detection" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to the determination", or "once [a described condition or event] is detected" or "in response to the detection [of a described condition or event]", depending on the context.

[0079] In addition, in the description of the present application and the appended claims, the terms "first", "second", "third", etc. are used only to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0080] In the present application, the reference to "one embodiment" or "some embodiments" means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in further some embodiments" and the like appearing in the present specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0081] It should be understood that the size of the serial number of each step in the following embodiments does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0082] In order to illustrate the technical solutions of the present application, the following will be described by specific embodiments.

[0083] Referring to Figure 1 is a flowchart of the manufacturing method of the three-dimensional packaging structure provided by an embodiment of the present application, and the method comprises:

[0084] S101, providing a substrate of organic resin material, processing a through hole on the substrate, and electroplating in the through hole to form an interconnection metal column.

[0085] Referring to Figure 2-1 and Figure 2-2 In an example, "providing a substrate 1 of organic resin material, processing a through hole 2 on the substrate 1, and electroplating in the through hole 2 to form an interconnection metal column 3" specifically comprises:

[0086] The substrate 1 of organic resin material is provided, and a through hole 2 is processed on the substrate 1 at the position where the interconnection metal column 3 needs to be manufactured;

[0087] A seed layer is manufactured, and the through hole 2 is electroplated to obtain the interconnection metal column 3, and the surface of the substrate 1 is completely covered with a copper layer, i.e. a metal layer.

[0088] Specifically, one organic resin substrate 1 is selected, and as preferred, the organic resin substrate 1 can be an organic resin substrate 1 with a copper foil covering the surface. A through hole 2 is processed at a preset position of the organic resin substrate 1 where the interconnection metal pillar 3 is to be made. The method for processing the through hole 2 on the organic resin substrate 1 can be to drill the through hole 2 on the organic resin substrate 1 by mechanical drilling, or to irradiate the organic resin substrate 1 by laser to form the through hole 2.

[0089] The inner wall of the through hole needs to be made into a seed layer. Currently, several seed layer making methods commonly used in the industry are:

[0090] (1) Sputtering (PVD) or evaporation (CVD). In this case, the surface and the hole wall will be attached with a metal layer, and the metal is generally one or two of copper, Ti, Ni, Cr, and Au. The most common one is Ti / Cu.

[0091] (2) Electroless copper plating. A reducing agent is used for catalytic reduction (catalyst is Pd), and a copper layer will be attached to the surface and the hole wall.

[0092] (3) Adsorption of conductive materials such as graphite, carbon black, graphene oxide, and conductive polymers, which will only be adsorbed at the position of the hole wall (without copper).

[0093] In the present application, the preferred order is electroless copper plating > sputtering / evaporation > adsorption of conductive materials.

[0094] Electroplating the through hole 2 refers to electroplating the through hole 2 of the organic resin substrate 1. The electroplating material can be copper, and the electroplating method is to fill the through hole 2 of the organic resin substrate 1 with metal by using direct current electroplating or pulse electroplating to form the interconnection metal pillar 3.

[0095] S102, processing a through slot at a preset position of the substrate, and embedding a preset chip in the through slot and plastic packaging.

[0096] Referring to Figures 2-3 to 2-8 , a through slot 4 is processed at a position of the organic resin substrate 1 where the preset chip 7 is to be embedded. The size of the through slot 4 is greater than the size of the preset chip. Alternatively, the space of the through slot 4 can accommodate one chip or two or more chips. The method for processing the through slot 4 on the organic resin substrate 1 can be to process the organic resin substrate 1 by laser to expose the through slot 4; or to process the organic resin substrate 1 by mechanical processing to expose the through slot 4.

[0097] Embedding the preset chip in the through slot and plastic packaging specifically includes:

[0098] As shown in Figure 2-4 , the adhesive is first pasted on one side of the substrate 1, and then as shown in Figure 2-5 , the adhesive 5 under the through slot is removed; and then as shown inFigure 2-6 As shown, the substrate 1 is bonded on the first temporary carrier 6 by the adhesive 5; as Figure 2-7 As shown, the preset chip 7 is attached in the through slot 4 of the first temporary carrier 6 by the attaching film 8, and the pads of the preset chip 7 are away from the first temporary carrier 6.

[0099] The attaching film 8 is used to replace the original tape on the non-pad side of the preset chip 7, and the preset chip 7 is attached to the first temporary carrier 6 with good coefficient of thermal expansion matching and uniformity, thereby avoiding the problem of large drift of the preset chip 7 caused by large difference in coefficient of thermal expansion of the tape in the prior art, and the fixing effect of the chip attaching film using resin curing and fixing is better than that of the tape with viscosity affected by temperature.

[0100] In an example, the adhesive 5 is a double-sided adhesive, one side of which is used to attach the organic resin substrate 1, and the other side is used to bond the first temporary carrier 6. The adhesive 5 is used to better fix the organic resin substrate 1 on the first temporary carrier 6.

[0101] Then, as shown, Figure 2-8 The preset chip 7 in the plastic encapsulation through slot specifically includes:

[0102] The plastic encapsulation material 9 is filled in the gap between the through slot wall of the organic resin substrate 1 and the preset chip 7 and covers the upper surface of the organic resin substrate 1. When more than two preset chips are placed in one through slot, the plastic encapsulation material also needs to fill the gap between the preset chips.

[0103] The plastic encapsulation material 9, also known as epoxy plastic encapsulation material, is a packaging material for electronic components, which is processed by using epoxy resin, phenolic resin as base resin, silicon powder as filler and various additives. It is a prior art.

[0104] The plastic encapsulation material 9 can be in the form of particles, liquid or film, and the plastic encapsulation method can be compression molding or vacuum film attaching. When vacuum film attaching is used for plastic encapsulation, only thin film type epoxy plastic encapsulation material can be used.

[0105] In an example, the first temporary carrier 6 is provided with a release layer on the side close to the organic resin substrate 1, and the attaching film is attached to the release layer.

[0106] The release layer can be a photosensitive debonding release layer, or a thermosensitive debonding release layer, and the photosensitive debonding release layer is preferred.

[0107] The purpose of the release layer is to facilitate the peeling of the organic resin substrate 1 and the attaching film 8 from the first temporary carrier. The release layer can ensure that the double-sided adhesive (adhesive) and the cured attaching film 8 are peeled off from the first temporary carrier without causing the first temporary carrier to break, the adhesive to remain, and the chip attaching film to break due to the huge stress during peeling.

[0108] S103, respectively making circuit on the pad side and the non-pad side of the substrate with the preset chip embedded to form conductive circuit layers, mounting the flip bare chip on one of the conductive circuit layers and plastic packaging, and planting balls on the other conductive circuit layer; wherein the conductive circuit layers are connected with the interconnection metal columns, and the conductive circuit layers include a first conductive circuit layer and a second conductive circuit layer.

[0109] It is particularly pointed out that the pad side in the text refers to the pad side of the preset chip, and the non-pad side in the text refers to the non-pad side of the preset chip.

[0110] Referring to Figures 2-9 to 2-16 In an example, "respectively making circuit on the pad side and the non-pad side of the substrate with the preset chip embedded to form conductive circuit layers, mounting the flip bare chip on one of the conductive circuit layers and plastic packaging, and planting balls on the other conductive circuit layer" specifically includes:

[0111] As shown in Figure 2-9 , the pad side of the substrate 1 is ground to expose the pads of the preset chip 7; circuit is made on the pad side of the ground substrate 1 to form a first conductive circuit layer 10;

[0112] Specifically, the pad side of the plastic packaged organic resin substrate 1 is ground to expose the pads of the preset chip. The grinding can be in the form of mechanical grinding, and the plastic packaging material and the metal layer on the pad side of the preset chip are ground off, so that the surface metal layer of the pad side of the organic resin substrate 1 is completely ground off and the pads on the surface of the preset chip are exposed. Because the flatness of the surface of the organic resin substrate 1 is high, the surface of the organic resin substrate 1 after grinding can obtain a high flatness surface, which is beneficial to the manufacture of fine circuit.

[0113] As shown in Figure 2-10 , the pad side of the ground organic resin substrate 1 is made to form a first conductive circuit 10, which specifically includes:

[0114] The pad side of the preset chip is made by a plurality of cycles of conductive circuit making by using the additive method, and each cycle is made by using the additive method to obtain a preset number of first connection circuits.

[0115] The target number of conductive lines is obtained by repeatedly fabricating the conductive lines on the pad side of the pre-defined chip using a multilayer stacking method. Each conductive line includes conductive lines and an insulating dielectric. The conductive lines are preferably fabricated using a semi-additive method. The photoresist material is selected based on the fineness of the conductive lines: liquid photoresist is preferred for lines below 8μm, while dry film is preferred for lines of 8μm and above. The insulating dielectric is selected based on the fineness of the conductive lines: photosensitive polyimide is preferred for lines below 8μm, ABF (Ajinomoto build-up film) is preferred for lines of 8μm and above, and epoxy resin reinforced with glass fiber cloth can be used for lines of 50μm and above.

[0116] The process of fabricating the first conductive circuit layer 10 is existing technology and will not be described in detail here.

[0117] Preferably, to ensure the reliability of subsequent installation of flip-chip bare chips, a surface treatment layer can be formed on the side of the first conductive line layer away from the chip pad on the side where the chip pad is embedded. The preferred method for forming the surface treatment layer is electroless nickel-gold plating, but electroplating nickel-gold, immersion silver, organic solder resist film, and tin plating can also be used.

[0118] like Figure 2-11 As shown, a flip-chip bare chip 11 is mounted on the first conductive circuit layer 10, such as... Figure 2-12 As shown, filler 13 is applied to the bottom of the flip-chip 11, and the flip-chip 11 is then encapsulated.

[0119] Specifically, this includes: the pads of the bare chip 11 are mounted on the first conductive circuit layer 10. When the bump size of the flip chip 11 is small, or the flip chip size is large, thermoforming bonding is preferred, and non-conductive adhesive film material is preferred for bottom filling of the chip; when the bump size of the flip chip is large, and the flip chip size is small, batch reflow soldering is preferred, and non-conductive adhesive film or capillary bottom filler is preferred for bottom filling of the chip. The flip chip 11 is encapsulated using molding compound 9, which is filled above the first conductive circuit layer 10 to form an encapsulation layer. The height of the encapsulation layer is not less than the height of the flip chip. Compression molding is preferred, and the molding compound can be epoxy molding compound, preferably granular or liquid molding compound, or film molding compound. Vacuum lamination is also an option; however, when vacuum lamination is used, only film-type epoxy molding compound can be used.

[0120] In one example, such as Figure 2-13 As shown, a second temporary carrier 15 can also be attached to the flip-chip bare chip side;

[0121] Specifically, this includes attaching a second temporary carrier 15 above the aforementioned flip-chip bare chip. The first temporary carrier 6 and the second temporary carrier 15 are rigid carriers, which can be one of a glass carrier, a stainless steel carrier, or a silicon wafer carrier.

[0122] When fabricating the second conductive line layer 14 on the substrate surface on the non-pad side of the embedded chip, a second temporary carrier 15 is added above the first conductive line layer 10 on the pad side of the embedded chip, and the substrate surface on the non-pad side of the embedded chip is ground to obtain a highly flat surface, thereby increasing the density of conductive lines on the non-pad side of the embedded chip and thus increasing the overall packaging density of the package. This is also to accommodate the increased demand for conductive lines due to the relatively higher actual chip (transistor) density within the package.

[0123] Remove the first temporary carrier 6, grind the copper layer on the non-pad side of the substrate after removing the first temporary carrier 6, and perform circuit fabrication on the non-pad side of the substrate to form the second conductive circuit layer 14.

[0124] Specifically, this includes: such as Figure 2-14 As shown, after removing the first temporary carrier 6, the non-pad side of the substrate 1 is ground away, removing the adhesive layer and the metal layer (copper layer) on the substrate surface. At this time, the chip pad side still has an attachment film of a preset thickness. When grinding the non-pad side of the substrate, there are no connection pads with a diameter slightly larger than the copper pillar at the copper pillar position, which is also beneficial to improving the design density of conductive lines on this side.

[0125] like Figure 2-15 As shown, the target number of conductive lines is obtained by multiple cycles of fabrication on the non-pad side of the embedded chip using a layering method. The conductive lines include conductive lines and insulating media. The conductive lines are preferably fabricated using a semi-additive method. The photoresist material is selected according to the fineness of the conductive lines: liquid photoresist is preferred for lines below 8μm, and dry film is preferred for lines of 8μm and above. The insulating media is selected according to the fineness of the conductive lines: photosensitive polyimide is preferred for lines below 8μm, ABF is preferred for lines of 8μm and above, and epoxy resin reinforced with glass fiber cloth can be selected for lines of 50μm and above.

[0126] The process of fabricating the second conductive circuit layer 14 is existing technology and will not be described in detail here.

[0127] Finally, as Figure 2-16 As shown, the second temporary carrier 15 is removed, and balls are planted on the second conductive circuit layer 14 to form BGA solder balls 16.

[0128] Specifically, this includes: removing the second temporary carrier 15 on the flip chip side, unbonding the method according to the release layer type, and removing the residual adhesive layer. Then, on the second conductive line layer on the non-pad side of the embedded chip, balls are placed on the surface away from the embedded chip to form BGA (Ball Grid Array) solder balls 16. The surface balling and forming BGA solder balls 16 are for soldering this three-dimensional package structure to the printed circuit board or other chip surface.

[0129] Instead of soldering the already packaged chip, the chip is directly flip-chip mounted on the embedded chip pad side and the whole chip is molded, which further reduces the thickness of the package and increases the chip density (transistor density) in the whole package.

[0130] Referring to the above-mentioned embodiments Figures 2-1 to 2-10 and Figures 3-1 to 3-7 In another example, the pad side and the non-pad side of the substrate embedded with the preset chip are respectively made into conductive circuit layers, the flip-chip is mounted on one of the conductive circuit layers and molded, and the ball is planted on the other conductive circuit layer, which specifically includes:

[0131] The steps of embedding the preset chip on the substrate and forming the first conductive circuit layer on the substrate are the same as those in the above-mentioned embodiments Figures 2-1 to 2-10 The above steps are the same as those in the above-mentioned embodiments, and will not be repeated here.

[0132] Then as shown in Figure 3-1 , the pad side of the substrate 1 is ground to expose the pad of the preset chip 7; the pad side of the ground substrate 1 is made into a circuit to form a first conductive circuit layer 10;

[0133] Then as shown in Figure 3-2 , the second temporary carrier 15 is attached to the first conductive circuit layer 10, and the first temporary carrier 6 is removed; then as shown in Figure 3-4 , the non-pad side of the substrate after the first temporary carrier is removed is ground, and as shown in Figure 3-5 , the non-pad side of the substrate is made into a circuit to form a second conductive circuit layer;

[0134] Specifically includes: attaching the second temporary carrier 15 to the upper surface of the first conductive circuit layer 10, removing the first temporary carrier 6, grinding off the adhesive and the metal layer on the surface of the organic resin substrate 1, and grinding off the preset thickness of the attached film on the non-pad side of the embedded chip. The non-pad side of the substrate 1 is made into a circuit to form a second conductive circuit layer 14. The second conductive circuit layer 14 is made of existing technology and will not be repeated here.

[0135] As shown in Figure 3-5 , the flip-chip 11 is mounted on the second conductive circuit layer 14, as shown in Figure 3-6 , the flip-chip 11 is filled with a filler 13 at the bottom, and the flip-chip 11 is molded;

[0136] Specifically, the pads of the bare chips 11 are connected to the second conductive circuit layer 14 through the micro bumps 12, the bare chips 11 and the second conductive circuit layer 14 are filled with a filler, the flip-chip is encapsulated by the plastic encapsulating material 9, the plastic encapsulating material 9 is filled on the side of the second conductive circuit layer 14 away from the non-pad side of the embedded chip, forming a plastic encapsulating layer, and the height of the plastic encapsulating layer is not less than the height of the flip-chip.

[0137] As shown in the figure, the second temporary carrier 15 is removed, and the BGA tin balls 16 are planted on the first conductive circuit layer 10. Figure 3-7

[0138] Specifically, the second temporary carrier 15 is removed, and the BGA tin balls 16 are planted on the first conductive circuit layer 10. The purpose of planting the BGA tin balls 16 is to weld the three-dimensional encapsulating structure to the printed circuit board or other chip surface.

[0139] The flip-chip is located on the non-pad side of the embedded chip. In the present example, higher density circuits and more tin balls can be arranged on the pad side of the embedded chip (the number of tin balls is limited by the density of the interconnection copper column when the tin balls are located on the non-pad side of the embedded chip). Therefore, a package with higher overall chip (transistor) density can be obtained, and a higher transistor density embedded chip or more embedded chips can be used.

[0140] The method for manufacturing the three-dimensional encapsulating structure provided by the present application encapsulates the bare chips together, which can further reduce the thickness of the package and improve the encapsulating density compared with the stacked package. The organic resin substrate is used to assist the chip encapsulation, which can not only manufacture the interconnection metal column with high density, low cost and high yield, but also improve the mechanical strength of the chip encapsulating layer, and is especially suitable for large-size advanced encapsulation. In addition, the amount of the plastic encapsulating material can be reduced, and the material cost of the encapsulation can be reduced. The organic resin substrate is used to assist the chip encapsulation, which can improve the warpage resistance of the package and is conducive to realizing larger-size packages and improving the integration of the encapsulation products. The temporary carrier is used to assist the chip encapsulation, specifically, the selection of the temporary carrier with small thermal expansion and isotropy can significantly improve the predictability of the position deviation of the chip during the chip encapsulation, the position accuracy of the chip after the chip encapsulation, and the alignment accuracy of the conductive circuit on the pad side of the chip and the chip. The temporary carrier is used to assist the circuit manufacturing for multiple times, specifically, the selection of the temporary carrier with high flatness combined with the grinding technology can obtain a surface with high flatness, which is conducive to manufacturing the conductive circuit with high precision and improving the encapsulating density of the chip.

[0141] The schematic diagram of the three-dimensional encapsulating structure provided by an embodiment of the present application, the three-dimensional encapsulating structure comprises:

[0142] The substrate of the organic resin material has a through hole, and the through hole is plated with an interconnection metal column;

[0143] ​The substrate is provided with a through slot, and a preset chip is embedded in the through slot and is plastic encapsulated;

[0144] The substrate is provided with conductive circuit layers on two sides, and the conductive circuit layers are connected with the interconnection metal column; a flip chip is mounted on one of the conductive circuit layers and is plastic encapsulated, and a ball is planted on the other conductive circuit layer.

[0145] In an example, referring to Figure 2-16 , a first conductive circuit layer 10 is arranged on the pad side of the substrate 1 in which the preset chip 7 is embedded; a second conductive circuit layer 14 is arranged on the non-pad side of the substrate 1 in which the preset chip 7 is embedded;

[0146] The first conductive circuit layer 10 and the second conductive circuit layer 14 are connected with the interconnection metal column 3;

[0147] The flip chip 11 is mounted on the first conductive circuit layer 10 and is plastic encapsulated, and a filler 13 is filled at the bottom of the flip chip 11; a ball is planted on the second conductive circuit layer 14.

[0148] The substrate 1 is a substrate of organic resin material. The embedded preset chip 7 and the inner wall of the substrate are filled with plastic encapsulant 9, the flip chip 11 and the first conductive circuit layer 10 are filled with plastic encapsulant 9, and the embedded preset chip 7 and the second conductive circuit layer 14 on the non-pad side also exist with the attached film 8.

[0149] In another example, referring to Figure 3-7 , a first conductive circuit layer 10 is arranged on the pad side of the substrate 1 in which the preset chip 7 is embedded; a second conductive circuit layer 14 is arranged on the non-pad side of the substrate 1 in which the preset chip 7 is embedded;

[0150] The first conductive circuit layer 10 and the second conductive circuit layer 14 are connected with the interconnection metal column 3;

[0151] The flip chip 11 is mounted on the second conductive circuit layer 14 and is plastic encapsulated, and a filler 13 is filled at the bottom of the flip chip 11; a ball is planted on the first conductive circuit layer 10.

[0152] In an example, the filler 13 at the bottom of the flip chip is a non-conductive adhesive film or a capillary bottom filling adhesive.

[0153] The substrate 1 is a substrate of organic resin material. The embedded preset chip 7 and the inner wall of the substrate are filled with plastic encapsulant 9, the flip chip 11 and the second conductive circuit layer 14 are filled with plastic encapsulant 9, and the embedded preset chip 7 and the second conductive circuit layer 14 on the non-pad side also exist with the attached film 8.

[0154] Compared with the conventional stack packaging technology, the three-dimensional packaging structure uses a bare chip stack packaging in structure, has higher packaging density, and has the advantages of high flatness of a temporary carrier, small chip drift, and good predictability.

[0155] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a three-dimensional encapsulation structure, characterized in that, The manufacturing method comprises: providing a substrate of organic resin material, processing a through hole on the substrate, and electroplating in the through hole to form an interconnection metal column; processing a through slot at a set position of the substrate, embedding a preset chip in the through slot and plastic packaging; wiring on the pad side and the non-pad side of the substrate embedding the preset chip respectively to form a conductive circuit layer, mounting a flip bare chip on one of the conductive circuit layers and plastic packaging, and ball mounting on the other conductive circuit layer; wherein the conductive circuit layer is connected with the interconnection metal column, and the conductive circuit layer comprises a first conductive circuit layer and a second conductive circuit layer; the "embedding the preset chip in the through slot and plastic packaging" specifically comprises: bonding one side of the substrate to a first temporary carrier by using adhesive, and attaching the preset chip to the through slot on the first temporary carrier by using an attaching film, wherein the pads of the preset chip are away from the first temporary carrier; plastic packaging the preset chip in the through slot.

2. The method of claim 1, wherein the "providing a substrate of organic resin material, processing a through hole on the substrate, and electroplating in the through hole to form an interconnection metal column" specifically comprises: providing a substrate of organic resin material, processing a through hole on the substrate at a position where the interconnection metal column is needed to be manufactured; manufacturing a seed layer and electroplating the through hole to obtain the interconnection metal column, wherein the surface of the substrate is completely covered by a copper layer.

3. The method of claim 1, wherein the method further comprises: the "wiring on the pad side and the non-pad side of the substrate embedding the preset chip respectively to form a conductive circuit layer, mounting a flip bare chip on one of the conductive circuit layers and plastic packaging, and ball mounting on the other conductive circuit layer" specifically comprises: polishing the pad side of the substrate to expose the pads of the preset chip, and wiring on the pad side of the preset chip to form a first conductive circuit layer; mounting a flip bare chip on the first conductive circuit layer, filling the bottom of the flip bare chip with a filler, and plastic packaging the flip bare chip; attaching a second temporary carrier to the side of the plastic packaging material of the flip bare chip; removing the first temporary carrier, polishing the non-pad side of the preset chip after removing the first temporary carrier, and wiring on the non-pad side of the preset chip to form a second conductive circuit layer; removing the second temporary carrier, and ball mounting on the second conductive circuit layer.

4. The method of claim 1, wherein the method further comprises: the "wiring on the pad side and the non-pad side of the substrate embedding the preset chip respectively to form a conductive circuit layer, mounting a flip bare chip on one of the conductive circuit layers and plastic packaging, and ball mounting on the other conductive circuit layer" specifically comprises: polishing the pad side of the substrate to expose the pads of the preset chip, and wiring on the pad side of the polished substrate to form a first conductive circuit layer; attaching a second temporary carrier to the first conductive circuit layer, and removing the first temporary carrier; polishing the non-pad side of the preset chip after removing the first temporary carrier, and wiring on the non-pad side of the preset chip to form a second conductive circuit layer; mounting the flip bare chip on the second conductive circuit layer, filling the bottom of the flip bare chip with a filler, and plastic packaging the flip bare chip; removing the second temporary carrier, and balling on the first conductive circuit layer.

5. The method of claim 1-4, wherein The "forming conductive circuit layer by circuit fabrication" specifically comprises: The target number of conductive circuit layers are obtained by multiple cycles of fabrication using the lamination method, the conductive circuit layer comprises conductive circuit and insulating medium, the conductive circuit is fabricated by the semi-additive method, and the insulating medium is one of photosensitive polyimide, thin composite material or epoxy resin.

6. The method of claim 1, wherein The method further comprises: fabricating a surface treatment layer on the conductive circuit layer on which the flip-chip is mounted; The balling on the other conductive circuit layer specifically comprises: fabricating a surface treatment layer on the conductive circuit layer on which the flip-chip is mounted, and then balling on the conductive circuit layer on which the surface treatment layer is fabricated.

7. A three-dimensional packaging structure, characterized in that, The three-dimensional packaging structure is prepared by the fabrication method according to any one of claims 1 to 6, and the three-dimensional packaging structure comprises: a substrate of organic resin material, the substrate has a through hole, and the through hole is plated with an interconnection metal column; the substrate is provided with a through slot, and the through slot is embedded with a preset chip and encapsulated; two sides of the substrate are respectively provided with conductive circuit layers, the conductive circuit layers are connected with the interconnection metal column, a flip-chip is mounted on one of the conductive circuit layers and encapsulated, and the other conductive circuit layer is balling.

8. The three-dimensional packaging structure of claim 7, wherein, a first conductive circuit layer is arranged on the pad side of the substrate embedded with the preset chip, and a second conductive circuit layer is arranged on the non-pad side of the substrate embedded with the preset chip; the first conductive circuit layer and the second conductive circuit layer are connected with the interconnection metal column; the flip-chip is mounted on the first conductive circuit layer and encapsulated, and the flip-chip is filled with a filler at the bottom; and the second conductive circuit layer is balling.

9. The three-dimensional packaging structure of claim 7, wherein, a first conductive circuit layer is arranged on the pad side of the substrate embedded with the preset chip, and a second conductive circuit layer is arranged on the non-pad side of the substrate embedded with the preset chip; the first conductive circuit layer and the second conductive circuit layer are connected with the interconnection metal column; the flip-chip is mounted on the second conductive circuit layer and encapsulated, and the flip-chip is filled with a filler at the bottom; and the first conductive circuit layer is balling.

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