An output version configurable circuit based on a dc-dc converter

Abstract

The application relates to an output version configurable circuit based on a DC-DC converter, and belongs to the field of DC-DC converter circuit design; the circuit comprises a voltage scaling circuit, a decoder logic circuit, a trimming circuit, an error amplifier and a feedback network; wherein the decoder logic circuit comprises a first-stage logic circuit, a second-stage logic circuit, a first NMOS tube matrix and a second NMOS tube matrix; in an initial state, each NMOS tube in the first NMOS tube matrix and the second NMOS tube matrix is in an off state; the circuit can adjust the feedback network voltage dividing resistor proportion through a trimming signal according to actual requirements, thereby changing the proportion of a feedback voltage Vsense and an output voltage VOUT, so that the adjustment of different output versions is realized; meanwhile, the voltage selection signal of the decoding logic is adjusted through the trimming signal, thereby changing a reference signal Vref, and the different output versions and the output voltage precision configurable are realized.

Description

Technical Field

[0001] This invention belongs to the field of DC-DC converter circuit design and relates to a configurable circuit for the output version of a DC-DC converter. Background Technology

[0002] The main function of a DC-DC converter is to achieve a stable voltage output, typically serving as the power supply for the entire system. The adjustable range of the DC-DC converter's output voltage directly determines its application range. Therefore, it is necessary to design configurable output circuits to make the DC-DC converter suitable for a wider range of applications.

[0003] Existing DC-DC converters typically have a fixed voltage output. This means that when downstream systems require different power supply voltages, fixed-voltage DC-DC converters cannot handle the situation, thus limiting their application range. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a configurable output version circuit based on a DC-DC converter, which can realize multiple configurable output versions according to the needs of the application environment, and the output voltage accuracy is configurable, thus broadening the application range of the DC-DC converter.

[0005] The solution of the present invention is:

[0006] A configurable output version circuit based on a DC-DC converter is characterized by comprising a voltage scaling circuit, a decoder logic circuit, a trimming circuit, an error amplifier, and a feedback network; wherein the decoder logic circuit comprises a first-stage logic circuit, a second-stage logic circuit, a first NMOS transistor matrix, and a second NMOS transistor matrix; initially, all NMOS transistors in the first and second NMOS transistor matrices are in the off state.

[0007] Voltage scaling circuit: used to obtain the voltage between the limit values. n ×2 m A scaling voltage V 11 ... V ij ... The scaled voltage is then output to the first NMOS transistor matrix; n is a positive integer not less than 0; m is a positive integer not less than 0, and m ≤ n; i is a positive integer, and i = 1, 2, ..., 2 n j is a positive integer, and j = 1, 2, ..., 2 m ;

[0008] Adjustment circuit: Receives externally input adjustment voltage and obtains n logic adjustment signals T. r1 -Trn and feedback adjustment signal T rs ; to modify n logic signals T r1 -T rn Send to the first-level logic circuit; and return the feedback adjustment signal T rs Send to the feedback network;

[0009] First-level logic circuit: Receives n logic adjustment signals T from the adjustment circuit. r1 T r2 ... T rn For logic adjustment signal T r1 T r2 ... T rn Decoding is performed to generate the first-stage selection signals b1, b2, ... Used to control the closing of the NMOS transistors that need to be closed in the first NMOS transistor matrix, and to set the first-stage selection signals b1, b2, ... Send to the first NMOS transistor matrix;

[0010] The first NMOS transistor matrix receives the first-stage selection signals b1, b2, ... from the first-stage logic circuit. Based on the first-level selection signals b1, b2, ... Close the NMOS transistor that needs to be closed; receive the voltage scaling circuit's 2 n ×2 m A scaling voltage V 11 ... V ij ... and 2 n ×2 m A scaling voltage V 11 ... V ij ... Send to the second NMOS transistor matrix;

[0011] Second-level logic circuit: Receives m externally input secondary tuning signals C1, C2, ..., C m For the secondary adjustment signals C1, C2, ..., C m Decode the signals to generate the second-stage selection signals d1, d2, ... Used to control the closing of the NMOS transistors that need to be closed in the second NMOS transistor matrix, and to set the second-stage selection signals d1, d2, ... Send to the second NMOS transistor matrix;

[0012] The second NMOS transistor matrix receives the second-stage selection signals d1, d2, ... from the second-stage logic circuit. Based on the second-level selection signals d1, d2, ... Select the NMOS transistors that need to be closed and close them; receive the 2 signals from the first NMOS transistor matrix. n ×2 m A scaling voltage V 11 ... V ij ... When all the NMOS transistors connected in series in the first and second NMOS transistor matrices are closed, forming a path, 2 n ×2 m A scaling voltage V 11 ... V ij ... Only one scaled voltage is output to the non-inverting input of the error amplifier via a path; this scaled voltage is defined as the reference signal V. ref ;

[0013] Feedback network: receives external input voltage V OUT And according to the input voltage V OUT The feedback voltage V is obtained sense ; Receive the feedback adjustment signal T from the adjustment circuit rs Based on the feedback adjustment signal T rs Changing the voltage divider resistors of the feedback network changes the feedback voltage V. sense With input voltage V OUT The ratio, and the feedback voltage V sense Send to the inverting input of the error amplifier;

[0014] Error amplifier: Receives the reference signal V from the second NMOS transistor matrix. ref ; Receive feedback voltage V from the feedback network sense By comparing the feedback voltage V sense With reference signal V ref Implement a negative feedback system in the circuit to change the output voltage.

[0015] In the aforementioned configurable circuit based on the output version of a DC-DC converter, the voltage scaling circuit includes an NMOS transistor M. b 2 n ×2 m A voltage divider resistor R 11 ... R ij ... and operational amplifier (OPA);

[0016] NMOS transistor M b The drain of the NMOS transistor is connected to the power supply VDD. b The gate is connected to the output of the operational amplifier OPA, 2 n ×2 m A voltage divider resistor R11 ... R ij ... After being connected in series, the voltage divider resistors R 11 With NMOS transistor M b Source connection; voltage divider resistor Grounded; the non-inverting input of the operational amplifier OPA is connected to the reference voltage V. bg The inverting input of the operational amplifier OPA is close to each voltage divider resistor and the NMOS transistor M. b One end is connected.

[0017] In the above-described configurable circuit based on the output version of a DC-DC converter, the 2 n ×2 m A voltage divider resistor R 11 ... R ij ... Same resistance value; 2 n ×2 m A scaling voltage V 11 ... V ij ... From 2 n ×2 m A voltage divider resistor R 11 ... R ij ... get.

[0018] In the aforementioned configurable circuit based on a DC-DC converter output version, the arbitrary voltage divider resistor R... ij Scaling voltage V ij The calculation method is as follows:

[0019]

[0020] In the aforementioned configurable circuit based on the output version of a DC-DC converter, the decoder logic circuit includes a first-stage logic circuit, a second-stage logic circuit, a first NMOS transistor matrix, a second NMOS transistor matrix, and a resistor R. f and capacitor C f The first NMOS transistor matrix includes 2 n ×2 m There are NMOS transistors, namely NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor The second NMOS transistor matrix includes 2 m There are NMOS transistors, namely NMOS transistor M1, NMOS transistor M2, ..., NMOS transistor M3.

[0021] In the first NMOS transistor matrix, NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor All are in parallel configuration; in the second NMOS transistor matrix, NMOS transistors M1, M2, ..., M3 are connected in parallel. All are in parallel; the first-stage logic circuit receives the trimming signal T. r1 T r2 ... T rn Output the first-stage selection signals b1, b2, ... NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor The drains are connected to the scaling voltage V one by one. 11 ...V ij ... NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor Arranged into 2 n Column 2 m A matrix of rows, where column 1-2 n The gates of the NMOS transistors in the column are connected one-to-one to the first-stage selection signals b1, b2, ..., Line 1-2 m The sources of the NMOS transistors in the row are connected one-to-one with NMOS transistors M1, M2, ..., M3 respectively. The drain of the second-stage logic circuit; the second-stage logic circuit receives the second-stage trimming signals C1, C2, ..., C n Output the second-stage selection signals d1, d2, ... NMOS transistors M1, M2, ..., NMOS transistors The gates are connected one-to-one with the second-stage selection signals d1, d2, ... NMOS transistors M1, M2, ..., NMOS transistors Source connection resistor R f Resistance R f and capacitor C f To form an RC filter circuit, the output reference signal V ref .

[0022] In one of the configurable output versions of the aforementioned DC-DC converter-based circuit, the feedback network includes a resistor R. o Resistance R s and NMOS transistor M s ;

[0023] resistor R o One end is connected to the output voltage VOUT, and the resistor R o The other end is connected to the NMOS transistor M s The drain terminals are connected to the feedback voltage V. sense NMOS transistor M s Source resistor R s One end, resistor R s The other end is grounded, NMOS transistor M s The gate terminal is connected to the feedback adjustment signal T rs .

[0024] In the aforementioned configurable circuit based on the output version of a DC-DC converter, the feedback adjustment signal T is used... rs Changing the voltage divider resistors of the feedback network changes the feedback voltage V. sense With input voltage V OUT The method of proportion is as follows:

[0025] When the feedback adjustment signal T rs Make NMOS transistor M s When disconnected, V sense =V OUT The feedback voltage V at the inverting input of the error amplifier sense Reference signal V at the in-phase input terminal ref They are equal, therefore we get V. OUT =V ref ;

[0026] When the feedback adjustment signal T rs Make NMOS transistor M s When closed, The feedback voltage V at the inverting input of the error amplifier sens Reference signal V at the in-phase input terminal ref They are equal, therefore we get

[0027] In the aforementioned configurable circuit based on the output version of a DC-DC converter, the error amplifier compares the feedback voltage V. sense and reference signal V ref Implement a negative feedback circuit system to achieve regulated output.

[0028] In the aforementioned configurable circuit based on the output version of a DC-DC converter, a feedback adjustment signal T is used. rs Adjusting the voltage divider resistor ratio of the feedback network changes the feedback voltage V. sense With input voltage V OUT The ratio is used to adjust the output voltage to different values; at the same time, the logic trimming signal T is used to adjust the output voltage. r1 T r2... T rn Adjusting the voltage selection signal of the decoder logic circuit changes the reference signal V. ref To achieve different V ref Output and output voltage accuracy configuration.

[0029] In the aforementioned configurable circuit based on the output version of a DC-DC converter, the first-stage logic circuit receives n logic adjustment signals T. r1 T r2 ... T rn Each logic trimming signal corresponds to two level states: high level and low level. Therefore, there are n logic trimming signals T. r1 T r2 ... T rn There are a total of 2 level state combinations n The first-level logic circuit will have 2 n The output level states generate the first-stage selection signals b1, b2, ...

[0030] The second-stage logic circuit receives m second-stage adjustment signals C1, C2, ..., C m Each secondary adjustment signal corresponds to two level states: high level and low level. Therefore, there are m secondary adjustment signals C1, C2, ..., C... m There are a total of 2 level state combinations m The second-level logic circuit will have 2 m The output level indicates the generation of the second-stage selection signals d1, d2, ...

[0031] The advantages of this invention compared to the prior art are:

[0032] (1) This invention includes a voltage scaling circuit with negative feedback. The non-inverting input of the operational amplifier OPA is a reference voltage Vbg. The reference voltage Vbg is a reference voltage signal generated by a bandgap reference circuit that is independent of temperature and power supply voltage. It is generated by the operational amplifier OPA, NMOS transistor Mb, and 2 n ×2 m A voltage divider resistor R 11 ... R ij ... The negative feedback system ensures that the scaling voltage Vii at the inverting input of the operational amplifier OPA is equal to the reference voltage Vbg at the non-inverting input. Therefore, the scaling voltage generated by the voltage divider resistor series is only related to the reference voltage Vbg and is not affected by temperature and power supply voltage.

[0033] (2) The first-stage logic selection circuit of this invention can adjust the NMOS transistor M according to the adjustment signal. 11... NMOS transistor M ij ... NMOS transistor The gate terminal signal is used to select different scaling voltages V11 to V2n2m according to the timing, and outputs the first-stage logic selection signal to the second-stage logic selection circuit to finally obtain the reference signal Vref. When the requirements of the DC-DC converter application environment for the output voltage change, the reference signal Vref can be changed by modifying the adjustment signal to achieve the goal of adjusting the output voltage.

[0034] (3) The decoder logic circuit of this invention adopts a two-stage logic selection structure, scaling voltage V 11 ... V ij ... NMOS M consisting of 2n columns and 2m rows 11 ... M ij ... Control is performed by the first-level logic circuit based on the adjustment signal T. r1 T r2 ... T rn Output the first-stage selection signals b1, b2, ... Used to select 1 to 2 n The proportional scaling voltage controlled by the NMOS transistor, the second-stage logic circuit based on signals C1, C2, ..., C m Output the second-stage selection signals d1, d2, ... Used to select 1 to 2 m The proportionally scaled voltage controlled by the NMOS transistor, after two stages of logic selection, outputs the design's reference signal Vref. Compared to the existing single-stage logic selection structure, the two-stage logic selection structure can use 2n+2m signals to select the 2... n ×2 m The voltage scaling factor can be selected to achieve more precise adjustment of the reference signal Vref, thereby further improving the accuracy of the DC-DC converter output voltage.

[0035] (4) In this invention, the decoder logic circuit is always in the switching state during operation, and its output noise is relatively large. This invention adds an anti-noise design to the output of the decoder logic circuit to prevent the reference signal Vref from being disturbed by noise and causing excessive fluctuations.

[0036] (5) The feedback network of this invention adopts an adjustable design. The ratio of the feedback voltage Vsense to the output voltage VOUT is adjusted according to the adjustment signal Trs, and the feedback voltage Vsense is output to the inverting input terminal of the error amplifier EA. The error amplifier realizes the circuit negative feedback system by comparing the feedback voltage Vsense with the reference signal Vref, and finally achieves the goal of changing the output voltage to meet the requirements of different application environments for the output voltage. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the overall configurable circuit for the output version of this invention;

[0038] Figure 2 This is a schematic diagram of the voltage scaling circuit of the present invention;

[0039] Figure 3 This is a schematic diagram of the decoder logic circuit of the present invention;

[0040] Figure 4 This is a schematic diagram of the feedback network of the present invention. Detailed Implementation

[0041] The present invention will be further described below with reference to the embodiments.

[0042] This invention provides a configurable output version circuit based on a DC-DC converter, which can configure the output version according to the needs of the application environment, and can also finely adjust the output voltage to further improve the accuracy of the output voltage and effectively broaden the application range of the DC-DC converter.

[0043] Output version configurable circuitry, such as Figure 1 As shown, it specifically includes a voltage scaling circuit, a decoder logic circuit, a trimming circuit, an error amplifier, and a feedback network; wherein, the decoder logic circuit includes a first-stage logic circuit, a second-stage logic circuit, a first NMOS transistor matrix, a second NMOS transistor matrix, and a resistor R. f and capacitor C f , specifically Figure 3 As shown, the first NMOS transistor matrix includes 2 n ×2 m There are NMOS transistors, namely NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor The second NMOS transistor matrix includes 2 m There are NMOS transistors, namely NMOS transistor M1, NMOS transistor M2, ..., NMOS transistor M3. In the initial state, all NMOS transistors in the first NMOS transistor matrix and the second NMOS transistor matrix are in the off state.

[0044] In the first NMOS transistor matrix, NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor All are in parallel configuration; in the second NMOS transistor matrix, NMOS transistors M1, M2, ..., M3 are connected in parallel. All are in parallel; the first-stage logic circuit receives the trimming signal T. r1 T r2 ... T rn Output the first-stage selection signals b1, b2, ... NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor The drains are connected to the scaling voltage V one by one. 11 ...V ij ... NMOS transistor M 11 ... NMOS transistor M ij ... NMOS transistor Arranged into 2 n Column 2 m A matrix of rows, where column 1-2 n The gates of the NMOS transistors in the column are connected one-to-one to the first-stage selection signals b1, b2, ..., Line 1-2 m The sources of the NMOS transistors in the row are connected one-to-one with NMOS transistors M1, M2, ..., M3 respectively. The drain of the second-stage logic circuit; the second-stage logic circuit receives the second-stage trimming signals C1, C2, ..., C n Output the second-stage selection signals d1, d2, ... NMOS transistors M1, M2, ..., NMOS transistors The gates are connected one-to-one with the second-stage selection signals d1, d2, ... NMOS transistors M1, M2, ..., NMOS transistors Source connection resistor R f Resistance R f and capacitor C f To form an RC filter circuit, the output reference signal V ref .

[0045] Voltage scaling circuit: including NMOS transistor M b 2 n ×2 m A voltage divider resistor R 11... R ij ... Operational amplifier (OPA); NMOS transistor (M) b The drain of the NMOS transistor is connected to the power supply VDD. b The gate is connected to the output terminal of the operational amplifier OPA, 2 n ×2 m A voltage divider resistor R 11 ... R ij ... After being connected in series, the voltage divider resistors R 11 With NMOS transistor M b Source connection; voltage divider resistor Grounded; the non-inverting input of the operational amplifier OPA is connected to the reference voltage V. bg The inverting input of the operational amplifier OPA is close to each voltage divider resistor and the NMOS transistor M. b One end is connected, such as Figure 2 As shown

[0046] Among them, 2 n ×2 m A voltage divider resistor R 11 ... R ij ... Same resistance value; 2 n ×2 m A scaling voltage V 11 ... V ij ... From 2 n ×2 m A voltage divider resistor R 11 ... R ij ... get.

[0047] Arbitrary voltage divider resistor R ij Scaling voltage V ij The calculation method is as follows:

[0048]

[0049] Voltage scaling circuits are used to obtain the range between limit values ​​of 2 n ×2 m A scaling voltage V 11 ... V ij ... The scaled voltage is then output to the first NMOS transistor matrix; n is a positive integer not less than 0; m is a positive integer not less than 0, and m ≤ n; i is the first subscript number, j is the second subscript number; i is a positive integer, and i = 1, 2, ..., 2 n j is a positive integer, and j = 1, 2, ..., 2m .

[0050] Adjustment circuit: Receives externally input adjustment voltage and obtains n logic adjustment signals T. r1 -T rn and feedback adjustment signal T rs ; to modify n logic signals T r1 -T rn Send to the first-level logic circuit; and return the feedback adjustment signal T rs Send to the feedback network.

[0051] First-level logic circuit: Receives n logic adjustment signals T from the adjustment circuit. r1 T r2 ... T rn For logic adjustment signal T r1 T r2 ... T rn Decoding is performed to generate the first-stage selection signals b1, b2, ... Used to control the closing of the NMOS transistors that need to be closed in the first NMOS transistor matrix, and to set the first-stage selection signals b1, b2, ... Send to the first NMOS transistor matrix.

[0052] Specifically, the first-stage logic circuit receives n logic tuning signals T. r1 T r2 ... T rn Each logic trimming signal corresponds to two level states: high level and low level. Therefore, there are n logic trimming signals T. r1 T r2 ... T rn There are a total of 2 level state combinations n The first-level logic circuit will have 2 n The output level states generate the first-stage selection signals b1, b2, ...

[0053] The first NMOS transistor matrix receives the first-stage selection signals b1, b2, ... from the first-stage logic circuit. Based on the first-level selection signals b1, b2, ... Close the NMOS transistor that needs to be closed; receive the voltage scaling circuit's 2 n ×2 m A scaling voltage V 11 ... V ij ... and 2 n ×2 m A scaling voltage V 11 ... V ij... Send to the second NMOS transistor matrix.

[0054] Second-level logic circuit: Receives m externally input secondary tuning signals C1, C2, ..., C m For the secondary adjustment signals C1, C2, ..., C m Decode the signals to generate the second-stage selection signals d1, d2, ... Used to control the closing of the NMOS transistors that need to be closed in the second NMOS transistor matrix, and to set the second-stage selection signals d1, d2, ... Send to the second NMOS transistor matrix.

[0055] Specifically, the second-stage logic circuit receives m second-stage tuning signals C1, C2, ..., C... m Each secondary adjustment signal corresponds to two level states: high level and low level. Therefore, there are m secondary adjustment signals C1, C2, ..., C... m There are a total of 2 level state combinations m The second-level logic circuit will have 2 m The output level indicates the generation of the second-stage selection signals d1, d2, ...

[0056] The second NMOS transistor matrix receives the second-stage selection signals d1, d2, ... from the second-stage logic circuit. Based on the second-level selection signals d1, d2, ... Select the NMOS transistors that need to be closed and close them; receive the 2 signals from the first NMOS transistor matrix. n ×2 m A scaling voltage V 11 ... V ij ... When all the NMOS transistors connected in series in the first and second NMOS transistor matrices are closed, forming a path, 2 n ×2 m A scaling voltage V 11 ... V ij ... Only one scaled voltage is output to the non-inverting input of the error amplifier via a path; this scaled voltage is defined as the reference signal V. ref .

[0057] like Figure 4 As shown, the feedback network includes a resistor R o Resistance R s and NMOS transistor M s Resistance R o One end is connected to the output voltage VOUT, and the resistor R oThe other end is connected to the NMOS transistor M s The drain terminals are connected to the feedback voltage V. sense NMOS transistor M s Source resistor R s One end, resistor R s The other end is grounded, NMOS transistor M s The gate terminal is connected to the feedback adjustment signal T rs .

[0058] Feedback network: receives external input voltage V OUT And according to the input voltage V OUT The feedback voltage V is obtained sense ; Receive the feedback adjustment signal T from the adjustment circuit rs Based on the feedback adjustment signal T rs Changing the voltage divider resistors of the feedback network changes the feedback voltage V. sense With input voltage V OUT The ratio, and the feedback voltage V sense The signal is sent to the inverting input of the error amplifier. The adjustment signal T is then fed back. rs Adjusting the voltage divider resistor ratio of the feedback network changes the feedback voltage V. sense With input voltage V OUT The ratio is used to adjust the output voltage to different values; at the same time, the logic trimming signal T is used to adjust the output voltage. r1 T r2 ... T rn Adjusting the voltage selection signal of the decoder logic circuit changes the reference signal V. ref To achieve different V ref Output and output voltage accuracy configuration.

[0059] Error amplifier: Receives the reference signal V from the second NMOS transistor matrix. ref ; Receive feedback voltage V from the feedback network sense By comparing the feedback voltage V sense With reference signal V ref Implement a negative feedback system in the circuit to change the output voltage.

[0060] The error amplifier compares the feedback voltage V sense and reference signal V ref Implement a negative feedback circuit system to achieve regulated output.

[0061] This invention designs a voltage scaling circuit with negative feedback. The non-inverting input of the operational amplifier OPA is a reference voltage Vbg. The reference voltage Vbg is a reference voltage signal generated by a bandgap reference circuit that is independent of temperature and power supply voltage. This signal is generated by the operational amplifier OPA, NMOS transistor Mb, and 2... n ×2m A voltage divider resistor R 11 ... R ij ... The negative feedback system ensures that the scaling voltage Vii at the inverting input of the operational amplifier OPA is equal to the reference voltage Vbg at the non-inverting input. Therefore, the scaling voltage generated by the voltage divider resistor series is only related to the reference voltage Vbg and is not affected by temperature and power supply voltage.

[0062] Furthermore, the first-stage logic selection circuit can adjust the NMOS transistor M according to the adjustment signal. 11 ... NMOS transistor M ij ... NMOS transistor The gate terminal signal is used to select different scaling voltages V11 to V2n2m according to the timing, and outputs the first-stage logic selection signal to the second-stage logic selection circuit to finally obtain the reference signal Vref. When the requirements of the DC-DC converter application environment for the output voltage change, the reference signal Vref can be changed by modifying the adjustment signal to achieve the goal of adjusting the output voltage.

[0063] The decoder logic circuit in this invention adopts a two-stage logic selection structure, scaling voltage V 11 ... V ij ... NMOS M consisting of 2n columns and 2m rows 11 ... M ij ... Control is performed by the first-level logic circuit based on the adjustment signal T. r1 T r2 ... T rn Output the first-stage selection signals b1, b2, ... Used to select 1 to 2 n The proportional scaling voltage controlled by the NMOS transistor, the second-stage logic circuit based on signals C1, C2, ..., C m Output the second-stage selection signals d1, d2, ... Used to select 1 to 2 m The proportionally scaled voltage controlled by the NMOS transistor, after two stages of logic selection, outputs the design's reference signal Vref. Compared to the existing single-stage logic selection structure, the two-stage logic selection structure can use 2n+2m signals to select the 2... n ×2 m The voltage scaling factor can be selected to achieve more precise adjustment of the reference signal Vref, thereby further improving the accuracy of the DC-DC converter's output voltage.

[0064] In the initial state, the decoder logic circuit is always in the switching state during operation, and its output noise is relatively large. This invention adds an anti-noise design to the output of the decoder logic circuit to prevent the reference signal Vref from being disturbed by noise and causing excessive fluctuations.

[0065] The feedback network of this invention adopts an adjustable design. The ratio of the feedback voltage Vsense to the output voltage VOUT is adjusted according to the adjustment signal Trs, and the feedback voltage Vsense is output to the inverting input of the error amplifier EA. The error amplifier realizes the circuit negative feedback system by comparing the feedback voltage Vsense with the reference signal Vref, and finally achieves the goal of changing the output voltage to meet the output voltage requirements of different application environments.

[0066] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A configurable output version circuit based on a DC-DC converter, characterized in that: It includes a voltage scaling circuit, a decoder logic circuit, a trimming circuit, an error amplifier, and a feedback network; wherein, the decoder logic circuit includes a first-stage logic circuit, a second-stage logic circuit, a first NMOS transistor matrix, and a second NMOS transistor matrix; in the initial state, all NMOS transistors in the first NMOS transistor matrix and the second NMOS transistor matrix are in the off state; Voltage scaling circuit: used to obtain the range between limit values Scaling voltage ... ... The scaled voltage is then output to the first NMOS transistor matrix; n is a positive integer not less than 0; m is a positive integer not less than 0, and m ≤ n; i is a positive integer, and i = 1, 2, ... j is a positive integer, and j = 1, 2, ... ; Trimming circuit: Receives externally input trimming voltage and obtains n logic trimming signals. - and feedback adjustment signal ; to modify n logic signals - Send to the first-level logic circuit; and return the feedback adjustment signal Send to the feedback network; First-level logic circuit: Receives n logic adjustment signals from the adjustment circuit. , ... , logic adjustment signal , ... Decode the signal to generate the first-stage selection signal. , ... This is used to control the closing of the NMOS transistors that need to be closed in the first NMOS transistor matrix, and to set the first-stage selection signal. , ... Send to the first NMOS transistor matrix; First NMOS transistor matrix: Receives the first-stage selection signal from the first-stage logic circuit. , ... According to the first-level selection signal , ... Close the NMOS transistor that needs to be closed; receive the voltage scaling circuit. Scaling voltage ... ... ; and will Scaling voltage ... ... Send to the second NMOS transistor matrix; Second-stage logic circuit: Receives m externally input secondary adjustment signals. , ... For the secondary adjustment signal , ... Decode the signal to generate a second-stage selection signal. , ... This is used to control the closing of the NMOS transistors that need to be closed in the second NMOS transistor matrix, and to set the second-stage selection signal. , ... Send to the second NMOS transistor matrix; Second NMOS transistor matrix: Receives the second-stage selection signal from the second-stage logic circuit. , ... According to the second-level selection signal , ... Select the NMOS transistors that need to be closed and close them; receive the signal from the first NMOS transistor matrix. Scaling voltage ... ... When all the NMOS transistors connected in series in the first and second NMOS transistor matrices are closed, a closed circuit is formed. Scaling voltage ... ... Only one scaled voltage is output to the non-inverting input of the error amplifier via a path; this scaled voltage is defined as the reference signal. ; Feedback network: receives external input voltage And based on the input voltage Obtain feedback voltage ; Receive feedback adjustment signals from the adjustment circuit Based on feedback adjustment signals Changing the voltage divider resistor in the feedback network changes the feedback voltage. With input voltage The ratio, and the feedback voltage Send to the inverting input of the error amplifier; Error amplifier: Receives the reference signal from the second NMOS transistor matrix. ; Receive feedback voltage from the feedback network By comparing feedback voltage With reference signal Implement a negative feedback circuit system to change the output voltage and achieve regulated output.

2. The configurable output version circuit based on a DC-DC converter according to claim 1, characterized in that: The voltage scaling circuit includes an NMOS transistor. , voltage divider resistors ... ... and operational amplifier (OPA); NMOS transistor The drain of the NMOS transistor is connected to the power supply VDD. The gate is connected to the output terminal of the operational amplifier OPA. voltage divider resistors ... ... After being connected in series, the voltage divider resistors With NMOS transistor The source connection; Voltage divider resistor Grounded; the non-inverting input of the operational amplifier (OPA) is connected to a reference voltage. The inverting input of the operational amplifier (OPA) is close to the voltage divider resistors and the NMOS transistor. One end is connected.

3. The configurable output version circuit based on a DC-DC converter according to claim 2, characterized in that: The voltage divider resistors ... ... Same resistance value; Scaling voltage ... ... Depend on voltage divider resistors ... ... get.

4. A configurable output version circuit based on a DC-DC converter according to claim 3, characterized in that: Arbitrary voltage divider resistor Scaling voltage The calculation method is as follows: 。 5. A configurable output version circuit based on a DC-DC converter according to claim 1, characterized in that: The decoder logic circuit includes a first-level logic circuit, a second-level logic circuit, a first NMOS transistor matrix, a second NMOS transistor matrix, and resistors. and capacitor The first NMOS transistor matrix includes... Each NMOS transistor is an NMOS transistor. ... NMOS transistor ... NMOS transistor The second NMOS transistor matrix includes Each NMOS transistor is an NMOS transistor. NMOS transistor ... NMOS transistor ; In the first NMOS transistor matrix, NMOS transistors ... NMOS transistor ... NMOS transistor All are in parallel configuration; in the second NMOS transistor matrix, the NMOS transistors NMOS transistor ... NMOS transistor All are in parallel configuration; the first-stage logic circuit receives the trimming signal. , ... Output the first-stage selection signal , ... NMOS transistor ... NMOS transistor ... NMOS transistor The drains are connected to the scaling voltages one by one. ... ... NMOS transistor ... NMOS transistor ... NMOS transistor Arranged into List, A matrix of rows, with 1 column - The gates of the NMOS transistors in the column are connected one-to-one to the first-stage selection signal output. , ... ; Line 1 - The sources of the NMOS transistors in each row are connected to the NMOS transistors respectively. NMOS transistor ... NMOS transistor The drain of the second-stage logic circuit; the second-stage logic circuit receives the second-stage adjustment signal. , ... Output the second-stage selection signal , ... NMOS transistor NMOS transistor ... NMOS transistor The gates are connected one-to-one to the second-stage selection signal. , ... NMOS transistor NMOS transistor ... NMOS transistor Source connection resistor ;resistance and capacitor To form an RC filter circuit, output a reference signal. .

6. A configurable output version circuit based on a DC-DC converter according to claim 1, characterized in that: The feedback network includes resistors. ,resistance and NMOS transistor ; resistance One end is connected to the output voltage VOUT, and the resistor The other end is connected to the NMOS transistor The drain terminals are connected to the feedback voltage. NMOS transistor Source resistor One end, resistor The other end is grounded, NMOS transistor The gate terminal is connected to the feedback adjustment signal. .

7. A configurable output version circuit based on a DC-DC converter according to claim 6, characterized in that: Based on feedback adjustment signals Changing the voltage divider resistor in the feedback network changes the feedback voltage. With input voltage The method of proportion is as follows: When feedback adjustment signal NMOS transistor When disconnected, Feedback voltage at the inverting input of the error amplifier Reference signal at in-phase input They are equal, therefore we get ; When feedback adjustment signal NMOS transistor When closed, Feedback voltage at the inverting input of the error amplifier Reference signal at in-phase input They are equal, therefore we get .

8. A configurable circuit based on the output version of a DC-DC converter according to claim 1, characterized in that: Through feedback adjustment signals Adjusting the voltage divider resistor ratio of the feedback network changes the feedback voltage. With input voltage The ratio is used to adjust the output voltage to different values; at the same time, the logic trimming signal is used to adjust the voltage. , ... Adjusting the voltage selection signal of the decoder logic circuit changes the reference signal. To achieve different Output and output voltage accuracy configuration.

9. A configurable output version circuit based on a DC-DC converter according to claim 1, characterized in that: The first-stage logic circuit receives n logic adjustment signals. , ... Each logic trimming signal corresponds to two level states: high level and low level. Therefore, there are n logic trimming signals. , ... The combination of level states The first-level logic circuit will The output level indicates the generation of the first-level selection signal. , ... ; The second-stage logic circuit receives m second-stage adjustment signals. , ... Each secondary adjustment signal corresponds to two level states: high level and low level. Therefore, there are m secondary adjustment signals. , ... The combination of level states The second-level logic circuit will This outputs a level state, which generates the second-level selection signal. , ... .

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