Dual-winding embedded solenoid inductor constructed by a layered process

Abstract

A method for constructing a solenoid inductor includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and performing the positioning of the inner winding and the outer winding using a layering process. The layering process includes machining a first electrically conductive layer to be a bottom layer of the outer winding, machining a first dielectric layer thereon, machining a second electrically conductive layer thereon to be a bottom layer of the inner winding, machining a second dielectric layer thereon, machining a magnetic core layer thereon, machining a third dielectric layer thereon, machining a third electrically conductive layer thereon to be a top layer of the inner winding, machining a fourth dielectric layer thereon, machining a fourth electrically conductive layer thereon to be a top layer of the outer winding, machining a fifth dielectric layer thereon, and the inner winding is electrically connected with the outer winding.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority based on U.S. Provisional Application Serial No. 62 / 989,076, filed on March 13, 2020, entitled LAYERED PROCESS-CONSTRUCTED DOUBLE-WINDING EMBEDDED SOLENOID INDUCTOR, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Inductors are essential components in many electronic applications. Historically, inductors have been used in applications such as radio frequency and mechanical applications. More recently, inductors have been used in applications such as mobile phones, laptops, and medical devices. Embedded inductors are ideal for many of these applications. Inductors come in various shapes and sizes, such as planar inductors, toroidal inductors, and spiral inductors. One type of inductor with increasing demand is the embedded solenoid inductor with a magnetic core. Due to space requirements in many applications, there is a need for embedded solenoid inductors with an increased inductance-to-size ratio. Summary of the Invention

[0004] An embodiment of a method for constructing an embedded solenoid inductor using a layered process is described, which positions an inner winding around a magnetic core and an outer winding around the inner winding. The layered process includes fabricating a bottom conductive layer of the outer winding, fabricating a first dielectric layer thereon, fabricating a bottom conductive layer of the inner winding thereon, fabricating a second dielectric layer thereon, fabricating a magnetic core layer thereon, fabricating a third dielectric layer thereon, fabricating a top conductive layer of the inner winding thereon, fabricating a fourth dielectric layer thereon, fabricating a top conductive layer of the outer winding thereon, and fabricating a fifth dielectric layer thereon, wherein the inner and outer windings are electrically connected. The process may further include fabricating vertical conductors through the first, second, third, and fourth dielectric layers to electrically connect the bottom and top layers of the outer winding, and fabricating vertical conductors through the second and third dielectric layers to electrically connect the bottom and top layers of the inner winding. For each conductive layer, the process may further include: separating the conductive layer into multiple conductors; electrically connecting corresponding conductors among the multiple conductors of the bottom and top layers of the outer winding using some vertical conductors to form corresponding turns of the outer winding; and electrically connecting corresponding conductors among the multiple conductors of the bottom and top layers of the inner winding using some vertical conductors to form corresponding turns of the inner winding. The inner and outer windings may be connected to generate a non-reverse magnetic field in the core, or they may be connected to generate a reverse magnetic field in the core. In the case of a reverse magnetic field, the inner and outer windings may have different numbers of turns to provide substantially matched inductance values. The layering process can be used to position an even number of additional windings around the inner and outer windings, such that each successive additional winding is substantially positioned around the previous additional winding. The layering process can be used to construct the solenoid inductor as a component of an integrated circuit device, a discrete device, an integrated circuit package having one or more active or passive devices, or as a component of a multilayer laminated printed circuit board (PCB).

[0005] In one embodiment, this disclosure provides a method for constructing a solenoid inductor, the method comprising positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and performing the positioning of the inner and outer windings using a layering process. The method may further comprise processing a first conductive layer as the bottom layer of the outer winding, processing a first dielectric layer over the first conductive layer, processing a second conductive layer over the first dielectric layer as the bottom layer of the inner winding, and processing a second dielectric layer over the second conductive layer, processing a magnetic core layer over the second dielectric layer, processing a third dielectric layer over the magnetic core layer, processing a third conductive layer over the third dielectric layer as the top layer of the inner winding, processing a fourth dielectric layer over the third conductive layer, processing a fourth conductive layer over the fourth dielectric layer as the top layer of the outer winding, processing a fifth dielectric layer over the fourth conductive layer, and the inner and outer windings are electrically connected. The method may further comprise the inner and outer windings being electrically connected in series and in a manner that generates a non-reverse magnetic field in the magnetic core. The method may further include electrically connecting the inner and outer windings in a manner that generates a reverse magnetic field in the core. The method may also include constructing the solenoid inductor as an integrated circuit device. The method may further include constructing the solenoid inductor as a discrete device. The method may further include constructing the solenoid inductor as a component of an integrated circuit package having one or more active or passive devices. The method may further include constructing the solenoid inductor as a component of a multilayer laminated printed circuit board.

[0006] In other embodiments, this disclosure provides a solenoid inductor constructed according to the method described above. Attached Figure Description

[0007] Figure 1 This is a flowchart illustrating an example method for constructing an embedded dual-winding solenoid inductor using a layered process according to an embodiment of this disclosure.

[0008] Figure 2 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated 3D illustration of an example embedded dual-winding solenoid inductor constructed using a layered process.

[0009] Figure 3 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated longitudinal two-dimensional cross-sectional view of an example of an embedded dual-winding solenoid inductor constructed using a layered process.

[0010] Figure 4 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated top view of an example of an embedded dual-winding solenoid inductor constructed using a layered process.

[0011] Figure 5 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated longitudinal two-dimensional cross-sectional view of an example of an embedded dual-winding solenoid inductor constructed using a layered process.

[0012] Figure 6 This is a flowchart illustrating an example method for constructing an embedded dual-winding solenoid inductor using a layered process according to an embodiment of this disclosure.

[0013] Figure 7 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated two-dimensional top view of an example of an embedded dual-winding solenoid inductor 70 constructed using a layered process. Detailed Implementation

[0014] This document describes embodiments of a method for constructing an embedded dual-winding solenoid inductor, comprising positioning an outer winding around an inner winding positioned around a magnetic core. The layering process may also include a positioning redistribution layer (RDL) to connect the solenoid inductor terminals to input / output pads of an integrated circuit (e.g., as shown in the image). Figure 5 (As shown).

[0015] Figure 1 This is a flowchart illustrating an example method for constructing an embedded dual-winding solenoid inductor using a layering process according to embodiments of the present disclosure. In one embodiment, the layering process may be a planar process that includes one or more steps such as photolithography, chemical vapor deposition, and etching to fabricate various conductive and dielectric layers as well as vertical conductors. In another embodiment, the layering process may be a process for constructing the solenoid inductor as a component of a multilayer laminated printed circuit board (PCB), which includes one or more steps such as copper patterning, chemical etching, lamination, drilling, printing, laser ablation, electroplating, and coating. The method begins at box 101.

[0016] At frame 101, a first conductive layer is fabricated as the bottom layer of the outer winding of a solenoid inductor. In one embodiment, the first conductive layer may be fabricated on top of a passivated semiconductor (e.g., silicon) substrate. In another embodiment, the bottom layer may be fabricated on top of an insulating layer of a PCB. Fabricating the first conductive layer includes separating the first conductive layer into a plurality of conductors that extend parallel to each other and are separated by a dielectric material.

[0017] At frame 103, the first dielectric layer is processed over the first conductive layer.

[0018] At frame 105, the second conductive layer is processed as the bottom layer of the inner winding of the solenoid inductor. The processing of the second conductive layer includes separating the second conductor layer into a plurality of conductors that extend parallel to each other and are separated by a dielectric material.

[0019] At frame 107, the second dielectric layer is processed over the second conductive layer.

[0020] At frame 109, the core layer is processed over the second dielectric layer. Preferably, the core material is a magnetic material, such as, for example, CoZrTa, but other materials as known to those skilled in the art can certainly be used.

[0021] At frame 111, the third dielectric layer is fabricated above the magnetic core layer.

[0022] At frame 113, the third conductive layer is fabricated as the top layer of the inner winding of the solenoid inductor. The fabrication of the third conductive layer includes separating the third conductor layer into a plurality of conductors that extend parallel to each other and are separated by a dielectric material.

[0023] At frame 115, the fourth dielectric layer is fabricated over the third conductive layer.

[0024] At frame 117, the fourth conductive layer is fabricated as the top layer of the outer winding of the solenoid inductor. Fabrication of the fourth conductive layer includes separating the fourth conductor layer into multiple conductors that extend parallel to each other and are separated by a dielectric material.

[0025] At frame 119, the fifth dielectric layer is fabricated over the fourth conductive layer.

[0026] At frame 121, a vertical conductor is machined through the first, second, third, and fourth dielectric layers to electrically connect the corresponding conductors of the bottom and top layers of the outer winding machined at frames 101 and 117, i.e., to create the corresponding number of turns of the outer winding. Additionally, a vertical conductor is machined through the second and third dielectric layers to electrically connect the corresponding conductors of the bottom and top layers of the inner winding machined at frames 105 and 113, i.e., to create the corresponding number of turns of the inner winding. In one embodiment, the vertical conductor is machined simultaneously with the machining of each associated dielectric layer; for example, the lowest portion of the outer winding vertical conductor may be machined in a hole etched from the first dielectric layer, the next higher portion of the outer winding vertical conductor may be machined in a hole etched from the second dielectric layer, the next higher portion of the outer winding vertical conductor may be machined in a hole etched from the third dielectric layer, and the highest portion of the outer winding vertical conductor may be machined in a hole etched from the fourth dielectric layer. Similarly, the lowest portion of the inner winding vertical conductor can be processed through holes etched from the second dielectric layer, and the highest portion of the inner winding vertical conductor can be processed through holes etched from the third dielectric layer. In another embodiment, the vertical conductor is subsequently processed, for example, using drilling and electroplating processes. In one embodiment, holes are drilled in the dielectric material (e.g., using photolithography, mechanical drilling, laser oblation, chemical etching, etc.), and then the holes are filled with a conductive material to process the vertical conductor. The vertical conductor can be processed using electroplating, printing, or lamination. In one embodiment, the pillar can be electroplated and then coated or laminated with a dielectric material, which can then be removed to expose the vertical conductor, and then the next conductive layer can be formed.

[0027] At box 123, the inner and outer windings are electrically connected. In one embodiment, the inner and outer windings are electrically connected in such a way that they generate a non-reverse magnetic field in the core when current flows through the windings. In another embodiment, the inner and outer windings are electrically connected in such a way that they generate a reverse magnetic field in the core when current flows through the windings. In one embodiment, the number of turns in the inner and outer windings may be different and are calculated to provide matching inductance values ​​for the inner and outer windings.

[0028] While the described steps are generally performed sequentially, some steps may be performed in a different order. For example, as described above, the steps at frame 121, which processes the vertical conductor, may be performed sequentially or substantially in conjunction with steps at other frames. Figure 1 The embedded dual-winding solenoid inductor constructed using this method can be used for applications including, but not limited to, power converters, filters, and resonators in audio, RF, and signal processing.

[0029] Figure 2 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated 3D illustration of an example of an embedded dual-winding solenoid inductor 20 constructed using a layered process. The solenoid inductor 20 includes a conductor in the bottom conductive layer of an outer winding 21, for example, according to... Figure 1 The frame 101 is processed. The solenoid inductor 20 includes a bottom conductive layer above the outer winding 21, for example, as per [reference needed]. Figure 1 The first dielectric layer 22 is processed on the frame 103; above the first dielectric layer 22, for example, as according to Figure 1 The conductor of the bottom conductive layer of the inner winding 23 is processed in frame 105; above the bottom conductive layer of the inner winding 23, for example, as according to Figure 1 The second dielectric layer 24 is processed in the frame 107; above the second dielectric layer 24, for example, as according to Figure 1 The core layer 25 is processed in the frame 109; above the core layer 25, for example, as according to Figure 1 The third dielectric layer 26 is processed in the frame 111; above the third dielectric layer 26, for example, as according to Figure 1 The conductor of the top conductive layer of the inner winding 27 is processed in the frame 113; above the top conductive layer of the inner winding 27, for example, as according to Figure 1 The fourth dielectric layer 28 is processed in the frame 115; above the fourth dielectric layer 28, for example, as per [reference to a specific configuration]... Figure 1 The conductor of the top conductive layer of the outer winding 29 is processed in frame 117; above the top conductive layer of the outer winding 29, for example, as according to Figure 1 The fifth dielectric layer 30 is processed in frame 119; and the vertical conductor of the outer winding 31 is electrically connected to the corresponding conductors of the bottom and top layers of the outer winding, and the vertical conductor of the inner winding 32 is electrically connected to the corresponding conductors of the bottom and top layers of the inner winding, for example, as according to Figure 1 The frame 121 in the middle is processed. Figure 2 The electrical connection between the inner and outer windings is not shown, for example, as per [reference needed]. Figure 1 The frame 123 is processed.

[0030] Figure 3 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated longitudinal two-dimensional cross-sectional view of an example of an embedded dual-winding solenoid inductor 39 constructed using a layered process. As shown, the solenoid inductor 39 includes... Figure 2The corresponding portions of the solenoid inductor 20, namely, the conductor of the bottom conductive layer of the outer winding 21, the first dielectric layer 22, the conductor of the bottom conductive layer of the inner winding 23, the second dielectric layer 24, the magnetic core layer 25, the third dielectric layer 26, the conductor of the top conductive layer of the inner winding 27, the fourth dielectric layer 28, the conductor of the top conductive layer of the outer winding 29, the fifth dielectric layer 30, and the vertical conductors of the outer winding 31 and the inner winding 32, for example, as according to Figure 1 The frames 101 to 121 are processed.

[0031] Figure 4 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated top view of an example of an embedded dual-winding solenoid inductor 40 constructed using a layered process. As shown, the solenoid inductor 40 includes a core layer 25, conductors from bottom and top conductive layers, and vertical conductors from the inner winding (e.g., ...). Figure 2 The inner winding 41 consists of turns of elements 23, 27, and 32, and conductors of the bottom and top conductive layers, as well as vertical conductors of the outer winding (e.g., Figure 2 The turns of the outer winding 42, which consists of elements 21, 29, and 31, for example, as according to Figure 1 The frames 101 to 121 are processed.

[0032] Figure 5 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated longitudinal two-dimensional cross-sectional view of an example of an embedded dual-winding solenoid inductor 50 constructed using a layered process. Figure 5 The solenoid inductor 50 in the middle is related to many aspects Figure 3 It is similar to the solenoid inductor 39 in the figure, and the corresponding component is not numbered. Figure 5 The diagram also shows solder bumps 53 for connecting to a chip or integrated circuit package for use with a system (e.g., a PCB). The chip or integrated circuit package in which the embedded dual-winding solenoid inductor 50 is a component may include one or more active or passive devices that can be connected to the embedded dual-winding solenoid inductor 50. Alternatively, the embedded dual-winding solenoid inductor 50 may be constructed as a discrete device. Figure 5The solenoid inductor 50 also includes an additional dielectric layer 51 located above the top conductive layer of the outer winding, which separates it from the redistribution layer (RDL) 52 of conductive material. A first portion of the RDL 52 is connected to one end of the outer winding, and a second portion of the RDL 52 is connected to the other end of the outer winding. The first portion of the RDL 52 is also connected to a first input / output pin, which is connected to a first solder bump serving as a first terminal 54 of the solenoid inductor 50, and the second portion of the RDL 52 is also connected to a second input / output pin, which is connected to a second solder bump serving as a second terminal 54 of the solenoid inductor 50.

[0033] Figure 6 This is a flowchart illustrating an example method for constructing an embedded dual-winding solenoid inductor using a layered process according to embodiments of the present disclosure. Figure 6 In this embodiment, the layering process is a planar process that includes fabricating various conductive and dielectric layers, as well as vertical conductors, using physical vapor deposition (PVD), photolithography, electroplating, etching, coating, curing, chemical vapor deposition (CVD), and other process steps. The method includes odd-numbered steps 601 through 627. Typically, steps 601 and 603, and 617 and 619, are designed to locate substantially corresponding to… Figure 1 The outer windings of frames 101, 103, 115, 117 and 121 (e.g., Figures 2 to 5 (of). Typically, steps 605 and 607, as well as 611 to 615, aim to locate essentially corresponding to Figure 1 The inner windings of frames 105, 107, 111, 113, and 121 (e.g., Figures 2 to 5 (of). Typically, step 609 aims to locate what substantially corresponds to Figure 1 The magnetic core of frame 109 (e.g., Figures 2 to 5 (Of). Typically, steps 621 to 627 target the positioning of RDL, I / O pins, and solder bumps (e.g., Figure 6 of).

[0034] Figure 7 This is an example of the use of embodiments according to this disclosure. Figure 1 A simulated two-dimensional top view of an example of an embedded dual-winding solenoid inductor 70 constructed using a layered process. Figure 7 It also includes a simulated two-dimensional top view of an example of a conventional two-winding solenoid inductor 71 with similar inductance, for the purpose of comparison with an embodiment of a two-winding solenoid inductor 70.

[0035] The inductance L of the solenoid inductor can be approximated by equation (1):

[0036]

[0037] Where μ0 is the permeability (or magnetic constant) of free space, μ r SF is the relative permeability of the magnetic core, N is the shape factor of the magnetic core, and W is the total number of turns in all windings. m It is the width of the magnetic core, t m Let P be the thickness of the magnetic core and N be the spacing of the windings, such that the product of P and N approximates the length of each winding. Therefore, it can be observed that for a given magnetic core, the inductance will be largely determined by the spacing P and the number of turns N of the solenoid inductor.

[0038] exist Figure 7 In the example, it is assumed that the embedded dual-winding solenoid inductor 70 and the conventional single-winding solenoid inductor 71 have the same magnetic core, the same turn pitch P, and the same number of turns (e.g., 28 turns), making their inductances approximately equal, although the inductance of the embedded dual-winding solenoid inductor 70 may be slightly different because the distance between the outer winding and the magnetic core is slightly larger than the distance between the inner winding and the magnetic core.

[0039] exist Figure 7 In the example, the 14-turn inner winding of the embedded dual-winding solenoid inductor 70 has an area dimension of X mm * Y mm, as shown in the figure. A comparable 14-turn portion of the conventional single-winding solenoid inductor 71 has similar dimensions, as shown in the figure. The extension of the single winding adds another 14 turns (as shown by the dashed rectangles), for a total of 28 turns, increasing the area dimension to X mm * 1.86Y mm, as shown in the figure, for a total area of ​​1.86XY square millimeters. Conversely, adding another 14 turns of outer winding to the embedded dual-winding solenoid inductor 70 (as shown by the two dashed rectangles) increases the area dimension to 1.18X mm * Y mm, as shown in the figure, for a total area of ​​1.18XY square millimeters, representing a reduction of approximately 37% in area compared to the conventional solution of extending the single winding along the Y dimension.

[0040] Therefore, the advantage of the embedded dual-winding solenoid inductor embodiment described herein is a significant reduction in the area of ​​the comparable inductor. Alternatively, the advantage of the embedded dual-winding solenoid inductor embodiment described herein can be a significant increase in the inductance-to-area ratio. Furthermore, compared to a conventional single-winding solenoid inductor of similar size, the embedded dual-winding solenoid inductor embodiment has the advantage of enjoying an increase in inductance per unit device area due to the increase in the number of turns N. The increase in inductance is only approximately proportional to the increase in the number of turns in the outer winding, because the distance between the outer winding and the core is slightly greater than the distance between the inner winding and the core. The embedded dual-winding solenoid inductor embodiment can be particularly advantageous in cases where given chip size constraints limit the maximum achievable inductance of a conventional single-winding solenoid inductor to an unacceptable value, but the embedded dual-winding solenoid inductor can achieve the desired inductance.

[0041] Another advantage of the embedded dual-winding solenoid inductor embodiment described herein is that it eliminates the need for additional core material, which leads to a reduction in cost per unit inductance per unit area. For example, regarding Figure 7 It can be observed that a conventional single-winding solenoid inductor 71 requires approximately twice the amount of core material as the embedded dual-winding solenoid inductor 70 to achieve comparable inductance. Another advantage of the embedded dual-winding solenoid inductor embodiments described herein is that they allow for lower Y / X or length / width aspect ratios in the core. For example, regarding... Figure 7 It can be observed that the length / width ratio of the conventional single-winding inductor 71 is approximately twice that of the embedded dual-winding solenoid inductor 70. Reducing the aspect ratio can lead to improvements in the magnetism of the core material, such as linearity of permeability relative to current.

[0042] In one embodiment, a dual anti-wound inductor using a single winding layer having alternating layers similar to those described in U.S. Patent Application Serial No. 16 / 709036, filed December 10, 2019, entitled “Current Control for a Boost Converter with a Dual Anti-Wound Inductor” by inventors Jason W. Lawrence, John L. Melanson, and Eric J. King, can be constructed using a method similar to the embodiments described herein.

[0043] Although embodiments in which the solenoid inductor has two windings—a single inner winding and a single outer winding—have been described, other embodiments in which the number of windings is greater than two are conceivable, i.e., including an additional outer winding. For example, modifications could be made... Figure 1 The method involves constructing a multi-winding solenoid inductor using a layered process, positioning an inner winding around a magnetic core, a second winding around the inner winding, a third winding around the second winding, and a fourth winding around the third winding. The layered process for positioning the third and fourth windings may include additional frames similar to frames 101-107 and 111-117, with additional processing at frame 121 to create vertical conductors to electrically connect corresponding conductors of the bottom and top layers of the third winding and to electrically connect corresponding conductors of the bottom and top layers of the fourth winding. Furthermore, the method can be extended to even more windings around four windings. In embodiments where windings are connected to create a reverse magnetic field in the magnetic material, the total number of windings should be even.

[0044] It should be understood—especially by those skilled in the art who benefit from this disclosure—that the various operations described herein, particularly those described in conjunction with the accompanying drawings, can be implemented by other circuit systems or other hardware components. Unless otherwise indicated, the order in which each operation of a given method is performed can be changed, and various elements of the system shown herein can be added, reordered, combined, omitted, modified, etc. This disclosure is intended to include all such modifications and changes; therefore, the above description should be considered illustrative rather than restrictive.

[0045] Similarly, although this disclosure relates to specific embodiments, certain modifications and changes may be made to these embodiments without departing from the scope and coverage of this disclosure. Furthermore, any benefits, advantages, or solutions to problems described herein with reference to specific embodiments are not intended to be construed as critical, essential, or fundamental features or elements.

[0046] Similarly, further embodiments benefiting from this disclosure will be apparent to those skilled in the art, and such embodiments should be considered to be included herein. All examples and conditional language described herein are intended for educational purposes to aid the reader in understanding the contents of this disclosure and the concepts contributed by the inventors to advance the art, and are to be construed as not being limited to these specifically enumerated examples and conditions.

[0047] This disclosure includes all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims include all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Furthermore, in the appended claims, references to a device or system or a component thereof, applicable to, arranged in, capable of, configured in, enabled in, operable in, or operated to perform a particular function, include the device, system, or component whether or not it or the particular function is activated, turned on, or unlocked, provided that the device, system, or component is so applicable, arranged, capable of, configured, enabled in, operable in, or operated.

[0048] Finally, the software can cause or configure the function, manufacture, and / or description of the apparatus and methods described herein. This can be implemented using a general-purpose programming language (e.g., C, C++), a hardware description language (HDL) including Verilog HDL, VHDL, etc., or other available programs. Such software can be placed on any known non-transitory computer-readable medium, such as magnetic tape, semiconductor, disk or optical disk (e.g., CD-ROM, DVD-ROM, etc.), network, wire, or other communication medium, having instructions stored thereon capable of causing or configuring the apparatus and methods described herein.

Claims

1. A method for constructing a solenoid inductor, comprising: The inner winding is positioned essentially around the magnetic core; The outer winding is positioned substantially around the inner winding; as well as The positioning of the inner and outer windings is performed using a layered process. The use of a layered process includes: Process the first conductive layer, which serves as the bottom layer of the outer winding; A first dielectric layer is fabricated above the first conductive layer; A second conductive layer is fabricated above the first dielectric layer, which serves as the bottom layer of the inner winding; A second dielectric layer is fabricated above the second conductive layer; A magnetic core layer is fabricated above the second dielectric layer; A third dielectric layer is fabricated above the magnetic core layer; A third conductive layer is fabricated above the third dielectric layer, which serves as the top layer of the inner winding; A fourth dielectric layer is fabricated above the third conductive layer; A fourth conductive layer is fabricated above the fourth dielectric layer, which serves as the top layer of the outer winding; A fifth dielectric layer is fabricated above the fourth conductive layer; and The inner winding and the outer winding are electrically connected.

2. The method according to claim 1, wherein, The use of the layered process also includes: Processing vertical conductors through the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer to electrically connect the bottom and top layers of the outer winding; and A vertical conductor is processed through the second and third dielectric layers to electrically connect the bottom and top layers of the inner winding.

3. The method according to claim 2, wherein, The use of the layered process also includes: For each of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer: The conductive layer is separated into multiple conductors; The process of processing vertical conductors through the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer to electrically connect the bottom and top layers of the outer winding includes: electrically connecting corresponding conductors among the plurality of conductors of the bottom and top layers of the outer winding to form corresponding turns of the outer winding; and The process of processing vertical conductors through the second dielectric layer and the third dielectric layer to electrically connect the bottom and top layers of the inner winding includes: electrically connecting corresponding conductors among the plurality of conductors of the bottom and top layers of the inner winding to form corresponding turns of the inner winding.

4. The method according to claim 1, wherein, The inner and outer windings are connected in series and electrically in a manner that generates a non-reverse magnetic field in the magnetic core.

5. The method according to claim 4, further comprising: The additional winding is positioned substantially around the inner winding and the outer winding using the layering process described above; Wherein, each successive additional winding of the additional winding is substantially positioned around the previous additional winding; and The inner winding, the outer winding, and the additional winding are connected in series and electrically in a manner that generates a non-reverse magnetic field in the magnetic core.

6. The method of claim 1, wherein the inner winding and the outer winding are electrically connected in such a way that they generate a reverse magnetic field in the magnetic core.

7. The method according to claim 6, wherein, The inner winding and the outer winding have different numbers of turns.

8. The method according to claim 7, wherein, The different numbers of turns provide corresponding inductance values ​​for a basic match between the inner and outer windings.

9. The method according to claim 6, further comprising: The layering process is used to position an even number of additional windings substantially around the inner winding and the outer winding; Wherein, each successive additional winding of the additional winding is substantially positioned around the previous additional winding; and The inner winding, the outer winding, and the additional winding are electrically connected in such a way that the outer half of all winding layers generates a magnetic field in the magnetic core that is opposite to the magnetic field generated by the inner half of all winding layers in the magnetic core.

10. The method according to claim 6, wherein, The inner winding and the outer winding have the same number of turns.

11. The method according to claim 1, wherein, The solenoid inductor is constructed as an integrated circuit device.

12. The method according to claim 1, wherein, The solenoid inductor is constructed as a discrete device.

13. The method according to claim 1, wherein, The solenoid inductor is constructed as a component in an integrated circuit package having one or more active or passive devices.

14. The method according to claim 1, wherein, The solenoid inductor is constructed as a component of a multilayer laminated printed circuit board.

15. A solenoid inductor constructed according to the method of claim 1.

16. A solenoid inductor constructed according to the method of claim 2.

17. A solenoid inductor constructed according to the method of claim 3.

18. A solenoid inductor constructed according to the method of claim 4.

19. A solenoid inductor constructed according to the method of claim 5.

20. A solenoid inductor constructed according to the method of claim 6.

21. A solenoid inductor constructed according to the method of claim 7.

22. A solenoid inductor constructed according to the method of claim 8.

23. A solenoid inductor constructed according to the method of claim 9.

24. A solenoid inductor constructed according to the method of claim 10.

25. A solenoid inductor constructed according to the method of claim 11.

26. A solenoid inductor constructed according to the method of claim 12.

27. A solenoid inductor constructed according to the method of claim 13.

28. A solenoid inductor constructed according to the method of claim 14.

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