Package comprising a substrate and a high-density interconnected integrated device coupled to the substrate

Abstract

The package includes a substrate, an integrated device, and an interconnected integrated device. The substrate includes a first surface and a second surface. The substrate also includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnected integrated device is coupled to a surface of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path at least running through the substrate, then through the interconnected integrated device, and back through the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Non-Provisional Application No. 17 / 017,361, filed in the U.S. Patent and Trademark Office on September 10, 2020, and Provisional Application No. 62 / 993,544, filed in the U.S. Patent and Trademark Office on March 23, 2020, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Various features relate to packages including integrated devices, but more particularly to packages including integrated devices and substrates. Background Art

[0004] Figure 1 FIG1 illustrates a package 100 including a substrate 102, an integrated device 104, an integrated device 106, and an encapsulation layer 108. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. The encapsulation layer 108 encapsulates the integrated device 104 and the integrated device 106. Manufacturing a small package including a substrate with a high density of interconnects can be challenging. There is a continuing need to provide more compact packages to accommodate high density interconnects and / or high pin counts. Summary of the Invention

[0005] Various features relate to packages including integrated devices, but more particularly to packages including integrated devices and substrates.

[0006] One example provides a package including a substrate, an integrated device, and an interconnected integrated device. The substrate includes a first surface and a second surface. The substrate also includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnected integrated device is coupled to a surface of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and back through the substrate.

[0007] Another example provides an apparatus comprising a substrate, an integrated device, and an apparatus for interconnecting the integrated device. The substrate comprises a first surface and a second surface. The substrate further comprises a plurality of interconnects. The integrated device is coupled to the substrate. The apparatus for interconnecting the integrated device is coupled to a surface of the substrate. The integrated device, the apparatus for interconnecting the integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the apparatus for interconnecting the integrated device, and back through the substrate.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate comprising a first surface and a second surface, wherein the substrate further comprises a plurality of interconnects. The method couples an integrated device to the substrate. The method couples the interconnected integrated device to a surface of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and back through the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, properties and advantages will become apparent from the following detailed description of the embodiments when taken in conjunction with the accompanying drawings, wherein like reference numerals are correspondingly identified throughout.

[0010] Figure 1 An outline view of a package including an integrated device and a substrate is shown.

[0011] Figure 2 An outline view of a package including a high density interconnected integrated device coupled to a substrate is illustrated.

[0012] Figure 3 A diagram showing possible electrical paths in a package including a high density interconnected integrated device coupled to a substrate is shown.

[0013] Figure 4 Illustrated is a view of possible electrical paths in a package including a high density interconnected integrated device coupled to a substrate.

[0014] Figure 5 Illustrated is a view of possible electrical paths in a package including a high density interconnected integrated device coupled to a substrate.

[0015] Figure 6 Illustrated is a view of possible electrical paths for a package-on-package (PoP) including high-density interconnected integrated devices coupled to a substrate.

[0016] Figure 7 An outline view of a package including a high density interconnected integrated device coupled to a substrate is illustrated.

[0017] Figures 8A-8D An exemplary sequence for fabricating a high-density interconnected integrated device is illustrated.

[0018] Figure 9 An exemplary flow chart of a method for fabricating a high-density interconnect integrated device is illustrated.

[0019] Figures 10A-10C An exemplary sequence for fabricating a substrate is illustrated.

[0020] Figure 11An exemplary flow chart of a method for manufacturing a substrate is illustrated.

[0021] Figures 12A-12B An exemplary sequence for fabricating a package including a high-density interconnected integrated device coupled to a substrate is illustrated.

[0022] Figure 13 An exemplary flow chart of a method for fabricating a package including a high-density interconnected integrated device coupled to a substrate is illustrated.

[0023] Figure 14 Illustrated are various electronic devices that may integrate dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0024] In the following description, specific details are provided to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the art will appreciate that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring various aspects with unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring various aspects of the present disclosure.

[0025] The present disclosure describes a package that includes a substrate, an electronic circuit (which may be formed in an integrated device), and an interconnected integrated device. The substrate includes a first surface and a second surface. The substrate also includes a plurality of interconnects for providing an electrical path to a board. The integrated device is coupled to the first surface (or second surface) of the substrate. The interconnected integrated device is coupled to the first surface (or second surface) of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and back through the substrate. The integrated device, the interconnected integrated device, and the substrate are coupled together such that the electrical path for the electrical signal of the integrated device is configured to extend (e.g., travel) through the substrate, then through the interconnected integrated device, and back through the substrate. The interconnected integrated device can provide at least one electrical path (e.g., an electrical connection) between two integrated devices coupled to the substrate. The interconnected integrated device can be a substrate including at least one dielectric layer and a plurality of interconnects. The interconnected integrated device can be a high-density interconnected integrated device configured to have interconnects with a minimum pitch smaller than the minimum pitch of the interconnects from the substrate. Interconnecting integrated devices can enable a package to have a small and compact form factor while also providing a high input / output (I / O) pin count. Interconnecting integrated devices can provide improved voltage drop, higher capacitance density, shorter paths between integrated devices, and / or lower inductance for the integrated devices.

[0026] Exemplary package including a high-density interconnect integrated device coupled to a substrate

[0027] Figure 2 The figure shows an outline diagram of a package 200 including high-density interconnected integrated devices. The package 200 is coupled to a board 290 (e.g., a printed circuit board (PCB)) via a plurality of solder interconnects 280. The package 200 provides a package with a compact form factor while also having a high input / output pin count. The package 200 provides improved capacitance density, shorter paths between integrated devices, lower inductance, and / or fewer routing constraints.

[0028] like Figure 2 As shown, package 200 includes substrate 202, first integrated device 204, second integrated device 206, encapsulation layer 208, interconnected integrated device 201, integrated device 205, and integrated device 207. Interconnected integrated device 201 can be configured as a bridge between two or more integrated devices. As will be further described below, the integrated devices (e.g., 204, 206), the interconnected integrated device (e.g., 201), and substrate 202 are coupled together so that when an electrical signal (e.g., a first electrical signal, a second electrical signal) travels between two integrated devices (e.g., 204, 206) and a board (e.g., 290), the electrical signal travels at least through substrate 202, then through the interconnected integrated device (e.g., 201), and back through substrate 202. This can be achieved by the interconnected integrated device (e.g., 201) providing at least one electrical path between a first electrical contact provided by the substrate 202 and a second electrical contact provided by the substrate 202, wherein the first contact is electrically connected to the integrated devices (e.g., 204, 206), and wherein the second contact is electrically connected to one or more interconnects. In the above example, the interconnected integrated device 201 can be configured as a bridge such that when at least one electrical signal travels between two integrated devices (e.g., 204, 206) and / or the board (e.g., 290), the at least one electrical signal can travel through the interconnected integrated device 201. The at least one electrical signal can travel through at least one electrical path defined by the interconnect of the package, the integrated device(s), the substrate, and / or the interconnected integrated device(s).

[0029] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The plurality of interconnects 222 can be configured to provide at least one electrical path to and / or from the board (e.g., 290). The plurality of interconnects 222 can provide at least one electrical path to at least one integrated device (e.g., 204, 205, 206, 207). The plurality of interconnects 222 can provide at least one electrical path (e.g., an electrical connection) between two or more integrated devices (e.g., 204, 205, 206, 207). The plurality of interconnects 222 can have a first minimum pitch and a first minimum line spacing (L / S). In some implementations, the first minimum pitch for the plurality of interconnects 222 is in the range of approximately 100-200 microns (μm). In some implementations, a first minimum line spacing (L / S) for the plurality of interconnects 222 is in the range of approximately 9 / 9-12 / 12 microns (μm) (e.g., a minimum line width of approximately 9-12 microns (μm), a minimum spacing of approximately 9-12 microns (μm)). Different implementations may use different substrates. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, a substrate including a core layer. In some implementations, at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The dielectric constant of at least one dielectric layer 220 may be in the range of approximately 3.5-3.7. At least one dielectric layer 220 may include a glass fabric for reinforcing the substrate 202. Examples of manufacturing substrates are described below. Figures 10A-10C As will be described further below, in some implementations, the substrate 202 can be manufactured using a modified semi-additive process (mSAP) or a semi-additive process (SAP).

[0030] A first integrated device 204 is coupled to a first surface (e.g., a top surface) of a substrate 202. The first integrated device 204 is coupled to the substrate via a plurality of interconnects 240. The plurality of interconnects 240 may include copper posts and / or solder interconnects. An underfill 243 is located between the substrate 202 and the first integrated device 204. The underfill 243 may surround the plurality of interconnects 240. A second integrated device 206 is coupled to a first surface (e.g., a top surface) of the substrate 202. The second integrated device 206 is coupled to the substrate via a plurality of interconnects 260. The plurality of interconnects 260 may include copper posts and / or solder interconnects. An underfill 263 is located between the substrate 202 and the second integrated device 206. The underfill 263 may surround the plurality of interconnects 240.

[0031] Integrated device 205 is coupled to the second surface (e.g., bottom surface) of substrate 202. Integrated device 205 is coupled to the substrate via a plurality of interconnects 250. The plurality of interconnects 250 may include copper posts and / or solder interconnects. An underfill 253 is located between substrate 202 and integrated device 205. The underfill 252 may surround the plurality of interconnects 250. Integrated device 207 is coupled to the second surface (e.g., bottom surface) of substrate 202. Integrated device 207 is coupled to the substrate via a plurality of interconnects 270. The plurality of interconnects 270 may include copper posts and / or solder interconnects. An underfill 272 is located between substrate 202 and integrated device 207. The underfill 272 may surround the plurality of interconnects 270. Integrated device 205 and integrated device 207 may be located on either side of a plurality of solder interconnects 280.

[0032] Interconnect integrated device 201 is coupled to a first surface of substrate 202. As will be described further below, interconnect integrated device 201 can be a high-density interconnect integrated device. Interconnect integrated device 201 can be coupled to substrate 202 via a plurality of solder interconnects 210 and / or guide pillar interconnects (e.g., copper guide pillar interconnects). Interconnect integrated device 201 is located between first integrated device 204 and second integrated device 206. This configuration helps improve package performance by reducing routing congestion in substrate 202 and / or by reducing current paths (e.g., signal paths) between integrated devices. The end result is a package with a more compact form factor. Additionally, interconnect integrated device 201 can help reduce the cost of substrate 202 because interconnects on substrate 202 do not need to be in close proximity (e.g., lower L / S) to achieve near-die disconnection, as the interconnects on interconnect integrated device 201 facilitate near-die disconnection. As will be described further below, at least one interconnect integrated device can be located on another surface of substrate 202. In some implementations, the interconnect integrated device can be integrated or embedded within substrate 202. The interconnection integrated device can be configured to provide at least one electrical path for at least one electrical signal. As will be further described below, the interconnection integrated device (e.g., 201, 701) can be configured as a bridge. The interconnection integrated device (e.g., 201, 701) can include a die (e.g., a passive device die). The interconnection integrated device configured as a bridge and / or a passive device die may not have active devices, such as transistors. Therefore, the interconnection integrated device configured as a bridge and / or a passive device die may not have transistors.

[0033] Encapsulation layer 208 is located on a first surface (e.g., top surface) of substrate 202 such that encapsulation layer 208 encapsulates first integrated device 204, second integrated device 206, and interconnected integrated device 201. Encapsulation layer 208 may include a mold, a resin, an epoxy, and / or a polymer. Encapsulation layer 208 may be a means for encapsulation.

[0034] The integrated device (e.g., 204, 205, 206, 207) may include a die (e.g., a semiconductor die). The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 204, 205, 206, 207) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0035] Different implementations may couple different components to substrate 202. Other components (eg, surface mounted components) that may be coupled to substrate 202 include passive devices (eg, capacitors).

[0036] The interconnected integrated device 201 can be a high-density interconnected integrated device having a second minimum pitch and a second minimum line spacing (L / S). In some implementations, the second minimum pitch of the interconnects for the interconnected integrated device (e.g., 201) is in the range of about 100-200 microns (μm). In some implementations, the second minimum line spacing (L / S) of the interconnects for the interconnected integrated device (e.g., 201, 701) is in the range of about 2 / 2-5 / 5 microns (μm) (e.g., a minimum line width of about 2–5 microns (μm), a minimum spacing of about 2–5 microns (μm)). For example, Figure 7 As shown, the interconnected integrated device 201 and the interconnected integrated device 701 can each have an interconnect whose corresponding second minimum pitch is less than the first minimum pitch of the substrate 202. Similarly, the interconnected integrated device 201 and the interconnected integrated device 701 can each have an interconnect whose corresponding minimum pitch is less than the first minimum line spacing (L / S) of the substrate 202. The pitch can be defined as the center-to-center distance between two adjacent interconnects. The interconnected integrated device (e.g., 201, 701) is a local integrated device configured to be placed in an area near the integrated device. The size of the interconnected integrated device can vary with different implementations. However, the footprint of the interconnected integrated device will be smaller than the footprint of the substrate 202.

[0037] As will be further described below, some electrical signals (e.g., first electrical signals, second electrical signals) to and from integrated devices (e.g., 204, 206) can be configured to travel through the interconnected integrated device 201. Interconnected integrated devices with higher density interconnects allow the package 200 to provide a higher I / O pin count without having to increase the size of the package 200. For example, using the interconnected integrated device 201 can allow the substrate 202 to have a smaller number of metal layers, which can help reduce the overall height of the package 200. One or more interconnected integrated devices 201 can help reduce congestion and / or entanglement in certain areas of the substrate 202 (e.g., areas near the integrated devices) due to a large pin count and / or netlist number. The interconnected integrated device 201 can have a lower height than the first integrated device 204 and / or the second integrated device 206.

[0038] Figure 2 The interconnected integrated device 201 is shown to include at least one dielectric layer 211, a plurality of interconnects 212, a passivation layer 214, and a substrate 216. The substrate 216 may include silicon (Si), glass, or quartz. The substrate 216 may be a die substrate. The interconnected integrated device 201 may include a front side and a back side. The back side of the interconnected integrated device 201 may be the side including the substrate 216. The front side of the interconnected integrated device 201 may be the side including the passivation layer 214 and / or the side where the solder interconnects are coupled to the interconnected integrated device 201. The front side of the interconnected integrated device may be opposite to the back side of the interconnected integrated device. As will be further described below, the interconnected integrated device 201 (and / or any interconnected integrated device described in this disclosure) may be configured as a bridge. The interconnected integrated device 201 may include a die (e.g., a passive device die). An interconnected integrated device configured as a bridge and / or a passive device die may not have active devices, such as transistors. Thus, the interconnected integrated device configured as a bridge and / or passive device die may not have transistors. As described above, the interconnects of the interconnected integrated device may have a higher density (e.g., a lower minimum pitch and / or a lower minimum L / S) than the interconnects of the substrate 202. The passivation layer 214 is located above the first surface of the interconnected integrated device 201. A plurality of solder interconnects 210 are coupled to the first surface of the interconnected integrated device 201.

[0039] As described above, the interconnected integrated devices can be components coupled to the substrate 202 so that the package 200 can provide a higher I / O pin count without having to increase the overall size of the package 200, and / or can provide shorter paths between the integrated devices. In some implementations, one or more electrical signals to and from one or more integrated devices can travel through one or more interconnected integrated devices. One or more interconnected integrated devices (e.g., 201) can help reduce congestion and / or entanglement in certain areas of the substrate due to a large number of pin counts and / or netlist numbers. A netlist is the arrangement of circuit components and how the components are electrically coupled together. One or more interconnected integrated devices 201 have improved capacitance density, provide shorter paths between integrated devices, help reduce inductance, and / or reduce wiring constraints.

[0040] In some implementations, the at least one dielectric layer 211 can include a prepreg layer and / or a photoimageable dielectric layer. The dielectric constant of the at least one dielectric layer 211 can be in the range of approximately 3.3-4.0. In some implementations, the at least one dielectric layer 211 interconnecting the integrated device can include a glass fabric. However, the glass fabric will be finer than the glass fabric in the at least one dielectric layer 220 of the substrate 202.

[0041] Figure 3 Illustrated is a diagram of how electrical signals are conceptually configured to travel within a package. Figure 3 The diagram illustrates (i) a first electrical path 301 for a first electrical signal, (ii) a second electrical path 302 for a second electrical signal, (iii) a third electrical path 303 for a third electrical signal, and (iv) a fourth electrical path 304 for a fourth electrical signal. The first electrical path 301 can be configured to allow signals to travel between the first integrated device 204 and the interconnected integrated device 201. The second electrical path 302 can be configured to allow signals to travel between the second integrated device 206 and the interconnected integrated device 201. The third electrical path 303 can be configured to allow signals to travel between the first integrated device 204 and the interconnected integrated device 201. The fourth electrical path 304 can be configured to allow signals to travel between the second integrated device 206 and the interconnected integrated device 201. An electrical path 311 can be coupled to the electrical path 301 and the electrical path 302. An electrical path 313 can be coupled to the electrical path 303 and the electrical path 304. The electrical path 311 can include interconnects from the interconnected integrated device 201. Electrical path 313 may include interconnects from interconnected integrated device 201 .

[0042] In some implementations, the first integrated device 204 and the second integrated device 206 can be configured to be electrically coupled to each other via the substrate 202 and the interconnected integrated device 201. For example, at least one current (e.g., an electrical signal) between the first integrated device 204 and the second integrated device 206 can travel through the substrate 202, the interconnected integrated device 201, and back through the substrate.

[0043] In one example, the first electrical path 301 and the second electrical path 302 may be configured to be coupled (eg, electrically coupled) together such that the first integrated device 204 and the second integrated device 206 are configured to be electrically coupled together via the interconnected integrated device 201 . Thus, as an example, the first integrated device 204 and the second integrated device 206 are configured to be electrically coupled together such that at least one current (e.g., an electrical signal) between the first integrated device 204 and the second integrated device 206 travels through (i) the first interconnect(s) from the plurality of interconnects 240, (ii) the first interconnect(s) from the plurality of interconnects 222 from the substrate 202, (iii) the first solder interconnect(s) from the plurality of solder interconnects 210, (iv) the first interconnect(s) (e.g., 212) from the interconnected integrated device 201, (v) the second solder interconnect(s) from the plurality of solder interconnects 210, (vi) the second interconnect(s) from the plurality of interconnects 222 from the substrate 202, and (vii) the first solder interconnect(s) from the plurality of interconnects 260.

[0044] The first electrical path 301 may include (i) first interconnect(s) from the plurality of interconnects 240, (ii) first interconnect(s) from the plurality of interconnects 222 of the substrate 202, (iii) first solder interconnect(s) from the plurality of solder interconnects 210, and / or (iv) first interconnect(s) (e.g., 212) from the interconnected integrated device 201.

[0045] The second electrical path 302 may include (i) first interconnect(s) from the plurality of interconnects 260, (ii) second interconnect(s) from the plurality of interconnects 222 of the substrate 202, (iii) second solder interconnect(s) from the plurality of solder interconnects 210, and / or (iv) first interconnect(s) (e.g., 212) from the interconnected integrated device 201.

[0046] The third electrical path 303 may include (i) first interconnect(s) from the plurality of interconnects 240, (ii) first interconnect(s) from the plurality of interconnects 222 of the substrate 202, (iii) first solder interconnect(s) from the plurality of solder interconnects 210, and / or (iv) first interconnect(s) (e.g., 212) from the interconnected integrated device 201.

[0047] The fourth electrical path 304 may include (i) first interconnect(s) from the plurality of interconnects 260, (ii) second interconnect(s) from the plurality of interconnects 222 of the substrate 202, (iii) second solder interconnect(s) from the plurality of solder interconnects 210, and / or (iv) first interconnect(s) (e.g., 212) from the interconnected integrated device 201.

[0048] Note that two or more of the various electrical paths described in this disclosure can be configured to be electrically coupled to each other. For example, electrical path 303 can be configured to be electrically coupled to electrical path 304 (e.g., via electrical path 313). In another example, electrical path 301 can be configured to be electrically coupled to electrical path 302 (e.g., via electrical path 311). Note that (multiple) electrical paths for one or more signals can enter and exit via the front side of an interconnected integrated device (e.g., 201). This means that at least one electrical signal traveling through an interconnected integrated device can (i) enter via the front side of the interconnected integrated device, (ii) travel through (multiple) interconnects in the interconnected integrated device, and (iii) exit via the front side of the interconnected integrated device. For example, at least one electrical signal can enter via electrical path 301, travel through interconnected integrated device 201 and exit via electrical path 302, or vice versa. Different implementations can have different numbers of electrical signals traveling to and from different integrated devices. The paths of these electrical signals can be different. The electrical signals can include I / O signals. The exemplary paths shown in this disclosure may also apply to power and / or ground instead of I / O signals.

[0049] Figure 4 Another view illustrating how electrical signals conceptually travel through a package. Figure 4 Illustrated are a substrate 402, a first integrated device 204 coupled to the substrate 402, a second integrated device 206 coupled to the substrate 402, and an interconnected integrated device 201 coupled to the substrate 402. The substrate 402 may be similar to the substrate 202 and, therefore, may include similar components as the substrate 202. The substrate 402 may be implemented in any of the packages described in this disclosure.

[0050] Figure 4The diagram shows an interconnected integrated device 201 located between the first integrated device 204 and the second integrated device 206. The first integrated device 204, the second integrated device 206, and the interconnected integrated device 201 are located on a surface (eg, first surface, second surface) of the substrate 402.

[0051] The first integrated device 204 includes electrical paths 410, 411, 412, 440, 441, 442, and 443 for current (e.g., electrical signals) of the first integrated device 204. The electrical paths 410, 411, 412, 440, 441, 442, and 443 may be conceptual representations of exemplary paths for current to and from the first integrated device 204. The electrical paths may include interconnects and / or solder interconnects. The electrical paths 410, 411, 412, 443, and / or 463 may illustrate paths by which at least one electrical signal may enter and exit the front side of the interconnected integrated device 201.

[0052] Second integrated device 206 includes electrical paths 410, 411, 412, 460, 461, 462, and 463 for current (e.g., electrical signals) for second integrated device 206. Electrical paths 410, 411, 412, 460, 461, 462, and 463 may be conceptual representations of exemplary paths for current to and from second integrated device 206. The electrical paths may include interconnects and / or solder interconnects.

[0053] like Figure 4 As shown, the first integrated device 204 and the second integrated device 206 can be configured to be electrically coupled together via electrical paths 410, 411, and 412. The electrical paths 410, 411, and 412 are electrical paths for current (e.g., signals) to travel through the interconnected integrated device 201. The electrical paths 410, 411, and 412 can include interconnects in the substrate 402 and interconnects in the interconnected integrated device 201. The electrical paths 410, 411, and / or 412 can be similar to Figure 3 Each electrical path (440, 441, 442, 460, 461, and 463) may include its own respective interconnect from the plurality of interconnects 222 of the substrate 402.

[0054] Figure 4The diagram illustrates that an electrical path for an integrated device can include interconnected integrated device 201, even if the electrical path does not provide an electrical path between two integrated devices. For example, a signal traveling through electrical path 443 can mean that signals to and from first integrated device 204 can travel through interconnected integrated device 203, even if the signals do not end at second integrated device 206. Similarly, a signal traveling through electrical path 463 can mean that signals to and from second integrated device 206 can travel through interconnected integrated device 203, even if the signals do not end at first integrated device 204.

[0055] Different implementations may have different numbers of electrical paths and / or occupy electrical paths with different routings.

[0056] Figure 5 Another view illustrating how electrical signals conceptually travel through a package. Figure 5 The diagram shows a substrate 502, a first integrated device 204 coupled to the substrate 502, a second integrated device 206 coupled to the substrate 502, an interconnected integrated device 201 coupled to the substrate 502, an integrated device 504 coupled to the substrate 502, and an integrated device 506 coupled to the substrate 502. The substrate 502 can be similar to the substrate 202 and, therefore, can include similar components as the substrate 202. The substrate 502 can be implemented in any of the packages described in the present disclosure.

[0057] Figure 5 1. The first integrated device 204 is shown to include electrical paths 530, 531, 540, and 541. The second integrated device 206 includes electrical paths 530, 532, and 560. The integrated device 504 includes electrical paths 533, 541, and 542. The integrated device 506 includes electrical paths 531, 532, 533, and 561. Each electrical path (540, 541, 542, 560, and 561) can include its own corresponding interconnect from the plurality of interconnects 222 of the substrate 502. The electrical paths 530, 531, 532, and / or 533 can illustrate a path(s) by which at least one electrical signal can enter and exit the front side of the interconnected integrated device 201.

[0058] First integrated device 204 is coupled to integrated device 504 via electrical path 541. First integrated device 204 is coupled to second integrated device 206 via electrical path 530. Electrical path 530 includes interconnects from integrated interconnect device 201. Thus, first integrated device 204 can be coupled to second integrated device 206 via substrate 502 and interconnect integrated device 201. First integrated device 204 is coupled to integrated device 506 via electrical path 531. Electrical path 531 includes interconnects from interconnect integrated device 201. Thus, first integrated device 204 can be coupled to integrated device 506 via substrate 502 and interconnect integrated device 201.

[0059] Second integrated device 206 is coupled to integrated device 506 via electrical path 532. Electrical path 532 includes interconnects from interconnect integrated device 201. Thus, second integrated device 206 can be coupled to integrated device 506 via substrate 502 and interconnect integrated device 201.

[0060] Integrated device 504 is coupled to integrated device 506 via electrical path 533. Electrical path 533 includes interconnects from interconnect integrated device 201. Thus, integrated device 504 can be coupled to integrated device 506 via substrate 502 and interconnect integrated device 201.

[0061] Figure 6 Another view illustrating how electrical signals conceptually travel through a package. Figure 6 The diagram illustrates a substrate 602, a first integrated device 204 coupled to the substrate 602, a second integrated device 206 coupled to the substrate 602, an interconnected integrated device 601a coupled to the substrate 602, an interconnected integrated device 601b coupled to the substrate 602, an interconnected integrated device 601c coupled to the substrate 602, an integrated device 504 coupled to the substrate 602, and an integrated device 506 coupled to the substrate 602. The substrate 602 can be similar to the substrate 202 and, therefore, can include similar components to the substrate 202. The interconnected integrated devices (e.g., 601a, 601b, 601c) can be similar to the interconnected integrated device 201 and, therefore, can include similar components to the interconnected integrated device 201. The substrate 602 and the interconnected integrated devices (e.g., 601a, 601b, 601c) can be implemented in any package described in the present disclosure.

[0062] Figure 6 The first integrated device 204 is shown coupled to the second integrated device 206 via an electrical path 630. The electrical path 630 includes interconnects in the substrate 602 and interconnects in the interconnect integrated device 601a. ​​Thus, the first integrated device 204 can be coupled to the second integrated device 206 via the substrate 602 and the interconnect integrated device 601a.

[0063] First integrated device 204 is coupled to integrated device 506 via electrical path 631. Electrical path 631 includes interconnects in substrate 602, interconnects in interconnect integrated device 601a, and interconnects in interconnect integrated device 601b. Thus, first integrated device 204 can be coupled to integrated device 506 via substrate 602, interconnect integrated device 601a, and interconnect integrated device 601b.

[0064] Second integrated device 206 is coupled to integrated device 506 via electrical path 632. Electrical path 632 includes interconnects in substrate 602 and interconnects in interconnect integrated device 601c. Thus, second integrated device 206 can be coupled to integrated device 506 via substrate 602 and interconnect integrated device 601c.

[0065] Integrated device 504 is coupled to integrated device 506 via electrical path 633. Electrical path 633 includes interconnects in substrate 602 and interconnects in interconnect integrated device 601b. Thus, integrated device 504 can be coupled to integrated device 506 via substrate 602 and interconnect integrated device 601b.

[0066] Electrical paths 630, 631, 632, and / or 633 may illustrate paths by which at least one electrical signal may enter and exit the front side of an interconnected integrated device (e.g., 601a, 601b, 601c). The paths taken by the various electrical signals may be similar to Figure 3 . However, please note that the paths of electrical signals shown in this disclosure are exemplary and / or conceptual. Different implementations may use different paths for electrical signals. In addition, electrical signals and / or electrical paths may travel through different types of interconnects (e.g., through-holes, traces, pads, guide posts), solder interconnects, and / or components (e.g., passive devices). Thus, for example, in some implementations, an electrical signal traveling between an integrated device and an interconnected integrated device may travel through at least one intermediate component (e.g., passive devices, capacitors) between the integrated device and the interconnected integrated device. The paths shown for electrical signals may also be applied to power and / or grounding.

[0067] As discussed above, the package may include different components and / or different numbers of components located on different portions of the substrate. Figure 7 The package 700 including interconnected integrated devices is shown. The package 700 is similar to Figure 2 The package 700 is similar to the package 200 and includes similar components to the package 200. The package 700 includes the first integrated device 204, the second integrated device 206, an integrated device 705, an integrated device 707, the interconnected integrated device 201, and the interconnected integrated device 701.

[0068] like Figure 7As shown, integrated device 705, integrated device 707, and interconnected integrated device 701 are coupled to the second surface (eg, bottom surface) of substrate 202. Integrated device 705, integrated device 707, and interconnected integrated device 701 may be located on the sides of plurality of solder interconnects 280.

[0069] The second interconnected integrated device 701 is similar to the interconnected integrated device 201. The second interconnected integrated device 701 may include the same components and / or materials as the interconnected integrated device 201. The second interconnected integrated device 701 may include a different number of metal layers than the interconnected integrated device 201. The interconnected integrated device may be used to provide at least one electrical path between two or more integrated devices. For example, an electrical signal between a first integrated device and a second integrated device may travel through a substrate (e.g., through a first plurality of interconnects of the substrate), through an interconnected integrated device (e.g., through a plurality of interconnects of the interconnected integrated device), and back through the substrate (e.g., through a second plurality of interconnects of the substrate). The first integrated device and the second integrated device may be located on the same surface of the substrate or on different surfaces of the substrate. The terms "first surface" and "second surface" of the substrate are arbitrary and may refer to any surface of the substrate. For example, the first surface of the substrate may be the bottom surface of the substrate, and the second surface of the substrate may be the top surface of the substrate. In another example, the first surface of the substrate may be the top surface of the substrate, and the second surface of the substrate may be the bottom surface of the substrate. The interconnected integrated device (e.g., 201, 701) may be a device for interconnecting integrated devices. An example of a method for fabricating an interconnected integrated device is described below. Figures 8A-8D Illustration and description.

[0070] Interconnected integrated device 701 can be coupled to multiple interconnects 222 via multiple interconnects 710. Multiple interconnects 710 can include copper posts and / or solder interconnects. Integrated device 705 can be coupled to multiple interconnects 222 via multiple interconnects 750. Multiple interconnects 750 can include copper posts and / or solder interconnects. Integrated device 707 can be coupled to multiple interconnects 222 via multiple interconnects 770. Multiple interconnects 770 can include copper posts and / or solder interconnects. Interconnected integrated device 701 is located between integrated device 705 and integrated device 707. Integrated device 705 and integrated device 707 can be configured to be electrically coupled to each other via interconnected integrated device 701.

[0071] Integrated device 705 may be coupled to interconnected integrated device 701 via electrical path 702. Integrated device 707 may be coupled to interconnected integrated device 701 via electrical path 704. Integrated device 705 may be coupled to integrated device 707 via electrical path 702 and electrical path 704.

[0072] The electrical path 702 may include (i) first interconnect(s) from the plurality of interconnects 750, (ii) first interconnect(s) from the plurality of interconnects 222 of the substrate 202, (iii) first solder interconnect(s) from the plurality of interconnects 710, and / or (iv) first interconnect(s) (e.g., 212) from the interconnected integrated device 701.

[0073] The electrical path 704 may include (i) first interconnect(s) from the plurality of interconnects 770, (ii) second interconnect(s) from the plurality of interconnects 222 of the substrate 202, (iii) second solder interconnect(s) from the plurality of interconnects 710, and / or (iv) first interconnect(s) (e.g., 212) from the interconnected integrated device 701.

[0074] 706 . The first integrated device 204 can be coupled to the integrated device 705 via an electrical path 706. The electrical path 706 can include (i) first interconnect(s) from the plurality of interconnects 750, (ii) first interconnect(s) from the plurality of interconnects 222 of the substrate 202, and / or (iii) first solder interconnect(s) from the plurality of interconnects 250. Note that two or more of the various electrical paths described in this disclosure can be configured to be electrically coupled to each other. For example, the electrical path 702 can be configured to be electrically coupled to the electrical path 704. In another example, the electrical path 702 can be configured to be electrically coupled to the electrical path 706. Note that the electrical path(s) for one or more signals can enter and exit via the front side of the interconnected integrated device (e.g., 201, 601a, 601b, 601c, 701). This means that electrical signals traveling through the interconnect integrated device can (i) enter via the front side of the interconnect integrated device, (ii) travel through the interconnect(s) in the interconnect integrated device, and (iii) exit via the front side of the interconnect integrated device. For example, at least one electrical signal can enter via electrical path 702, travel through interconnect integrated device 701, and exit via electrical path 704, or vice versa.

[0075] It should be noted that Figures 4 to 6 The configuration and electrical paths described in can be applied to Figure 7 Note that any package described in this disclosure may be part of a package-on-package (PoP). Additionally, the packages described in this disclosure (eg, 200, 700) may be coupled to an interposer.

[0076] In some implementations, the interconnect integrated device (e.g., 201, 701) can be configured to include a passive device (e.g., a capacitor), or can be configured as a passive device. For example, the interconnect integrated device can be configured as a decoupling integrated device. At least one passive device of the interconnect integrated device can be configured as an electrical decoupler for a power distribution network (PDN) of the package. When the interconnect integrated device includes at least one passive device such as a capacitor, one or more of the electrical paths described in the present disclosure can pass through at least one passive device of the interconnect integrated device.

[0077] Passive devices such as capacitors can be metal insulator metal (MIM) capacitors, which are formed based on interconnects on two metal layers of an interconnected integrated device. A high-K dielectric layer can be located between the interconnects defining the MIM capacitor on the two metal layers. For example, a MIM capacitor in an interconnected integrated device can be defined by interconnects from a plurality of interconnects 212 on two metal layers. A high-K dielectric layer (which can be different from dielectric layer 211) can be located between the interconnects defining the MIM capacitor on the two metal layers. The capacitor can be a high-density capacitor having a capacitance density in the range of approximately 25 nanofarads per square millimeter (nF / mm2) to 1000 nF / mm2, an equivalent series inductance (ESL) equal to or less than 40 petahenries (pH), and a frequency response equal to or greater than 1 gigahertz (GHz).

[0078] Exemplary sequence for fabricating high density interconnect integrated devices

[0079] Figures 8A-8D An exemplary sequence for providing or manufacturing a high density interconnect integrated device is illustrated. In some implementations, Figures 8A-8D The sequence can be used to provide or make Figure 2 The interconnected integrated device 201 or any interconnected integrated device described in this disclosure.

[0080] It should be noted that in order to simplify and / or clarify the sequence for providing or manufacturing an interconnected integrated device, Figures 8A-8D The sequence may combine one or more stages. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of this disclosure. Different implementations may manufacture interconnected integrated devices differently.

[0081] Stage 1, such as Figure 8A , which illustrates a state after providing a substrate 216. The substrate 216 may include glass and / or silicon.

[0082] Stage 2 illustrates a state after a plurality of interconnects 822 are formed on substrate 216. Plurality of interconnects 822 may include traces and / or pads. Forming plurality of interconnects 822 may include forming a seed layer, performing a photolithography process, an electroplating process, a stripping process, and / or an etching process. Plurality of interconnects 822 may be a portion of plurality of interconnects 212.

[0083] Stage 3 illustrates a state after dielectric layer 830 is formed over the plurality of interconnects 822 and substrate 216. Dielectric layer 830 may be deposited and / or coated over the plurality of interconnects 822 and dielectric layer 820. Dielectric layer 830 may include a polymer. Dielectric layer 830 may be similar to dielectric layer 211.

[0084] Stage 4 illustrates the state after cavity 831 is formed in dielectric layer 830. An etching process may be used to form cavity 831.

[0085] Stage 5, such as Figure 8B , a state after a plurality of interconnects 832 are formed on dielectric layer 830 is illustrated. The plurality of interconnects 832 may include vias, traces, and / or pads. Forming the plurality of interconnects 832 may include performing a photolithography process, a plating process, a stripping process, and / or an etching process. The plurality of interconnects 832 may be part of the plurality of interconnects 212.

[0086] Stage 6 illustrates a state after dielectric layer 840 is formed over the plurality of interconnects 832 and dielectric layer 830. Dielectric layer 840 may be deposited and / or coated over the plurality of interconnects 832 and dielectric layer 830. Dielectric layer 840 may include a polymer. Dielectric layer 840 may be similar to dielectric layer 830.

[0087] Stage 7 illustrates the state after cavity 841 is formed in dielectric layer 840. An etching process may be used to form cavity 841.

[0088] Stage 8 illustrates a state after a plurality of interconnects 842 are formed over dielectric layer 840. Plurality of interconnects 842 may include vias, traces, and / or pads. Forming plurality of interconnects 842 may include performing a photolithography process, a plating process, a stripping process, and / or an etching process. Plurality of interconnects 842 may be a portion of plurality of interconnects 212.

[0089] Stage 9, such as Figure 8C , which illustrates a state after dielectric layer 850 is formed over a plurality of interconnects 842 and dielectric layer 840. Dielectric layer 850 may be deposited and / or coated over a plurality of interconnects 842 and dielectric layer 840. Dielectric layer 850 may include a polymer. Dielectric layer 850 may be similar to dielectric layer 840.

[0090] Stage 10 illustrates the state after cavity 851 is formed in dielectric layer 850. An etching process may be used to form cavity 851.

[0091] Stage 11 illustrates a state after a plurality of interconnects 852 are formed over dielectric layer 850. Plurality of interconnects 852 may include vias, traces, and / or pads. Forming plurality of interconnects 852 may include performing a photolithography process, a plating process, a stripping process, and / or an etching process. Plurality of interconnects 852 may be a portion of plurality of interconnects 212.

[0092] Stage 12, such as Figure 8D , illustrates a state after a passivation layer 214 is formed on at least one dielectric layer 211. The at least one dielectric layer 211 may represent dielectric layers 830, 840, and 850. Stage 12 may illustrate a plurality of interconnects 212, which may include a plurality of interconnects 832, 842, and / or 852.

[0093] Stage 13 illustrates the state after the plurality of solder interconnects 210 are coupled to the interconnected integrated device 201. Stage 13 may be illustrated as follows: Figure 2 In some implementations, the interconnected integrated device 201 is part of a wafer, and singulation can be performed to cut the wafer into individual interconnected integrated devices. Figures 8A-8D The sequence can be used to manufacture the interconnected integrated device 701.

[0094] As described above, the interconnected integrated device can be configured to include at least one passive device or can be configured as a passive device. Passive devices such as capacitors can be metal insulator metal (MIM) capacitors formed based on interconnects (e.g., 822, 832, 842) from any two metal layers of the interconnected integrated device. A high-K dielectric layer (which can be different from dielectric layers 830, 840, and / or 850) can be formed between the interconnects from the two metal layers of the interconnected integrated device. The high-K dielectric layer can be formed in a manner similar to any of the above-mentioned dielectric layers. Other dielectric layers (e.g., 830, 840, 850) can surround the high-K dielectric layer. At least one passive device of the interconnected integrated device can be configured as an electrical decoupler for a power distribution network (PDN) of the package.

[0095] Exemplary flow chart of a method for manufacturing a high-density interconnected integrated device

[0096] In some implementations, fabricating a package including a high-density interconnected integrated device includes several processes. Figure 9 FIG2 illustrates an exemplary flow chart of a method 900 for providing or manufacturing a high density interconnect integrated device. In some implementations, Figure 9 The method 900 may be used to provide or manufacture the Figure 2 and / or Figure 7 However, the method 900 can be used to provide or manufacture any interconnected integrated device described in the present disclosure.

[0097] It should be noted that in order to simplify and / or clarify the method for providing or manufacturing an interconnected integrated device, Figure 9 The method can combine one or more processes. In some implementations, the order of the processes can be changed or modified. Figure 9 The description will be based on making redistribution interconnects. However, Figure 9 The method can be used to manufacture any type of interconnect.

[0098] The method provides (at 905) a substrate (eg, 216). The substrate 216 may include glass, quartz, and / or silicon. Figure 8A Stage 1 of the diagram illustrates an example of a substrate.

[0099] The method forms (at 910) a first metal layer by forming a plurality of interconnects 822 over a substrate (eg, 216). Forming the plurality of interconnects may include performing a photolithography process, performing an electroplating process, performing a lift-off process, and / or performing an etching process. Figure 8A Stage 2 illustrates an example of forming a first metal layer for a high density interconnect integrated device.

[0100] The method forms (at 915) a second metal layer by forming a dielectric layer (e.g., 830) and a plurality of interconnects 832 over the first metal layer. The dielectric layer may include a polymer. Forming the dielectric layer and the plurality of interconnects may include disposing the dielectric layer 830 over the dielectric layer 820 and the interconnects 822; performing a photolithography process; performing an electroplating process; performing a stripping process; and / or performing an etching process. Figure 8A-8B Stages 3-5 illustrate an example of forming a second metal layer (e.g., a redistribution layer, redistribution metal layer) for a high-density interconnected integrated device. The redistribution layer (RDL) can be in the form of a metallization layer. The RDL can include interconnects that include U-shapes or V-shapes. The terms "U-shaped" and "V-shaped" should be interchangeable. The terms "U-shaped" and "V-shaped" can refer to the side profile shape of the interconnect and / or the redistribution interconnect. The U-shaped interconnect and the V-shaped interconnect can have a top and a bottom. The bottom of the U-shaped interconnect (or V-shaped interconnect) can be coupled to the top of another U-shaped interconnect (or V-shaped interconnect). Forming the metal layer and the dielectric layer can include using a back-end of line (BEOL) process.

[0101] The method forms (at 920) an additional metal layer by forming one or more dielectric layers (e.g., 840, 850) and a plurality of interconnects (e.g., 842, 852) over the second metal layer. The dielectric layer may include a polymer. Forming the dielectric layer and the plurality of interconnects may include disposing one or more dielectric layers (e.g., 840, 850) over the dielectric layer 830 and the interconnects 832, performing a photolithography process, performing an electroplating process, performing a stripping process, and / or performing an etching process. Figure 8B-Figure 8C Stages 7-11 of the present invention illustrate an example of forming an additional metal layer for a high density interconnect integrated device. Forming the additional metal layer and the additional dielectric layer may include using a back end of line (BEOL) process.

[0102] The method forms (at 925) a passivation layer (eg, 214) over the dielectric layer interconnecting the integrated device (eg, 201). The passivation layer (eg, 214) can be disposed over the dielectric layer 211. Figure 8D Stage 12 illustrates an example of forming a passivation layer over a dielectric layer that interconnects integrated devices.

[0103] The method couples (at 930 ) a plurality of solder interconnects (eg, 210 ) to an interconnected integrated device (eg, 201 ). Figure 8D Stage 13 may illustrate an example of a solder interconnect coupled with an interconnected integrated device.

[0104] In some implementations, the interconnected integrated device 201 is part of a wafer, and singulation may be performed to cut the wafer into individual interconnected integrated devices. The method 900 may be used to fabricate the interconnected integrated device 201 including the plurality of interconnects 212 .

[0105] Exemplary sequence for fabricating a substrate

[0106] In some implementations, fabricating the substrate includes several processes. Figures 10A-10C An exemplary sequence for providing or manufacturing a substrate is illustrated. In some implementations, Figures 10A-10C The sequence can be used to provide or make Figure 2 substrate 202. However, Figures 10A-10C The process can be used to manufacture any substrate described in this disclosure.

[0107] It should be noted that in order to simplify and / or clarify the sequence for providing or manufacturing a substrate, Figures 10A-10C The sequence of steps may combine one or more stages. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0108] Stage 1, such as Figure 10A, illustrates a state after providing a carrier 1000 and forming a metal layer over the carrier 1000. The metal layer may be patterned to form an interconnection 1002. An electroplating process and an etching process may be used to form the metal layer and the interconnection.

[0109] Stage 2 illustrates the state after a dielectric layer 1020 is formed over the carrier 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0110] Stage 3 illustrates a state after the plurality of cavities 1010 are formed in the dielectric layer 1020. The plurality of cavities 1010 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0111] Stage 4 illustrates the state after interconnects 1012 are formed in and on dielectric layer 1020. For example, vias, pads, and / or traces may be formed. An electroplating process may be used to form the interconnects.

[0112] Stage 5 illustrates the state after another dielectric layer 1022 is formed over dielectric layer 1020. Dielectric layer 1022 may be the same material as dielectric layer 1020. However, different implementations may use different materials for the dielectric layer.

[0113] Stage 6, such as Figure 10B , a state is illustrated after a plurality of cavities 1030 are formed in the dielectric layer 1022. An etching process or a laser process may be used to form the cavities 1030.

[0114] Stage 7 illustrates the state after interconnects 1014 are formed in and on dielectric layer 1022. For example, vias, pads, and / or traces may be formed. An electroplating process may be used to form the interconnects.

[0115] Stage 8 illustrates the state after another dielectric layer 1024 is formed over dielectric layer 1022. Dielectric layer 1024 may be the same material as dielectric layer 1020. However, different implementations may use different materials for the dielectric layer.

[0116] Stage 9 illustrates the state after a plurality of cavities 1040 are formed in the dielectric layer 1024. An etching process or a laser process may be used to form the cavities 1040.

[0117] Stage 10, such as Figure 10C , illustrates a state after interconnects 1016 are formed in and on dielectric layer 1024. For example, vias, pads, and / or traces may be formed. An electroplating process may be used to form the interconnects.

[0118] Some or all of interconnects 1002, 1012, 1014, and / or 1016 may define plurality of interconnects 222 of substrate 202. Dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 220.

[0119] Stage 11 illustrates the state after the carrier 1000 has been decoupled (eg, removed, ground away) from the dielectric layer 220 , leaving the substrate 202 .

[0120] Stage 12 illustrates a state after a first solder resist layer 224 and a second solder resist layer 226 are formed over the substrate 202 .

[0121] Different implementations can use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form the metal layer. For example, a sputtering process, a spray coating process, and / or an electroplating process can be used to form the metal layer(s).

[0122] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0123] In some implementations, fabricating the substrate includes several processes. Figure 11 An exemplary flow chart of a method 1100 for providing or manufacturing a substrate is shown. In some implementations, Figure 11 The method 1100 may be used to provide or manufacture Figure 2 For example, Figure 11 The method may be used to manufacture the substrate 202 .

[0124] It should be noted that in order to simplify and / or clarify the method for providing or manufacturing a substrate, Figure 11 The method can combine one or more processes. In some implementations, the order of the processes can be changed or modified.

[0125] The method provides (at 1105) a carrier 1000. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or a carrier tape. Figure 10A Stage 1 of FIG. 1 illustrates the state after the carrier is provided.

[0126] The method forms (at 1110) a metal layer over the carrier 1000. The metal layer may be patterned to form interconnects. An electroplating process may be used to form the metal layer and the interconnects. Figure 10A Stage 1 illustrates the state after the metal layers and interconnects 1002 are formed.

[0127] The method forms (at 1115) a dielectric layer 1020 over the carrier 1000 and the interconnect 1002. The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. An etching process (e.g., photoetching) or a laser process may be used to form the plurality of cavities. Figure 10A Stages 2-3 illustrate forming a dielectric layer and a cavity in the dielectric layer.

[0128] The method forms (at 1120) interconnects in and on the dielectric layer. For example, interconnect 1012 can be formed in and on dielectric layer 1020. An electroplating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer on and / or in the dielectric layer. Figure 10A Stage 4 of FIG. 1 illustrates an example of forming interconnects in and over the dielectric layer.

[0129] The method forms (at 1125) a dielectric layer 1022 over the dielectric layer 1020 and the interconnects. The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Figures 10A-10B Stages 5-6 illustrate forming a dielectric layer and a cavity in the dielectric layer.

[0130] The method forms (at 1130) an interconnect in and / or on the dielectric layer. For example, the interconnect 1014 can be formed. An electroplating process can be used to form the interconnect. Forming the interconnect can include providing a patterned metal layer on the dielectric layer. Figure 10B Stage 7 of FIG. 1 illustrates an example of forming interconnects in and over the dielectric layer.

[0131] The method may form additional dielectric layers and additional interconnects as described at 1125 and 1130 . Figure 10B-10C Stages 8-10 illustrate examples of forming interconnects in and over the dielectric layer.

[0132] Once all dielectric layers and additional interconnects are formed, methods can decouple (e.g., remove, grind) the carrier (e.g., 1000) from the dielectric layer 1020, leaving the substrate. In some implementations, methods can form a solder resist layer (e.g., 224, 226) over the substrate.

[0133] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or an electroplating process may be used to form the metal layer(s).

[0134] Exemplary sequence for fabricating a package comprising a high density interconnected integrated device coupled to a substrate

[0135] Figures 12A-12B An exemplary sequence for providing or manufacturing a package comprising a high-density interconnected integrated device coupled to a substrate is illustrated. In some implementations, Figures 12A-12B The sequence may be used to provide or manufacture package 200 or any package described in the present disclosure, package 200 comprising Figure 2 substrate 202 and interconnected integrated device 201.

[0136] It should be noted that in order to simplify and / or clarify the sequence for providing or manufacturing a package, Figures 12A-12B The sequence of steps may combine one or more stages. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure. Figures 12A-12B The sequence can be used to manufacture one package or several packages at a time (as part of a wafer).

[0137] Stage 1, such as Figure 12A , which illustrates a state after providing a substrate 202. The substrate 202 may be provided or manufactured by a supplier. Figures 10A-10C A process similar to the process shown in can be used to manufacture substrate 202. However, different implementations can use different processes to manufacture substrate 202. Examples of processes that can be used to manufacture substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Substrate 202 can be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer. In some implementations, at least one dielectric layer 220 can include a core layer and / or a prepreg layer.

[0138] Stage 2 illustrates a state after integrated device 205 and integrated device 207 are coupled to the second surface (e.g., bottom surface) of substrate 202. Integrated device 205 is coupled to substrate 202 via a plurality of interconnects 250. The plurality of interconnects 250 may be coupled to interconnects from a plurality of interconnects 222 of substrate 202. Integrated device 205 may be coupled to substrate 202 such that a front side (e.g., an active side) of integrated device 205 faces substrate 202. Integrated device 207 is coupled to substrate 202 via a plurality of interconnects 270. The plurality of interconnects 270 may be coupled to interconnects from a plurality of interconnects 222 of substrate 202. Integrated device 207 may be coupled to substrate 202 such that a front side (e.g., an active side) of integrated device 207 faces substrate 202.

[0139] Stage 3 illustrates the state after underfill 252 is provided between substrate 202 and integrated device 205 and underfill 272 is provided between substrate 202 and integrated device 207. Underfill may be provided between substrate 202 and respective integrated device 207.

[0140] Stage 4 illustrates a state after the plurality of solder interconnects 280 are coupled to the second surface of the substrate 202. The plurality of solder interconnects 280 may be coupled to interconnects from the plurality of interconnects 222 of the substrate 202. A reflow process may be used to couple the plurality of solder interconnects 280 to the substrate 202.

[0141] Stage 5, such as Figure 12B , the substrate 202 having the integrated device 205 , the integrated device 207 and the plurality of solder interconnections 280 is shown as being turned over.

[0142] Stage 6 illustrates a state after first integrated device 204, second integrated device 206, and interconnected integrated device 201 are coupled to a first surface (e.g., a top surface) of substrate 202. First integrated device 204 may be coupled to substrate 202 via a plurality of interconnects 240. Second integrated device 206 may be coupled to substrate 202 via a plurality of interconnects 260. Interconnected integrated device 201 may be coupled to substrate 202 via a plurality of solder interconnects 210.

[0143] Stage 6 may also illustrate a state after underfill is formed between the integrated devices and substrate 202. For example, underfill 243 may be disposed between first integrated device 204 and substrate 202, underfill 263 may be disposed between second integrated device 206 and substrate 202, and underfill 213 may be disposed between interconnected integrated device 201 and substrate 202.

[0144] Stage 7 illustrates a state after encapsulation layer 208 is formed over the first surface of substrate 202 such that encapsulation layer 208 encapsulates first integrated device 204, second integrated device 206, and interconnected integrated device 201. The process of forming and / or disposing encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 8 may illustrate a state including at least Figure 2 The package 200 includes the substrate 202, the first integrated device 204, the second integrated device 206, the interconnected integrated device 201, the integrated device 205, the integrated device 207 and the encapsulation layer 208 described in FIG.

[0145] The packages described in this disclosure (eg, 200 , 700 ) can be manufactured one at a time, or can be manufactured together as part of one or more wafers and then singulated into individual packages.

[0146] Exemplary flow chart of a method for manufacturing a package including a high-density interconnected integrated device coupled to a substrate

[0147] In some implementations, fabricating a package including a high-density interconnected integrated device coupled to a substrate includes several processes. Figure 13 An exemplary flow chart of a method 1300 for providing or manufacturing a package comprising a high density interconnected integrated device coupled to a substrate is illustrated. In some implementations, Figure 13 The method 1300 may be used to provide or manufacture the Figure 2 However, the method 1300 may be used to provide or manufacture any package described in this disclosure.

[0148] It should be noted that for the purpose of simplifying and / or clarifying the method for providing or manufacturing a package comprising a high density interconnected integrated device coupled to a substrate, Figure 13 The method can combine one or more processes. In some implementations, the order of the processes can be changed or modified.

[0149] The method provides (at 1305) a substrate (e.g., 202). The substrate 202 may be provided or manufactured by a supplier. The substrate 202 includes a first surface and a second surface. The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Different implementations may provide different substrates. Figures 10A-10C A process similar to the one shown may be used to fabricate substrate 202. However, different implementations may use different processes to fabricate substrate 202. Figure 12A Stage 1 of FIG. 1 illustrates and describes an example of providing a substrate.

[0150] The method couples (at 1310) components to the second surface of substrate 202. Different implementations may couple different components and / or different numbers of components. The components may include integrated device 205, integrated device 207, and / or passive devices (e.g., discrete capacitors). Coupling the components may include providing an underfill between the integrated device and the substrate. Figure 12B Stages 2-3 illustrate and describe an example where various components are coupled to the second surface of the substrate.

[0151] The method couples (at 1315 ) a plurality of solder interconnects (eg, 280 ) to the second surface (eg, 202 ) of the substrate. Figure 12A Stage 4 of FIG. 1 illustrates and describes an example of coupling a solder interconnect to a substrate.

[0152] The method couples (at 1320) at least one integrated device (e.g., 204, 206) and an interconnected integrated device (e.g., 201) to a first surface of a substrate (e.g., 202). The first integrated device 204 can be coupled to the substrate 202 via a plurality of interconnects 240. The plurality of interconnects 240 can be coupled to interconnects from a plurality of interconnects 222 of the substrate 202. The first integrated device 204 can be coupled to the substrate 202 such that a front side (e.g., an active side) of the first integrated device 204 faces the substrate 202. As an example, the first integrated device 204 and the interconnected integrated device 201 can be coupled to the substrate 202 such that the integrated device, the interconnected integrated device, and the substrate are coupled together such that when a first electrical signal travels between the integrated device and the board (e.g., 290), the first electrical signal travels through the substrate 202, then through the interconnected integrated device 201, and back through the substrate 202. The substrate 202 can be flipped before the integrated device is coupled to the substrate 202.

[0153] Second integrated device 206 may be coupled to substrate 202 via plurality of interconnects 260. Plurality of interconnects 640 may be coupled to interconnects from plurality of interconnects 222 of substrate 202. Second integrated device 206 may be coupled to substrate 202 such that a front side (e.g., an active side) of second integrated device 206 faces substrate 202.

[0154] As an example, first integrated device 204, second integrated device 206, and interconnect integrated device 201 can be coupled to substrate 202 such that the integrated devices, interconnect integrated device, and substrate are coupled together such that when a first electrical signal travels between first integrated device 204 and second integrated device 206, it travels through interconnect integrated device 201. For example, a first electrical signal between first integrated device 204 and second integrated device 206 can travel through substrate 202, then through interconnect integrated device 201, and back through substrate 202. Figure 12B Stage 6 illustrates and describes an example of an integrated device and interconnected integrated device coupled to a substrate. Coupling the integrated device to the substrate may also include providing an underfill (e.g., 213, 243, 263) between the respective integrated device (e.g., 204, 206) and the substrate 202. Figure 12B Stage 6 of FIG. 1 illustrates and describes an example of providing an underfill.

[0155] The method forms (at 1325) an encapsulation layer (e.g., 208) over the second surface of the substrate (e.g., 202) such that encapsulation layer 208 encapsulates first integrated device 204, second integrated device 206, and interconnected integrated device 201. The process of forming and / or disposing encapsulation layer 208 can include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Figure 12BStage 7 of FIG. 1 illustrates and describes an example of an encapsulation layer located above the substrate and encapsulating the integrated device.

[0156] Exemplary electronic devices

[0157] Figure 14 Various electronic devices are shown that can be integrated with any of the above-described devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed-location terminal device 1406, a wearable device 1408, or a motor vehicle 1410 can include a device 1400 as described herein. For example, the device 1400 can be any device and / or integrated circuit (IC) package described herein. Figure 14 The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 shown in the figure are merely exemplary. Other electronic devices may also have features of device 1400, including but not limited to the group of devices (electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting global positioning systems (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., self-driving cars), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0158] Figure 2-Figure 7 、 Figures 8A-8D 、 Figure 9 、 Figures 10A-10C 、 Figure 11 、 Figures 12A-12B and / or Figure 13-14 One or more of the components, processes, features, and / or functions shown in the drawings may be rearranged and / or combined into a single component, process, feature, or function or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 2-Figure 7 、 Figures 8A-8D 、 Figure 9 、 Figures 10A-10C 、 Figure 11 、 Figures 12A-12B and / or Figure 13-14 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 2-Figure 7 、 Figures 8A-8D 、 Figure 9 、 Figures 10A-10C 、 Figure 11 、 Figures 12A-12B and / or Figure 13-14 The present invention and its corresponding description can be used to manufacture, create, provide and / or produce devices and / or integrated devices. In some implementations, the device can include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink and / or an interposer.

[0159] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, parts, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the drawings may not be drawn to scale. In some cases, for the sake of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0160] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Similarly, the term "aspect" does not require that all aspects of the disclosure include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other even if they are not in direct physical contact. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together so that current (e.g., signal, power, ground) can flow between the two objects. Two objects that are electrically coupled may or may not have current flowing between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any component described can be the first, second, third, or fourth component. For example, a component referred to as the second component can be the first, second, third, or fourth component. The term "encapsulate" means that an object can partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be located above a component located at the bottom. A top component can be considered a bottom component and vice versa. As described in this disclosure, depending on how the bottom or top is arbitrarily defined, a first component being "above" a second component can mean that the first component is above or below the second component. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. Further note that the term "above" as used in this application in the context of one component being located above another component can be used to refer to components on and / or in (e.g., on the surface of or embedded in) another component. Thus, for example, a first component being above a second component may mean (1) the first component is above the second component but not directly contacting the second component, (2) the first component is on the second component (e.g., on a surface of the second component), and / or (3) the first component is within (e.g., embedded in) the second component. A first component being "in" a second component may be partially within or completely within the second component. As used in this disclosure, the term "about 'X value'" or "about X value" means within 10% of "X value." For example, about 1 or a value of about 1 would mean a value in the range of 0.9–1.1.

[0161] In some implementations, an interconnect is an element or component in a device or package that allows or facilitates electrical connection between two points, elements and / or components. In some implementations, the interconnect may include traces, through-holes, pads, guide pillars, metallization layers, redistribution layers and / or under-bump metallization (UBM) layers / interconnects. In some implementations, the interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), grounding and / or power. The interconnect may include more than one element or component. The interconnect may be defined by one or more interconnects. The interconnect may include one or more metal layers. The interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form the interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating and / or an electroplating process may be used to form the interconnect.

[0162] In addition, it should be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as a sequential process, many operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0163] Hereinafter, further examples are described to facilitate understanding of the present invention.

[0164] In yet another first example, a package is described that includes a substrate having a plurality of interconnects, an integrated device coupled to the substrate, and an interconnected integrated device coupled to a surface of the substrate, wherein the integrated device, the interconnected integrated device, and the substrate are configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path extending (e.g., traveling) at least through the substrate, then through the interconnected integrated device, and back through the substrate. Additionally, the plurality of interconnects of the substrate may include a first minimum pitch, and the interconnected integrated device may include a plurality of interconnects having a second minimum pitch, the second minimum pitch being less than the first minimum pitch. Additionally, the interconnected integrated device may include a die substrate, at least one dielectric layer, and a plurality of interconnects. Additionally, the die substrate may include silicon, glass, and / or quartz. Additionally, the interconnected integrated device may include a die without transistors. Additionally, the package may include a second integrated device coupled to the surface of the substrate, wherein the interconnected integrated device may be located between the integrated device and the second integrated device. In addition, the integrated device, the interconnected integrated device, the second integrated device, and the substrate can be configured to provide a first electrical path for a first electrical signal between the integrated device and the second integrated device, the first electrical path extending at least through the substrate, then through the interconnected integrated device, and back through the substrate, and the interconnected integrated device can be configured as a bridge between the integrated device and the second integrated device for at least the first electrical signal. In addition, the integrated device and the interconnected integrated device can be coupled to a first surface of the substrate. In addition, the integrated device and the interconnected integrated device can be coupled to a second surface of the substrate. In addition, the interconnected integrated device can include a second substrate having a plurality of interconnects. In addition, the integrated device, the interconnected integrated device, and the substrate can be configured to provide a first electrical path for the first electrical signal of the integrated device, the first electrical path (i) extending (e.g., entering) through the front side of the interconnected integrated device, (ii) extending (e.g., traveling) through at least one interconnect in the interconnected integrated device, and (iii) extending (e.g., exiting) through the front side of the interconnected integrated device. Entering, traveling, and / or exiting can apply to electrical paths and / or electrical signals.

[0165] In another further example, an apparatus is described that includes a substrate having a plurality of interconnects, an integrated device coupled to the substrate, and an apparatus for interconnecting the integrated devices coupled to a surface of the substrate, wherein the integrated device, the apparatus for interconnecting the integrated devices, and the substrate are configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path extending (e.g., traveling) at least through the substrate, then through the apparatus for interconnecting the integrated devices, and back through the substrate. Additionally, the plurality of interconnects of the substrate may include a first minimum pitch, and the apparatus for interconnecting the integrated devices may include a plurality of interconnects having a second minimum pitch, the second minimum pitch being less than the first minimum pitch. Additionally, the apparatus for interconnecting the integrated devices may include a die substrate, at least one dielectric layer, and a plurality of interconnects. Additionally, the die substrate may include silicon, glass, and / or quartz. Additionally, the apparatus for interconnecting the integrated devices may include a die without transistors. Additionally, the apparatus may include a second integrated device coupled to the surface of the substrate, wherein the apparatus for interconnecting the integrated devices is located between the integrated device and the second integrated device. In addition, the integrated device, the apparatus for interconnecting the integrated devices, the second integrated device, and the substrate can be configured to provide a first electrical path for a first electrical signal between the integrated device and the second integrated device, the first electrical path traveling at least through the substrate, then through the apparatus for interconnecting the integrated devices, and back through the substrate, and the apparatus for interconnecting the integrated devices can be configured as a bridge between the integrated device and the second integrated device for at least the first electrical signal. In addition, the integrated device and the apparatus for interconnecting the integrated devices can be coupled to a first surface of the substrate or a second surface of the substrate. In addition, the interconnected integrated device can include a second substrate having a plurality of interconnects. In addition, the integrated device, the apparatus for interconnecting the integrated devices, and the substrate can be configured to provide a first electrical path for the first electrical signal, the first electrical path (i) extending (e.g., entering) through a front side of the apparatus for interconnecting the integrated devices, (ii) extending (e.g., traveling) through at least one interconnect in the apparatus for interconnecting the integrated devices, and (iii) extending (e.g., exiting) through the front side of the apparatus for interconnecting the integrated devices. The entry, travel, and / or exit can apply to the electrical path and / or the electrical signal.

[0166] In another further example, a method for manufacturing a package is described, the method comprising providing a substrate comprising a plurality of interconnects; coupling an integrated device to the substrate; and coupling an interconnected integrated device to a surface of the substrate, wherein the integrated device, the interconnected integrated device, and the substrate are configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path extending (e.g., running) at least through the substrate, then through the interconnected integrated device, and back through the substrate. Furthermore, the plurality of interconnects of the substrate may comprise a first minimum pitch, and wherein the interconnected integrated device may comprise a plurality of interconnects having a second minimum pitch, the second minimum pitch being less than the first minimum pitch. Furthermore, the interconnected integrated device may comprise a die substrate, at least one dielectric layer, and a plurality of interconnects. Furthermore, the integrated device, the interconnected integrated device, and the substrate may be configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path (i) extending (e.g., entering) through a front side of the interconnected integrated device, (ii) extending (e.g., running) through at least one interconnect in the interconnected integrated device, and (iii) extending (e.g., exiting) through the front side of the interconnected integrated device. The entering, running, and / or exiting may apply to the electrical path and / or the electrical signal.

[0167] Without departing from the present disclosure, the various features of the present disclosure described herein can be implemented in different systems. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, not to limit the scope of the claims. Therefore, the present teachings can be easily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: a substrate comprising a plurality of interconnects; an integrated device coupled to the first surface of the substrate; as well as an interconnect integrated device coupled to the first surface of the substrate, The interconnected integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, such that the electrical path extends at least through the first surface of the substrate, through the interconnected integrated device and back through the first surface of the substrate.

2. The package according to claim 1, Wherein the plurality of interconnects of the substrate comprises a first minimum pitch, and wherein the interconnected integrated device comprises a plurality of interconnects having a second minimum pitch, the second minimum pitch being smaller than the first minimum pitch. 3 . The package of claim 1 , wherein the interconnected integrated device comprises a die substrate, at least one dielectric layer, and a plurality of interconnects. The package of claim 3 , wherein the die substrate comprises silicon, glass, and / or quartz.

5. The package of claim 1, wherein the interconnected integrated device comprises a die without transistors.

6. The package of claim 1, further comprising a second integrated device coupled to the surface of the substrate, wherein the interconnect integrated device is located between the integrated device and the second integrated device.

7. The package according to claim 6, wherein the integrated device, the interconnected integrated device, the second integrated device, and the substrate are configured to provide the electrical path for the electrical signal between the integrated device and the second integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and back through the substrate, and The interconnect integrated device is configured as a bridge between the first integrated device and the second integrated device for at least the electrical signal.

8. The package of claim 1, wherein the integrated device and the interconnected integrated device are coupled to a first surface of the substrate.

9. The package according to claim 1, wherein the substrate comprises a first surface and a second surface, and wherein the integrated device and the interconnected integrated device are coupled to the second surface of the substrate.

10. The package of claim 1 , wherein the integrated device, the interconnected integrated device, and the substrate are configured to provide the electrical path for the electrical signal of the integrated device, the electrical path (i) entering through the front side of the interconnected integrated device, (ii) traveling through at least one interconnect in the interconnected integrated device, and (iii) exiting through the front side of the interconnected integrated device.

11. The package of claim 1 , wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a notebook computer, a server, an Internet of Things (IoT) device, and a device in an automobile.

12. A device comprising: a substrate comprising a plurality of interconnects; an integrated device coupled to the first surface of the substrate; as well as means for interconnecting integrated devices, coupled to the first surface of the substrate, The apparatus for interconnecting integrated devices and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, such that the electrical path extends at least through the first surface of the substrate, through the apparatus for interconnecting integrated devices, and back through the first surface of the substrate.

13. The device according to claim 12, Wherein the plurality of interconnects of the substrate comprises a first minimum pitch, and wherein the means for interconnecting an integrated device comprises a plurality of interconnects having a second minimum pitch, the second minimum pitch being smaller than the first minimum pitch.

14. The apparatus of claim 12, wherein the means for interconnecting an integrated device comprises a die substrate, at least one dielectric layer, and a plurality of interconnects.

15. The apparatus of claim 14, wherein the die substrate comprises silicon, glass, and / or quartz.

16. The apparatus of claim 12, wherein the means for integrated device interconnection comprises a die without transistors.

17. The apparatus of claim 12, further comprising a second integrated device coupled to the surface of the substrate, wherein the means for interconnecting integrated devices is located between the integrated device and the second integrated device.

18. The apparatus according to claim 17, wherein the integrated device, the apparatus for interconnecting integrated devices, the second integrated device and the substrate are configured to provide the electrical path for the electrical signal between the integrated device and the second integrated device, the electrical path at least running through the substrate, then passing through the apparatus for interconnecting integrated devices and returning through the substrate, and wherein the apparatus for interconnecting integrated devices is configured as a bridge between the integrated device and the second integrated device for at least the electrical path of the electrical signal.

19. The apparatus of claim 12, wherein the integrated device and the means for interconnecting an integrated device are coupled to a first surface of the substrate.

20. The apparatus of claim 12, wherein the integrated device and the means for interconnecting an integrated device are coupled to the second surface of the substrate.

21. The apparatus of claim 12 , wherein the integrated device, the apparatus for interconnecting integrated devices, and the substrate are configured to provide the electrical path for the electrical signal, the electrical path (i) entering through the front side of the apparatus for interconnecting integrated devices, (ii) traveling through at least one interconnect in the apparatus for interconnecting integrated devices, and (iii) exiting through the front side of the apparatus for interconnecting integrated devices.

22. The device of claim 12, wherein the device is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a notebook computer, a server, an Internet of Things (IoT) device, and a device in an automobile.

23. A method for manufacturing a package, comprising: providing a substrate including a plurality of interconnects; coupling an integrated device to the first surface of the substrate; as well as coupling an interconnect integrated device to the first surface of the substrate, The interconnected integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, such that the electrical path travels at least through the first surface of the substrate, through the interconnected integrated device and back through the first surface of the substrate.

24. The method according to claim 23, Wherein the plurality of interconnects of the substrate comprises a first minimum pitch, and wherein the interconnected integrated device comprises a plurality of interconnects having a second minimum pitch, the second minimum pitch being smaller than the first minimum pitch.

25. The method of claim 23, wherein the interconnected integrated device comprises a die substrate, at least one dielectric layer, and a plurality of interconnects.

26. The method of claim 23, wherein the integrated device, the interconnected integrated device, and the substrate are configured to provide the electrical path for the electrical signal of the integrated device, the electrical path (i) entering through the front side of the interconnected integrated device, (ii) traveling through at least one interconnect in the interconnected integrated device, and (iii) exiting through the front side of the interconnected integrated device.

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